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HAL_L476/stm32l4xx_ll_rcc.h@1:d0dfbce63a89, 2017-02-24 (annotated)

Committer:
elmot
Date:
Fri Feb 24 21:13:56 2017 +0000
Revision:
1:d0dfbce63a89
Ready-to-copy

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elmot 1:d0dfbce63a89 1 /**
elmot 1:d0dfbce63a89 2 ******************************************************************************
elmot 1:d0dfbce63a89 3 * @file stm32l4xx_ll_rcc.h
elmot 1:d0dfbce63a89 4 * @author MCD Application Team
elmot 1:d0dfbce63a89 5 * @version V1.5.1
elmot 1:d0dfbce63a89 6 * @date 31-May-2016
elmot 1:d0dfbce63a89 7 * @brief Header file of RCC LL module.
elmot 1:d0dfbce63a89 8 ******************************************************************************
elmot 1:d0dfbce63a89 9 * @attention
elmot 1:d0dfbce63a89 10 *
elmot 1:d0dfbce63a89 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
elmot 1:d0dfbce63a89 12 *
elmot 1:d0dfbce63a89 13 * Redistribution and use in source and binary forms, with or without modification,
elmot 1:d0dfbce63a89 14 * are permitted provided that the following conditions are met:
elmot 1:d0dfbce63a89 15 * 1. Redistributions of source code must retain the above copyright notice,
elmot 1:d0dfbce63a89 16 * this list of conditions and the following disclaimer.
elmot 1:d0dfbce63a89 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
elmot 1:d0dfbce63a89 18 * this list of conditions and the following disclaimer in the documentation
elmot 1:d0dfbce63a89 19 * and/or other materials provided with the distribution.
elmot 1:d0dfbce63a89 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
elmot 1:d0dfbce63a89 21 * may be used to endorse or promote products derived from this software
elmot 1:d0dfbce63a89 22 * without specific prior written permission.
elmot 1:d0dfbce63a89 23 *
elmot 1:d0dfbce63a89 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elmot 1:d0dfbce63a89 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elmot 1:d0dfbce63a89 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elmot 1:d0dfbce63a89 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
elmot 1:d0dfbce63a89 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
elmot 1:d0dfbce63a89 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
elmot 1:d0dfbce63a89 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
elmot 1:d0dfbce63a89 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
elmot 1:d0dfbce63a89 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
elmot 1:d0dfbce63a89 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elmot 1:d0dfbce63a89 34 *
elmot 1:d0dfbce63a89 35 ******************************************************************************
elmot 1:d0dfbce63a89 36 */
elmot 1:d0dfbce63a89 37
elmot 1:d0dfbce63a89 38 /* Define to prevent recursive inclusion -------------------------------------*/
elmot 1:d0dfbce63a89 39 #ifndef __STM32L4xx_LL_RCC_H
elmot 1:d0dfbce63a89 40 #define __STM32L4xx_LL_RCC_H
elmot 1:d0dfbce63a89 41
elmot 1:d0dfbce63a89 42 #ifdef __cplusplus
elmot 1:d0dfbce63a89 43 extern "C" {
elmot 1:d0dfbce63a89 44 #endif
elmot 1:d0dfbce63a89 45
elmot 1:d0dfbce63a89 46 /* Includes ------------------------------------------------------------------*/
elmot 1:d0dfbce63a89 47 #include "stm32l4xx.h"
elmot 1:d0dfbce63a89 48
elmot 1:d0dfbce63a89 49 /** @addtogroup STM32L4xx_LL_Driver
elmot 1:d0dfbce63a89 50 * @{
elmot 1:d0dfbce63a89 51 */
elmot 1:d0dfbce63a89 52
elmot 1:d0dfbce63a89 53 #if defined(RCC)
elmot 1:d0dfbce63a89 54
elmot 1:d0dfbce63a89 55 /** @defgroup RCC_LL RCC
elmot 1:d0dfbce63a89 56 * @{
elmot 1:d0dfbce63a89 57 */
elmot 1:d0dfbce63a89 58
elmot 1:d0dfbce63a89 59 /* Private types -------------------------------------------------------------*/
elmot 1:d0dfbce63a89 60 /* Private variables ---------------------------------------------------------*/
elmot 1:d0dfbce63a89 61 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
elmot 1:d0dfbce63a89 62 * @{
elmot 1:d0dfbce63a89 63 */
elmot 1:d0dfbce63a89 64
elmot 1:d0dfbce63a89 65 static const uint8_t aRCC_APBAHBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
elmot 1:d0dfbce63a89 66
elmot 1:d0dfbce63a89 67 /**
elmot 1:d0dfbce63a89 68 * @}
elmot 1:d0dfbce63a89 69 */
elmot 1:d0dfbce63a89 70
elmot 1:d0dfbce63a89 71 /* Private constants ---------------------------------------------------------*/
elmot 1:d0dfbce63a89 72 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
elmot 1:d0dfbce63a89 73 * @{
elmot 1:d0dfbce63a89 74 */
elmot 1:d0dfbce63a89 75 /* Defines used for the bit position in the register and perform offsets*/
elmot 1:d0dfbce63a89 76 #define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE)
elmot 1:d0dfbce63a89 77 #define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1)
elmot 1:d0dfbce63a89 78 #define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2)
elmot 1:d0dfbce63a89 79 #define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_HSICAL)
elmot 1:d0dfbce63a89 80 #define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_HSITRIM)
elmot 1:d0dfbce63a89 81 #define RCC_POSITION_MSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_MSICAL)
elmot 1:d0dfbce63a89 82 #define RCC_POSITION_MSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_MSITRIM)
elmot 1:d0dfbce63a89 83 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 84 #define RCC_POSITION_HSI48CAL (uint32_t)POSITION_VAL(RCC_CRRCR_HSI48CAL)
elmot 1:d0dfbce63a89 85 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 86 #define RCC_POSITION_PLLN (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLN)
elmot 1:d0dfbce63a89 87 #define RCC_POSITION_PLLM (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLM)
elmot 1:d0dfbce63a89 88 #define RCC_POSITION_PLLR (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLR)
elmot 1:d0dfbce63a89 89 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 90 #define RCC_POSITION_PLLP (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLPDIV)
elmot 1:d0dfbce63a89 91 #else
elmot 1:d0dfbce63a89 92 #define RCC_POSITION_PLLP (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLP)
elmot 1:d0dfbce63a89 93 #endif /* RCC_PLLP_DIV_2_31_SUPPOR T*/
elmot 1:d0dfbce63a89 94 #define RCC_POSITION_PLLQ (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLQ)
elmot 1:d0dfbce63a89 95 #define RCC_POSITION_PLLSAI1N (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)
elmot 1:d0dfbce63a89 96 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 97 #define RCC_POSITION_PLLSAI1P (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)
elmot 1:d0dfbce63a89 98 #else
elmot 1:d0dfbce63a89 99 #define RCC_POSITION_PLLSAI1P (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)
elmot 1:d0dfbce63a89 100 #endif /*RCC_PLLSAI1P_DIV_2_31_SUPPORT*/
elmot 1:d0dfbce63a89 101 #define RCC_POSITION_PLLSAI1Q (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)
elmot 1:d0dfbce63a89 102 #define RCC_POSITION_PLLSAI1R (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)
elmot 1:d0dfbce63a89 103 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 104 #define RCC_POSITION_PLLSAI2N (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)
elmot 1:d0dfbce63a89 105 #define RCC_POSITION_PLLSAI2P (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)
elmot 1:d0dfbce63a89 106 #define RCC_POSITION_PLLSAI2R (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)
elmot 1:d0dfbce63a89 107 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 108
elmot 1:d0dfbce63a89 109 /**
elmot 1:d0dfbce63a89 110 * @}
elmot 1:d0dfbce63a89 111 */
elmot 1:d0dfbce63a89 112
elmot 1:d0dfbce63a89 113 /* Private macros ------------------------------------------------------------*/
elmot 1:d0dfbce63a89 114 #if defined(USE_FULL_LL_DRIVER)
elmot 1:d0dfbce63a89 115 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
elmot 1:d0dfbce63a89 116 * @{
elmot 1:d0dfbce63a89 117 */
elmot 1:d0dfbce63a89 118 /**
elmot 1:d0dfbce63a89 119 * @}
elmot 1:d0dfbce63a89 120 */
elmot 1:d0dfbce63a89 121 #endif /*USE_FULL_LL_DRIVER*/
elmot 1:d0dfbce63a89 122 /* Exported types ------------------------------------------------------------*/
elmot 1:d0dfbce63a89 123 #if defined(USE_FULL_LL_DRIVER)
elmot 1:d0dfbce63a89 124 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
elmot 1:d0dfbce63a89 125 * @{
elmot 1:d0dfbce63a89 126 */
elmot 1:d0dfbce63a89 127
elmot 1:d0dfbce63a89 128 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
elmot 1:d0dfbce63a89 129 * @{
elmot 1:d0dfbce63a89 130 */
elmot 1:d0dfbce63a89 131
elmot 1:d0dfbce63a89 132 /**
elmot 1:d0dfbce63a89 133 * @brief RCC Clocks Frequency Structure
elmot 1:d0dfbce63a89 134 */
elmot 1:d0dfbce63a89 135 typedef struct
elmot 1:d0dfbce63a89 136 {
elmot 1:d0dfbce63a89 137 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
elmot 1:d0dfbce63a89 138 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
elmot 1:d0dfbce63a89 139 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
elmot 1:d0dfbce63a89 140 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
elmot 1:d0dfbce63a89 141 } LL_RCC_ClocksTypeDef;
elmot 1:d0dfbce63a89 142
elmot 1:d0dfbce63a89 143 /**
elmot 1:d0dfbce63a89 144 * @}
elmot 1:d0dfbce63a89 145 */
elmot 1:d0dfbce63a89 146
elmot 1:d0dfbce63a89 147 /**
elmot 1:d0dfbce63a89 148 * @}
elmot 1:d0dfbce63a89 149 */
elmot 1:d0dfbce63a89 150 #endif /* USE_FULL_LL_DRIVER */
elmot 1:d0dfbce63a89 151
elmot 1:d0dfbce63a89 152 /* Exported constants --------------------------------------------------------*/
elmot 1:d0dfbce63a89 153 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
elmot 1:d0dfbce63a89 154 * @{
elmot 1:d0dfbce63a89 155 */
elmot 1:d0dfbce63a89 156
elmot 1:d0dfbce63a89 157 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
elmot 1:d0dfbce63a89 158 * @brief Defines used to adapt values of different oscillators
elmot 1:d0dfbce63a89 159 * @note These values could be modified in the user environment according to
elmot 1:d0dfbce63a89 160 * HW set-up.
elmot 1:d0dfbce63a89 161 * @{
elmot 1:d0dfbce63a89 162 */
elmot 1:d0dfbce63a89 163 #if !defined (HSE_VALUE)
elmot 1:d0dfbce63a89 164 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the HSE oscillator in Hz */
elmot 1:d0dfbce63a89 165 #endif /* HSE_VALUE */
elmot 1:d0dfbce63a89 166
elmot 1:d0dfbce63a89 167 #if !defined (HSI_VALUE)
elmot 1:d0dfbce63a89 168 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the HSI oscillator in Hz */
elmot 1:d0dfbce63a89 169 #endif /* HSI_VALUE */
elmot 1:d0dfbce63a89 170
elmot 1:d0dfbce63a89 171 #if !defined (LSE_VALUE)
elmot 1:d0dfbce63a89 172 #define LSE_VALUE ((uint32_t)32768) /*!< Value of the LSE oscillator in Hz */
elmot 1:d0dfbce63a89 173 #endif /* LSE_VALUE */
elmot 1:d0dfbce63a89 174
elmot 1:d0dfbce63a89 175 #if !defined (LSI_VALUE)
elmot 1:d0dfbce63a89 176 #define LSI_VALUE ((uint32_t)32000) /*!< Value of the LSI oscillator in Hz */
elmot 1:d0dfbce63a89 177 #endif /* LSI_VALUE */
elmot 1:d0dfbce63a89 178 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 179
elmot 1:d0dfbce63a89 180 #if !defined (HSI48_VALUE)
elmot 1:d0dfbce63a89 181 #define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the HSI48 oscillator in Hz */
elmot 1:d0dfbce63a89 182 #endif /* HSI48_VALUE */
elmot 1:d0dfbce63a89 183 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 184 /**
elmot 1:d0dfbce63a89 185 * @}
elmot 1:d0dfbce63a89 186 */
elmot 1:d0dfbce63a89 187
elmot 1:d0dfbce63a89 188 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
elmot 1:d0dfbce63a89 189 * @brief Flags defines which can be used with LL_RCC_WriteReg function
elmot 1:d0dfbce63a89 190 * @{
elmot 1:d0dfbce63a89 191 */
elmot 1:d0dfbce63a89 192 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
elmot 1:d0dfbce63a89 193 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
elmot 1:d0dfbce63a89 194 #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */
elmot 1:d0dfbce63a89 195 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
elmot 1:d0dfbce63a89 196 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
elmot 1:d0dfbce63a89 197 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
elmot 1:d0dfbce63a89 198 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 199 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
elmot 1:d0dfbce63a89 200 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 201 #define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */
elmot 1:d0dfbce63a89 202 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 203 #define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC /*!< PLLSAI2 Ready Interrupt Clear */
elmot 1:d0dfbce63a89 204 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 205 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
elmot 1:d0dfbce63a89 206 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
elmot 1:d0dfbce63a89 207 /**
elmot 1:d0dfbce63a89 208 * @}
elmot 1:d0dfbce63a89 209 */
elmot 1:d0dfbce63a89 210
elmot 1:d0dfbce63a89 211 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
elmot 1:d0dfbce63a89 212 * @brief Flags defines which can be used with LL_RCC_ReadReg function
elmot 1:d0dfbce63a89 213 * @{
elmot 1:d0dfbce63a89 214 */
elmot 1:d0dfbce63a89 215 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
elmot 1:d0dfbce63a89 216 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
elmot 1:d0dfbce63a89 217 #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
elmot 1:d0dfbce63a89 218 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
elmot 1:d0dfbce63a89 219 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
elmot 1:d0dfbce63a89 220 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
elmot 1:d0dfbce63a89 221 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 222 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
elmot 1:d0dfbce63a89 223 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 224 #define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
elmot 1:d0dfbce63a89 225 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 226 #define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */
elmot 1:d0dfbce63a89 227 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 228 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
elmot 1:d0dfbce63a89 229 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
elmot 1:d0dfbce63a89 230 #define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /*!< Firewall reset flag */
elmot 1:d0dfbce63a89 231 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
elmot 1:d0dfbce63a89 232 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
elmot 1:d0dfbce63a89 233 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
elmot 1:d0dfbce63a89 234 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
elmot 1:d0dfbce63a89 235 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
elmot 1:d0dfbce63a89 236 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
elmot 1:d0dfbce63a89 237 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
elmot 1:d0dfbce63a89 238 /**
elmot 1:d0dfbce63a89 239 * @}
elmot 1:d0dfbce63a89 240 */
elmot 1:d0dfbce63a89 241
elmot 1:d0dfbce63a89 242 /** @defgroup RCC_LL_EC_IT IT Defines
elmot 1:d0dfbce63a89 243 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
elmot 1:d0dfbce63a89 244 * @{
elmot 1:d0dfbce63a89 245 */
elmot 1:d0dfbce63a89 246 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
elmot 1:d0dfbce63a89 247 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
elmot 1:d0dfbce63a89 248 #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */
elmot 1:d0dfbce63a89 249 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
elmot 1:d0dfbce63a89 250 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
elmot 1:d0dfbce63a89 251 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
elmot 1:d0dfbce63a89 252 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 253 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
elmot 1:d0dfbce63a89 254 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 255 #define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */
elmot 1:d0dfbce63a89 256 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 257 #define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE /*!< PLLSAI2 Ready Interrupt Enable */
elmot 1:d0dfbce63a89 258 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 259 #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */
elmot 1:d0dfbce63a89 260 /**
elmot 1:d0dfbce63a89 261 * @}
elmot 1:d0dfbce63a89 262 */
elmot 1:d0dfbce63a89 263
elmot 1:d0dfbce63a89 264 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
elmot 1:d0dfbce63a89 265 * @{
elmot 1:d0dfbce63a89 266 */
elmot 1:d0dfbce63a89 267 #define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) /*!< Xtal mode lower driving capability */
elmot 1:d0dfbce63a89 268 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
elmot 1:d0dfbce63a89 269 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
elmot 1:d0dfbce63a89 270 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
elmot 1:d0dfbce63a89 271 /**
elmot 1:d0dfbce63a89 272 * @}
elmot 1:d0dfbce63a89 273 */
elmot 1:d0dfbce63a89 274
elmot 1:d0dfbce63a89 275 /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
elmot 1:d0dfbce63a89 276 * @{
elmot 1:d0dfbce63a89 277 */
elmot 1:d0dfbce63a89 278 #define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
elmot 1:d0dfbce63a89 279 #define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
elmot 1:d0dfbce63a89 280 #define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
elmot 1:d0dfbce63a89 281 #define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
elmot 1:d0dfbce63a89 282 #define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
elmot 1:d0dfbce63a89 283 #define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
elmot 1:d0dfbce63a89 284 #define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
elmot 1:d0dfbce63a89 285 #define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
elmot 1:d0dfbce63a89 286 #define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
elmot 1:d0dfbce63a89 287 #define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
elmot 1:d0dfbce63a89 288 #define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
elmot 1:d0dfbce63a89 289 #define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
elmot 1:d0dfbce63a89 290 /**
elmot 1:d0dfbce63a89 291 * @}
elmot 1:d0dfbce63a89 292 */
elmot 1:d0dfbce63a89 293
elmot 1:d0dfbce63a89 294 /** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode
elmot 1:d0dfbce63a89 295 * @{
elmot 1:d0dfbce63a89 296 */
elmot 1:d0dfbce63a89 297 #define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /*!< MSI = 1 MHz */
elmot 1:d0dfbce63a89 298 #define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /*!< MSI = 2 MHz */
elmot 1:d0dfbce63a89 299 #define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /*!< MSI = 4 MHz */
elmot 1:d0dfbce63a89 300 #define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /*!< MSI = 8 MHz */
elmot 1:d0dfbce63a89 301 /**
elmot 1:d0dfbce63a89 302 * @}
elmot 1:d0dfbce63a89 303 */
elmot 1:d0dfbce63a89 304
elmot 1:d0dfbce63a89 305 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
elmot 1:d0dfbce63a89 306 * @{
elmot 1:d0dfbce63a89 307 */
elmot 1:d0dfbce63a89 308 #define LL_RCC_LSCO_CLKSOURCE_LSI (uint32_t)0x00000000 /*!< LSI selection for low speed clock */
elmot 1:d0dfbce63a89 309 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
elmot 1:d0dfbce63a89 310 /**
elmot 1:d0dfbce63a89 311 * @}
elmot 1:d0dfbce63a89 312 */
elmot 1:d0dfbce63a89 313
elmot 1:d0dfbce63a89 314 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
elmot 1:d0dfbce63a89 315 * @{
elmot 1:d0dfbce63a89 316 */
elmot 1:d0dfbce63a89 317 #define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */
elmot 1:d0dfbce63a89 318 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
elmot 1:d0dfbce63a89 319 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
elmot 1:d0dfbce63a89 320 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
elmot 1:d0dfbce63a89 321 /**
elmot 1:d0dfbce63a89 322 * @}
elmot 1:d0dfbce63a89 323 */
elmot 1:d0dfbce63a89 324
elmot 1:d0dfbce63a89 325 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
elmot 1:d0dfbce63a89 326 * @{
elmot 1:d0dfbce63a89 327 */
elmot 1:d0dfbce63a89 328 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
elmot 1:d0dfbce63a89 329 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
elmot 1:d0dfbce63a89 330 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
elmot 1:d0dfbce63a89 331 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
elmot 1:d0dfbce63a89 332 /**
elmot 1:d0dfbce63a89 333 * @}
elmot 1:d0dfbce63a89 334 */
elmot 1:d0dfbce63a89 335
elmot 1:d0dfbce63a89 336 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
elmot 1:d0dfbce63a89 337 * @{
elmot 1:d0dfbce63a89 338 */
elmot 1:d0dfbce63a89 339 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
elmot 1:d0dfbce63a89 340 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
elmot 1:d0dfbce63a89 341 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
elmot 1:d0dfbce63a89 342 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
elmot 1:d0dfbce63a89 343 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
elmot 1:d0dfbce63a89 344 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
elmot 1:d0dfbce63a89 345 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
elmot 1:d0dfbce63a89 346 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
elmot 1:d0dfbce63a89 347 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
elmot 1:d0dfbce63a89 348 /**
elmot 1:d0dfbce63a89 349 * @}
elmot 1:d0dfbce63a89 350 */
elmot 1:d0dfbce63a89 351
elmot 1:d0dfbce63a89 352 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
elmot 1:d0dfbce63a89 353 * @{
elmot 1:d0dfbce63a89 354 */
elmot 1:d0dfbce63a89 355 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
elmot 1:d0dfbce63a89 356 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
elmot 1:d0dfbce63a89 357 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
elmot 1:d0dfbce63a89 358 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
elmot 1:d0dfbce63a89 359 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
elmot 1:d0dfbce63a89 360 /**
elmot 1:d0dfbce63a89 361 * @}
elmot 1:d0dfbce63a89 362 */
elmot 1:d0dfbce63a89 363 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
elmot 1:d0dfbce63a89 364 * @{
elmot 1:d0dfbce63a89 365 */
elmot 1:d0dfbce63a89 366 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
elmot 1:d0dfbce63a89 367 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
elmot 1:d0dfbce63a89 368 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
elmot 1:d0dfbce63a89 369 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
elmot 1:d0dfbce63a89 370 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
elmot 1:d0dfbce63a89 371 /**
elmot 1:d0dfbce63a89 372 * @}
elmot 1:d0dfbce63a89 373 */
elmot 1:d0dfbce63a89 374 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
elmot 1:d0dfbce63a89 375 * @{
elmot 1:d0dfbce63a89 376 */
elmot 1:d0dfbce63a89 377 #define LL_RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000) /*!< MSI selection after wake-up from STOP */
elmot 1:d0dfbce63a89 378 #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
elmot 1:d0dfbce63a89 379 /**
elmot 1:d0dfbce63a89 380 * @}
elmot 1:d0dfbce63a89 381 */
elmot 1:d0dfbce63a89 382
elmot 1:d0dfbce63a89 383 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
elmot 1:d0dfbce63a89 384 * @{
elmot 1:d0dfbce63a89 385 */
elmot 1:d0dfbce63a89 386 #define LL_RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000) /*!< MCO output disabled, no clock on MCO */
elmot 1:d0dfbce63a89 387 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
elmot 1:d0dfbce63a89 388 #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
elmot 1:d0dfbce63a89 389 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
elmot 1:d0dfbce63a89 390 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
elmot 1:d0dfbce63a89 391 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
elmot 1:d0dfbce63a89 392 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
elmot 1:d0dfbce63a89 393 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
elmot 1:d0dfbce63a89 394 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 395 #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
elmot 1:d0dfbce63a89 396 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 397 /**
elmot 1:d0dfbce63a89 398 * @}
elmot 1:d0dfbce63a89 399 */
elmot 1:d0dfbce63a89 400
elmot 1:d0dfbce63a89 401 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
elmot 1:d0dfbce63a89 402 * @{
elmot 1:d0dfbce63a89 403 */
elmot 1:d0dfbce63a89 404 #define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
elmot 1:d0dfbce63a89 405 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
elmot 1:d0dfbce63a89 406 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
elmot 1:d0dfbce63a89 407 #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
elmot 1:d0dfbce63a89 408 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
elmot 1:d0dfbce63a89 409 /**
elmot 1:d0dfbce63a89 410 * @}
elmot 1:d0dfbce63a89 411 */
elmot 1:d0dfbce63a89 412
elmot 1:d0dfbce63a89 413 #if defined(USE_FULL_LL_DRIVER)
elmot 1:d0dfbce63a89 414 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
elmot 1:d0dfbce63a89 415 * @{
elmot 1:d0dfbce63a89 416 */
elmot 1:d0dfbce63a89 417 #define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000 /*!< No clock enabled for the peripheral */
elmot 1:d0dfbce63a89 418 #define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
elmot 1:d0dfbce63a89 419 /**
elmot 1:d0dfbce63a89 420 * @}
elmot 1:d0dfbce63a89 421 */
elmot 1:d0dfbce63a89 422 #endif /* USE_FULL_LL_DRIVER */
elmot 1:d0dfbce63a89 423
elmot 1:d0dfbce63a89 424 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
elmot 1:d0dfbce63a89 425 * @{
elmot 1:d0dfbce63a89 426 */
elmot 1:d0dfbce63a89 427 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_CCIPR_USART1SEL << 16) | 0x00000000) /*!< PCLK2 clock used as USART1 clock source */
elmot 1:d0dfbce63a89 428 #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
elmot 1:d0dfbce63a89 429 #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
elmot 1:d0dfbce63a89 430 #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */
elmot 1:d0dfbce63a89 431 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART2SEL << 16) | 0x00000000) /*!< PCLK1 clock used as USART2 clock source */
elmot 1:d0dfbce63a89 432 #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
elmot 1:d0dfbce63a89 433 #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
elmot 1:d0dfbce63a89 434 #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */
elmot 1:d0dfbce63a89 435 #if defined(RCC_CCIPR_USART3SEL)
elmot 1:d0dfbce63a89 436 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART3SEL << 16) | 0x00000000) /*!< PCLK1 clock used as USART3 clock source */
elmot 1:d0dfbce63a89 437 #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
elmot 1:d0dfbce63a89 438 #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
elmot 1:d0dfbce63a89 439 #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */
elmot 1:d0dfbce63a89 440 #endif /* RCC_CCIPR_USART3SEL */
elmot 1:d0dfbce63a89 441 /**
elmot 1:d0dfbce63a89 442 * @}
elmot 1:d0dfbce63a89 443 */
elmot 1:d0dfbce63a89 444
elmot 1:d0dfbce63a89 445 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
elmot 1:d0dfbce63a89 446 /** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
elmot 1:d0dfbce63a89 447 * @{
elmot 1:d0dfbce63a89 448 */
elmot 1:d0dfbce63a89 449 #if defined(RCC_CCIPR_UART4SEL)
elmot 1:d0dfbce63a89 450 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_UART4SEL << 16) | 0x00000000) /*!< PCLK1 clock used as UART4 clock source */
elmot 1:d0dfbce63a89 451 #define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
elmot 1:d0dfbce63a89 452 #define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
elmot 1:d0dfbce63a89 453 #define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL) /*!< LSE clock used as UART4 clock source */
elmot 1:d0dfbce63a89 454 #endif /* RCC_CCIPR_UART4SEL */
elmot 1:d0dfbce63a89 455 #if defined(RCC_CCIPR_UART5SEL)
elmot 1:d0dfbce63a89 456 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_UART5SEL << 16) | 0x00000000) /*!< PCLK1 clock used as UART5 clock source */
elmot 1:d0dfbce63a89 457 #define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
elmot 1:d0dfbce63a89 458 #define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
elmot 1:d0dfbce63a89 459 #define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL) /*!< LSE clock used as UART5 clock source */
elmot 1:d0dfbce63a89 460 #endif /* RCC_CCIPR_UART5SEL */
elmot 1:d0dfbce63a89 461 /**
elmot 1:d0dfbce63a89 462 * @}
elmot 1:d0dfbce63a89 463 */
elmot 1:d0dfbce63a89 464 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
elmot 1:d0dfbce63a89 465
elmot 1:d0dfbce63a89 466 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection
elmot 1:d0dfbce63a89 467 * @{
elmot 1:d0dfbce63a89 468 */
elmot 1:d0dfbce63a89 469 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 (uint32_t)0x00000000 /*!< PCLK1 clock used as LPUART1 clock source */
elmot 1:d0dfbce63a89 470 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
elmot 1:d0dfbce63a89 471 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
elmot 1:d0dfbce63a89 472 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE clock used as LPUART1 clock source */
elmot 1:d0dfbce63a89 473 /**
elmot 1:d0dfbce63a89 474 * @}
elmot 1:d0dfbce63a89 475 */
elmot 1:d0dfbce63a89 476
elmot 1:d0dfbce63a89 477 /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
elmot 1:d0dfbce63a89 478 * @{
elmot 1:d0dfbce63a89 479 */
elmot 1:d0dfbce63a89 480 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000 >> 4)) /*!< PCLK1 clock used as I2C1 clock source */
elmot 1:d0dfbce63a89 481 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4)) /*!< SYSCLK clock used as I2C1 clock source */
elmot 1:d0dfbce63a89 482 #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4)) /*!< HSI clock used as I2C1 clock source */
elmot 1:d0dfbce63a89 483 #if defined(RCC_CCIPR_I2C2SEL)
elmot 1:d0dfbce63a89 484 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (0x00000000 >> 4)) /*!< PCLK1 clock used as I2C2 clock source */
elmot 1:d0dfbce63a89 485 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_0 >> 4)) /*!< SYSCLK clock used as I2C2 clock source */
elmot 1:d0dfbce63a89 486 #define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_1 >> 4)) /*!< HSI clock used as I2C2 clock source */
elmot 1:d0dfbce63a89 487 #endif /* RCC_CCIPR_I2C2SEL */
elmot 1:d0dfbce63a89 488 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000 >> 4)) /*!< PCLK1 clock used as I2C3 clock source */
elmot 1:d0dfbce63a89 489 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4)) /*!< SYSCLK clock used as I2C3 clock source */
elmot 1:d0dfbce63a89 490 #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4)) /*!< HSI clock used as I2C3 clock source */
elmot 1:d0dfbce63a89 491 /**
elmot 1:d0dfbce63a89 492 * @}
elmot 1:d0dfbce63a89 493 */
elmot 1:d0dfbce63a89 494
elmot 1:d0dfbce63a89 495 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
elmot 1:d0dfbce63a89 496 * @{
elmot 1:d0dfbce63a89 497 */
elmot 1:d0dfbce63a89 498 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000 >> 16)) /*!< PCLK1 clock used as LPTIM1 clock source */
elmot 1:d0dfbce63a89 499 #define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16)) /*!< LSI clock used as LPTIM1 clock source */
elmot 1:d0dfbce63a89 500 #define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16)) /*!< HSI clock used as LPTIM1 clock source */
elmot 1:d0dfbce63a89 501 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16)) /*!< LSE clock used as LPTIM1 clock source */
elmot 1:d0dfbce63a89 502 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000 >> 16)) /*!< PCLK1 clock used as LPTIM2 clock source */
elmot 1:d0dfbce63a89 503 #define LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16)) /*!< LSI clock used as LPTIM2 clock source */
elmot 1:d0dfbce63a89 504 #define LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16)) /*!< HSI clock used as LPTIM2 clock source */
elmot 1:d0dfbce63a89 505 #define LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16)) /*!< LSE clock used as LPTIM2 clock source */
elmot 1:d0dfbce63a89 506 /**
elmot 1:d0dfbce63a89 507 * @}
elmot 1:d0dfbce63a89 508 */
elmot 1:d0dfbce63a89 509
elmot 1:d0dfbce63a89 510 /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
elmot 1:d0dfbce63a89 511 * @{
elmot 1:d0dfbce63a89 512 */
elmot 1:d0dfbce63a89 513 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_SAI1SEL | (0x00000000 >> 16)) /*!< PLLSAI1 clock used as SAI1 clock source */
elmot 1:d0dfbce63a89 514 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 515 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16)) /*!< PLLSAI2 clock used as SAI1 clock source */
elmot 1:d0dfbce63a89 516 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 517 #define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16)) /*!< PLL clock used as SAI1 clock source */
elmot 1:d0dfbce63a89 518 #define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16)) /*!< External input clock used as SAI1 clock source */
elmot 1:d0dfbce63a89 519 #if defined(RCC_CCIPR_SAI2SEL)
elmot 1:d0dfbce63a89 520 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_SAI2SEL | (0x00000000 >> 16)) /*!< PLLSAI1 clock used as SAI2 clock source */
elmot 1:d0dfbce63a89 521 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 522 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16)) /*!< PLLSAI2 clock used as SAI2 clock source */
elmot 1:d0dfbce63a89 523 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 524 #define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16)) /*!< PLL clock used as SAI2 clock source */
elmot 1:d0dfbce63a89 525 #define LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16)) /*!< External input clock used as SAI2 clock source */
elmot 1:d0dfbce63a89 526 #endif /* RCC_CCIPR_SAI2SEL */
elmot 1:d0dfbce63a89 527 /**
elmot 1:d0dfbce63a89 528 * @}
elmot 1:d0dfbce63a89 529 */
elmot 1:d0dfbce63a89 530
elmot 1:d0dfbce63a89 531 /** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection
elmot 1:d0dfbce63a89 532 * @{
elmot 1:d0dfbce63a89 533 */
elmot 1:d0dfbce63a89 534 #define LL_RCC_SDMMC1_CLKSOURCE_NONE (uint32_t)(0x00000000) /*!< No clock used as SDMMC1 clock source */
elmot 1:d0dfbce63a89 535 #define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0) /*!< PLLSAI1 clock used as SDMMC1 clock source */
elmot 1:d0dfbce63a89 536 #define LL_RCC_SDMMC1_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1) /*!< PLL clock used as SDMMC1 clock source */
elmot 1:d0dfbce63a89 537 #define LL_RCC_SDMMC1_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL) /*!< MSI clock used as SDMMC1 clock source */
elmot 1:d0dfbce63a89 538 /**
elmot 1:d0dfbce63a89 539 * @}
elmot 1:d0dfbce63a89 540 */
elmot 1:d0dfbce63a89 541
elmot 1:d0dfbce63a89 542 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
elmot 1:d0dfbce63a89 543 * @{
elmot 1:d0dfbce63a89 544 */
elmot 1:d0dfbce63a89 545 #define LL_RCC_RNG_CLKSOURCE_NONE (uint32_t)(0x00000000) /*!< No clock used as RNG clock source */
elmot 1:d0dfbce63a89 546 #define LL_RCC_RNG_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0) /*!< PLLSAI1 clock used as RNG clock source */
elmot 1:d0dfbce63a89 547 #define LL_RCC_RNG_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1) /*!< PLL clock used as RNG clock source */
elmot 1:d0dfbce63a89 548 #define LL_RCC_RNG_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL) /*!< MSI clock used as RNG clock source */
elmot 1:d0dfbce63a89 549 /**
elmot 1:d0dfbce63a89 550 * @}
elmot 1:d0dfbce63a89 551 */
elmot 1:d0dfbce63a89 552
elmot 1:d0dfbce63a89 553 #if defined(USB_OTG_FS) || defined(USB)
elmot 1:d0dfbce63a89 554 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
elmot 1:d0dfbce63a89 555 * @{
elmot 1:d0dfbce63a89 556 */
elmot 1:d0dfbce63a89 557 #define LL_RCC_USB_CLKSOURCE_NONE (uint32_t)(0x00000000) /*!< No clock used as USB clock source */
elmot 1:d0dfbce63a89 558 #define LL_RCC_USB_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0) /*!< PLLSAI1 clock used as USB clock source */
elmot 1:d0dfbce63a89 559 #define LL_RCC_USB_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1) /*!< PLL clock used as USB clock source */
elmot 1:d0dfbce63a89 560 #define LL_RCC_USB_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL) /*!< MSI clock used as USB clock source */
elmot 1:d0dfbce63a89 561 /**
elmot 1:d0dfbce63a89 562 * @}
elmot 1:d0dfbce63a89 563 */
elmot 1:d0dfbce63a89 564
elmot 1:d0dfbce63a89 565 #endif /* USB_OTG_FS || USB */
elmot 1:d0dfbce63a89 566
elmot 1:d0dfbce63a89 567 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
elmot 1:d0dfbce63a89 568 * @{
elmot 1:d0dfbce63a89 569 */
elmot 1:d0dfbce63a89 570 #define LL_RCC_ADC_CLKSOURCE_NONE (uint32_t)(0x00000000) /*!< No clock used as ADC clock source */
elmot 1:d0dfbce63a89 571 #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_ADCSEL_0) /*!< PLLSAI1 clock used as ADC clock source */
elmot 1:d0dfbce63a89 572 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 573 #define LL_RCC_ADC_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_ADCSEL_1) /*!< PLLSAI2 clock used as ADC clock source */
elmot 1:d0dfbce63a89 574 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 575 #define LL_RCC_ADC_CLKSOURCE_SYSCLK (uint32_t)(RCC_CCIPR_ADCSEL) /*!< SYSCLK clock used as ADC clock source */
elmot 1:d0dfbce63a89 576 /**
elmot 1:d0dfbce63a89 577 * @}
elmot 1:d0dfbce63a89 578 */
elmot 1:d0dfbce63a89 579
elmot 1:d0dfbce63a89 580 /** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE Peripheral SWPMI clock source selection
elmot 1:d0dfbce63a89 581 * @{
elmot 1:d0dfbce63a89 582 */
elmot 1:d0dfbce63a89 583 #define LL_RCC_SWPMI1_CLKSOURCE_PCLK (uint32_t)(0x00000000) /*!< PCLK used as SWPMI1 clock source */
elmot 1:d0dfbce63a89 584 #define LL_RCC_SWPMI1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_SWPMI1SEL) /*!< HSI used as SWPMI1 clock source */
elmot 1:d0dfbce63a89 585 /**
elmot 1:d0dfbce63a89 586 * @}
elmot 1:d0dfbce63a89 587 */
elmot 1:d0dfbce63a89 588
elmot 1:d0dfbce63a89 589 #if defined(DFSDM1_Channel0)
elmot 1:d0dfbce63a89 590 /** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE Peripheral DFSDM clock source selection
elmot 1:d0dfbce63a89 591 * @{
elmot 1:d0dfbce63a89 592 */
elmot 1:d0dfbce63a89 593 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK (uint32_t)(0x00000000) /*!< PCLK used as DFSDM1 clock source */
elmot 1:d0dfbce63a89 594 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (uint32_t)(RCC_CCIPR_DFSDM1SEL) /*!< SYSCLK used as DFSDM1 clock source */
elmot 1:d0dfbce63a89 595 /**
elmot 1:d0dfbce63a89 596 * @}
elmot 1:d0dfbce63a89 597 */
elmot 1:d0dfbce63a89 598 #endif /* DFSDM1_Channel0 */
elmot 1:d0dfbce63a89 599
elmot 1:d0dfbce63a89 600 /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
elmot 1:d0dfbce63a89 601 * @{
elmot 1:d0dfbce63a89 602 */
elmot 1:d0dfbce63a89 603 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
elmot 1:d0dfbce63a89 604 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
elmot 1:d0dfbce63a89 605 #if defined(RCC_CCIPR_USART3SEL)
elmot 1:d0dfbce63a89 606 #define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
elmot 1:d0dfbce63a89 607 #endif /* RCC_CCIPR_USART3SEL */
elmot 1:d0dfbce63a89 608 /**
elmot 1:d0dfbce63a89 609 * @}
elmot 1:d0dfbce63a89 610 */
elmot 1:d0dfbce63a89 611
elmot 1:d0dfbce63a89 612 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
elmot 1:d0dfbce63a89 613 /** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source
elmot 1:d0dfbce63a89 614 * @{
elmot 1:d0dfbce63a89 615 */
elmot 1:d0dfbce63a89 616 #if defined(RCC_CCIPR_UART4SEL)
elmot 1:d0dfbce63a89 617 #define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */
elmot 1:d0dfbce63a89 618 #endif /* RCC_CCIPR_UART4SEL */
elmot 1:d0dfbce63a89 619 #if defined(RCC_CCIPR_UART5SEL)
elmot 1:d0dfbce63a89 620 #define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */
elmot 1:d0dfbce63a89 621 #endif /* RCC_CCIPR_UART5SEL */
elmot 1:d0dfbce63a89 622 /**
elmot 1:d0dfbce63a89 623 * @}
elmot 1:d0dfbce63a89 624 */
elmot 1:d0dfbce63a89 625 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
elmot 1:d0dfbce63a89 626
elmot 1:d0dfbce63a89 627 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
elmot 1:d0dfbce63a89 628 * @{
elmot 1:d0dfbce63a89 629 */
elmot 1:d0dfbce63a89 630 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
elmot 1:d0dfbce63a89 631 /**
elmot 1:d0dfbce63a89 632 * @}
elmot 1:d0dfbce63a89 633 */
elmot 1:d0dfbce63a89 634
elmot 1:d0dfbce63a89 635 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
elmot 1:d0dfbce63a89 636 * @{
elmot 1:d0dfbce63a89 637 */
elmot 1:d0dfbce63a89 638 #define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 Clock source selection */
elmot 1:d0dfbce63a89 639 #if defined(RCC_CCIPR_I2C2SEL)
elmot 1:d0dfbce63a89 640 #define LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL /*!< I2C2 Clock source selection */
elmot 1:d0dfbce63a89 641 #endif /* RCC_CCIPR_I2C2SEL */
elmot 1:d0dfbce63a89 642 #define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL /*!< I2C3 Clock source selection */
elmot 1:d0dfbce63a89 643 /**
elmot 1:d0dfbce63a89 644 * @}
elmot 1:d0dfbce63a89 645 */
elmot 1:d0dfbce63a89 646
elmot 1:d0dfbce63a89 647 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
elmot 1:d0dfbce63a89 648 * @{
elmot 1:d0dfbce63a89 649 */
elmot 1:d0dfbce63a89 650 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */
elmot 1:d0dfbce63a89 651 #define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */
elmot 1:d0dfbce63a89 652 /**
elmot 1:d0dfbce63a89 653 * @}
elmot 1:d0dfbce63a89 654 */
elmot 1:d0dfbce63a89 655
elmot 1:d0dfbce63a89 656 /** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
elmot 1:d0dfbce63a89 657 * @{
elmot 1:d0dfbce63a89 658 */
elmot 1:d0dfbce63a89 659 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */
elmot 1:d0dfbce63a89 660 #if defined(RCC_CCIPR_SAI2SEL)
elmot 1:d0dfbce63a89 661 #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL /*!< SAI2 Clock source selection */
elmot 1:d0dfbce63a89 662 #endif /* RCC_CCIPR_SAI2SEL */
elmot 1:d0dfbce63a89 663 /**
elmot 1:d0dfbce63a89 664 * @}
elmot 1:d0dfbce63a89 665 */
elmot 1:d0dfbce63a89 666
elmot 1:d0dfbce63a89 667 /** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source
elmot 1:d0dfbce63a89 668 * @{
elmot 1:d0dfbce63a89 669 */
elmot 1:d0dfbce63a89 670 #define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< SDMMC1 Clock source selection */
elmot 1:d0dfbce63a89 671 /**
elmot 1:d0dfbce63a89 672 * @}
elmot 1:d0dfbce63a89 673 */
elmot 1:d0dfbce63a89 674
elmot 1:d0dfbce63a89 675 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
elmot 1:d0dfbce63a89 676 * @{
elmot 1:d0dfbce63a89 677 */
elmot 1:d0dfbce63a89 678 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */
elmot 1:d0dfbce63a89 679 /**
elmot 1:d0dfbce63a89 680 * @}
elmot 1:d0dfbce63a89 681 */
elmot 1:d0dfbce63a89 682
elmot 1:d0dfbce63a89 683 #if defined(USB_OTG_FS) || defined(USB)
elmot 1:d0dfbce63a89 684 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
elmot 1:d0dfbce63a89 685 * @{
elmot 1:d0dfbce63a89 686 */
elmot 1:d0dfbce63a89 687 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */
elmot 1:d0dfbce63a89 688 /**
elmot 1:d0dfbce63a89 689 * @}
elmot 1:d0dfbce63a89 690 */
elmot 1:d0dfbce63a89 691
elmot 1:d0dfbce63a89 692 #endif /* USB_OTG_FS || USB */
elmot 1:d0dfbce63a89 693
elmot 1:d0dfbce63a89 694 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
elmot 1:d0dfbce63a89 695 * @{
elmot 1:d0dfbce63a89 696 */
elmot 1:d0dfbce63a89 697 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */
elmot 1:d0dfbce63a89 698 /**
elmot 1:d0dfbce63a89 699 * @}
elmot 1:d0dfbce63a89 700 */
elmot 1:d0dfbce63a89 701
elmot 1:d0dfbce63a89 702 /** @defgroup RCC_LL_EC_SWPMI1 Peripheral SWPMI get clock source
elmot 1:d0dfbce63a89 703 * @{
elmot 1:d0dfbce63a89 704 */
elmot 1:d0dfbce63a89 705 #define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL /*!< SWPMI1 Clock source selection */
elmot 1:d0dfbce63a89 706 /**
elmot 1:d0dfbce63a89 707 * @}
elmot 1:d0dfbce63a89 708 */
elmot 1:d0dfbce63a89 709
elmot 1:d0dfbce63a89 710 #if defined(DFSDM1_Channel0)
elmot 1:d0dfbce63a89 711 /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
elmot 1:d0dfbce63a89 712 * @{
elmot 1:d0dfbce63a89 713 */
elmot 1:d0dfbce63a89 714 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL /*!< DFSDM1 Clock source selection */
elmot 1:d0dfbce63a89 715 /**
elmot 1:d0dfbce63a89 716 * @}
elmot 1:d0dfbce63a89 717 */
elmot 1:d0dfbce63a89 718 #endif /* DFSDM1_Channel0 */
elmot 1:d0dfbce63a89 719
elmot 1:d0dfbce63a89 720 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
elmot 1:d0dfbce63a89 721 * @{
elmot 1:d0dfbce63a89 722 */
elmot 1:d0dfbce63a89 723 #define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000) /*!< No clock used as RTC clock */
elmot 1:d0dfbce63a89 724 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
elmot 1:d0dfbce63a89 725 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
elmot 1:d0dfbce63a89 726 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
elmot 1:d0dfbce63a89 727 /**
elmot 1:d0dfbce63a89 728 * @}
elmot 1:d0dfbce63a89 729 */
elmot 1:d0dfbce63a89 730
elmot 1:d0dfbce63a89 731 /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source
elmot 1:d0dfbce63a89 732 * @{
elmot 1:d0dfbce63a89 733 */
elmot 1:d0dfbce63a89 734 #define LL_RCC_PLLSOURCE_NONE (uint32_t)0x00000000 /*!< No clock */
elmot 1:d0dfbce63a89 735 #define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */
elmot 1:d0dfbce63a89 736 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
elmot 1:d0dfbce63a89 737 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
elmot 1:d0dfbce63a89 738 /**
elmot 1:d0dfbce63a89 739 * @}
elmot 1:d0dfbce63a89 740 */
elmot 1:d0dfbce63a89 741
elmot 1:d0dfbce63a89 742 /** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLSAI1 and PLLSAI2 division factor
elmot 1:d0dfbce63a89 743 * @{
elmot 1:d0dfbce63a89 744 */
elmot 1:d0dfbce63a89 745 #define LL_RCC_PLLM_DIV_1 ((uint32_t)0x00000000) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 1 */
elmot 1:d0dfbce63a89 746 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 2 */
elmot 1:d0dfbce63a89 747 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 3 */
elmot 1:d0dfbce63a89 748 #define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 4 */
elmot 1:d0dfbce63a89 749 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 5 */
elmot 1:d0dfbce63a89 750 #define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 6 */
elmot 1:d0dfbce63a89 751 #define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 7 */
elmot 1:d0dfbce63a89 752 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 8 */
elmot 1:d0dfbce63a89 753 /**
elmot 1:d0dfbce63a89 754 * @}
elmot 1:d0dfbce63a89 755 */
elmot 1:d0dfbce63a89 756
elmot 1:d0dfbce63a89 757 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
elmot 1:d0dfbce63a89 758 * @{
elmot 1:d0dfbce63a89 759 */
elmot 1:d0dfbce63a89 760 #define LL_RCC_PLLR_DIV_2 ((uint32_t)0x00000000) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
elmot 1:d0dfbce63a89 761 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
elmot 1:d0dfbce63a89 762 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
elmot 1:d0dfbce63a89 763 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
elmot 1:d0dfbce63a89 764 /**
elmot 1:d0dfbce63a89 765 * @}
elmot 1:d0dfbce63a89 766 */
elmot 1:d0dfbce63a89 767
elmot 1:d0dfbce63a89 768 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
elmot 1:d0dfbce63a89 769 * @{
elmot 1:d0dfbce63a89 770 */
elmot 1:d0dfbce63a89 771 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 772 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 */
elmot 1:d0dfbce63a89 773 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 3 */
elmot 1:d0dfbce63a89 774 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 */
elmot 1:d0dfbce63a89 775 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 5 */
elmot 1:d0dfbce63a89 776 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 6 */
elmot 1:d0dfbce63a89 777 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 7 */
elmot 1:d0dfbce63a89 778 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 */
elmot 1:d0dfbce63a89 779 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 9 */
elmot 1:d0dfbce63a89 780 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 10 */
elmot 1:d0dfbce63a89 781 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3)) /*!< Main PLL division factor for PLLP output by 11 */
elmot 1:d0dfbce63a89 782 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 12 */
elmot 1:d0dfbce63a89 783 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 13 */
elmot 1:d0dfbce63a89 784 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 14 */
elmot 1:d0dfbce63a89 785 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 15 */
elmot 1:d0dfbce63a89 786 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 */
elmot 1:d0dfbce63a89 787 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 17 */
elmot 1:d0dfbce63a89 788 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 18 */
elmot 1:d0dfbce63a89 789 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_4)) /*!< Main PLL division factor for PLLP output by 19 */
elmot 1:d0dfbce63a89 790 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 20 */
elmot 1:d0dfbce63a89 791 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 21 */
elmot 1:d0dfbce63a89 792 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 22 */
elmot 1:d0dfbce63a89 793 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 23 */
elmot 1:d0dfbce63a89 794 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 24 */
elmot 1:d0dfbce63a89 795 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 25 */
elmot 1:d0dfbce63a89 796 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 26 */
elmot 1:d0dfbce63a89 797 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 27 */
elmot 1:d0dfbce63a89 798 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 28 */
elmot 1:d0dfbce63a89 799 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 29 */
elmot 1:d0dfbce63a89 800 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 30 */
elmot 1:d0dfbce63a89 801 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 31 */
elmot 1:d0dfbce63a89 802 #else
elmot 1:d0dfbce63a89 803 #define LL_RCC_PLLP_DIV_7 ((uint32_t)0x00000000) /*!< Main PLL division factor for PLLP output by 7 */
elmot 1:d0dfbce63a89 804 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP) /*!< Main PLL division factor for PLLP output by 17 */
elmot 1:d0dfbce63a89 805 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 806 /**
elmot 1:d0dfbce63a89 807 * @}
elmot 1:d0dfbce63a89 808 */
elmot 1:d0dfbce63a89 809
elmot 1:d0dfbce63a89 810 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
elmot 1:d0dfbce63a89 811 * @{
elmot 1:d0dfbce63a89 812 */
elmot 1:d0dfbce63a89 813 #define LL_RCC_PLLQ_DIV_2 ((uint32_t)0x00000000) /*!< Main PLL division factor for PLLQ output by 2 */
elmot 1:d0dfbce63a89 814 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
elmot 1:d0dfbce63a89 815 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
elmot 1:d0dfbce63a89 816 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
elmot 1:d0dfbce63a89 817 /**
elmot 1:d0dfbce63a89 818 * @}
elmot 1:d0dfbce63a89 819 */
elmot 1:d0dfbce63a89 820
elmot 1:d0dfbce63a89 821 /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q)
elmot 1:d0dfbce63a89 822 * @{
elmot 1:d0dfbce63a89 823 */
elmot 1:d0dfbce63a89 824 #define LL_RCC_PLLSAI1Q_DIV_2 ((uint32_t)0x00000000) /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */
elmot 1:d0dfbce63a89 825 #define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */
elmot 1:d0dfbce63a89 826 #define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */
elmot 1:d0dfbce63a89 827 #define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q) /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */
elmot 1:d0dfbce63a89 828 /**
elmot 1:d0dfbce63a89 829 * @}
elmot 1:d0dfbce63a89 830 */
elmot 1:d0dfbce63a89 831
elmot 1:d0dfbce63a89 832 /** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLSAI1P)
elmot 1:d0dfbce63a89 833 * @{
elmot 1:d0dfbce63a89 834 */
elmot 1:d0dfbce63a89 835 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 836 #define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 2 */
elmot 1:d0dfbce63a89 837 #define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */
elmot 1:d0dfbce63a89 838 #define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 4 */
elmot 1:d0dfbce63a89 839 #define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */
elmot 1:d0dfbce63a89 840 #define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */
elmot 1:d0dfbce63a89 841 #define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */
elmot 1:d0dfbce63a89 842 #define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 8 */
elmot 1:d0dfbce63a89 843 #define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */
elmot 1:d0dfbce63a89 844 #define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */
elmot 1:d0dfbce63a89 845 #define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3)) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */
elmot 1:d0dfbce63a89 846 #define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */
elmot 1:d0dfbce63a89 847 #define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */
elmot 1:d0dfbce63a89 848 #define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */
elmot 1:d0dfbce63a89 849 #define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */
elmot 1:d0dfbce63a89 850 #define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 16 */
elmot 1:d0dfbce63a89 851 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */
elmot 1:d0dfbce63a89 852 #define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */
elmot 1:d0dfbce63a89 853 #define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4)) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */
elmot 1:d0dfbce63a89 854 #define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */
elmot 1:d0dfbce63a89 855 #define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */
elmot 1:d0dfbce63a89 856 #define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */
elmot 1:d0dfbce63a89 857 #define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */
elmot 1:d0dfbce63a89 858 #define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */
elmot 1:d0dfbce63a89 859 #define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */
elmot 1:d0dfbce63a89 860 #define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */
elmot 1:d0dfbce63a89 861 #define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */
elmot 1:d0dfbce63a89 862 #define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */
elmot 1:d0dfbce63a89 863 #define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */
elmot 1:d0dfbce63a89 864 #define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */
elmot 1:d0dfbce63a89 865 #define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */
elmot 1:d0dfbce63a89 866 #else
elmot 1:d0dfbce63a89 867 #define LL_RCC_PLLSAI1P_DIV_7 ((uint32_t)0x00000000) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */
elmot 1:d0dfbce63a89 868 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */
elmot 1:d0dfbce63a89 869 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 870 /**
elmot 1:d0dfbce63a89 871 * @}
elmot 1:d0dfbce63a89 872 */
elmot 1:d0dfbce63a89 873
elmot 1:d0dfbce63a89 874 /** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLSAI1R)
elmot 1:d0dfbce63a89 875 * @{
elmot 1:d0dfbce63a89 876 */
elmot 1:d0dfbce63a89 877 #define LL_RCC_PLLSAI1R_DIV_2 ((uint32_t)0x00000000) /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */
elmot 1:d0dfbce63a89 878 #define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */
elmot 1:d0dfbce63a89 879 #define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */
elmot 1:d0dfbce63a89 880 #define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R) /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */
elmot 1:d0dfbce63a89 881 /**
elmot 1:d0dfbce63a89 882 * @}
elmot 1:d0dfbce63a89 883 */
elmot 1:d0dfbce63a89 884
elmot 1:d0dfbce63a89 885 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 886 /** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P)
elmot 1:d0dfbce63a89 887 * @{
elmot 1:d0dfbce63a89 888 */
elmot 1:d0dfbce63a89 889 #define LL_RCC_PLLSAI2P_DIV_7 ((uint32_t)0x00000000) /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */
elmot 1:d0dfbce63a89 890 #define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */
elmot 1:d0dfbce63a89 891 /**
elmot 1:d0dfbce63a89 892 * @}
elmot 1:d0dfbce63a89 893 */
elmot 1:d0dfbce63a89 894
elmot 1:d0dfbce63a89 895 /** @defgroup RCC_LL_EC_PLLSAI2R PLLSAI2 division factor (PLLSAI2R)
elmot 1:d0dfbce63a89 896 * @{
elmot 1:d0dfbce63a89 897 */
elmot 1:d0dfbce63a89 898 #define LL_RCC_PLLSAI2R_DIV_2 ((uint32_t)0x00000000) /*!< PLLSAI2 division factor for PLLSAI2R output by 2 */
elmot 1:d0dfbce63a89 899 #define LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0) /*!< PLLSAI2 division factor for PLLSAI2R output by 4 */
elmot 1:d0dfbce63a89 900 #define LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1) /*!< PLLSAI2 division factor for PLLSAI2R output by 6 */
elmot 1:d0dfbce63a89 901 #define LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R) /*!< PLLSAI2 division factor for PLLSAI2R output by 8 */
elmot 1:d0dfbce63a89 902 /**
elmot 1:d0dfbce63a89 903 * @}
elmot 1:d0dfbce63a89 904 */
elmot 1:d0dfbce63a89 905 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 906
elmot 1:d0dfbce63a89 907 /** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection
elmot 1:d0dfbce63a89 908 * @{
elmot 1:d0dfbce63a89 909 */
elmot 1:d0dfbce63a89 910 #define LL_RCC_MSIRANGESEL_STANDBY (uint32_t)0 /*!< MSI Range is provided by MSISRANGE */
elmot 1:d0dfbce63a89 911 #define LL_RCC_MSIRANGESEL_RUN (uint32_t)1 /*!< MSI Range is provided by MSIRANGE */
elmot 1:d0dfbce63a89 912 /**
elmot 1:d0dfbce63a89 913 * @}
elmot 1:d0dfbce63a89 914 */
elmot 1:d0dfbce63a89 915
elmot 1:d0dfbce63a89 916 /** Legacy definitions for compatibility purpose
elmot 1:d0dfbce63a89 917 @cond 0
elmot 1:d0dfbce63a89 918 */
elmot 1:d0dfbce63a89 919 #if defined(DFSDM1_Channel0)
elmot 1:d0dfbce63a89 920 #define LL_RCC_DFSDM_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK
elmot 1:d0dfbce63a89 921 #define LL_RCC_DFSDM_CLKSOURCE_SYSCLK LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 922 #define LL_RCC_DFSDM_CLKSOURCE LL_RCC_DFSDM1_CLKSOURCE
elmot 1:d0dfbce63a89 923 #endif /* DFSDM1_Channel0 */
elmot 1:d0dfbce63a89 924 /**
elmot 1:d0dfbce63a89 925 @endcond
elmot 1:d0dfbce63a89 926 */
elmot 1:d0dfbce63a89 927
elmot 1:d0dfbce63a89 928 /**
elmot 1:d0dfbce63a89 929 * @}
elmot 1:d0dfbce63a89 930 */
elmot 1:d0dfbce63a89 931
elmot 1:d0dfbce63a89 932 /* Exported macro ------------------------------------------------------------*/
elmot 1:d0dfbce63a89 933 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
elmot 1:d0dfbce63a89 934 * @{
elmot 1:d0dfbce63a89 935 */
elmot 1:d0dfbce63a89 936
elmot 1:d0dfbce63a89 937 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
elmot 1:d0dfbce63a89 938 * @{
elmot 1:d0dfbce63a89 939 */
elmot 1:d0dfbce63a89 940
elmot 1:d0dfbce63a89 941 /**
elmot 1:d0dfbce63a89 942 * @brief Write a value in RCC register
elmot 1:d0dfbce63a89 943 * @param __REG__ Register to be written
elmot 1:d0dfbce63a89 944 * @param __VALUE__ Value to be written in the register
elmot 1:d0dfbce63a89 945 * @retval None
elmot 1:d0dfbce63a89 946 */
elmot 1:d0dfbce63a89 947 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
elmot 1:d0dfbce63a89 948
elmot 1:d0dfbce63a89 949 /**
elmot 1:d0dfbce63a89 950 * @brief Read a value in RCC register
elmot 1:d0dfbce63a89 951 * @param __REG__ Register to be read
elmot 1:d0dfbce63a89 952 * @retval Register value
elmot 1:d0dfbce63a89 953 */
elmot 1:d0dfbce63a89 954 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
elmot 1:d0dfbce63a89 955 /**
elmot 1:d0dfbce63a89 956 * @}
elmot 1:d0dfbce63a89 957 */
elmot 1:d0dfbce63a89 958
elmot 1:d0dfbce63a89 959 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
elmot 1:d0dfbce63a89 960 * @{
elmot 1:d0dfbce63a89 961 */
elmot 1:d0dfbce63a89 962
elmot 1:d0dfbce63a89 963 /**
elmot 1:d0dfbce63a89 964 * @brief Helper macro to calculate the PLLCLK frequency on system domain
elmot 1:d0dfbce63a89 965 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
elmot 1:d0dfbce63a89 966 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
elmot 1:d0dfbce63a89 967 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
elmot 1:d0dfbce63a89 968 * @param __PLLM__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 969 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 970 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 971 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 972 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 973 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 974 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 975 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 976 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 977 * @param __PLLN__ Between 8 and 86
elmot 1:d0dfbce63a89 978 * @param __PLLR__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 979 * @arg @ref LL_RCC_PLLR_DIV_2
elmot 1:d0dfbce63a89 980 * @arg @ref LL_RCC_PLLR_DIV_4
elmot 1:d0dfbce63a89 981 * @arg @ref LL_RCC_PLLR_DIV_6
elmot 1:d0dfbce63a89 982 * @arg @ref LL_RCC_PLLR_DIV_8
elmot 1:d0dfbce63a89 983 * @retval PLL clock frequency (in Hz)
elmot 1:d0dfbce63a89 984 */
elmot 1:d0dfbce63a89 985 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \
elmot 1:d0dfbce63a89 986 ((((__PLLR__) >> RCC_POSITION_PLLR ) + 1 ) * 2))
elmot 1:d0dfbce63a89 987
elmot 1:d0dfbce63a89 988 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 989 /**
elmot 1:d0dfbce63a89 990 * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
elmot 1:d0dfbce63a89 991 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
elmot 1:d0dfbce63a89 992 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
elmot 1:d0dfbce63a89 993 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
elmot 1:d0dfbce63a89 994 * @param __PLLM__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 995 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 996 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 997 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 998 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 999 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 1000 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 1001 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 1002 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 1003 * @param __PLLN__ Between 8 and 86
elmot 1:d0dfbce63a89 1004 * @param __PLLP__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1005 * @arg @ref LL_RCC_PLLP_DIV_2
elmot 1:d0dfbce63a89 1006 * @arg @ref LL_RCC_PLLP_DIV_3
elmot 1:d0dfbce63a89 1007 * @arg @ref LL_RCC_PLLP_DIV_4
elmot 1:d0dfbce63a89 1008 * @arg @ref LL_RCC_PLLP_DIV_5
elmot 1:d0dfbce63a89 1009 * @arg @ref LL_RCC_PLLP_DIV_6
elmot 1:d0dfbce63a89 1010 * @arg @ref LL_RCC_PLLP_DIV_7
elmot 1:d0dfbce63a89 1011 * @arg @ref LL_RCC_PLLP_DIV_8
elmot 1:d0dfbce63a89 1012 * @arg @ref LL_RCC_PLLP_DIV_9
elmot 1:d0dfbce63a89 1013 * @arg @ref LL_RCC_PLLP_DIV_10
elmot 1:d0dfbce63a89 1014 * @arg @ref LL_RCC_PLLP_DIV_11
elmot 1:d0dfbce63a89 1015 * @arg @ref LL_RCC_PLLP_DIV_12
elmot 1:d0dfbce63a89 1016 * @arg @ref LL_RCC_PLLP_DIV_13
elmot 1:d0dfbce63a89 1017 * @arg @ref LL_RCC_PLLP_DIV_14
elmot 1:d0dfbce63a89 1018 * @arg @ref LL_RCC_PLLP_DIV_15
elmot 1:d0dfbce63a89 1019 * @arg @ref LL_RCC_PLLP_DIV_16
elmot 1:d0dfbce63a89 1020 * @arg @ref LL_RCC_PLLP_DIV_17
elmot 1:d0dfbce63a89 1021 * @arg @ref LL_RCC_PLLP_DIV_18
elmot 1:d0dfbce63a89 1022 * @arg @ref LL_RCC_PLLP_DIV_19
elmot 1:d0dfbce63a89 1023 * @arg @ref LL_RCC_PLLP_DIV_20
elmot 1:d0dfbce63a89 1024 * @arg @ref LL_RCC_PLLP_DIV_21
elmot 1:d0dfbce63a89 1025 * @arg @ref LL_RCC_PLLP_DIV_22
elmot 1:d0dfbce63a89 1026 * @arg @ref LL_RCC_PLLP_DIV_23
elmot 1:d0dfbce63a89 1027 * @arg @ref LL_RCC_PLLP_DIV_24
elmot 1:d0dfbce63a89 1028 * @arg @ref LL_RCC_PLLP_DIV_25
elmot 1:d0dfbce63a89 1029 * @arg @ref LL_RCC_PLLP_DIV_26
elmot 1:d0dfbce63a89 1030 * @arg @ref LL_RCC_PLLP_DIV_27
elmot 1:d0dfbce63a89 1031 * @arg @ref LL_RCC_PLLP_DIV_28
elmot 1:d0dfbce63a89 1032 * @arg @ref LL_RCC_PLLP_DIV_29
elmot 1:d0dfbce63a89 1033 * @arg @ref LL_RCC_PLLP_DIV_30
elmot 1:d0dfbce63a89 1034 * @arg @ref LL_RCC_PLLP_DIV_31
elmot 1:d0dfbce63a89 1035 * @retval PLL clock frequency (in Hz)
elmot 1:d0dfbce63a89 1036 */
elmot 1:d0dfbce63a89 1037 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \
elmot 1:d0dfbce63a89 1038 ((__PLLP__) >> RCC_POSITION_PLLP))
elmot 1:d0dfbce63a89 1039
elmot 1:d0dfbce63a89 1040 #else
elmot 1:d0dfbce63a89 1041 /**
elmot 1:d0dfbce63a89 1042 * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
elmot 1:d0dfbce63a89 1043 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
elmot 1:d0dfbce63a89 1044 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
elmot 1:d0dfbce63a89 1045 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
elmot 1:d0dfbce63a89 1046 * @param __PLLM__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1047 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 1048 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 1049 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 1050 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 1051 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 1052 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 1053 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 1054 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 1055 * @param __PLLN__ Between 8 and 86
elmot 1:d0dfbce63a89 1056 * @param __PLLP__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1057 * @arg @ref LL_RCC_PLLP_DIV_7
elmot 1:d0dfbce63a89 1058 * @arg @ref LL_RCC_PLLP_DIV_17
elmot 1:d0dfbce63a89 1059 * @retval PLL clock frequency (in Hz)
elmot 1:d0dfbce63a89 1060 */
elmot 1:d0dfbce63a89 1061 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \
elmot 1:d0dfbce63a89 1062 (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7 : 17))
elmot 1:d0dfbce63a89 1063
elmot 1:d0dfbce63a89 1064 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 1065 /**
elmot 1:d0dfbce63a89 1066 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
elmot 1:d0dfbce63a89 1067 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
elmot 1:d0dfbce63a89 1068 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
elmot 1:d0dfbce63a89 1069 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
elmot 1:d0dfbce63a89 1070 * @param __PLLM__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1071 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 1072 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 1073 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 1074 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 1075 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 1076 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 1077 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 1078 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 1079 * @param __PLLN__ Between 8 and 86
elmot 1:d0dfbce63a89 1080 * @param __PLLQ__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1081 * @arg @ref LL_RCC_PLLQ_DIV_2
elmot 1:d0dfbce63a89 1082 * @arg @ref LL_RCC_PLLQ_DIV_4
elmot 1:d0dfbce63a89 1083 * @arg @ref LL_RCC_PLLQ_DIV_6
elmot 1:d0dfbce63a89 1084 * @arg @ref LL_RCC_PLLQ_DIV_8
elmot 1:d0dfbce63a89 1085 * @retval PLL clock frequency (in Hz)
elmot 1:d0dfbce63a89 1086 */
elmot 1:d0dfbce63a89 1087 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \
elmot 1:d0dfbce63a89 1088 ((((__PLLQ__) >> RCC_POSITION_PLLQ) + 1) << 1))
elmot 1:d0dfbce63a89 1089
elmot 1:d0dfbce63a89 1090 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 1091 /**
elmot 1:d0dfbce63a89 1092 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
elmot 1:d0dfbce63a89 1093 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
elmot 1:d0dfbce63a89 1094 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
elmot 1:d0dfbce63a89 1095 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
elmot 1:d0dfbce63a89 1096 * @param __PLLM__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1097 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 1098 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 1099 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 1100 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 1101 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 1102 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 1103 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 1104 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 1105 * @param __PLLSAI1N__ Between 8 and 86
elmot 1:d0dfbce63a89 1106 * @param __PLLSAI1P__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1107 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
elmot 1:d0dfbce63a89 1108 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
elmot 1:d0dfbce63a89 1109 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
elmot 1:d0dfbce63a89 1110 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
elmot 1:d0dfbce63a89 1111 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
elmot 1:d0dfbce63a89 1112 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
elmot 1:d0dfbce63a89 1113 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
elmot 1:d0dfbce63a89 1114 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
elmot 1:d0dfbce63a89 1115 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
elmot 1:d0dfbce63a89 1116 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
elmot 1:d0dfbce63a89 1117 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
elmot 1:d0dfbce63a89 1118 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
elmot 1:d0dfbce63a89 1119 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
elmot 1:d0dfbce63a89 1120 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
elmot 1:d0dfbce63a89 1121 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
elmot 1:d0dfbce63a89 1122 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
elmot 1:d0dfbce63a89 1123 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
elmot 1:d0dfbce63a89 1124 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
elmot 1:d0dfbce63a89 1125 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
elmot 1:d0dfbce63a89 1126 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
elmot 1:d0dfbce63a89 1127 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
elmot 1:d0dfbce63a89 1128 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
elmot 1:d0dfbce63a89 1129 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
elmot 1:d0dfbce63a89 1130 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
elmot 1:d0dfbce63a89 1131 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
elmot 1:d0dfbce63a89 1132 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
elmot 1:d0dfbce63a89 1133 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
elmot 1:d0dfbce63a89 1134 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
elmot 1:d0dfbce63a89 1135 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
elmot 1:d0dfbce63a89 1136 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
elmot 1:d0dfbce63a89 1137 * @retval PLLSAI1 clock frequency (in Hz)
elmot 1:d0dfbce63a89 1138 */
elmot 1:d0dfbce63a89 1139 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \
elmot 1:d0dfbce63a89 1140 ((__PLLSAI1P__) >> RCC_POSITION_PLLSAI1P))
elmot 1:d0dfbce63a89 1141 #else
elmot 1:d0dfbce63a89 1142 /**
elmot 1:d0dfbce63a89 1143 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
elmot 1:d0dfbce63a89 1144 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
elmot 1:d0dfbce63a89 1145 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
elmot 1:d0dfbce63a89 1146 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
elmot 1:d0dfbce63a89 1147 * @param __PLLM__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1148 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 1149 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 1150 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 1151 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 1152 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 1153 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 1154 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 1155 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 1156 * @param __PLLSAI1N__ Between 8 and 86
elmot 1:d0dfbce63a89 1157 * @param __PLLSAI1P__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1158 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
elmot 1:d0dfbce63a89 1159 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
elmot 1:d0dfbce63a89 1160 * @retval PLLSAI1 clock frequency (in Hz)
elmot 1:d0dfbce63a89 1161 */
elmot 1:d0dfbce63a89 1162 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \
elmot 1:d0dfbce63a89 1163 (((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7 : 17))
elmot 1:d0dfbce63a89 1164 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 1165
elmot 1:d0dfbce63a89 1166 /**
elmot 1:d0dfbce63a89 1167 * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
elmot 1:d0dfbce63a89 1168 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
elmot 1:d0dfbce63a89 1169 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
elmot 1:d0dfbce63a89 1170 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
elmot 1:d0dfbce63a89 1171 * @param __PLLM__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1172 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 1173 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 1174 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 1175 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 1176 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 1177 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 1178 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 1179 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 1180 * @param __PLLSAI1N__ Between 8 and 86
elmot 1:d0dfbce63a89 1181 * @param __PLLSAI1Q__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1182 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
elmot 1:d0dfbce63a89 1183 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
elmot 1:d0dfbce63a89 1184 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
elmot 1:d0dfbce63a89 1185 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
elmot 1:d0dfbce63a89 1186 * @retval PLLSAI1 clock frequency (in Hz)
elmot 1:d0dfbce63a89 1187 */
elmot 1:d0dfbce63a89 1188 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \
elmot 1:d0dfbce63a89 1189 ((((__PLLSAI1Q__) >> RCC_POSITION_PLLSAI1Q) + 1) << 1))
elmot 1:d0dfbce63a89 1190
elmot 1:d0dfbce63a89 1191 /**
elmot 1:d0dfbce63a89 1192 * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
elmot 1:d0dfbce63a89 1193 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
elmot 1:d0dfbce63a89 1194 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
elmot 1:d0dfbce63a89 1195 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
elmot 1:d0dfbce63a89 1196 * @param __PLLM__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1197 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 1198 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 1199 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 1200 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 1201 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 1202 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 1203 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 1204 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 1205 * @param __PLLSAI1N__ Between 8 and 86
elmot 1:d0dfbce63a89 1206 * @param __PLLSAI1R__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1207 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
elmot 1:d0dfbce63a89 1208 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
elmot 1:d0dfbce63a89 1209 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
elmot 1:d0dfbce63a89 1210 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
elmot 1:d0dfbce63a89 1211 * @retval PLLSAI1 clock frequency (in Hz)
elmot 1:d0dfbce63a89 1212 */
elmot 1:d0dfbce63a89 1213 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \
elmot 1:d0dfbce63a89 1214 ((((__PLLSAI1R__) >> RCC_POSITION_PLLSAI1R ) + 1 ) * 2))
elmot 1:d0dfbce63a89 1215
elmot 1:d0dfbce63a89 1216 /**
elmot 1:d0dfbce63a89 1217 * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
elmot 1:d0dfbce63a89 1218 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
elmot 1:d0dfbce63a89 1219 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
elmot 1:d0dfbce63a89 1220 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
elmot 1:d0dfbce63a89 1221 * @param __PLLM__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1222 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 1223 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 1224 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 1225 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 1226 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 1227 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 1228 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 1229 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 1230 * @param __PLLSAI2N__ Between 8 and 86
elmot 1:d0dfbce63a89 1231 * @param __PLLSAI2P__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1232 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
elmot 1:d0dfbce63a89 1233 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
elmot 1:d0dfbce63a89 1234 * @retval PLLSAI2 clock frequency (in Hz)
elmot 1:d0dfbce63a89 1235 */
elmot 1:d0dfbce63a89 1236 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI2N__) / \
elmot 1:d0dfbce63a89 1237 (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7 : 17))
elmot 1:d0dfbce63a89 1238
elmot 1:d0dfbce63a89 1239 /**
elmot 1:d0dfbce63a89 1240 * @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain
elmot 1:d0dfbce63a89 1241 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
elmot 1:d0dfbce63a89 1242 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR ());
elmot 1:d0dfbce63a89 1243 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
elmot 1:d0dfbce63a89 1244 * @param __PLLM__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1245 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 1246 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 1247 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 1248 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 1249 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 1250 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 1251 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 1252 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 1253 * @param __PLLSAI2N__ Between 8 and 86
elmot 1:d0dfbce63a89 1254 * @param __PLLSAI2R__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1255 * @arg @ref LL_RCC_PLLSAI2R_DIV_2
elmot 1:d0dfbce63a89 1256 * @arg @ref LL_RCC_PLLSAI2R_DIV_4
elmot 1:d0dfbce63a89 1257 * @arg @ref LL_RCC_PLLSAI2R_DIV_6
elmot 1:d0dfbce63a89 1258 * @arg @ref LL_RCC_PLLSAI2R_DIV_8
elmot 1:d0dfbce63a89 1259 * @retval PLLSAI2 clock frequency (in Hz)
elmot 1:d0dfbce63a89 1260 */
elmot 1:d0dfbce63a89 1261 #define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI2N__) / \
elmot 1:d0dfbce63a89 1262 ((((__PLLSAI2R__) >> RCC_POSITION_PLLSAI2R ) + 1 ) * 2))
elmot 1:d0dfbce63a89 1263
elmot 1:d0dfbce63a89 1264 /**
elmot 1:d0dfbce63a89 1265 * @brief Helper macro to calculate the HCLK frequency
elmot 1:d0dfbce63a89 1266 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
elmot 1:d0dfbce63a89 1267 * @param __AHBPRESCALER__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1268 * @arg @ref LL_RCC_SYSCLK_DIV_1
elmot 1:d0dfbce63a89 1269 * @arg @ref LL_RCC_SYSCLK_DIV_2
elmot 1:d0dfbce63a89 1270 * @arg @ref LL_RCC_SYSCLK_DIV_4
elmot 1:d0dfbce63a89 1271 * @arg @ref LL_RCC_SYSCLK_DIV_8
elmot 1:d0dfbce63a89 1272 * @arg @ref LL_RCC_SYSCLK_DIV_16
elmot 1:d0dfbce63a89 1273 * @arg @ref LL_RCC_SYSCLK_DIV_64
elmot 1:d0dfbce63a89 1274 * @arg @ref LL_RCC_SYSCLK_DIV_128
elmot 1:d0dfbce63a89 1275 * @arg @ref LL_RCC_SYSCLK_DIV_256
elmot 1:d0dfbce63a89 1276 * @arg @ref LL_RCC_SYSCLK_DIV_512
elmot 1:d0dfbce63a89 1277 * @retval HCLK clock frequency (in Hz)
elmot 1:d0dfbce63a89 1278 */
elmot 1:d0dfbce63a89 1279 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE])
elmot 1:d0dfbce63a89 1280
elmot 1:d0dfbce63a89 1281 /**
elmot 1:d0dfbce63a89 1282 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
elmot 1:d0dfbce63a89 1283 * @param __HCLKFREQ__ HCLK frequency
elmot 1:d0dfbce63a89 1284 * @param __APB1PRESCALER__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1285 * @arg @ref LL_RCC_APB1_DIV_1
elmot 1:d0dfbce63a89 1286 * @arg @ref LL_RCC_APB1_DIV_2
elmot 1:d0dfbce63a89 1287 * @arg @ref LL_RCC_APB1_DIV_4
elmot 1:d0dfbce63a89 1288 * @arg @ref LL_RCC_APB1_DIV_8
elmot 1:d0dfbce63a89 1289 * @arg @ref LL_RCC_APB1_DIV_16
elmot 1:d0dfbce63a89 1290 * @retval PCLK1 clock frequency (in Hz)
elmot 1:d0dfbce63a89 1291 */
elmot 1:d0dfbce63a89 1292 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1])
elmot 1:d0dfbce63a89 1293
elmot 1:d0dfbce63a89 1294 /**
elmot 1:d0dfbce63a89 1295 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
elmot 1:d0dfbce63a89 1296 * @param __HCLKFREQ__ HCLK frequency
elmot 1:d0dfbce63a89 1297 * @param __APB2PRESCALER__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1298 * @arg @ref LL_RCC_APB2_DIV_1
elmot 1:d0dfbce63a89 1299 * @arg @ref LL_RCC_APB2_DIV_2
elmot 1:d0dfbce63a89 1300 * @arg @ref LL_RCC_APB2_DIV_4
elmot 1:d0dfbce63a89 1301 * @arg @ref LL_RCC_APB2_DIV_8
elmot 1:d0dfbce63a89 1302 * @arg @ref LL_RCC_APB2_DIV_16
elmot 1:d0dfbce63a89 1303 * @retval PCLK2 clock frequency (in Hz)
elmot 1:d0dfbce63a89 1304 */
elmot 1:d0dfbce63a89 1305 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB2PRESCALER__) >> RCC_POSITION_PPRE2])
elmot 1:d0dfbce63a89 1306
elmot 1:d0dfbce63a89 1307 /**
elmot 1:d0dfbce63a89 1308 * @brief Helper macro to calculate the MSI frequency (in Hz)
elmot 1:d0dfbce63a89 1309 * @note: __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect
elmot 1:d0dfbce63a89 1310 * @note: if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
elmot 1:d0dfbce63a89 1311 * __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby
elmot 1:d0dfbce63a89 1312 * else by LL_RCC_MSI_GetRange
elmot 1:d0dfbce63a89 1313 * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
elmot 1:d0dfbce63a89 1314 * (LL_RCC_MSI_IsEnabledRangeSelect()?
elmot 1:d0dfbce63a89 1315 * LL_RCC_MSI_GetRange():
elmot 1:d0dfbce63a89 1316 * LL_RCC_MSI_GetRangeAfterStandby()))
elmot 1:d0dfbce63a89 1317 * @param __MSISEL__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1318 * @arg @ref LL_RCC_MSIRANGESEL_STANDBY
elmot 1:d0dfbce63a89 1319 * @arg @ref LL_RCC_MSIRANGESEL_RUN
elmot 1:d0dfbce63a89 1320 * @param __MSIRANGE__ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1321 * @arg @ref LL_RCC_MSIRANGE_0
elmot 1:d0dfbce63a89 1322 * @arg @ref LL_RCC_MSIRANGE_1
elmot 1:d0dfbce63a89 1323 * @arg @ref LL_RCC_MSIRANGE_2
elmot 1:d0dfbce63a89 1324 * @arg @ref LL_RCC_MSIRANGE_3
elmot 1:d0dfbce63a89 1325 * @arg @ref LL_RCC_MSIRANGE_4
elmot 1:d0dfbce63a89 1326 * @arg @ref LL_RCC_MSIRANGE_5
elmot 1:d0dfbce63a89 1327 * @arg @ref LL_RCC_MSIRANGE_6
elmot 1:d0dfbce63a89 1328 * @arg @ref LL_RCC_MSIRANGE_7
elmot 1:d0dfbce63a89 1329 * @arg @ref LL_RCC_MSIRANGE_8
elmot 1:d0dfbce63a89 1330 * @arg @ref LL_RCC_MSIRANGE_9
elmot 1:d0dfbce63a89 1331 * @arg @ref LL_RCC_MSIRANGE_10
elmot 1:d0dfbce63a89 1332 * @arg @ref LL_RCC_MSIRANGE_11
elmot 1:d0dfbce63a89 1333 * @arg @ref LL_RCC_MSISRANGE_4
elmot 1:d0dfbce63a89 1334 * @arg @ref LL_RCC_MSISRANGE_5
elmot 1:d0dfbce63a89 1335 * @arg @ref LL_RCC_MSISRANGE_6
elmot 1:d0dfbce63a89 1336 * @arg @ref LL_RCC_MSISRANGE_7
elmot 1:d0dfbce63a89 1337 * @retval MSI clock frequency (in Hz)
elmot 1:d0dfbce63a89 1338 */
elmot 1:d0dfbce63a89 1339 #define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
elmot 1:d0dfbce63a89 1340 (MSIRangeTable[(__MSIRANGE__) >> 8]) : \
elmot 1:d0dfbce63a89 1341 (MSIRangeTable[(__MSIRANGE__) >> 4]))
elmot 1:d0dfbce63a89 1342
elmot 1:d0dfbce63a89 1343 /**
elmot 1:d0dfbce63a89 1344 * @}
elmot 1:d0dfbce63a89 1345 */
elmot 1:d0dfbce63a89 1346
elmot 1:d0dfbce63a89 1347 /**
elmot 1:d0dfbce63a89 1348 * @}
elmot 1:d0dfbce63a89 1349 */
elmot 1:d0dfbce63a89 1350
elmot 1:d0dfbce63a89 1351 /* Exported functions --------------------------------------------------------*/
elmot 1:d0dfbce63a89 1352 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
elmot 1:d0dfbce63a89 1353 * @{
elmot 1:d0dfbce63a89 1354 */
elmot 1:d0dfbce63a89 1355
elmot 1:d0dfbce63a89 1356 /** @defgroup RCC_LL_EF_HSE HSE
elmot 1:d0dfbce63a89 1357 * @{
elmot 1:d0dfbce63a89 1358 */
elmot 1:d0dfbce63a89 1359
elmot 1:d0dfbce63a89 1360 /**
elmot 1:d0dfbce63a89 1361 * @brief Enable the Clock Security System.
elmot 1:d0dfbce63a89 1362 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
elmot 1:d0dfbce63a89 1363 * @retval None
elmot 1:d0dfbce63a89 1364 */
elmot 1:d0dfbce63a89 1365 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
elmot 1:d0dfbce63a89 1366 {
elmot 1:d0dfbce63a89 1367 SET_BIT(RCC->CR, RCC_CR_CSSON);
elmot 1:d0dfbce63a89 1368 }
elmot 1:d0dfbce63a89 1369
elmot 1:d0dfbce63a89 1370 /**
elmot 1:d0dfbce63a89 1371 * @brief Enable HSE external oscillator (HSE Bypass)
elmot 1:d0dfbce63a89 1372 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
elmot 1:d0dfbce63a89 1373 * @retval None
elmot 1:d0dfbce63a89 1374 */
elmot 1:d0dfbce63a89 1375 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
elmot 1:d0dfbce63a89 1376 {
elmot 1:d0dfbce63a89 1377 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
elmot 1:d0dfbce63a89 1378 }
elmot 1:d0dfbce63a89 1379
elmot 1:d0dfbce63a89 1380 /**
elmot 1:d0dfbce63a89 1381 * @brief Disable HSE external oscillator (HSE Bypass)
elmot 1:d0dfbce63a89 1382 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
elmot 1:d0dfbce63a89 1383 * @retval None
elmot 1:d0dfbce63a89 1384 */
elmot 1:d0dfbce63a89 1385 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
elmot 1:d0dfbce63a89 1386 {
elmot 1:d0dfbce63a89 1387 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
elmot 1:d0dfbce63a89 1388 }
elmot 1:d0dfbce63a89 1389
elmot 1:d0dfbce63a89 1390 /**
elmot 1:d0dfbce63a89 1391 * @brief Enable HSE crystal oscillator (HSE ON)
elmot 1:d0dfbce63a89 1392 * @rmtoll CR HSEON LL_RCC_HSE_Enable
elmot 1:d0dfbce63a89 1393 * @retval None
elmot 1:d0dfbce63a89 1394 */
elmot 1:d0dfbce63a89 1395 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
elmot 1:d0dfbce63a89 1396 {
elmot 1:d0dfbce63a89 1397 SET_BIT(RCC->CR, RCC_CR_HSEON);
elmot 1:d0dfbce63a89 1398 }
elmot 1:d0dfbce63a89 1399
elmot 1:d0dfbce63a89 1400 /**
elmot 1:d0dfbce63a89 1401 * @brief Disable HSE crystal oscillator (HSE ON)
elmot 1:d0dfbce63a89 1402 * @rmtoll CR HSEON LL_RCC_HSE_Disable
elmot 1:d0dfbce63a89 1403 * @retval None
elmot 1:d0dfbce63a89 1404 */
elmot 1:d0dfbce63a89 1405 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
elmot 1:d0dfbce63a89 1406 {
elmot 1:d0dfbce63a89 1407 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
elmot 1:d0dfbce63a89 1408 }
elmot 1:d0dfbce63a89 1409
elmot 1:d0dfbce63a89 1410 /**
elmot 1:d0dfbce63a89 1411 * @brief Check if HSE oscillator Ready
elmot 1:d0dfbce63a89 1412 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
elmot 1:d0dfbce63a89 1413 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1414 */
elmot 1:d0dfbce63a89 1415 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
elmot 1:d0dfbce63a89 1416 {
elmot 1:d0dfbce63a89 1417 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
elmot 1:d0dfbce63a89 1418 }
elmot 1:d0dfbce63a89 1419
elmot 1:d0dfbce63a89 1420 /**
elmot 1:d0dfbce63a89 1421 * @}
elmot 1:d0dfbce63a89 1422 */
elmot 1:d0dfbce63a89 1423
elmot 1:d0dfbce63a89 1424 /** @defgroup RCC_LL_EF_HSI HSI
elmot 1:d0dfbce63a89 1425 * @{
elmot 1:d0dfbce63a89 1426 */
elmot 1:d0dfbce63a89 1427
elmot 1:d0dfbce63a89 1428 /**
elmot 1:d0dfbce63a89 1429 * @brief Enable HSI even in stop mode
elmot 1:d0dfbce63a89 1430 * @note HSI oscillator is forced ON even in Stop mode
elmot 1:d0dfbce63a89 1431 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
elmot 1:d0dfbce63a89 1432 * @retval None
elmot 1:d0dfbce63a89 1433 */
elmot 1:d0dfbce63a89 1434 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
elmot 1:d0dfbce63a89 1435 {
elmot 1:d0dfbce63a89 1436 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
elmot 1:d0dfbce63a89 1437 }
elmot 1:d0dfbce63a89 1438
elmot 1:d0dfbce63a89 1439 /**
elmot 1:d0dfbce63a89 1440 * @brief Disable HSI in stop mode
elmot 1:d0dfbce63a89 1441 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
elmot 1:d0dfbce63a89 1442 * @retval None
elmot 1:d0dfbce63a89 1443 */
elmot 1:d0dfbce63a89 1444 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
elmot 1:d0dfbce63a89 1445 {
elmot 1:d0dfbce63a89 1446 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
elmot 1:d0dfbce63a89 1447 }
elmot 1:d0dfbce63a89 1448
elmot 1:d0dfbce63a89 1449 /**
elmot 1:d0dfbce63a89 1450 * @brief Enable HSI oscillator
elmot 1:d0dfbce63a89 1451 * @rmtoll CR HSION LL_RCC_HSI_Enable
elmot 1:d0dfbce63a89 1452 * @retval None
elmot 1:d0dfbce63a89 1453 */
elmot 1:d0dfbce63a89 1454 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
elmot 1:d0dfbce63a89 1455 {
elmot 1:d0dfbce63a89 1456 SET_BIT(RCC->CR, RCC_CR_HSION);
elmot 1:d0dfbce63a89 1457 }
elmot 1:d0dfbce63a89 1458
elmot 1:d0dfbce63a89 1459 /**
elmot 1:d0dfbce63a89 1460 * @brief Disable HSI oscillator
elmot 1:d0dfbce63a89 1461 * @rmtoll CR HSION LL_RCC_HSI_Disable
elmot 1:d0dfbce63a89 1462 * @retval None
elmot 1:d0dfbce63a89 1463 */
elmot 1:d0dfbce63a89 1464 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
elmot 1:d0dfbce63a89 1465 {
elmot 1:d0dfbce63a89 1466 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
elmot 1:d0dfbce63a89 1467 }
elmot 1:d0dfbce63a89 1468
elmot 1:d0dfbce63a89 1469 /**
elmot 1:d0dfbce63a89 1470 * @brief Check if HSI clock is ready
elmot 1:d0dfbce63a89 1471 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
elmot 1:d0dfbce63a89 1472 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1473 */
elmot 1:d0dfbce63a89 1474 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
elmot 1:d0dfbce63a89 1475 {
elmot 1:d0dfbce63a89 1476 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
elmot 1:d0dfbce63a89 1477 }
elmot 1:d0dfbce63a89 1478
elmot 1:d0dfbce63a89 1479 /**
elmot 1:d0dfbce63a89 1480 * @brief Enable HSI Automatic from stop mode
elmot 1:d0dfbce63a89 1481 * @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
elmot 1:d0dfbce63a89 1482 * @retval None
elmot 1:d0dfbce63a89 1483 */
elmot 1:d0dfbce63a89 1484 __STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
elmot 1:d0dfbce63a89 1485 {
elmot 1:d0dfbce63a89 1486 SET_BIT(RCC->CR, RCC_CR_HSIASFS);
elmot 1:d0dfbce63a89 1487 }
elmot 1:d0dfbce63a89 1488
elmot 1:d0dfbce63a89 1489 /**
elmot 1:d0dfbce63a89 1490 * @brief Disable HSI Automatic from stop mode
elmot 1:d0dfbce63a89 1491 * @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
elmot 1:d0dfbce63a89 1492 * @retval None
elmot 1:d0dfbce63a89 1493 */
elmot 1:d0dfbce63a89 1494 __STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
elmot 1:d0dfbce63a89 1495 {
elmot 1:d0dfbce63a89 1496 CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
elmot 1:d0dfbce63a89 1497 }
elmot 1:d0dfbce63a89 1498 /**
elmot 1:d0dfbce63a89 1499 * @brief Get HSI Calibration value
elmot 1:d0dfbce63a89 1500 * @note When HSITRIM is written, HSICAL is updated with the sum of
elmot 1:d0dfbce63a89 1501 * HSITRIM and the factory trim value
elmot 1:d0dfbce63a89 1502 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
elmot 1:d0dfbce63a89 1503 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
elmot 1:d0dfbce63a89 1504 */
elmot 1:d0dfbce63a89 1505 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
elmot 1:d0dfbce63a89 1506 {
elmot 1:d0dfbce63a89 1507 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_POSITION_HSICAL);
elmot 1:d0dfbce63a89 1508 }
elmot 1:d0dfbce63a89 1509
elmot 1:d0dfbce63a89 1510 /**
elmot 1:d0dfbce63a89 1511 * @brief Set HSI Calibration trimming
elmot 1:d0dfbce63a89 1512 * @note user-programmable trimming value that is added to the HSICAL
elmot 1:d0dfbce63a89 1513 * @note Default value is 16, which, when added to the HSICAL value,
elmot 1:d0dfbce63a89 1514 * should trim the HSI to 16 MHz +/- 1 %
elmot 1:d0dfbce63a89 1515 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
elmot 1:d0dfbce63a89 1516 * @param Value Between Min_Data = 0 and Max_Data = 31
elmot 1:d0dfbce63a89 1517 * @retval None
elmot 1:d0dfbce63a89 1518 */
elmot 1:d0dfbce63a89 1519 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
elmot 1:d0dfbce63a89 1520 {
elmot 1:d0dfbce63a89 1521 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_POSITION_HSITRIM);
elmot 1:d0dfbce63a89 1522 }
elmot 1:d0dfbce63a89 1523
elmot 1:d0dfbce63a89 1524 /**
elmot 1:d0dfbce63a89 1525 * @brief Get HSI Calibration trimming
elmot 1:d0dfbce63a89 1526 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
elmot 1:d0dfbce63a89 1527 * @retval Between Min_Data = 0 and Max_Data = 31
elmot 1:d0dfbce63a89 1528 */
elmot 1:d0dfbce63a89 1529 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
elmot 1:d0dfbce63a89 1530 {
elmot 1:d0dfbce63a89 1531 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_POSITION_HSITRIM);
elmot 1:d0dfbce63a89 1532 }
elmot 1:d0dfbce63a89 1533
elmot 1:d0dfbce63a89 1534 /**
elmot 1:d0dfbce63a89 1535 * @}
elmot 1:d0dfbce63a89 1536 */
elmot 1:d0dfbce63a89 1537
elmot 1:d0dfbce63a89 1538 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 1539 /** @defgroup RCC_LL_EF_HSI48 HSI48
elmot 1:d0dfbce63a89 1540 * @{
elmot 1:d0dfbce63a89 1541 */
elmot 1:d0dfbce63a89 1542
elmot 1:d0dfbce63a89 1543 /**
elmot 1:d0dfbce63a89 1544 * @brief Enable HSI48
elmot 1:d0dfbce63a89 1545 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
elmot 1:d0dfbce63a89 1546 * @retval None
elmot 1:d0dfbce63a89 1547 */
elmot 1:d0dfbce63a89 1548 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
elmot 1:d0dfbce63a89 1549 {
elmot 1:d0dfbce63a89 1550 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
elmot 1:d0dfbce63a89 1551 }
elmot 1:d0dfbce63a89 1552
elmot 1:d0dfbce63a89 1553 /**
elmot 1:d0dfbce63a89 1554 * @brief Disable HSI48
elmot 1:d0dfbce63a89 1555 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
elmot 1:d0dfbce63a89 1556 * @retval None
elmot 1:d0dfbce63a89 1557 */
elmot 1:d0dfbce63a89 1558 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
elmot 1:d0dfbce63a89 1559 {
elmot 1:d0dfbce63a89 1560 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
elmot 1:d0dfbce63a89 1561 }
elmot 1:d0dfbce63a89 1562
elmot 1:d0dfbce63a89 1563 /**
elmot 1:d0dfbce63a89 1564 * @brief Check if HSI48 oscillator Ready
elmot 1:d0dfbce63a89 1565 * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
elmot 1:d0dfbce63a89 1566 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1567 */
elmot 1:d0dfbce63a89 1568 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
elmot 1:d0dfbce63a89 1569 {
elmot 1:d0dfbce63a89 1570 return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY));
elmot 1:d0dfbce63a89 1571 }
elmot 1:d0dfbce63a89 1572
elmot 1:d0dfbce63a89 1573 /**
elmot 1:d0dfbce63a89 1574 * @brief Get HSI48 Calibration value
elmot 1:d0dfbce63a89 1575 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
elmot 1:d0dfbce63a89 1576 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
elmot 1:d0dfbce63a89 1577 */
elmot 1:d0dfbce63a89 1578 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
elmot 1:d0dfbce63a89 1579 {
elmot 1:d0dfbce63a89 1580 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_POSITION_HSI48CAL);
elmot 1:d0dfbce63a89 1581 }
elmot 1:d0dfbce63a89 1582
elmot 1:d0dfbce63a89 1583 /**
elmot 1:d0dfbce63a89 1584 * @}
elmot 1:d0dfbce63a89 1585 */
elmot 1:d0dfbce63a89 1586 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 1587
elmot 1:d0dfbce63a89 1588 /** @defgroup RCC_LL_EF_LSE LSE
elmot 1:d0dfbce63a89 1589 * @{
elmot 1:d0dfbce63a89 1590 */
elmot 1:d0dfbce63a89 1591
elmot 1:d0dfbce63a89 1592 /**
elmot 1:d0dfbce63a89 1593 * @brief Enable Low Speed External (LSE) crystal.
elmot 1:d0dfbce63a89 1594 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
elmot 1:d0dfbce63a89 1595 * @retval None
elmot 1:d0dfbce63a89 1596 */
elmot 1:d0dfbce63a89 1597 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
elmot 1:d0dfbce63a89 1598 {
elmot 1:d0dfbce63a89 1599 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
elmot 1:d0dfbce63a89 1600 }
elmot 1:d0dfbce63a89 1601
elmot 1:d0dfbce63a89 1602 /**
elmot 1:d0dfbce63a89 1603 * @brief Disable Low Speed External (LSE) crystal.
elmot 1:d0dfbce63a89 1604 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
elmot 1:d0dfbce63a89 1605 * @retval None
elmot 1:d0dfbce63a89 1606 */
elmot 1:d0dfbce63a89 1607 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
elmot 1:d0dfbce63a89 1608 {
elmot 1:d0dfbce63a89 1609 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
elmot 1:d0dfbce63a89 1610 }
elmot 1:d0dfbce63a89 1611
elmot 1:d0dfbce63a89 1612 /**
elmot 1:d0dfbce63a89 1613 * @brief Enable external clock source (LSE bypass).
elmot 1:d0dfbce63a89 1614 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
elmot 1:d0dfbce63a89 1615 * @retval None
elmot 1:d0dfbce63a89 1616 */
elmot 1:d0dfbce63a89 1617 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
elmot 1:d0dfbce63a89 1618 {
elmot 1:d0dfbce63a89 1619 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
elmot 1:d0dfbce63a89 1620 }
elmot 1:d0dfbce63a89 1621
elmot 1:d0dfbce63a89 1622 /**
elmot 1:d0dfbce63a89 1623 * @brief Disable external clock source (LSE bypass).
elmot 1:d0dfbce63a89 1624 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
elmot 1:d0dfbce63a89 1625 * @retval None
elmot 1:d0dfbce63a89 1626 */
elmot 1:d0dfbce63a89 1627 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
elmot 1:d0dfbce63a89 1628 {
elmot 1:d0dfbce63a89 1629 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
elmot 1:d0dfbce63a89 1630 }
elmot 1:d0dfbce63a89 1631
elmot 1:d0dfbce63a89 1632 /**
elmot 1:d0dfbce63a89 1633 * @brief Set LSE oscillator drive capability
elmot 1:d0dfbce63a89 1634 * @note The oscillator is in Xtal mode when it is not in bypass mode.
elmot 1:d0dfbce63a89 1635 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
elmot 1:d0dfbce63a89 1636 * @param LSEDrive This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1637 * @arg @ref LL_RCC_LSEDRIVE_LOW
elmot 1:d0dfbce63a89 1638 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
elmot 1:d0dfbce63a89 1639 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
elmot 1:d0dfbce63a89 1640 * @arg @ref LL_RCC_LSEDRIVE_HIGH
elmot 1:d0dfbce63a89 1641 * @retval None
elmot 1:d0dfbce63a89 1642 */
elmot 1:d0dfbce63a89 1643 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
elmot 1:d0dfbce63a89 1644 {
elmot 1:d0dfbce63a89 1645 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
elmot 1:d0dfbce63a89 1646 }
elmot 1:d0dfbce63a89 1647
elmot 1:d0dfbce63a89 1648 /**
elmot 1:d0dfbce63a89 1649 * @brief Get LSE oscillator drive capability
elmot 1:d0dfbce63a89 1650 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
elmot 1:d0dfbce63a89 1651 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 1652 * @arg @ref LL_RCC_LSEDRIVE_LOW
elmot 1:d0dfbce63a89 1653 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
elmot 1:d0dfbce63a89 1654 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
elmot 1:d0dfbce63a89 1655 * @arg @ref LL_RCC_LSEDRIVE_HIGH
elmot 1:d0dfbce63a89 1656 */
elmot 1:d0dfbce63a89 1657 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
elmot 1:d0dfbce63a89 1658 {
elmot 1:d0dfbce63a89 1659 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
elmot 1:d0dfbce63a89 1660 }
elmot 1:d0dfbce63a89 1661
elmot 1:d0dfbce63a89 1662 /**
elmot 1:d0dfbce63a89 1663 * @brief Enable Clock security system on LSE.
elmot 1:d0dfbce63a89 1664 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
elmot 1:d0dfbce63a89 1665 * @retval None
elmot 1:d0dfbce63a89 1666 */
elmot 1:d0dfbce63a89 1667 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
elmot 1:d0dfbce63a89 1668 {
elmot 1:d0dfbce63a89 1669 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
elmot 1:d0dfbce63a89 1670 }
elmot 1:d0dfbce63a89 1671
elmot 1:d0dfbce63a89 1672 /**
elmot 1:d0dfbce63a89 1673 * @brief Disable Clock security system on LSE.
elmot 1:d0dfbce63a89 1674 * @note Clock security system can be disabled only after a LSE
elmot 1:d0dfbce63a89 1675 * failure detection. In that case it MUST be disabled by software.
elmot 1:d0dfbce63a89 1676 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
elmot 1:d0dfbce63a89 1677 * @retval None
elmot 1:d0dfbce63a89 1678 */
elmot 1:d0dfbce63a89 1679 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
elmot 1:d0dfbce63a89 1680 {
elmot 1:d0dfbce63a89 1681 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
elmot 1:d0dfbce63a89 1682 }
elmot 1:d0dfbce63a89 1683
elmot 1:d0dfbce63a89 1684 /**
elmot 1:d0dfbce63a89 1685 * @brief Check if LSE oscillator Ready
elmot 1:d0dfbce63a89 1686 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
elmot 1:d0dfbce63a89 1687 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1688 */
elmot 1:d0dfbce63a89 1689 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
elmot 1:d0dfbce63a89 1690 {
elmot 1:d0dfbce63a89 1691 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
elmot 1:d0dfbce63a89 1692 }
elmot 1:d0dfbce63a89 1693
elmot 1:d0dfbce63a89 1694 /**
elmot 1:d0dfbce63a89 1695 * @brief Check if CSS on LSE failure Detection
elmot 1:d0dfbce63a89 1696 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
elmot 1:d0dfbce63a89 1697 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1698 */
elmot 1:d0dfbce63a89 1699 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
elmot 1:d0dfbce63a89 1700 {
elmot 1:d0dfbce63a89 1701 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD));
elmot 1:d0dfbce63a89 1702 }
elmot 1:d0dfbce63a89 1703
elmot 1:d0dfbce63a89 1704 /**
elmot 1:d0dfbce63a89 1705 * @}
elmot 1:d0dfbce63a89 1706 */
elmot 1:d0dfbce63a89 1707
elmot 1:d0dfbce63a89 1708 /** @defgroup RCC_LL_EF_LSI LSI
elmot 1:d0dfbce63a89 1709 * @{
elmot 1:d0dfbce63a89 1710 */
elmot 1:d0dfbce63a89 1711
elmot 1:d0dfbce63a89 1712 /**
elmot 1:d0dfbce63a89 1713 * @brief Enable LSI Oscillator
elmot 1:d0dfbce63a89 1714 * @rmtoll CSR LSION LL_RCC_LSI_Enable
elmot 1:d0dfbce63a89 1715 * @retval None
elmot 1:d0dfbce63a89 1716 */
elmot 1:d0dfbce63a89 1717 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
elmot 1:d0dfbce63a89 1718 {
elmot 1:d0dfbce63a89 1719 SET_BIT(RCC->CSR, RCC_CSR_LSION);
elmot 1:d0dfbce63a89 1720 }
elmot 1:d0dfbce63a89 1721
elmot 1:d0dfbce63a89 1722 /**
elmot 1:d0dfbce63a89 1723 * @brief Disable LSI Oscillator
elmot 1:d0dfbce63a89 1724 * @rmtoll CSR LSION LL_RCC_LSI_Disable
elmot 1:d0dfbce63a89 1725 * @retval None
elmot 1:d0dfbce63a89 1726 */
elmot 1:d0dfbce63a89 1727 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
elmot 1:d0dfbce63a89 1728 {
elmot 1:d0dfbce63a89 1729 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
elmot 1:d0dfbce63a89 1730 }
elmot 1:d0dfbce63a89 1731
elmot 1:d0dfbce63a89 1732 /**
elmot 1:d0dfbce63a89 1733 * @brief Check if LSI is Ready
elmot 1:d0dfbce63a89 1734 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
elmot 1:d0dfbce63a89 1735 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1736 */
elmot 1:d0dfbce63a89 1737 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
elmot 1:d0dfbce63a89 1738 {
elmot 1:d0dfbce63a89 1739 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
elmot 1:d0dfbce63a89 1740 }
elmot 1:d0dfbce63a89 1741
elmot 1:d0dfbce63a89 1742 /**
elmot 1:d0dfbce63a89 1743 * @}
elmot 1:d0dfbce63a89 1744 */
elmot 1:d0dfbce63a89 1745
elmot 1:d0dfbce63a89 1746 /** @defgroup RCC_LL_EF_MSI MSI
elmot 1:d0dfbce63a89 1747 * @{
elmot 1:d0dfbce63a89 1748 */
elmot 1:d0dfbce63a89 1749
elmot 1:d0dfbce63a89 1750 /**
elmot 1:d0dfbce63a89 1751 * @brief Enable MSI oscillator
elmot 1:d0dfbce63a89 1752 * @rmtoll CR MSION LL_RCC_MSI_Enable
elmot 1:d0dfbce63a89 1753 * @retval None
elmot 1:d0dfbce63a89 1754 */
elmot 1:d0dfbce63a89 1755 __STATIC_INLINE void LL_RCC_MSI_Enable(void)
elmot 1:d0dfbce63a89 1756 {
elmot 1:d0dfbce63a89 1757 SET_BIT(RCC->CR, RCC_CR_MSION);
elmot 1:d0dfbce63a89 1758 }
elmot 1:d0dfbce63a89 1759
elmot 1:d0dfbce63a89 1760 /**
elmot 1:d0dfbce63a89 1761 * @brief Disable MSI oscillator
elmot 1:d0dfbce63a89 1762 * @rmtoll CR MSION LL_RCC_MSI_Disable
elmot 1:d0dfbce63a89 1763 * @retval None
elmot 1:d0dfbce63a89 1764 */
elmot 1:d0dfbce63a89 1765 __STATIC_INLINE void LL_RCC_MSI_Disable(void)
elmot 1:d0dfbce63a89 1766 {
elmot 1:d0dfbce63a89 1767 CLEAR_BIT(RCC->CR, RCC_CR_MSION);
elmot 1:d0dfbce63a89 1768 }
elmot 1:d0dfbce63a89 1769
elmot 1:d0dfbce63a89 1770 /**
elmot 1:d0dfbce63a89 1771 * @brief Check if MSI oscillator Ready
elmot 1:d0dfbce63a89 1772 * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
elmot 1:d0dfbce63a89 1773 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1774 */
elmot 1:d0dfbce63a89 1775 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
elmot 1:d0dfbce63a89 1776 {
elmot 1:d0dfbce63a89 1777 return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY));
elmot 1:d0dfbce63a89 1778 }
elmot 1:d0dfbce63a89 1779
elmot 1:d0dfbce63a89 1780 /**
elmot 1:d0dfbce63a89 1781 * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
elmot 1:d0dfbce63a89 1782 * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
elmot 1:d0dfbce63a89 1783 * and ready (LSERDY set by hardware)
elmot 1:d0dfbce63a89 1784 * @note hardware protection to avoid enabling MSIPLLEN if LSE is not
elmot 1:d0dfbce63a89 1785 * ready
elmot 1:d0dfbce63a89 1786 * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
elmot 1:d0dfbce63a89 1787 * @retval None
elmot 1:d0dfbce63a89 1788 */
elmot 1:d0dfbce63a89 1789 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
elmot 1:d0dfbce63a89 1790 {
elmot 1:d0dfbce63a89 1791 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
elmot 1:d0dfbce63a89 1792 }
elmot 1:d0dfbce63a89 1793
elmot 1:d0dfbce63a89 1794 /**
elmot 1:d0dfbce63a89 1795 * @brief Disable MSI-PLL mode
elmot 1:d0dfbce63a89 1796 * @note cleared by hardware when LSE is disabled (LSEON = 0) or when
elmot 1:d0dfbce63a89 1797 * the Clock Security System on LSE detects a LSE failure
elmot 1:d0dfbce63a89 1798 * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
elmot 1:d0dfbce63a89 1799 * @retval None
elmot 1:d0dfbce63a89 1800 */
elmot 1:d0dfbce63a89 1801 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
elmot 1:d0dfbce63a89 1802 {
elmot 1:d0dfbce63a89 1803 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
elmot 1:d0dfbce63a89 1804 }
elmot 1:d0dfbce63a89 1805
elmot 1:d0dfbce63a89 1806 /**
elmot 1:d0dfbce63a89 1807 * @brief Enable MSI clock range selection with MSIRANGE register
elmot 1:d0dfbce63a89 1808 * @note Write 0 has no effect. After a standby or a reset
elmot 1:d0dfbce63a89 1809 * MSIRGSEL is at 0 and the MSI range value is provided by
elmot 1:d0dfbce63a89 1810 * MSISRANGE
elmot 1:d0dfbce63a89 1811 * @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
elmot 1:d0dfbce63a89 1812 * @retval None
elmot 1:d0dfbce63a89 1813 */
elmot 1:d0dfbce63a89 1814 __STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
elmot 1:d0dfbce63a89 1815 {
elmot 1:d0dfbce63a89 1816 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
elmot 1:d0dfbce63a89 1817 }
elmot 1:d0dfbce63a89 1818
elmot 1:d0dfbce63a89 1819 /**
elmot 1:d0dfbce63a89 1820 * @brief Check if MSI clock range is selected with MSIRANGE register
elmot 1:d0dfbce63a89 1821 * @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect
elmot 1:d0dfbce63a89 1822 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1823 */
elmot 1:d0dfbce63a89 1824 __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
elmot 1:d0dfbce63a89 1825 {
elmot 1:d0dfbce63a89 1826 return (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL));
elmot 1:d0dfbce63a89 1827 }
elmot 1:d0dfbce63a89 1828
elmot 1:d0dfbce63a89 1829 /**
elmot 1:d0dfbce63a89 1830 * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
elmot 1:d0dfbce63a89 1831 * @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange
elmot 1:d0dfbce63a89 1832 * @param Range This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1833 * @arg @ref LL_RCC_MSIRANGE_0
elmot 1:d0dfbce63a89 1834 * @arg @ref LL_RCC_MSIRANGE_1
elmot 1:d0dfbce63a89 1835 * @arg @ref LL_RCC_MSIRANGE_2
elmot 1:d0dfbce63a89 1836 * @arg @ref LL_RCC_MSIRANGE_3
elmot 1:d0dfbce63a89 1837 * @arg @ref LL_RCC_MSIRANGE_4
elmot 1:d0dfbce63a89 1838 * @arg @ref LL_RCC_MSIRANGE_5
elmot 1:d0dfbce63a89 1839 * @arg @ref LL_RCC_MSIRANGE_6
elmot 1:d0dfbce63a89 1840 * @arg @ref LL_RCC_MSIRANGE_7
elmot 1:d0dfbce63a89 1841 * @arg @ref LL_RCC_MSIRANGE_8
elmot 1:d0dfbce63a89 1842 * @arg @ref LL_RCC_MSIRANGE_9
elmot 1:d0dfbce63a89 1843 * @arg @ref LL_RCC_MSIRANGE_10
elmot 1:d0dfbce63a89 1844 * @arg @ref LL_RCC_MSIRANGE_11
elmot 1:d0dfbce63a89 1845 * @retval None
elmot 1:d0dfbce63a89 1846 */
elmot 1:d0dfbce63a89 1847 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
elmot 1:d0dfbce63a89 1848 {
elmot 1:d0dfbce63a89 1849 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
elmot 1:d0dfbce63a89 1850 }
elmot 1:d0dfbce63a89 1851
elmot 1:d0dfbce63a89 1852 /**
elmot 1:d0dfbce63a89 1853 * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
elmot 1:d0dfbce63a89 1854 * @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange
elmot 1:d0dfbce63a89 1855 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 1856 * @arg @ref LL_RCC_MSIRANGE_0
elmot 1:d0dfbce63a89 1857 * @arg @ref LL_RCC_MSIRANGE_1
elmot 1:d0dfbce63a89 1858 * @arg @ref LL_RCC_MSIRANGE_2
elmot 1:d0dfbce63a89 1859 * @arg @ref LL_RCC_MSIRANGE_3
elmot 1:d0dfbce63a89 1860 * @arg @ref LL_RCC_MSIRANGE_4
elmot 1:d0dfbce63a89 1861 * @arg @ref LL_RCC_MSIRANGE_5
elmot 1:d0dfbce63a89 1862 * @arg @ref LL_RCC_MSIRANGE_6
elmot 1:d0dfbce63a89 1863 * @arg @ref LL_RCC_MSIRANGE_7
elmot 1:d0dfbce63a89 1864 * @arg @ref LL_RCC_MSIRANGE_8
elmot 1:d0dfbce63a89 1865 * @arg @ref LL_RCC_MSIRANGE_9
elmot 1:d0dfbce63a89 1866 * @arg @ref LL_RCC_MSIRANGE_10
elmot 1:d0dfbce63a89 1867 * @arg @ref LL_RCC_MSIRANGE_11
elmot 1:d0dfbce63a89 1868 */
elmot 1:d0dfbce63a89 1869 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
elmot 1:d0dfbce63a89 1870 {
elmot 1:d0dfbce63a89 1871 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
elmot 1:d0dfbce63a89 1872 }
elmot 1:d0dfbce63a89 1873
elmot 1:d0dfbce63a89 1874 /**
elmot 1:d0dfbce63a89 1875 * @brief Configure MSI range used after standby
elmot 1:d0dfbce63a89 1876 * @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby
elmot 1:d0dfbce63a89 1877 * @param Range This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1878 * @arg @ref LL_RCC_MSISRANGE_4
elmot 1:d0dfbce63a89 1879 * @arg @ref LL_RCC_MSISRANGE_5
elmot 1:d0dfbce63a89 1880 * @arg @ref LL_RCC_MSISRANGE_6
elmot 1:d0dfbce63a89 1881 * @arg @ref LL_RCC_MSISRANGE_7
elmot 1:d0dfbce63a89 1882 * @retval None
elmot 1:d0dfbce63a89 1883 */
elmot 1:d0dfbce63a89 1884 __STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
elmot 1:d0dfbce63a89 1885 {
elmot 1:d0dfbce63a89 1886 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);
elmot 1:d0dfbce63a89 1887 }
elmot 1:d0dfbce63a89 1888
elmot 1:d0dfbce63a89 1889 /**
elmot 1:d0dfbce63a89 1890 * @brief Get MSI range used after standby
elmot 1:d0dfbce63a89 1891 * @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby
elmot 1:d0dfbce63a89 1892 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 1893 * @arg @ref LL_RCC_MSISRANGE_4
elmot 1:d0dfbce63a89 1894 * @arg @ref LL_RCC_MSISRANGE_5
elmot 1:d0dfbce63a89 1895 * @arg @ref LL_RCC_MSISRANGE_6
elmot 1:d0dfbce63a89 1896 * @arg @ref LL_RCC_MSISRANGE_7
elmot 1:d0dfbce63a89 1897 */
elmot 1:d0dfbce63a89 1898 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
elmot 1:d0dfbce63a89 1899 {
elmot 1:d0dfbce63a89 1900 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
elmot 1:d0dfbce63a89 1901 }
elmot 1:d0dfbce63a89 1902
elmot 1:d0dfbce63a89 1903 /**
elmot 1:d0dfbce63a89 1904 * @brief Get MSI Calibration value
elmot 1:d0dfbce63a89 1905 * @note When MSITRIM is written, MSICAL is updated with the sum of
elmot 1:d0dfbce63a89 1906 * MSITRIM and the factory trim value
elmot 1:d0dfbce63a89 1907 * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
elmot 1:d0dfbce63a89 1908 * @retval Between Min_Data = 0 and Max_Data = 255
elmot 1:d0dfbce63a89 1909 */
elmot 1:d0dfbce63a89 1910 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
elmot 1:d0dfbce63a89 1911 {
elmot 1:d0dfbce63a89 1912 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_POSITION_MSICAL);
elmot 1:d0dfbce63a89 1913 }
elmot 1:d0dfbce63a89 1914
elmot 1:d0dfbce63a89 1915 /**
elmot 1:d0dfbce63a89 1916 * @brief Set MSI Calibration trimming
elmot 1:d0dfbce63a89 1917 * @note user-programmable trimming value that is added to the MSICAL
elmot 1:d0dfbce63a89 1918 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
elmot 1:d0dfbce63a89 1919 * @param Value Between Min_Data = 0 and Max_Data = 255
elmot 1:d0dfbce63a89 1920 * @retval None
elmot 1:d0dfbce63a89 1921 */
elmot 1:d0dfbce63a89 1922 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
elmot 1:d0dfbce63a89 1923 {
elmot 1:d0dfbce63a89 1924 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_POSITION_MSITRIM);
elmot 1:d0dfbce63a89 1925 }
elmot 1:d0dfbce63a89 1926
elmot 1:d0dfbce63a89 1927 /**
elmot 1:d0dfbce63a89 1928 * @brief Get MSI Calibration trimming
elmot 1:d0dfbce63a89 1929 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
elmot 1:d0dfbce63a89 1930 * @retval Between 0 and 255
elmot 1:d0dfbce63a89 1931 */
elmot 1:d0dfbce63a89 1932 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
elmot 1:d0dfbce63a89 1933 {
elmot 1:d0dfbce63a89 1934 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_POSITION_MSITRIM);
elmot 1:d0dfbce63a89 1935 }
elmot 1:d0dfbce63a89 1936
elmot 1:d0dfbce63a89 1937 /**
elmot 1:d0dfbce63a89 1938 * @}
elmot 1:d0dfbce63a89 1939 */
elmot 1:d0dfbce63a89 1940
elmot 1:d0dfbce63a89 1941 /** @defgroup RCC_LL_EF_LSCO LSCO
elmot 1:d0dfbce63a89 1942 * @{
elmot 1:d0dfbce63a89 1943 */
elmot 1:d0dfbce63a89 1944
elmot 1:d0dfbce63a89 1945 /**
elmot 1:d0dfbce63a89 1946 * @brief Enable Low speed clock
elmot 1:d0dfbce63a89 1947 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
elmot 1:d0dfbce63a89 1948 * @retval None
elmot 1:d0dfbce63a89 1949 */
elmot 1:d0dfbce63a89 1950 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
elmot 1:d0dfbce63a89 1951 {
elmot 1:d0dfbce63a89 1952 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
elmot 1:d0dfbce63a89 1953 }
elmot 1:d0dfbce63a89 1954
elmot 1:d0dfbce63a89 1955 /**
elmot 1:d0dfbce63a89 1956 * @brief Disable Low speed clock
elmot 1:d0dfbce63a89 1957 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
elmot 1:d0dfbce63a89 1958 * @retval None
elmot 1:d0dfbce63a89 1959 */
elmot 1:d0dfbce63a89 1960 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
elmot 1:d0dfbce63a89 1961 {
elmot 1:d0dfbce63a89 1962 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
elmot 1:d0dfbce63a89 1963 }
elmot 1:d0dfbce63a89 1964
elmot 1:d0dfbce63a89 1965 /**
elmot 1:d0dfbce63a89 1966 * @brief Configure Low speed clock selection
elmot 1:d0dfbce63a89 1967 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
elmot 1:d0dfbce63a89 1968 * @param Source This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1969 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
elmot 1:d0dfbce63a89 1970 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 1971 * @retval None
elmot 1:d0dfbce63a89 1972 */
elmot 1:d0dfbce63a89 1973 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
elmot 1:d0dfbce63a89 1974 {
elmot 1:d0dfbce63a89 1975 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
elmot 1:d0dfbce63a89 1976 }
elmot 1:d0dfbce63a89 1977
elmot 1:d0dfbce63a89 1978 /**
elmot 1:d0dfbce63a89 1979 * @brief Get Low speed clock selection
elmot 1:d0dfbce63a89 1980 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
elmot 1:d0dfbce63a89 1981 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 1982 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
elmot 1:d0dfbce63a89 1983 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 1984 */
elmot 1:d0dfbce63a89 1985 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
elmot 1:d0dfbce63a89 1986 {
elmot 1:d0dfbce63a89 1987 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
elmot 1:d0dfbce63a89 1988 }
elmot 1:d0dfbce63a89 1989
elmot 1:d0dfbce63a89 1990 /**
elmot 1:d0dfbce63a89 1991 * @}
elmot 1:d0dfbce63a89 1992 */
elmot 1:d0dfbce63a89 1993
elmot 1:d0dfbce63a89 1994 /** @defgroup RCC_LL_EF_System System
elmot 1:d0dfbce63a89 1995 * @{
elmot 1:d0dfbce63a89 1996 */
elmot 1:d0dfbce63a89 1997
elmot 1:d0dfbce63a89 1998 /**
elmot 1:d0dfbce63a89 1999 * @brief Configure the system clock source
elmot 1:d0dfbce63a89 2000 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
elmot 1:d0dfbce63a89 2001 * @param Source This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2002 * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
elmot 1:d0dfbce63a89 2003 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2004 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
elmot 1:d0dfbce63a89 2005 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
elmot 1:d0dfbce63a89 2006 * @retval None
elmot 1:d0dfbce63a89 2007 */
elmot 1:d0dfbce63a89 2008 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
elmot 1:d0dfbce63a89 2009 {
elmot 1:d0dfbce63a89 2010 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
elmot 1:d0dfbce63a89 2011 }
elmot 1:d0dfbce63a89 2012
elmot 1:d0dfbce63a89 2013 /**
elmot 1:d0dfbce63a89 2014 * @brief Get the system clock source
elmot 1:d0dfbce63a89 2015 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
elmot 1:d0dfbce63a89 2016 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2017 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
elmot 1:d0dfbce63a89 2018 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
elmot 1:d0dfbce63a89 2019 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
elmot 1:d0dfbce63a89 2020 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
elmot 1:d0dfbce63a89 2021 */
elmot 1:d0dfbce63a89 2022 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
elmot 1:d0dfbce63a89 2023 {
elmot 1:d0dfbce63a89 2024 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
elmot 1:d0dfbce63a89 2025 }
elmot 1:d0dfbce63a89 2026
elmot 1:d0dfbce63a89 2027 /**
elmot 1:d0dfbce63a89 2028 * @brief Set AHB prescaler
elmot 1:d0dfbce63a89 2029 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
elmot 1:d0dfbce63a89 2030 * @param Prescaler This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2031 * @arg @ref LL_RCC_SYSCLK_DIV_1
elmot 1:d0dfbce63a89 2032 * @arg @ref LL_RCC_SYSCLK_DIV_2
elmot 1:d0dfbce63a89 2033 * @arg @ref LL_RCC_SYSCLK_DIV_4
elmot 1:d0dfbce63a89 2034 * @arg @ref LL_RCC_SYSCLK_DIV_8
elmot 1:d0dfbce63a89 2035 * @arg @ref LL_RCC_SYSCLK_DIV_16
elmot 1:d0dfbce63a89 2036 * @arg @ref LL_RCC_SYSCLK_DIV_64
elmot 1:d0dfbce63a89 2037 * @arg @ref LL_RCC_SYSCLK_DIV_128
elmot 1:d0dfbce63a89 2038 * @arg @ref LL_RCC_SYSCLK_DIV_256
elmot 1:d0dfbce63a89 2039 * @arg @ref LL_RCC_SYSCLK_DIV_512
elmot 1:d0dfbce63a89 2040 * @retval None
elmot 1:d0dfbce63a89 2041 */
elmot 1:d0dfbce63a89 2042 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
elmot 1:d0dfbce63a89 2043 {
elmot 1:d0dfbce63a89 2044 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
elmot 1:d0dfbce63a89 2045 }
elmot 1:d0dfbce63a89 2046
elmot 1:d0dfbce63a89 2047 /**
elmot 1:d0dfbce63a89 2048 * @brief Set APB1 prescaler
elmot 1:d0dfbce63a89 2049 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
elmot 1:d0dfbce63a89 2050 * @param Prescaler This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2051 * @arg @ref LL_RCC_APB1_DIV_1
elmot 1:d0dfbce63a89 2052 * @arg @ref LL_RCC_APB1_DIV_2
elmot 1:d0dfbce63a89 2053 * @arg @ref LL_RCC_APB1_DIV_4
elmot 1:d0dfbce63a89 2054 * @arg @ref LL_RCC_APB1_DIV_8
elmot 1:d0dfbce63a89 2055 * @arg @ref LL_RCC_APB1_DIV_16
elmot 1:d0dfbce63a89 2056 * @retval None
elmot 1:d0dfbce63a89 2057 */
elmot 1:d0dfbce63a89 2058 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
elmot 1:d0dfbce63a89 2059 {
elmot 1:d0dfbce63a89 2060 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
elmot 1:d0dfbce63a89 2061 }
elmot 1:d0dfbce63a89 2062
elmot 1:d0dfbce63a89 2063 /**
elmot 1:d0dfbce63a89 2064 * @brief Set APB2 prescaler
elmot 1:d0dfbce63a89 2065 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
elmot 1:d0dfbce63a89 2066 * @param Prescaler This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2067 * @arg @ref LL_RCC_APB2_DIV_1
elmot 1:d0dfbce63a89 2068 * @arg @ref LL_RCC_APB2_DIV_2
elmot 1:d0dfbce63a89 2069 * @arg @ref LL_RCC_APB2_DIV_4
elmot 1:d0dfbce63a89 2070 * @arg @ref LL_RCC_APB2_DIV_8
elmot 1:d0dfbce63a89 2071 * @arg @ref LL_RCC_APB2_DIV_16
elmot 1:d0dfbce63a89 2072 * @retval None
elmot 1:d0dfbce63a89 2073 */
elmot 1:d0dfbce63a89 2074 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
elmot 1:d0dfbce63a89 2075 {
elmot 1:d0dfbce63a89 2076 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
elmot 1:d0dfbce63a89 2077 }
elmot 1:d0dfbce63a89 2078
elmot 1:d0dfbce63a89 2079 /**
elmot 1:d0dfbce63a89 2080 * @brief Get AHB prescaler
elmot 1:d0dfbce63a89 2081 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
elmot 1:d0dfbce63a89 2082 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2083 * @arg @ref LL_RCC_SYSCLK_DIV_1
elmot 1:d0dfbce63a89 2084 * @arg @ref LL_RCC_SYSCLK_DIV_2
elmot 1:d0dfbce63a89 2085 * @arg @ref LL_RCC_SYSCLK_DIV_4
elmot 1:d0dfbce63a89 2086 * @arg @ref LL_RCC_SYSCLK_DIV_8
elmot 1:d0dfbce63a89 2087 * @arg @ref LL_RCC_SYSCLK_DIV_16
elmot 1:d0dfbce63a89 2088 * @arg @ref LL_RCC_SYSCLK_DIV_64
elmot 1:d0dfbce63a89 2089 * @arg @ref LL_RCC_SYSCLK_DIV_128
elmot 1:d0dfbce63a89 2090 * @arg @ref LL_RCC_SYSCLK_DIV_256
elmot 1:d0dfbce63a89 2091 * @arg @ref LL_RCC_SYSCLK_DIV_512
elmot 1:d0dfbce63a89 2092 */
elmot 1:d0dfbce63a89 2093 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
elmot 1:d0dfbce63a89 2094 {
elmot 1:d0dfbce63a89 2095 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
elmot 1:d0dfbce63a89 2096 }
elmot 1:d0dfbce63a89 2097
elmot 1:d0dfbce63a89 2098 /**
elmot 1:d0dfbce63a89 2099 * @brief Get APB1 prescaler
elmot 1:d0dfbce63a89 2100 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
elmot 1:d0dfbce63a89 2101 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2102 * @arg @ref LL_RCC_APB1_DIV_1
elmot 1:d0dfbce63a89 2103 * @arg @ref LL_RCC_APB1_DIV_2
elmot 1:d0dfbce63a89 2104 * @arg @ref LL_RCC_APB1_DIV_4
elmot 1:d0dfbce63a89 2105 * @arg @ref LL_RCC_APB1_DIV_8
elmot 1:d0dfbce63a89 2106 * @arg @ref LL_RCC_APB1_DIV_16
elmot 1:d0dfbce63a89 2107 */
elmot 1:d0dfbce63a89 2108 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
elmot 1:d0dfbce63a89 2109 {
elmot 1:d0dfbce63a89 2110 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
elmot 1:d0dfbce63a89 2111 }
elmot 1:d0dfbce63a89 2112
elmot 1:d0dfbce63a89 2113 /**
elmot 1:d0dfbce63a89 2114 * @brief Get APB2 prescaler
elmot 1:d0dfbce63a89 2115 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
elmot 1:d0dfbce63a89 2116 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2117 * @arg @ref LL_RCC_APB2_DIV_1
elmot 1:d0dfbce63a89 2118 * @arg @ref LL_RCC_APB2_DIV_2
elmot 1:d0dfbce63a89 2119 * @arg @ref LL_RCC_APB2_DIV_4
elmot 1:d0dfbce63a89 2120 * @arg @ref LL_RCC_APB2_DIV_8
elmot 1:d0dfbce63a89 2121 * @arg @ref LL_RCC_APB2_DIV_16
elmot 1:d0dfbce63a89 2122 */
elmot 1:d0dfbce63a89 2123 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
elmot 1:d0dfbce63a89 2124 {
elmot 1:d0dfbce63a89 2125 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
elmot 1:d0dfbce63a89 2126 }
elmot 1:d0dfbce63a89 2127
elmot 1:d0dfbce63a89 2128
elmot 1:d0dfbce63a89 2129 /**
elmot 1:d0dfbce63a89 2130 * @brief Set Clock After Wake-Up From Stop mode
elmot 1:d0dfbce63a89 2131 * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
elmot 1:d0dfbce63a89 2132 * @param Clock This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2133 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
elmot 1:d0dfbce63a89 2134 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
elmot 1:d0dfbce63a89 2135 * @retval None
elmot 1:d0dfbce63a89 2136 */
elmot 1:d0dfbce63a89 2137 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
elmot 1:d0dfbce63a89 2138 {
elmot 1:d0dfbce63a89 2139 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
elmot 1:d0dfbce63a89 2140 }
elmot 1:d0dfbce63a89 2141
elmot 1:d0dfbce63a89 2142 /**
elmot 1:d0dfbce63a89 2143 * @brief Get Clock After Wake-Up From Stop mode
elmot 1:d0dfbce63a89 2144 * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
elmot 1:d0dfbce63a89 2145 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2146 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
elmot 1:d0dfbce63a89 2147 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
elmot 1:d0dfbce63a89 2148 */
elmot 1:d0dfbce63a89 2149 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
elmot 1:d0dfbce63a89 2150 {
elmot 1:d0dfbce63a89 2151 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
elmot 1:d0dfbce63a89 2152 }
elmot 1:d0dfbce63a89 2153
elmot 1:d0dfbce63a89 2154 /**
elmot 1:d0dfbce63a89 2155 * @}
elmot 1:d0dfbce63a89 2156 */
elmot 1:d0dfbce63a89 2157
elmot 1:d0dfbce63a89 2158 /** @defgroup RCC_LL_EF_MCO MCO
elmot 1:d0dfbce63a89 2159 * @{
elmot 1:d0dfbce63a89 2160 */
elmot 1:d0dfbce63a89 2161
elmot 1:d0dfbce63a89 2162 /**
elmot 1:d0dfbce63a89 2163 * @brief Configure MCOx
elmot 1:d0dfbce63a89 2164 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
elmot 1:d0dfbce63a89 2165 * CFGR MCOPRE LL_RCC_ConfigMCO
elmot 1:d0dfbce63a89 2166 * @param MCOxSource This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2167 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
elmot 1:d0dfbce63a89 2168 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
elmot 1:d0dfbce63a89 2169 * @arg @ref LL_RCC_MCO1SOURCE_MSI
elmot 1:d0dfbce63a89 2170 * @arg @ref LL_RCC_MCO1SOURCE_HSI
elmot 1:d0dfbce63a89 2171 * @arg @ref LL_RCC_MCO1SOURCE_HSE
elmot 1:d0dfbce63a89 2172 * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
elmot 1:d0dfbce63a89 2173 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
elmot 1:d0dfbce63a89 2174 * @arg @ref LL_RCC_MCO1SOURCE_LSI
elmot 1:d0dfbce63a89 2175 * @arg @ref LL_RCC_MCO1SOURCE_LSE
elmot 1:d0dfbce63a89 2176 *
elmot 1:d0dfbce63a89 2177 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 2178 * @param MCOxPrescaler This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2179 * @arg @ref LL_RCC_MCO1_DIV_1
elmot 1:d0dfbce63a89 2180 * @arg @ref LL_RCC_MCO1_DIV_2
elmot 1:d0dfbce63a89 2181 * @arg @ref LL_RCC_MCO1_DIV_4
elmot 1:d0dfbce63a89 2182 * @arg @ref LL_RCC_MCO1_DIV_8
elmot 1:d0dfbce63a89 2183 * @arg @ref LL_RCC_MCO1_DIV_16
elmot 1:d0dfbce63a89 2184 * @retval None
elmot 1:d0dfbce63a89 2185 */
elmot 1:d0dfbce63a89 2186 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
elmot 1:d0dfbce63a89 2187 {
elmot 1:d0dfbce63a89 2188 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
elmot 1:d0dfbce63a89 2189 }
elmot 1:d0dfbce63a89 2190
elmot 1:d0dfbce63a89 2191 /**
elmot 1:d0dfbce63a89 2192 * @}
elmot 1:d0dfbce63a89 2193 */
elmot 1:d0dfbce63a89 2194
elmot 1:d0dfbce63a89 2195 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
elmot 1:d0dfbce63a89 2196 * @{
elmot 1:d0dfbce63a89 2197 */
elmot 1:d0dfbce63a89 2198
elmot 1:d0dfbce63a89 2199 /**
elmot 1:d0dfbce63a89 2200 * @brief Configure USARTx clock source
elmot 1:d0dfbce63a89 2201 * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
elmot 1:d0dfbce63a89 2202 * @param USARTxSource This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2203 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
elmot 1:d0dfbce63a89 2204 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2205 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2206 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 2207 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
elmot 1:d0dfbce63a89 2208 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2209 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2210 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 2211 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
elmot 1:d0dfbce63a89 2212 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
elmot 1:d0dfbce63a89 2213 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
elmot 1:d0dfbce63a89 2214 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
elmot 1:d0dfbce63a89 2215 *
elmot 1:d0dfbce63a89 2216 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 2217 * @retval None
elmot 1:d0dfbce63a89 2218 */
elmot 1:d0dfbce63a89 2219 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
elmot 1:d0dfbce63a89 2220 {
elmot 1:d0dfbce63a89 2221 MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFF));
elmot 1:d0dfbce63a89 2222 }
elmot 1:d0dfbce63a89 2223
elmot 1:d0dfbce63a89 2224 #if defined(UART4) || defined(UART5)
elmot 1:d0dfbce63a89 2225 /**
elmot 1:d0dfbce63a89 2226 * @brief Configure UARTx clock source
elmot 1:d0dfbce63a89 2227 * @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource
elmot 1:d0dfbce63a89 2228 * @param UARTxSource This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2229 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
elmot 1:d0dfbce63a89 2230 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2231 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2232 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 2233 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
elmot 1:d0dfbce63a89 2234 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2235 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2236 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 2237 * @retval None
elmot 1:d0dfbce63a89 2238 */
elmot 1:d0dfbce63a89 2239 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
elmot 1:d0dfbce63a89 2240 {
elmot 1:d0dfbce63a89 2241 MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16), (UARTxSource & 0x0000FFFF));
elmot 1:d0dfbce63a89 2242 }
elmot 1:d0dfbce63a89 2243 #endif /* UART4 || UART5 */
elmot 1:d0dfbce63a89 2244
elmot 1:d0dfbce63a89 2245 /**
elmot 1:d0dfbce63a89 2246 * @brief Configure LPUART1x clock source
elmot 1:d0dfbce63a89 2247 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
elmot 1:d0dfbce63a89 2248 * @param LPUARTxSource This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2249 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
elmot 1:d0dfbce63a89 2250 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2251 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2252 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 2253 * @retval None
elmot 1:d0dfbce63a89 2254 */
elmot 1:d0dfbce63a89 2255 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
elmot 1:d0dfbce63a89 2256 {
elmot 1:d0dfbce63a89 2257 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
elmot 1:d0dfbce63a89 2258 }
elmot 1:d0dfbce63a89 2259
elmot 1:d0dfbce63a89 2260 /**
elmot 1:d0dfbce63a89 2261 * @brief Configure I2Cx clock source
elmot 1:d0dfbce63a89 2262 * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
elmot 1:d0dfbce63a89 2263 * @param I2CxSource This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2264 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
elmot 1:d0dfbce63a89 2265 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2266 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2267 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
elmot 1:d0dfbce63a89 2268 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
elmot 1:d0dfbce63a89 2269 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
elmot 1:d0dfbce63a89 2270 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
elmot 1:d0dfbce63a89 2271 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2272 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2273 *
elmot 1:d0dfbce63a89 2274 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 2275 * @retval None
elmot 1:d0dfbce63a89 2276 */
elmot 1:d0dfbce63a89 2277 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
elmot 1:d0dfbce63a89 2278 {
elmot 1:d0dfbce63a89 2279 MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000), ((I2CxSource << 4) & 0x000FF000));
elmot 1:d0dfbce63a89 2280 }
elmot 1:d0dfbce63a89 2281
elmot 1:d0dfbce63a89 2282 /**
elmot 1:d0dfbce63a89 2283 * @brief Configure LPTIMx clock source
elmot 1:d0dfbce63a89 2284 * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
elmot 1:d0dfbce63a89 2285 * @param LPTIMxSource This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2286 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
elmot 1:d0dfbce63a89 2287 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
elmot 1:d0dfbce63a89 2288 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2289 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 2290 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
elmot 1:d0dfbce63a89 2291 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
elmot 1:d0dfbce63a89 2292 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2293 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 2294 * @retval None
elmot 1:d0dfbce63a89 2295 */
elmot 1:d0dfbce63a89 2296 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
elmot 1:d0dfbce63a89 2297 {
elmot 1:d0dfbce63a89 2298 MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16));
elmot 1:d0dfbce63a89 2299 }
elmot 1:d0dfbce63a89 2300
elmot 1:d0dfbce63a89 2301 /**
elmot 1:d0dfbce63a89 2302 * @brief Configure SAIx clock source
elmot 1:d0dfbce63a89 2303 * @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource
elmot 1:d0dfbce63a89 2304 * @param SAIxSource This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2305 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
elmot 1:d0dfbce63a89 2306 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
elmot 1:d0dfbce63a89 2307 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
elmot 1:d0dfbce63a89 2308 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
elmot 1:d0dfbce63a89 2309 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
elmot 1:d0dfbce63a89 2310 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
elmot 1:d0dfbce63a89 2311 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
elmot 1:d0dfbce63a89 2312 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
elmot 1:d0dfbce63a89 2313 *
elmot 1:d0dfbce63a89 2314 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 2315 * @retval None
elmot 1:d0dfbce63a89 2316 */
elmot 1:d0dfbce63a89 2317 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
elmot 1:d0dfbce63a89 2318 {
elmot 1:d0dfbce63a89 2319 MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16));
elmot 1:d0dfbce63a89 2320 }
elmot 1:d0dfbce63a89 2321
elmot 1:d0dfbce63a89 2322 /**
elmot 1:d0dfbce63a89 2323 * @brief Configure SDMMC1 clock source
elmot 1:d0dfbce63a89 2324 * @rmtoll CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource
elmot 1:d0dfbce63a89 2325 * @param SDMMCxSource This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2326 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE
elmot 1:d0dfbce63a89 2327 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
elmot 1:d0dfbce63a89 2328 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
elmot 1:d0dfbce63a89 2329 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
elmot 1:d0dfbce63a89 2330 * @retval None
elmot 1:d0dfbce63a89 2331 */
elmot 1:d0dfbce63a89 2332 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
elmot 1:d0dfbce63a89 2333 {
elmot 1:d0dfbce63a89 2334 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource);
elmot 1:d0dfbce63a89 2335 }
elmot 1:d0dfbce63a89 2336
elmot 1:d0dfbce63a89 2337 /**
elmot 1:d0dfbce63a89 2338 * @brief Configure RNG clock source
elmot 1:d0dfbce63a89 2339 * @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource
elmot 1:d0dfbce63a89 2340 * @param RNGxSource This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2341 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
elmot 1:d0dfbce63a89 2342 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
elmot 1:d0dfbce63a89 2343 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
elmot 1:d0dfbce63a89 2344 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
elmot 1:d0dfbce63a89 2345 * @retval None
elmot 1:d0dfbce63a89 2346 */
elmot 1:d0dfbce63a89 2347 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
elmot 1:d0dfbce63a89 2348 {
elmot 1:d0dfbce63a89 2349 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
elmot 1:d0dfbce63a89 2350 }
elmot 1:d0dfbce63a89 2351
elmot 1:d0dfbce63a89 2352 #if defined(USB_OTG_FS) || defined(USB)
elmot 1:d0dfbce63a89 2353 /**
elmot 1:d0dfbce63a89 2354 * @brief Configure USB clock source
elmot 1:d0dfbce63a89 2355 * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
elmot 1:d0dfbce63a89 2356 * @param USBxSource This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2357 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE
elmot 1:d0dfbce63a89 2358 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
elmot 1:d0dfbce63a89 2359 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
elmot 1:d0dfbce63a89 2360 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
elmot 1:d0dfbce63a89 2361 * @retval None
elmot 1:d0dfbce63a89 2362 */
elmot 1:d0dfbce63a89 2363 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
elmot 1:d0dfbce63a89 2364 {
elmot 1:d0dfbce63a89 2365 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
elmot 1:d0dfbce63a89 2366 }
elmot 1:d0dfbce63a89 2367 #endif /* USB_OTG_FS || USB */
elmot 1:d0dfbce63a89 2368
elmot 1:d0dfbce63a89 2369 /**
elmot 1:d0dfbce63a89 2370 * @brief Configure ADC clock source
elmot 1:d0dfbce63a89 2371 * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
elmot 1:d0dfbce63a89 2372 * @param ADCxSource This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2373 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
elmot 1:d0dfbce63a89 2374 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
elmot 1:d0dfbce63a89 2375 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
elmot 1:d0dfbce63a89 2376 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2377 *
elmot 1:d0dfbce63a89 2378 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 2379 * @retval None
elmot 1:d0dfbce63a89 2380 */
elmot 1:d0dfbce63a89 2381 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
elmot 1:d0dfbce63a89 2382 {
elmot 1:d0dfbce63a89 2383 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
elmot 1:d0dfbce63a89 2384 }
elmot 1:d0dfbce63a89 2385
elmot 1:d0dfbce63a89 2386 /**
elmot 1:d0dfbce63a89 2387 * @brief Configure SWPMI clock source
elmot 1:d0dfbce63a89 2388 * @rmtoll CCIPR SWPMI1SEL LL_RCC_SetSWPMIClockSource
elmot 1:d0dfbce63a89 2389 * @param SWPMIxSource This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2390 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK
elmot 1:d0dfbce63a89 2391 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2392 * @retval None
elmot 1:d0dfbce63a89 2393 */
elmot 1:d0dfbce63a89 2394 __STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)
elmot 1:d0dfbce63a89 2395 {
elmot 1:d0dfbce63a89 2396 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource);
elmot 1:d0dfbce63a89 2397 }
elmot 1:d0dfbce63a89 2398
elmot 1:d0dfbce63a89 2399 #if defined(DFSDM1_Channel0)
elmot 1:d0dfbce63a89 2400 /**
elmot 1:d0dfbce63a89 2401 * @brief Configure DFSDM clock source
elmot 1:d0dfbce63a89 2402 * @rmtoll CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource
elmot 1:d0dfbce63a89 2403 * @param DFSDMxSource This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2404 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK
elmot 1:d0dfbce63a89 2405 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2406 * @retval None
elmot 1:d0dfbce63a89 2407 */
elmot 1:d0dfbce63a89 2408 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
elmot 1:d0dfbce63a89 2409 {
elmot 1:d0dfbce63a89 2410 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource);
elmot 1:d0dfbce63a89 2411 }
elmot 1:d0dfbce63a89 2412 #endif /* DFSDM1_Channel0 */
elmot 1:d0dfbce63a89 2413
elmot 1:d0dfbce63a89 2414 /**
elmot 1:d0dfbce63a89 2415 * @brief Get USARTx clock source
elmot 1:d0dfbce63a89 2416 * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
elmot 1:d0dfbce63a89 2417 * @param USARTx This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2418 * @arg @ref LL_RCC_USART1_CLKSOURCE
elmot 1:d0dfbce63a89 2419 * @arg @ref LL_RCC_USART2_CLKSOURCE
elmot 1:d0dfbce63a89 2420 * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
elmot 1:d0dfbce63a89 2421 *
elmot 1:d0dfbce63a89 2422 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 2423 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2424 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
elmot 1:d0dfbce63a89 2425 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2426 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2427 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 2428 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
elmot 1:d0dfbce63a89 2429 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2430 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2431 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 2432 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
elmot 1:d0dfbce63a89 2433 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
elmot 1:d0dfbce63a89 2434 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
elmot 1:d0dfbce63a89 2435 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
elmot 1:d0dfbce63a89 2436 *
elmot 1:d0dfbce63a89 2437 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 2438 */
elmot 1:d0dfbce63a89 2439 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
elmot 1:d0dfbce63a89 2440 {
elmot 1:d0dfbce63a89 2441 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16));
elmot 1:d0dfbce63a89 2442 }
elmot 1:d0dfbce63a89 2443
elmot 1:d0dfbce63a89 2444 #if defined(UART4) || defined(UART5)
elmot 1:d0dfbce63a89 2445 /**
elmot 1:d0dfbce63a89 2446 * @brief Get UARTx clock source
elmot 1:d0dfbce63a89 2447 * @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource
elmot 1:d0dfbce63a89 2448 * @param UARTx This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2449 * @arg @ref LL_RCC_UART4_CLKSOURCE
elmot 1:d0dfbce63a89 2450 * @arg @ref LL_RCC_UART5_CLKSOURCE
elmot 1:d0dfbce63a89 2451 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2452 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
elmot 1:d0dfbce63a89 2453 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2454 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2455 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 2456 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
elmot 1:d0dfbce63a89 2457 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2458 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2459 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 2460 */
elmot 1:d0dfbce63a89 2461 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
elmot 1:d0dfbce63a89 2462 {
elmot 1:d0dfbce63a89 2463 return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16));
elmot 1:d0dfbce63a89 2464 }
elmot 1:d0dfbce63a89 2465 #endif /* UART4 || UART5 */
elmot 1:d0dfbce63a89 2466
elmot 1:d0dfbce63a89 2467 /**
elmot 1:d0dfbce63a89 2468 * @brief Get LPUARTx clock source
elmot 1:d0dfbce63a89 2469 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
elmot 1:d0dfbce63a89 2470 * @param LPUARTx This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2471 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
elmot 1:d0dfbce63a89 2472 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2473 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
elmot 1:d0dfbce63a89 2474 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2475 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2476 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 2477 */
elmot 1:d0dfbce63a89 2478 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
elmot 1:d0dfbce63a89 2479 {
elmot 1:d0dfbce63a89 2480 return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
elmot 1:d0dfbce63a89 2481 }
elmot 1:d0dfbce63a89 2482
elmot 1:d0dfbce63a89 2483 /**
elmot 1:d0dfbce63a89 2484 * @brief Get I2Cx clock source
elmot 1:d0dfbce63a89 2485 * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
elmot 1:d0dfbce63a89 2486 * @param I2Cx This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2487 * @arg @ref LL_RCC_I2C1_CLKSOURCE
elmot 1:d0dfbce63a89 2488 * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
elmot 1:d0dfbce63a89 2489 * @arg @ref LL_RCC_I2C3_CLKSOURCE
elmot 1:d0dfbce63a89 2490 *
elmot 1:d0dfbce63a89 2491 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 2492 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2493 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
elmot 1:d0dfbce63a89 2494 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2495 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2496 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
elmot 1:d0dfbce63a89 2497 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
elmot 1:d0dfbce63a89 2498 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
elmot 1:d0dfbce63a89 2499 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
elmot 1:d0dfbce63a89 2500 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2501 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2502 *
elmot 1:d0dfbce63a89 2503 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 2504 */
elmot 1:d0dfbce63a89 2505 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
elmot 1:d0dfbce63a89 2506 {
elmot 1:d0dfbce63a89 2507 return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4) | (I2Cx << 4));
elmot 1:d0dfbce63a89 2508 }
elmot 1:d0dfbce63a89 2509
elmot 1:d0dfbce63a89 2510 /**
elmot 1:d0dfbce63a89 2511 * @brief Get LPTIMx clock source
elmot 1:d0dfbce63a89 2512 * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
elmot 1:d0dfbce63a89 2513 * @param LPTIMx This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2514 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
elmot 1:d0dfbce63a89 2515 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
elmot 1:d0dfbce63a89 2516 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2517 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
elmot 1:d0dfbce63a89 2518 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
elmot 1:d0dfbce63a89 2519 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2520 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 2521 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
elmot 1:d0dfbce63a89 2522 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
elmot 1:d0dfbce63a89 2523 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2524 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 2525 */
elmot 1:d0dfbce63a89 2526 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
elmot 1:d0dfbce63a89 2527 {
elmot 1:d0dfbce63a89 2528 return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx) >> 16 | LPTIMx);
elmot 1:d0dfbce63a89 2529 }
elmot 1:d0dfbce63a89 2530
elmot 1:d0dfbce63a89 2531 /**
elmot 1:d0dfbce63a89 2532 * @brief Get SAIx clock source
elmot 1:d0dfbce63a89 2533 * @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource
elmot 1:d0dfbce63a89 2534 * @param SAIx This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2535 * @arg @ref LL_RCC_SAI1_CLKSOURCE
elmot 1:d0dfbce63a89 2536 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
elmot 1:d0dfbce63a89 2537 *
elmot 1:d0dfbce63a89 2538 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 2539 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2540 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
elmot 1:d0dfbce63a89 2541 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
elmot 1:d0dfbce63a89 2542 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
elmot 1:d0dfbce63a89 2543 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
elmot 1:d0dfbce63a89 2544 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
elmot 1:d0dfbce63a89 2545 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
elmot 1:d0dfbce63a89 2546 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
elmot 1:d0dfbce63a89 2547 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
elmot 1:d0dfbce63a89 2548 *
elmot 1:d0dfbce63a89 2549 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 2550 */
elmot 1:d0dfbce63a89 2551 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
elmot 1:d0dfbce63a89 2552 {
elmot 1:d0dfbce63a89 2553 return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16 | SAIx);
elmot 1:d0dfbce63a89 2554 }
elmot 1:d0dfbce63a89 2555
elmot 1:d0dfbce63a89 2556 /**
elmot 1:d0dfbce63a89 2557 * @brief Get SDMMCx clock source
elmot 1:d0dfbce63a89 2558 * @rmtoll CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource
elmot 1:d0dfbce63a89 2559 * @param SDMMCx This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2560 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
elmot 1:d0dfbce63a89 2561 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2562 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE
elmot 1:d0dfbce63a89 2563 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
elmot 1:d0dfbce63a89 2564 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
elmot 1:d0dfbce63a89 2565 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
elmot 1:d0dfbce63a89 2566 */
elmot 1:d0dfbce63a89 2567 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
elmot 1:d0dfbce63a89 2568 {
elmot 1:d0dfbce63a89 2569 return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx));
elmot 1:d0dfbce63a89 2570 }
elmot 1:d0dfbce63a89 2571
elmot 1:d0dfbce63a89 2572 /**
elmot 1:d0dfbce63a89 2573 * @brief Get RNGx clock source
elmot 1:d0dfbce63a89 2574 * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
elmot 1:d0dfbce63a89 2575 * @param RNGx This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2576 * @arg @ref LL_RCC_RNG_CLKSOURCE
elmot 1:d0dfbce63a89 2577 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2578 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
elmot 1:d0dfbce63a89 2579 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
elmot 1:d0dfbce63a89 2580 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
elmot 1:d0dfbce63a89 2581 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
elmot 1:d0dfbce63a89 2582 */
elmot 1:d0dfbce63a89 2583 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
elmot 1:d0dfbce63a89 2584 {
elmot 1:d0dfbce63a89 2585 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
elmot 1:d0dfbce63a89 2586 }
elmot 1:d0dfbce63a89 2587
elmot 1:d0dfbce63a89 2588 #if defined(USB_OTG_FS) || defined(USB)
elmot 1:d0dfbce63a89 2589 /**
elmot 1:d0dfbce63a89 2590 * @brief Get USBx clock source
elmot 1:d0dfbce63a89 2591 * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
elmot 1:d0dfbce63a89 2592 * @param USBx This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2593 * @arg @ref LL_RCC_USB_CLKSOURCE
elmot 1:d0dfbce63a89 2594 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2595 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE
elmot 1:d0dfbce63a89 2596 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
elmot 1:d0dfbce63a89 2597 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
elmot 1:d0dfbce63a89 2598 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
elmot 1:d0dfbce63a89 2599 */
elmot 1:d0dfbce63a89 2600 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
elmot 1:d0dfbce63a89 2601 {
elmot 1:d0dfbce63a89 2602 return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
elmot 1:d0dfbce63a89 2603 }
elmot 1:d0dfbce63a89 2604 #endif /* USB_OTG_FS || USB */
elmot 1:d0dfbce63a89 2605
elmot 1:d0dfbce63a89 2606 /**
elmot 1:d0dfbce63a89 2607 * @brief Get ADCx clock source
elmot 1:d0dfbce63a89 2608 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
elmot 1:d0dfbce63a89 2609 * @param ADCx This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2610 * @arg @ref LL_RCC_ADC_CLKSOURCE
elmot 1:d0dfbce63a89 2611 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2612 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
elmot 1:d0dfbce63a89 2613 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
elmot 1:d0dfbce63a89 2614 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
elmot 1:d0dfbce63a89 2615 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2616 *
elmot 1:d0dfbce63a89 2617 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 2618 */
elmot 1:d0dfbce63a89 2619 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
elmot 1:d0dfbce63a89 2620 {
elmot 1:d0dfbce63a89 2621 return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
elmot 1:d0dfbce63a89 2622 }
elmot 1:d0dfbce63a89 2623
elmot 1:d0dfbce63a89 2624 /**
elmot 1:d0dfbce63a89 2625 * @brief Get SWPMIx clock source
elmot 1:d0dfbce63a89 2626 * @rmtoll CCIPR SWPMI1SEL LL_RCC_GetSWPMIClockSource
elmot 1:d0dfbce63a89 2627 * @param SPWMIx This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2628 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE
elmot 1:d0dfbce63a89 2629 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2630 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK
elmot 1:d0dfbce63a89 2631 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
elmot 1:d0dfbce63a89 2632 */
elmot 1:d0dfbce63a89 2633 __STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)
elmot 1:d0dfbce63a89 2634 {
elmot 1:d0dfbce63a89 2635 return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx));
elmot 1:d0dfbce63a89 2636 }
elmot 1:d0dfbce63a89 2637
elmot 1:d0dfbce63a89 2638 #if defined(DFSDM1_Channel0)
elmot 1:d0dfbce63a89 2639 /**
elmot 1:d0dfbce63a89 2640 * @brief Get DFSDMx clock source
elmot 1:d0dfbce63a89 2641 * @rmtoll CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource
elmot 1:d0dfbce63a89 2642 * @param DFSDMx This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2643 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
elmot 1:d0dfbce63a89 2644 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2645 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK
elmot 1:d0dfbce63a89 2646 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
elmot 1:d0dfbce63a89 2647 */
elmot 1:d0dfbce63a89 2648 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
elmot 1:d0dfbce63a89 2649 {
elmot 1:d0dfbce63a89 2650 return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx));
elmot 1:d0dfbce63a89 2651 }
elmot 1:d0dfbce63a89 2652 #endif /* DFSDM1_Channel0 */
elmot 1:d0dfbce63a89 2653
elmot 1:d0dfbce63a89 2654 /**
elmot 1:d0dfbce63a89 2655 * @}
elmot 1:d0dfbce63a89 2656 */
elmot 1:d0dfbce63a89 2657
elmot 1:d0dfbce63a89 2658 /** @defgroup RCC_LL_EF_RTC RTC
elmot 1:d0dfbce63a89 2659 * @{
elmot 1:d0dfbce63a89 2660 */
elmot 1:d0dfbce63a89 2661
elmot 1:d0dfbce63a89 2662 /**
elmot 1:d0dfbce63a89 2663 * @brief Set RTC Clock Source
elmot 1:d0dfbce63a89 2664 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
elmot 1:d0dfbce63a89 2665 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
elmot 1:d0dfbce63a89 2666 * set). The BDRST bit can be used to reset them.
elmot 1:d0dfbce63a89 2667 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
elmot 1:d0dfbce63a89 2668 * @param Source This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2669 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
elmot 1:d0dfbce63a89 2670 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 2671 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
elmot 1:d0dfbce63a89 2672 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
elmot 1:d0dfbce63a89 2673 * @retval None
elmot 1:d0dfbce63a89 2674 */
elmot 1:d0dfbce63a89 2675 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
elmot 1:d0dfbce63a89 2676 {
elmot 1:d0dfbce63a89 2677 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
elmot 1:d0dfbce63a89 2678 }
elmot 1:d0dfbce63a89 2679
elmot 1:d0dfbce63a89 2680 /**
elmot 1:d0dfbce63a89 2681 * @brief Get RTC Clock Source
elmot 1:d0dfbce63a89 2682 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
elmot 1:d0dfbce63a89 2683 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2684 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
elmot 1:d0dfbce63a89 2685 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
elmot 1:d0dfbce63a89 2686 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
elmot 1:d0dfbce63a89 2687 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
elmot 1:d0dfbce63a89 2688 */
elmot 1:d0dfbce63a89 2689 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
elmot 1:d0dfbce63a89 2690 {
elmot 1:d0dfbce63a89 2691 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
elmot 1:d0dfbce63a89 2692 }
elmot 1:d0dfbce63a89 2693
elmot 1:d0dfbce63a89 2694 /**
elmot 1:d0dfbce63a89 2695 * @brief Enable RTC
elmot 1:d0dfbce63a89 2696 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
elmot 1:d0dfbce63a89 2697 * @retval None
elmot 1:d0dfbce63a89 2698 */
elmot 1:d0dfbce63a89 2699 __STATIC_INLINE void LL_RCC_EnableRTC(void)
elmot 1:d0dfbce63a89 2700 {
elmot 1:d0dfbce63a89 2701 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
elmot 1:d0dfbce63a89 2702 }
elmot 1:d0dfbce63a89 2703
elmot 1:d0dfbce63a89 2704 /**
elmot 1:d0dfbce63a89 2705 * @brief Disable RTC
elmot 1:d0dfbce63a89 2706 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
elmot 1:d0dfbce63a89 2707 * @retval None
elmot 1:d0dfbce63a89 2708 */
elmot 1:d0dfbce63a89 2709 __STATIC_INLINE void LL_RCC_DisableRTC(void)
elmot 1:d0dfbce63a89 2710 {
elmot 1:d0dfbce63a89 2711 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
elmot 1:d0dfbce63a89 2712 }
elmot 1:d0dfbce63a89 2713
elmot 1:d0dfbce63a89 2714 /**
elmot 1:d0dfbce63a89 2715 * @brief Check if RTC has been enabled or not
elmot 1:d0dfbce63a89 2716 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
elmot 1:d0dfbce63a89 2717 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 2718 */
elmot 1:d0dfbce63a89 2719 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
elmot 1:d0dfbce63a89 2720 {
elmot 1:d0dfbce63a89 2721 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
elmot 1:d0dfbce63a89 2722 }
elmot 1:d0dfbce63a89 2723
elmot 1:d0dfbce63a89 2724 /**
elmot 1:d0dfbce63a89 2725 * @brief Force the Backup domain reset
elmot 1:d0dfbce63a89 2726 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
elmot 1:d0dfbce63a89 2727 * @retval None
elmot 1:d0dfbce63a89 2728 */
elmot 1:d0dfbce63a89 2729 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
elmot 1:d0dfbce63a89 2730 {
elmot 1:d0dfbce63a89 2731 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
elmot 1:d0dfbce63a89 2732 }
elmot 1:d0dfbce63a89 2733
elmot 1:d0dfbce63a89 2734 /**
elmot 1:d0dfbce63a89 2735 * @brief Release the Backup domain reset
elmot 1:d0dfbce63a89 2736 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
elmot 1:d0dfbce63a89 2737 * @retval None
elmot 1:d0dfbce63a89 2738 */
elmot 1:d0dfbce63a89 2739 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
elmot 1:d0dfbce63a89 2740 {
elmot 1:d0dfbce63a89 2741 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
elmot 1:d0dfbce63a89 2742 }
elmot 1:d0dfbce63a89 2743
elmot 1:d0dfbce63a89 2744 /**
elmot 1:d0dfbce63a89 2745 * @}
elmot 1:d0dfbce63a89 2746 */
elmot 1:d0dfbce63a89 2747
elmot 1:d0dfbce63a89 2748 /** @defgroup RCC_LL_EF_PLL PLL
elmot 1:d0dfbce63a89 2749 * @{
elmot 1:d0dfbce63a89 2750 */
elmot 1:d0dfbce63a89 2751
elmot 1:d0dfbce63a89 2752 /**
elmot 1:d0dfbce63a89 2753 * @brief Enable PLL
elmot 1:d0dfbce63a89 2754 * @rmtoll CR PLLON LL_RCC_PLL_Enable
elmot 1:d0dfbce63a89 2755 * @retval None
elmot 1:d0dfbce63a89 2756 */
elmot 1:d0dfbce63a89 2757 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
elmot 1:d0dfbce63a89 2758 {
elmot 1:d0dfbce63a89 2759 SET_BIT(RCC->CR, RCC_CR_PLLON);
elmot 1:d0dfbce63a89 2760 }
elmot 1:d0dfbce63a89 2761
elmot 1:d0dfbce63a89 2762 /**
elmot 1:d0dfbce63a89 2763 * @brief Disable PLL
elmot 1:d0dfbce63a89 2764 * @note Cannot be disabled if the PLL clock is used as the system clock
elmot 1:d0dfbce63a89 2765 * @rmtoll CR PLLON LL_RCC_PLL_Disable
elmot 1:d0dfbce63a89 2766 * @retval None
elmot 1:d0dfbce63a89 2767 */
elmot 1:d0dfbce63a89 2768 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
elmot 1:d0dfbce63a89 2769 {
elmot 1:d0dfbce63a89 2770 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
elmot 1:d0dfbce63a89 2771 }
elmot 1:d0dfbce63a89 2772
elmot 1:d0dfbce63a89 2773 /**
elmot 1:d0dfbce63a89 2774 * @brief Check if PLL Ready
elmot 1:d0dfbce63a89 2775 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
elmot 1:d0dfbce63a89 2776 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 2777 */
elmot 1:d0dfbce63a89 2778 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
elmot 1:d0dfbce63a89 2779 {
elmot 1:d0dfbce63a89 2780 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
elmot 1:d0dfbce63a89 2781 }
elmot 1:d0dfbce63a89 2782
elmot 1:d0dfbce63a89 2783 /**
elmot 1:d0dfbce63a89 2784 * @brief Configure PLL used for SYSCLK Domain
elmot 1:d0dfbce63a89 2785 * @note PLL Source and PLLM Divider can be written only when PLL,
elmot 1:d0dfbce63a89 2786 * PLLSAI1 and PLLSAI2 (*) are disabled
elmot 1:d0dfbce63a89 2787 * @note PLLN/PLLR can be written only when PLL is disabled
elmot 1:d0dfbce63a89 2788 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
elmot 1:d0dfbce63a89 2789 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
elmot 1:d0dfbce63a89 2790 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
elmot 1:d0dfbce63a89 2791 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
elmot 1:d0dfbce63a89 2792 * @param Source This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2793 * @arg @ref LL_RCC_PLLSOURCE_NONE
elmot 1:d0dfbce63a89 2794 * @arg @ref LL_RCC_PLLSOURCE_MSI
elmot 1:d0dfbce63a89 2795 * @arg @ref LL_RCC_PLLSOURCE_HSI
elmot 1:d0dfbce63a89 2796 * @arg @ref LL_RCC_PLLSOURCE_HSE
elmot 1:d0dfbce63a89 2797 * @param PLLM This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2798 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 2799 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 2800 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 2801 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 2802 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 2803 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 2804 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 2805 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 2806 * @param PLLN Between 8 and 86
elmot 1:d0dfbce63a89 2807 * @param PLLR This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2808 * @arg @ref LL_RCC_PLLR_DIV_2
elmot 1:d0dfbce63a89 2809 * @arg @ref LL_RCC_PLLR_DIV_4
elmot 1:d0dfbce63a89 2810 * @arg @ref LL_RCC_PLLR_DIV_6
elmot 1:d0dfbce63a89 2811 * @arg @ref LL_RCC_PLLR_DIV_8
elmot 1:d0dfbce63a89 2812 * @retval None
elmot 1:d0dfbce63a89 2813 */
elmot 1:d0dfbce63a89 2814 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
elmot 1:d0dfbce63a89 2815 {
elmot 1:d0dfbce63a89 2816 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
elmot 1:d0dfbce63a89 2817 Source | PLLM | PLLN << RCC_POSITION_PLLN | PLLR);
elmot 1:d0dfbce63a89 2818 }
elmot 1:d0dfbce63a89 2819
elmot 1:d0dfbce63a89 2820 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 2821 /**
elmot 1:d0dfbce63a89 2822 * @brief Configure PLL used for SAI domain clock
elmot 1:d0dfbce63a89 2823 * @note PLL Source and PLLM Divider can be written only when PLL,
elmot 1:d0dfbce63a89 2824 * PLLSAI1 and PLLSAI2 (*) are disabled
elmot 1:d0dfbce63a89 2825 * @note PLLN/PLLP can be written only when PLL is disabled
elmot 1:d0dfbce63a89 2826 * @note This can be selected for SAI1 or SAI2 (*)
elmot 1:d0dfbce63a89 2827 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
elmot 1:d0dfbce63a89 2828 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
elmot 1:d0dfbce63a89 2829 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
elmot 1:d0dfbce63a89 2830 * PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_SAI
elmot 1:d0dfbce63a89 2831 * @param Source This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2832 * @arg @ref LL_RCC_PLLSOURCE_NONE
elmot 1:d0dfbce63a89 2833 * @arg @ref LL_RCC_PLLSOURCE_MSI
elmot 1:d0dfbce63a89 2834 * @arg @ref LL_RCC_PLLSOURCE_HSI
elmot 1:d0dfbce63a89 2835 * @arg @ref LL_RCC_PLLSOURCE_HSE
elmot 1:d0dfbce63a89 2836 * @param PLLM This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2837 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 2838 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 2839 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 2840 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 2841 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 2842 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 2843 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 2844 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 2845 * @param PLLN Between 8 and 86
elmot 1:d0dfbce63a89 2846 * @param PLLP This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2847 * @arg @ref LL_RCC_PLLP_DIV_2
elmot 1:d0dfbce63a89 2848 * @arg @ref LL_RCC_PLLP_DIV_3
elmot 1:d0dfbce63a89 2849 * @arg @ref LL_RCC_PLLP_DIV_4
elmot 1:d0dfbce63a89 2850 * @arg @ref LL_RCC_PLLP_DIV_5
elmot 1:d0dfbce63a89 2851 * @arg @ref LL_RCC_PLLP_DIV_6
elmot 1:d0dfbce63a89 2852 * @arg @ref LL_RCC_PLLP_DIV_7
elmot 1:d0dfbce63a89 2853 * @arg @ref LL_RCC_PLLP_DIV_8
elmot 1:d0dfbce63a89 2854 * @arg @ref LL_RCC_PLLP_DIV_9
elmot 1:d0dfbce63a89 2855 * @arg @ref LL_RCC_PLLP_DIV_10
elmot 1:d0dfbce63a89 2856 * @arg @ref LL_RCC_PLLP_DIV_11
elmot 1:d0dfbce63a89 2857 * @arg @ref LL_RCC_PLLP_DIV_12
elmot 1:d0dfbce63a89 2858 * @arg @ref LL_RCC_PLLP_DIV_13
elmot 1:d0dfbce63a89 2859 * @arg @ref LL_RCC_PLLP_DIV_14
elmot 1:d0dfbce63a89 2860 * @arg @ref LL_RCC_PLLP_DIV_15
elmot 1:d0dfbce63a89 2861 * @arg @ref LL_RCC_PLLP_DIV_16
elmot 1:d0dfbce63a89 2862 * @arg @ref LL_RCC_PLLP_DIV_17
elmot 1:d0dfbce63a89 2863 * @arg @ref LL_RCC_PLLP_DIV_18
elmot 1:d0dfbce63a89 2864 * @arg @ref LL_RCC_PLLP_DIV_19
elmot 1:d0dfbce63a89 2865 * @arg @ref LL_RCC_PLLP_DIV_20
elmot 1:d0dfbce63a89 2866 * @arg @ref LL_RCC_PLLP_DIV_21
elmot 1:d0dfbce63a89 2867 * @arg @ref LL_RCC_PLLP_DIV_22
elmot 1:d0dfbce63a89 2868 * @arg @ref LL_RCC_PLLP_DIV_23
elmot 1:d0dfbce63a89 2869 * @arg @ref LL_RCC_PLLP_DIV_24
elmot 1:d0dfbce63a89 2870 * @arg @ref LL_RCC_PLLP_DIV_25
elmot 1:d0dfbce63a89 2871 * @arg @ref LL_RCC_PLLP_DIV_26
elmot 1:d0dfbce63a89 2872 * @arg @ref LL_RCC_PLLP_DIV_27
elmot 1:d0dfbce63a89 2873 * @arg @ref LL_RCC_PLLP_DIV_28
elmot 1:d0dfbce63a89 2874 * @arg @ref LL_RCC_PLLP_DIV_29
elmot 1:d0dfbce63a89 2875 * @arg @ref LL_RCC_PLLP_DIV_30
elmot 1:d0dfbce63a89 2876 * @arg @ref LL_RCC_PLLP_DIV_31
elmot 1:d0dfbce63a89 2877 * @retval None
elmot 1:d0dfbce63a89 2878 */
elmot 1:d0dfbce63a89 2879 #else
elmot 1:d0dfbce63a89 2880 /**
elmot 1:d0dfbce63a89 2881 * @brief Configure PLL used for SAI domain clock
elmot 1:d0dfbce63a89 2882 * @note PLL Source and PLLM Divider can be written only when PLL,
elmot 1:d0dfbce63a89 2883 * PLLSAI1 and PLLSAI2 (*) are disabled
elmot 1:d0dfbce63a89 2884 * @note PLLN/PLLP can be written only when PLL is disabled
elmot 1:d0dfbce63a89 2885 * @note This can be selected for SAI1 or SAI2 (*)
elmot 1:d0dfbce63a89 2886 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
elmot 1:d0dfbce63a89 2887 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
elmot 1:d0dfbce63a89 2888 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
elmot 1:d0dfbce63a89 2889 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI
elmot 1:d0dfbce63a89 2890 * @param Source This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2891 * @arg @ref LL_RCC_PLLSOURCE_NONE
elmot 1:d0dfbce63a89 2892 * @arg @ref LL_RCC_PLLSOURCE_MSI
elmot 1:d0dfbce63a89 2893 * @arg @ref LL_RCC_PLLSOURCE_HSI
elmot 1:d0dfbce63a89 2894 * @arg @ref LL_RCC_PLLSOURCE_HSE
elmot 1:d0dfbce63a89 2895 * @param PLLM This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2896 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 2897 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 2898 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 2899 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 2900 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 2901 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 2902 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 2903 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 2904 * @param PLLN Between 8 and 86
elmot 1:d0dfbce63a89 2905 * @param PLLP This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2906 * @arg @ref LL_RCC_PLLP_DIV_7
elmot 1:d0dfbce63a89 2907 * @arg @ref LL_RCC_PLLP_DIV_17
elmot 1:d0dfbce63a89 2908 * @retval None
elmot 1:d0dfbce63a89 2909 */
elmot 1:d0dfbce63a89 2910 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 2911 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
elmot 1:d0dfbce63a89 2912 {
elmot 1:d0dfbce63a89 2913 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 2914 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV,
elmot 1:d0dfbce63a89 2915 Source | PLLM | PLLN << RCC_POSITION_PLLN | PLLP);
elmot 1:d0dfbce63a89 2916 #else
elmot 1:d0dfbce63a89 2917 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
elmot 1:d0dfbce63a89 2918 Source | PLLM | PLLN << RCC_POSITION_PLLN | PLLP);
elmot 1:d0dfbce63a89 2919 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 2920 }
elmot 1:d0dfbce63a89 2921
elmot 1:d0dfbce63a89 2922 /**
elmot 1:d0dfbce63a89 2923 * @brief Configure PLL used for 48Mhz domain clock
elmot 1:d0dfbce63a89 2924 * @note PLL Source and PLLM Divider can be written only when PLL,
elmot 1:d0dfbce63a89 2925 * PLLSAI1 and PLLSAI2 (*) are disabled
elmot 1:d0dfbce63a89 2926 * @note PLLN/PLLQ can be written only when PLL is disabled
elmot 1:d0dfbce63a89 2927 * @note This can be selected for USB, RNG, SDMMC
elmot 1:d0dfbce63a89 2928 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
elmot 1:d0dfbce63a89 2929 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
elmot 1:d0dfbce63a89 2930 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
elmot 1:d0dfbce63a89 2931 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
elmot 1:d0dfbce63a89 2932 * @param Source This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2933 * @arg @ref LL_RCC_PLLSOURCE_NONE
elmot 1:d0dfbce63a89 2934 * @arg @ref LL_RCC_PLLSOURCE_MSI
elmot 1:d0dfbce63a89 2935 * @arg @ref LL_RCC_PLLSOURCE_HSI
elmot 1:d0dfbce63a89 2936 * @arg @ref LL_RCC_PLLSOURCE_HSE
elmot 1:d0dfbce63a89 2937 * @param PLLM This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2938 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 2939 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 2940 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 2941 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 2942 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 2943 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 2944 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 2945 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 2946 * @param PLLN Between 8 and 86
elmot 1:d0dfbce63a89 2947 * @param PLLQ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2948 * @arg @ref LL_RCC_PLLQ_DIV_2
elmot 1:d0dfbce63a89 2949 * @arg @ref LL_RCC_PLLQ_DIV_4
elmot 1:d0dfbce63a89 2950 * @arg @ref LL_RCC_PLLQ_DIV_6
elmot 1:d0dfbce63a89 2951 * @arg @ref LL_RCC_PLLQ_DIV_8
elmot 1:d0dfbce63a89 2952 * @retval None
elmot 1:d0dfbce63a89 2953 */
elmot 1:d0dfbce63a89 2954 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
elmot 1:d0dfbce63a89 2955 {
elmot 1:d0dfbce63a89 2956 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
elmot 1:d0dfbce63a89 2957 Source | PLLM | PLLN << RCC_POSITION_PLLN | PLLQ);
elmot 1:d0dfbce63a89 2958 }
elmot 1:d0dfbce63a89 2959
elmot 1:d0dfbce63a89 2960 /**
elmot 1:d0dfbce63a89 2961 * @brief Get Main PLL multiplication factor for VCO
elmot 1:d0dfbce63a89 2962 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
elmot 1:d0dfbce63a89 2963 * @retval Between 8 and 86
elmot 1:d0dfbce63a89 2964 */
elmot 1:d0dfbce63a89 2965 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
elmot 1:d0dfbce63a89 2966 {
elmot 1:d0dfbce63a89 2967 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_POSITION_PLLN);
elmot 1:d0dfbce63a89 2968 }
elmot 1:d0dfbce63a89 2969
elmot 1:d0dfbce63a89 2970 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 2971 /**
elmot 1:d0dfbce63a89 2972 * @brief Get Main PLL division factor for PLLP
elmot 1:d0dfbce63a89 2973 * @note used for PLLSAI3CLK (SAI1 and SAI2 clock)
elmot 1:d0dfbce63a89 2974 * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP
elmot 1:d0dfbce63a89 2975 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 2976 * @arg @ref LL_RCC_PLLP_DIV_2
elmot 1:d0dfbce63a89 2977 * @arg @ref LL_RCC_PLLP_DIV_3
elmot 1:d0dfbce63a89 2978 * @arg @ref LL_RCC_PLLP_DIV_4
elmot 1:d0dfbce63a89 2979 * @arg @ref LL_RCC_PLLP_DIV_5
elmot 1:d0dfbce63a89 2980 * @arg @ref LL_RCC_PLLP_DIV_6
elmot 1:d0dfbce63a89 2981 * @arg @ref LL_RCC_PLLP_DIV_7
elmot 1:d0dfbce63a89 2982 * @arg @ref LL_RCC_PLLP_DIV_8
elmot 1:d0dfbce63a89 2983 * @arg @ref LL_RCC_PLLP_DIV_9
elmot 1:d0dfbce63a89 2984 * @arg @ref LL_RCC_PLLP_DIV_10
elmot 1:d0dfbce63a89 2985 * @arg @ref LL_RCC_PLLP_DIV_11
elmot 1:d0dfbce63a89 2986 * @arg @ref LL_RCC_PLLP_DIV_12
elmot 1:d0dfbce63a89 2987 * @arg @ref LL_RCC_PLLP_DIV_13
elmot 1:d0dfbce63a89 2988 * @arg @ref LL_RCC_PLLP_DIV_14
elmot 1:d0dfbce63a89 2989 * @arg @ref LL_RCC_PLLP_DIV_15
elmot 1:d0dfbce63a89 2990 * @arg @ref LL_RCC_PLLP_DIV_16
elmot 1:d0dfbce63a89 2991 * @arg @ref LL_RCC_PLLP_DIV_17
elmot 1:d0dfbce63a89 2992 * @arg @ref LL_RCC_PLLP_DIV_18
elmot 1:d0dfbce63a89 2993 * @arg @ref LL_RCC_PLLP_DIV_19
elmot 1:d0dfbce63a89 2994 * @arg @ref LL_RCC_PLLP_DIV_20
elmot 1:d0dfbce63a89 2995 * @arg @ref LL_RCC_PLLP_DIV_21
elmot 1:d0dfbce63a89 2996 * @arg @ref LL_RCC_PLLP_DIV_22
elmot 1:d0dfbce63a89 2997 * @arg @ref LL_RCC_PLLP_DIV_23
elmot 1:d0dfbce63a89 2998 * @arg @ref LL_RCC_PLLP_DIV_24
elmot 1:d0dfbce63a89 2999 * @arg @ref LL_RCC_PLLP_DIV_25
elmot 1:d0dfbce63a89 3000 * @arg @ref LL_RCC_PLLP_DIV_26
elmot 1:d0dfbce63a89 3001 * @arg @ref LL_RCC_PLLP_DIV_27
elmot 1:d0dfbce63a89 3002 * @arg @ref LL_RCC_PLLP_DIV_28
elmot 1:d0dfbce63a89 3003 * @arg @ref LL_RCC_PLLP_DIV_29
elmot 1:d0dfbce63a89 3004 * @arg @ref LL_RCC_PLLP_DIV_30
elmot 1:d0dfbce63a89 3005 * @arg @ref LL_RCC_PLLP_DIV_31
elmot 1:d0dfbce63a89 3006 */
elmot 1:d0dfbce63a89 3007 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
elmot 1:d0dfbce63a89 3008 {
elmot 1:d0dfbce63a89 3009 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV));
elmot 1:d0dfbce63a89 3010 }
elmot 1:d0dfbce63a89 3011 #else
elmot 1:d0dfbce63a89 3012 /**
elmot 1:d0dfbce63a89 3013 * @brief Get Main PLL division factor for PLLP
elmot 1:d0dfbce63a89 3014 * @note used for PLLSAI3CLK (SAI1 and SAI2 clock)
elmot 1:d0dfbce63a89 3015 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
elmot 1:d0dfbce63a89 3016 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 3017 * @arg @ref LL_RCC_PLLP_DIV_7
elmot 1:d0dfbce63a89 3018 * @arg @ref LL_RCC_PLLP_DIV_17
elmot 1:d0dfbce63a89 3019 */
elmot 1:d0dfbce63a89 3020 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
elmot 1:d0dfbce63a89 3021 {
elmot 1:d0dfbce63a89 3022 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
elmot 1:d0dfbce63a89 3023 }
elmot 1:d0dfbce63a89 3024 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 3025
elmot 1:d0dfbce63a89 3026 /**
elmot 1:d0dfbce63a89 3027 * @brief Get Main PLL division factor for PLLQ
elmot 1:d0dfbce63a89 3028 * @note used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
elmot 1:d0dfbce63a89 3029 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
elmot 1:d0dfbce63a89 3030 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 3031 * @arg @ref LL_RCC_PLLQ_DIV_2
elmot 1:d0dfbce63a89 3032 * @arg @ref LL_RCC_PLLQ_DIV_4
elmot 1:d0dfbce63a89 3033 * @arg @ref LL_RCC_PLLQ_DIV_6
elmot 1:d0dfbce63a89 3034 * @arg @ref LL_RCC_PLLQ_DIV_8
elmot 1:d0dfbce63a89 3035 */
elmot 1:d0dfbce63a89 3036 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
elmot 1:d0dfbce63a89 3037 {
elmot 1:d0dfbce63a89 3038 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
elmot 1:d0dfbce63a89 3039 }
elmot 1:d0dfbce63a89 3040
elmot 1:d0dfbce63a89 3041 /**
elmot 1:d0dfbce63a89 3042 * @brief Get Main PLL division factor for PLLR
elmot 1:d0dfbce63a89 3043 * @note used for PLLCLK (system clock)
elmot 1:d0dfbce63a89 3044 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
elmot 1:d0dfbce63a89 3045 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 3046 * @arg @ref LL_RCC_PLLR_DIV_2
elmot 1:d0dfbce63a89 3047 * @arg @ref LL_RCC_PLLR_DIV_4
elmot 1:d0dfbce63a89 3048 * @arg @ref LL_RCC_PLLR_DIV_6
elmot 1:d0dfbce63a89 3049 * @arg @ref LL_RCC_PLLR_DIV_8
elmot 1:d0dfbce63a89 3050 */
elmot 1:d0dfbce63a89 3051 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
elmot 1:d0dfbce63a89 3052 {
elmot 1:d0dfbce63a89 3053 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
elmot 1:d0dfbce63a89 3054 }
elmot 1:d0dfbce63a89 3055
elmot 1:d0dfbce63a89 3056 /**
elmot 1:d0dfbce63a89 3057 * @brief Get the oscillator used as PLL clock source.
elmot 1:d0dfbce63a89 3058 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
elmot 1:d0dfbce63a89 3059 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 3060 * @arg @ref LL_RCC_PLLSOURCE_NONE
elmot 1:d0dfbce63a89 3061 * @arg @ref LL_RCC_PLLSOURCE_MSI
elmot 1:d0dfbce63a89 3062 * @arg @ref LL_RCC_PLLSOURCE_HSI
elmot 1:d0dfbce63a89 3063 * @arg @ref LL_RCC_PLLSOURCE_HSE
elmot 1:d0dfbce63a89 3064 */
elmot 1:d0dfbce63a89 3065 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
elmot 1:d0dfbce63a89 3066 {
elmot 1:d0dfbce63a89 3067 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
elmot 1:d0dfbce63a89 3068 }
elmot 1:d0dfbce63a89 3069
elmot 1:d0dfbce63a89 3070 /**
elmot 1:d0dfbce63a89 3071 * @brief Get Division factor for the main PLL and other PLL
elmot 1:d0dfbce63a89 3072 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
elmot 1:d0dfbce63a89 3073 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 3074 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 3075 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 3076 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 3077 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 3078 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 3079 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 3080 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 3081 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 3082 */
elmot 1:d0dfbce63a89 3083 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
elmot 1:d0dfbce63a89 3084 {
elmot 1:d0dfbce63a89 3085 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
elmot 1:d0dfbce63a89 3086 }
elmot 1:d0dfbce63a89 3087
elmot 1:d0dfbce63a89 3088 /**
elmot 1:d0dfbce63a89 3089 * @brief Enable PLL output mapped on SAI domain clock
elmot 1:d0dfbce63a89 3090 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI
elmot 1:d0dfbce63a89 3091 * @retval None
elmot 1:d0dfbce63a89 3092 */
elmot 1:d0dfbce63a89 3093 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
elmot 1:d0dfbce63a89 3094 {
elmot 1:d0dfbce63a89 3095 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
elmot 1:d0dfbce63a89 3096 }
elmot 1:d0dfbce63a89 3097
elmot 1:d0dfbce63a89 3098 /**
elmot 1:d0dfbce63a89 3099 * @brief Disable PLL output mapped on SAI domain clock
elmot 1:d0dfbce63a89 3100 * @note Cannot be disabled if the PLL clock is used as the system
elmot 1:d0dfbce63a89 3101 * clock
elmot 1:d0dfbce63a89 3102 * @note In order to save power, when the PLLCLK of the PLL is
elmot 1:d0dfbce63a89 3103 * not used, should be 0
elmot 1:d0dfbce63a89 3104 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
elmot 1:d0dfbce63a89 3105 * @retval None
elmot 1:d0dfbce63a89 3106 */
elmot 1:d0dfbce63a89 3107 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
elmot 1:d0dfbce63a89 3108 {
elmot 1:d0dfbce63a89 3109 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
elmot 1:d0dfbce63a89 3110 }
elmot 1:d0dfbce63a89 3111
elmot 1:d0dfbce63a89 3112 /**
elmot 1:d0dfbce63a89 3113 * @brief Enable PLL output mapped on 48MHz domain clock
elmot 1:d0dfbce63a89 3114 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
elmot 1:d0dfbce63a89 3115 * @retval None
elmot 1:d0dfbce63a89 3116 */
elmot 1:d0dfbce63a89 3117 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
elmot 1:d0dfbce63a89 3118 {
elmot 1:d0dfbce63a89 3119 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
elmot 1:d0dfbce63a89 3120 }
elmot 1:d0dfbce63a89 3121
elmot 1:d0dfbce63a89 3122 /**
elmot 1:d0dfbce63a89 3123 * @brief Disable PLL output mapped on 48MHz domain clock
elmot 1:d0dfbce63a89 3124 * @note Cannot be disabled if the PLL clock is used as the system
elmot 1:d0dfbce63a89 3125 * clock
elmot 1:d0dfbce63a89 3126 * @note In order to save power, when the PLLCLK of the PLL is
elmot 1:d0dfbce63a89 3127 * not used, should be 0
elmot 1:d0dfbce63a89 3128 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
elmot 1:d0dfbce63a89 3129 * @retval None
elmot 1:d0dfbce63a89 3130 */
elmot 1:d0dfbce63a89 3131 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
elmot 1:d0dfbce63a89 3132 {
elmot 1:d0dfbce63a89 3133 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
elmot 1:d0dfbce63a89 3134 }
elmot 1:d0dfbce63a89 3135
elmot 1:d0dfbce63a89 3136 /**
elmot 1:d0dfbce63a89 3137 * @brief Enable PLL output mapped on SYSCLK domain
elmot 1:d0dfbce63a89 3138 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
elmot 1:d0dfbce63a89 3139 * @retval None
elmot 1:d0dfbce63a89 3140 */
elmot 1:d0dfbce63a89 3141 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
elmot 1:d0dfbce63a89 3142 {
elmot 1:d0dfbce63a89 3143 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
elmot 1:d0dfbce63a89 3144 }
elmot 1:d0dfbce63a89 3145
elmot 1:d0dfbce63a89 3146 /**
elmot 1:d0dfbce63a89 3147 * @brief Disable PLL output mapped on SYSCLK domain
elmot 1:d0dfbce63a89 3148 * @note Cannot be disabled if the PLL clock is used as the system
elmot 1:d0dfbce63a89 3149 * clock
elmot 1:d0dfbce63a89 3150 * @note In order to save power, when the PLLCLK of the PLL is
elmot 1:d0dfbce63a89 3151 * not used, Main PLL should be 0
elmot 1:d0dfbce63a89 3152 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
elmot 1:d0dfbce63a89 3153 * @retval None
elmot 1:d0dfbce63a89 3154 */
elmot 1:d0dfbce63a89 3155 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
elmot 1:d0dfbce63a89 3156 {
elmot 1:d0dfbce63a89 3157 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
elmot 1:d0dfbce63a89 3158 }
elmot 1:d0dfbce63a89 3159
elmot 1:d0dfbce63a89 3160 /**
elmot 1:d0dfbce63a89 3161 * @}
elmot 1:d0dfbce63a89 3162 */
elmot 1:d0dfbce63a89 3163
elmot 1:d0dfbce63a89 3164 /** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
elmot 1:d0dfbce63a89 3165 * @{
elmot 1:d0dfbce63a89 3166 */
elmot 1:d0dfbce63a89 3167
elmot 1:d0dfbce63a89 3168 /**
elmot 1:d0dfbce63a89 3169 * @brief Enable PLLSAI1
elmot 1:d0dfbce63a89 3170 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable
elmot 1:d0dfbce63a89 3171 * @retval None
elmot 1:d0dfbce63a89 3172 */
elmot 1:d0dfbce63a89 3173 __STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
elmot 1:d0dfbce63a89 3174 {
elmot 1:d0dfbce63a89 3175 SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
elmot 1:d0dfbce63a89 3176 }
elmot 1:d0dfbce63a89 3177
elmot 1:d0dfbce63a89 3178 /**
elmot 1:d0dfbce63a89 3179 * @brief Disable PLLSAI1
elmot 1:d0dfbce63a89 3180 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable
elmot 1:d0dfbce63a89 3181 * @retval None
elmot 1:d0dfbce63a89 3182 */
elmot 1:d0dfbce63a89 3183 __STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
elmot 1:d0dfbce63a89 3184 {
elmot 1:d0dfbce63a89 3185 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
elmot 1:d0dfbce63a89 3186 }
elmot 1:d0dfbce63a89 3187
elmot 1:d0dfbce63a89 3188 /**
elmot 1:d0dfbce63a89 3189 * @brief Check if PLLSAI1 Ready
elmot 1:d0dfbce63a89 3190 * @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady
elmot 1:d0dfbce63a89 3191 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 3192 */
elmot 1:d0dfbce63a89 3193 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
elmot 1:d0dfbce63a89 3194 {
elmot 1:d0dfbce63a89 3195 return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY));
elmot 1:d0dfbce63a89 3196 }
elmot 1:d0dfbce63a89 3197
elmot 1:d0dfbce63a89 3198 /**
elmot 1:d0dfbce63a89 3199 * @brief Configure PLLSAI1 used for 48Mhz domain clock
elmot 1:d0dfbce63a89 3200 * @note PLL Source and PLLM Divider can be written only when PLL,
elmot 1:d0dfbce63a89 3201 * PLLSAI1 and PLLSAI2 (*) are disabled
elmot 1:d0dfbce63a89 3202 * @note PLLN/PLLQ can be written only when PLLSAI1 is disabled
elmot 1:d0dfbce63a89 3203 * @note This can be selected for USB, RNG, SDMMC
elmot 1:d0dfbce63a89 3204 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
elmot 1:d0dfbce63a89 3205 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n
elmot 1:d0dfbce63a89 3206 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
elmot 1:d0dfbce63a89 3207 * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
elmot 1:d0dfbce63a89 3208 * @param Source This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3209 * @arg @ref LL_RCC_PLLSOURCE_NONE
elmot 1:d0dfbce63a89 3210 * @arg @ref LL_RCC_PLLSOURCE_MSI
elmot 1:d0dfbce63a89 3211 * @arg @ref LL_RCC_PLLSOURCE_HSI
elmot 1:d0dfbce63a89 3212 * @arg @ref LL_RCC_PLLSOURCE_HSE
elmot 1:d0dfbce63a89 3213 * @param PLLM This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3214 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 3215 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 3216 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 3217 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 3218 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 3219 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 3220 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 3221 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 3222 * @param PLLN Between 8 and 86
elmot 1:d0dfbce63a89 3223 * @param PLLQ This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3224 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
elmot 1:d0dfbce63a89 3225 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
elmot 1:d0dfbce63a89 3226 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
elmot 1:d0dfbce63a89 3227 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
elmot 1:d0dfbce63a89 3228 * @retval None
elmot 1:d0dfbce63a89 3229 */
elmot 1:d0dfbce63a89 3230 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
elmot 1:d0dfbce63a89 3231 {
elmot 1:d0dfbce63a89 3232 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
elmot 1:d0dfbce63a89 3233 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_POSITION_PLLSAI1N | PLLQ);
elmot 1:d0dfbce63a89 3234 }
elmot 1:d0dfbce63a89 3235
elmot 1:d0dfbce63a89 3236 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 3237 /**
elmot 1:d0dfbce63a89 3238 * @brief Configure PLLSAI1 used for SAI domain clock
elmot 1:d0dfbce63a89 3239 * @note PLL Source and PLLM Divider can be written only when PLL,
elmot 1:d0dfbce63a89 3240 * PLLSAI1 and PLLSAI2 (*) are disabled
elmot 1:d0dfbce63a89 3241 * @note PLLN/PLLP can be written only when PLLSAI1 is disabled
elmot 1:d0dfbce63a89 3242 * @note This can be selected for SAI1 or SAI2 (*)
elmot 1:d0dfbce63a89 3243 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
elmot 1:d0dfbce63a89 3244 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
elmot 1:d0dfbce63a89 3245 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
elmot 1:d0dfbce63a89 3246 * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
elmot 1:d0dfbce63a89 3247 * @param Source This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3248 * @arg @ref LL_RCC_PLLSOURCE_NONE
elmot 1:d0dfbce63a89 3249 * @arg @ref LL_RCC_PLLSOURCE_MSI
elmot 1:d0dfbce63a89 3250 * @arg @ref LL_RCC_PLLSOURCE_HSI
elmot 1:d0dfbce63a89 3251 * @arg @ref LL_RCC_PLLSOURCE_HSE
elmot 1:d0dfbce63a89 3252 * @param PLLM This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3253 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 3254 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 3255 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 3256 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 3257 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 3258 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 3259 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 3260 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 3261 * @param PLLN Between 8 and 86
elmot 1:d0dfbce63a89 3262 * @param PLLP This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3263 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
elmot 1:d0dfbce63a89 3264 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
elmot 1:d0dfbce63a89 3265 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
elmot 1:d0dfbce63a89 3266 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
elmot 1:d0dfbce63a89 3267 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
elmot 1:d0dfbce63a89 3268 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
elmot 1:d0dfbce63a89 3269 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
elmot 1:d0dfbce63a89 3270 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
elmot 1:d0dfbce63a89 3271 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
elmot 1:d0dfbce63a89 3272 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
elmot 1:d0dfbce63a89 3273 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
elmot 1:d0dfbce63a89 3274 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
elmot 1:d0dfbce63a89 3275 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
elmot 1:d0dfbce63a89 3276 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
elmot 1:d0dfbce63a89 3277 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
elmot 1:d0dfbce63a89 3278 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
elmot 1:d0dfbce63a89 3279 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
elmot 1:d0dfbce63a89 3280 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
elmot 1:d0dfbce63a89 3281 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
elmot 1:d0dfbce63a89 3282 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
elmot 1:d0dfbce63a89 3283 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
elmot 1:d0dfbce63a89 3284 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
elmot 1:d0dfbce63a89 3285 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
elmot 1:d0dfbce63a89 3286 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
elmot 1:d0dfbce63a89 3287 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
elmot 1:d0dfbce63a89 3288 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
elmot 1:d0dfbce63a89 3289 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
elmot 1:d0dfbce63a89 3290 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
elmot 1:d0dfbce63a89 3291 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
elmot 1:d0dfbce63a89 3292 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
elmot 1:d0dfbce63a89 3293 * @retval None
elmot 1:d0dfbce63a89 3294 */
elmot 1:d0dfbce63a89 3295 #else
elmot 1:d0dfbce63a89 3296 /**
elmot 1:d0dfbce63a89 3297 * @brief Configure PLLSAI1 used for SAI domain clock
elmot 1:d0dfbce63a89 3298 * @note PLL Source and PLLM Divider can be written only when PLL,
elmot 1:d0dfbce63a89 3299 * PLLSAI1 and PLLSAI2 (*) are disabled
elmot 1:d0dfbce63a89 3300 * @note PLLN/PLLP can be written only when PLLSAI1 is disabled
elmot 1:d0dfbce63a89 3301 * @note This can be selected for SAI1 or SAI2 (*)
elmot 1:d0dfbce63a89 3302 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
elmot 1:d0dfbce63a89 3303 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
elmot 1:d0dfbce63a89 3304 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
elmot 1:d0dfbce63a89 3305 * PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI
elmot 1:d0dfbce63a89 3306 * @param Source This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3307 * @arg @ref LL_RCC_PLLSOURCE_NONE
elmot 1:d0dfbce63a89 3308 * @arg @ref LL_RCC_PLLSOURCE_MSI
elmot 1:d0dfbce63a89 3309 * @arg @ref LL_RCC_PLLSOURCE_HSI
elmot 1:d0dfbce63a89 3310 * @arg @ref LL_RCC_PLLSOURCE_HSE
elmot 1:d0dfbce63a89 3311 * @param PLLM This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3312 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 3313 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 3314 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 3315 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 3316 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 3317 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 3318 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 3319 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 3320 * @param PLLN Between 8 and 86
elmot 1:d0dfbce63a89 3321 * @param PLLP This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3322 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
elmot 1:d0dfbce63a89 3323 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
elmot 1:d0dfbce63a89 3324 * @retval None
elmot 1:d0dfbce63a89 3325 */
elmot 1:d0dfbce63a89 3326 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 3327 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
elmot 1:d0dfbce63a89 3328 {
elmot 1:d0dfbce63a89 3329 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
elmot 1:d0dfbce63a89 3330 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 3331 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
elmot 1:d0dfbce63a89 3332 PLLN << RCC_POSITION_PLLSAI1N | PLLP);
elmot 1:d0dfbce63a89 3333 #else
elmot 1:d0dfbce63a89 3334 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_POSITION_PLLSAI1N | PLLP);
elmot 1:d0dfbce63a89 3335 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 3336 }
elmot 1:d0dfbce63a89 3337
elmot 1:d0dfbce63a89 3338 /**
elmot 1:d0dfbce63a89 3339 * @brief Configure PLLSAI1 used for ADC domain clock
elmot 1:d0dfbce63a89 3340 * @note PLL Source and PLLM Divider can be written only when PLL,
elmot 1:d0dfbce63a89 3341 * PLLSAI1 and PLLSAI2 (*) are disabled
elmot 1:d0dfbce63a89 3342 * @note PLLN/PLLR can be written only when PLLSAI1 is disabled
elmot 1:d0dfbce63a89 3343 * @note This can be selected for ADC
elmot 1:d0dfbce63a89 3344 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
elmot 1:d0dfbce63a89 3345 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n
elmot 1:d0dfbce63a89 3346 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
elmot 1:d0dfbce63a89 3347 * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
elmot 1:d0dfbce63a89 3348 * @param Source This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3349 * @arg @ref LL_RCC_PLLSOURCE_NONE
elmot 1:d0dfbce63a89 3350 * @arg @ref LL_RCC_PLLSOURCE_MSI
elmot 1:d0dfbce63a89 3351 * @arg @ref LL_RCC_PLLSOURCE_HSI
elmot 1:d0dfbce63a89 3352 * @arg @ref LL_RCC_PLLSOURCE_HSE
elmot 1:d0dfbce63a89 3353 * @param PLLM This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3354 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 3355 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 3356 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 3357 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 3358 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 3359 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 3360 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 3361 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 3362 * @param PLLN Between 8 and 86
elmot 1:d0dfbce63a89 3363 * @param PLLR This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3364 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
elmot 1:d0dfbce63a89 3365 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
elmot 1:d0dfbce63a89 3366 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
elmot 1:d0dfbce63a89 3367 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
elmot 1:d0dfbce63a89 3368 * @retval None
elmot 1:d0dfbce63a89 3369 */
elmot 1:d0dfbce63a89 3370 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
elmot 1:d0dfbce63a89 3371 {
elmot 1:d0dfbce63a89 3372 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
elmot 1:d0dfbce63a89 3373 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_POSITION_PLLSAI1N | PLLR);
elmot 1:d0dfbce63a89 3374 }
elmot 1:d0dfbce63a89 3375
elmot 1:d0dfbce63a89 3376 /**
elmot 1:d0dfbce63a89 3377 * @brief Get SAI1PLL multiplication factor for VCO
elmot 1:d0dfbce63a89 3378 * @rmtoll PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN
elmot 1:d0dfbce63a89 3379 * @retval Between 8 and 86
elmot 1:d0dfbce63a89 3380 */
elmot 1:d0dfbce63a89 3381 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
elmot 1:d0dfbce63a89 3382 {
elmot 1:d0dfbce63a89 3383 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_POSITION_PLLSAI1N);
elmot 1:d0dfbce63a89 3384 }
elmot 1:d0dfbce63a89 3385
elmot 1:d0dfbce63a89 3386 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 3387 /**
elmot 1:d0dfbce63a89 3388 * @brief Get SAI1PLL division factor for PLLSAI1P
elmot 1:d0dfbce63a89 3389 * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
elmot 1:d0dfbce63a89 3390 * @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP
elmot 1:d0dfbce63a89 3391 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 3392 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
elmot 1:d0dfbce63a89 3393 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
elmot 1:d0dfbce63a89 3394 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
elmot 1:d0dfbce63a89 3395 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
elmot 1:d0dfbce63a89 3396 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
elmot 1:d0dfbce63a89 3397 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
elmot 1:d0dfbce63a89 3398 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
elmot 1:d0dfbce63a89 3399 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
elmot 1:d0dfbce63a89 3400 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
elmot 1:d0dfbce63a89 3401 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
elmot 1:d0dfbce63a89 3402 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
elmot 1:d0dfbce63a89 3403 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
elmot 1:d0dfbce63a89 3404 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
elmot 1:d0dfbce63a89 3405 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
elmot 1:d0dfbce63a89 3406 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
elmot 1:d0dfbce63a89 3407 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
elmot 1:d0dfbce63a89 3408 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
elmot 1:d0dfbce63a89 3409 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
elmot 1:d0dfbce63a89 3410 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
elmot 1:d0dfbce63a89 3411 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
elmot 1:d0dfbce63a89 3412 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
elmot 1:d0dfbce63a89 3413 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
elmot 1:d0dfbce63a89 3414 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
elmot 1:d0dfbce63a89 3415 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
elmot 1:d0dfbce63a89 3416 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
elmot 1:d0dfbce63a89 3417 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
elmot 1:d0dfbce63a89 3418 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
elmot 1:d0dfbce63a89 3419 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
elmot 1:d0dfbce63a89 3420 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
elmot 1:d0dfbce63a89 3421 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
elmot 1:d0dfbce63a89 3422 */
elmot 1:d0dfbce63a89 3423 #else
elmot 1:d0dfbce63a89 3424 /**
elmot 1:d0dfbce63a89 3425 * @brief Get SAI1PLL division factor for PLLSAI1P
elmot 1:d0dfbce63a89 3426 * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
elmot 1:d0dfbce63a89 3427 * @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP
elmot 1:d0dfbce63a89 3428 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 3429 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
elmot 1:d0dfbce63a89 3430 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
elmot 1:d0dfbce63a89 3431 */
elmot 1:d0dfbce63a89 3432 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 3433 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
elmot 1:d0dfbce63a89 3434 {
elmot 1:d0dfbce63a89 3435 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 3436 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));
elmot 1:d0dfbce63a89 3437 #else
elmot 1:d0dfbce63a89 3438 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));
elmot 1:d0dfbce63a89 3439 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 3440 }
elmot 1:d0dfbce63a89 3441
elmot 1:d0dfbce63a89 3442 /**
elmot 1:d0dfbce63a89 3443 * @brief Get SAI1PLL division factor for PLLSAI1Q
elmot 1:d0dfbce63a89 3444 * @note used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
elmot 1:d0dfbce63a89 3445 * @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ
elmot 1:d0dfbce63a89 3446 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 3447 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
elmot 1:d0dfbce63a89 3448 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
elmot 1:d0dfbce63a89 3449 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
elmot 1:d0dfbce63a89 3450 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
elmot 1:d0dfbce63a89 3451 */
elmot 1:d0dfbce63a89 3452 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
elmot 1:d0dfbce63a89 3453 {
elmot 1:d0dfbce63a89 3454 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));
elmot 1:d0dfbce63a89 3455 }
elmot 1:d0dfbce63a89 3456
elmot 1:d0dfbce63a89 3457 /**
elmot 1:d0dfbce63a89 3458 * @brief Get PLLSAI1 division factor for PLLSAIR
elmot 1:d0dfbce63a89 3459 * @note used for PLLADC1CLK (ADC clock)
elmot 1:d0dfbce63a89 3460 * @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR
elmot 1:d0dfbce63a89 3461 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 3462 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
elmot 1:d0dfbce63a89 3463 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
elmot 1:d0dfbce63a89 3464 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
elmot 1:d0dfbce63a89 3465 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
elmot 1:d0dfbce63a89 3466 */
elmot 1:d0dfbce63a89 3467 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
elmot 1:d0dfbce63a89 3468 {
elmot 1:d0dfbce63a89 3469 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
elmot 1:d0dfbce63a89 3470 }
elmot 1:d0dfbce63a89 3471
elmot 1:d0dfbce63a89 3472 /**
elmot 1:d0dfbce63a89 3473 * @brief Enable PLLSAI1 output mapped on SAI domain clock
elmot 1:d0dfbce63a89 3474 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI
elmot 1:d0dfbce63a89 3475 * @retval None
elmot 1:d0dfbce63a89 3476 */
elmot 1:d0dfbce63a89 3477 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
elmot 1:d0dfbce63a89 3478 {
elmot 1:d0dfbce63a89 3479 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
elmot 1:d0dfbce63a89 3480 }
elmot 1:d0dfbce63a89 3481
elmot 1:d0dfbce63a89 3482 /**
elmot 1:d0dfbce63a89 3483 * @brief Disable PLLSAI1 output mapped on SAI domain clock
elmot 1:d0dfbce63a89 3484 * @note In order to save power, when of the PLLSAI1 is
elmot 1:d0dfbce63a89 3485 * not used, should be 0
elmot 1:d0dfbce63a89 3486 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI
elmot 1:d0dfbce63a89 3487 * @retval None
elmot 1:d0dfbce63a89 3488 */
elmot 1:d0dfbce63a89 3489 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
elmot 1:d0dfbce63a89 3490 {
elmot 1:d0dfbce63a89 3491 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
elmot 1:d0dfbce63a89 3492 }
elmot 1:d0dfbce63a89 3493
elmot 1:d0dfbce63a89 3494 /**
elmot 1:d0dfbce63a89 3495 * @brief Enable PLLSAI1 output mapped on 48MHz domain clock
elmot 1:d0dfbce63a89 3496 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M
elmot 1:d0dfbce63a89 3497 * @retval None
elmot 1:d0dfbce63a89 3498 */
elmot 1:d0dfbce63a89 3499 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
elmot 1:d0dfbce63a89 3500 {
elmot 1:d0dfbce63a89 3501 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
elmot 1:d0dfbce63a89 3502 }
elmot 1:d0dfbce63a89 3503
elmot 1:d0dfbce63a89 3504 /**
elmot 1:d0dfbce63a89 3505 * @brief Disable PLLSAI1 output mapped on 48MHz domain clock
elmot 1:d0dfbce63a89 3506 * @note In order to save power, when of the PLLSAI1 is
elmot 1:d0dfbce63a89 3507 * not used, should be 0
elmot 1:d0dfbce63a89 3508 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M
elmot 1:d0dfbce63a89 3509 * @retval None
elmot 1:d0dfbce63a89 3510 */
elmot 1:d0dfbce63a89 3511 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
elmot 1:d0dfbce63a89 3512 {
elmot 1:d0dfbce63a89 3513 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
elmot 1:d0dfbce63a89 3514 }
elmot 1:d0dfbce63a89 3515
elmot 1:d0dfbce63a89 3516 /**
elmot 1:d0dfbce63a89 3517 * @brief Enable PLLSAI1 output mapped on ADC domain clock
elmot 1:d0dfbce63a89 3518 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC
elmot 1:d0dfbce63a89 3519 * @retval None
elmot 1:d0dfbce63a89 3520 */
elmot 1:d0dfbce63a89 3521 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
elmot 1:d0dfbce63a89 3522 {
elmot 1:d0dfbce63a89 3523 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
elmot 1:d0dfbce63a89 3524 }
elmot 1:d0dfbce63a89 3525
elmot 1:d0dfbce63a89 3526 /**
elmot 1:d0dfbce63a89 3527 * @brief Disable PLLSAI1 output mapped on ADC domain clock
elmot 1:d0dfbce63a89 3528 * @note In order to save power, when of the PLLSAI1 is
elmot 1:d0dfbce63a89 3529 * not used, Main PLLSAI1 should be 0
elmot 1:d0dfbce63a89 3530 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC
elmot 1:d0dfbce63a89 3531 * @retval None
elmot 1:d0dfbce63a89 3532 */
elmot 1:d0dfbce63a89 3533 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
elmot 1:d0dfbce63a89 3534 {
elmot 1:d0dfbce63a89 3535 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
elmot 1:d0dfbce63a89 3536 }
elmot 1:d0dfbce63a89 3537
elmot 1:d0dfbce63a89 3538 /**
elmot 1:d0dfbce63a89 3539 * @}
elmot 1:d0dfbce63a89 3540 */
elmot 1:d0dfbce63a89 3541
elmot 1:d0dfbce63a89 3542 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 3543 /** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2
elmot 1:d0dfbce63a89 3544 * @{
elmot 1:d0dfbce63a89 3545 */
elmot 1:d0dfbce63a89 3546
elmot 1:d0dfbce63a89 3547 /**
elmot 1:d0dfbce63a89 3548 * @brief Enable PLLSAI2
elmot 1:d0dfbce63a89 3549 * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Enable
elmot 1:d0dfbce63a89 3550 * @retval None
elmot 1:d0dfbce63a89 3551 */
elmot 1:d0dfbce63a89 3552 __STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)
elmot 1:d0dfbce63a89 3553 {
elmot 1:d0dfbce63a89 3554 SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
elmot 1:d0dfbce63a89 3555 }
elmot 1:d0dfbce63a89 3556
elmot 1:d0dfbce63a89 3557 /**
elmot 1:d0dfbce63a89 3558 * @brief Disable PLLSAI2
elmot 1:d0dfbce63a89 3559 * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Disable
elmot 1:d0dfbce63a89 3560 * @retval None
elmot 1:d0dfbce63a89 3561 */
elmot 1:d0dfbce63a89 3562 __STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)
elmot 1:d0dfbce63a89 3563 {
elmot 1:d0dfbce63a89 3564 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
elmot 1:d0dfbce63a89 3565 }
elmot 1:d0dfbce63a89 3566
elmot 1:d0dfbce63a89 3567 /**
elmot 1:d0dfbce63a89 3568 * @brief Check if PLLSAI2 Ready
elmot 1:d0dfbce63a89 3569 * @rmtoll CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady
elmot 1:d0dfbce63a89 3570 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 3571 */
elmot 1:d0dfbce63a89 3572 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
elmot 1:d0dfbce63a89 3573 {
elmot 1:d0dfbce63a89 3574 return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY));
elmot 1:d0dfbce63a89 3575 }
elmot 1:d0dfbce63a89 3576
elmot 1:d0dfbce63a89 3577 /**
elmot 1:d0dfbce63a89 3578 * @brief Configure PLLSAI2 used for SAI domain clock
elmot 1:d0dfbce63a89 3579 * @note PLL Source and PLLM Divider can be written only when PLL,
elmot 1:d0dfbce63a89 3580 * PLLSAI2 and PLLSAI2 are disabled
elmot 1:d0dfbce63a89 3581 * @note PLLN/PLLP can be written only when PLLSAI2 is disabled
elmot 1:d0dfbce63a89 3582 * @note This can be selected for SAI1 or SAI2
elmot 1:d0dfbce63a89 3583 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
elmot 1:d0dfbce63a89 3584 * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
elmot 1:d0dfbce63a89 3585 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
elmot 1:d0dfbce63a89 3586 * PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_ConfigDomain_SAI
elmot 1:d0dfbce63a89 3587 * @param Source This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3588 * @arg @ref LL_RCC_PLLSOURCE_NONE
elmot 1:d0dfbce63a89 3589 * @arg @ref LL_RCC_PLLSOURCE_MSI
elmot 1:d0dfbce63a89 3590 * @arg @ref LL_RCC_PLLSOURCE_HSI
elmot 1:d0dfbce63a89 3591 * @arg @ref LL_RCC_PLLSOURCE_HSE
elmot 1:d0dfbce63a89 3592 * @param PLLM This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3593 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 3594 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 3595 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 3596 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 3597 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 3598 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 3599 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 3600 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 3601 * @param PLLN Between 8 and 86
elmot 1:d0dfbce63a89 3602 * @param PLLP This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3603 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
elmot 1:d0dfbce63a89 3604 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
elmot 1:d0dfbce63a89 3605 * @retval None
elmot 1:d0dfbce63a89 3606 */
elmot 1:d0dfbce63a89 3607 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
elmot 1:d0dfbce63a89 3608 {
elmot 1:d0dfbce63a89 3609 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
elmot 1:d0dfbce63a89 3610 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_POSITION_PLLSAI2N | PLLP);
elmot 1:d0dfbce63a89 3611 }
elmot 1:d0dfbce63a89 3612
elmot 1:d0dfbce63a89 3613 /**
elmot 1:d0dfbce63a89 3614 * @brief Configure PLLSAI2 used for ADC domain clock
elmot 1:d0dfbce63a89 3615 * @note PLL Source and PLLM Divider can be written only when PLL,
elmot 1:d0dfbce63a89 3616 * PLLSAI2 and PLLSAI2 are disabled
elmot 1:d0dfbce63a89 3617 * @note PLLN/PLLR can be written only when PLLSAI2 is disabled
elmot 1:d0dfbce63a89 3618 * @note This can be selected for ADC
elmot 1:d0dfbce63a89 3619 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n
elmot 1:d0dfbce63a89 3620 * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n
elmot 1:d0dfbce63a89 3621 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_ADC\n
elmot 1:d0dfbce63a89 3622 * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_ADC
elmot 1:d0dfbce63a89 3623 * @param Source This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3624 * @arg @ref LL_RCC_PLLSOURCE_NONE
elmot 1:d0dfbce63a89 3625 * @arg @ref LL_RCC_PLLSOURCE_MSI
elmot 1:d0dfbce63a89 3626 * @arg @ref LL_RCC_PLLSOURCE_HSI
elmot 1:d0dfbce63a89 3627 * @arg @ref LL_RCC_PLLSOURCE_HSE
elmot 1:d0dfbce63a89 3628 * @param PLLM This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3629 * @arg @ref LL_RCC_PLLM_DIV_1
elmot 1:d0dfbce63a89 3630 * @arg @ref LL_RCC_PLLM_DIV_2
elmot 1:d0dfbce63a89 3631 * @arg @ref LL_RCC_PLLM_DIV_3
elmot 1:d0dfbce63a89 3632 * @arg @ref LL_RCC_PLLM_DIV_4
elmot 1:d0dfbce63a89 3633 * @arg @ref LL_RCC_PLLM_DIV_5
elmot 1:d0dfbce63a89 3634 * @arg @ref LL_RCC_PLLM_DIV_6
elmot 1:d0dfbce63a89 3635 * @arg @ref LL_RCC_PLLM_DIV_7
elmot 1:d0dfbce63a89 3636 * @arg @ref LL_RCC_PLLM_DIV_8
elmot 1:d0dfbce63a89 3637 * @param PLLN Between 8 and 86
elmot 1:d0dfbce63a89 3638 * @param PLLR This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3639 * @arg @ref LL_RCC_PLLSAI2R_DIV_2
elmot 1:d0dfbce63a89 3640 * @arg @ref LL_RCC_PLLSAI2R_DIV_4
elmot 1:d0dfbce63a89 3641 * @arg @ref LL_RCC_PLLSAI2R_DIV_6
elmot 1:d0dfbce63a89 3642 * @arg @ref LL_RCC_PLLSAI2R_DIV_8
elmot 1:d0dfbce63a89 3643 * @retval None
elmot 1:d0dfbce63a89 3644 */
elmot 1:d0dfbce63a89 3645 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
elmot 1:d0dfbce63a89 3646 {
elmot 1:d0dfbce63a89 3647 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
elmot 1:d0dfbce63a89 3648 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_POSITION_PLLSAI2N | PLLR);
elmot 1:d0dfbce63a89 3649 }
elmot 1:d0dfbce63a89 3650
elmot 1:d0dfbce63a89 3651 /**
elmot 1:d0dfbce63a89 3652 * @brief Get SAI2PLL multiplication factor for VCO
elmot 1:d0dfbce63a89 3653 * @rmtoll PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN
elmot 1:d0dfbce63a89 3654 * @retval Between 8 and 86
elmot 1:d0dfbce63a89 3655 */
elmot 1:d0dfbce63a89 3656 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)
elmot 1:d0dfbce63a89 3657 {
elmot 1:d0dfbce63a89 3658 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_POSITION_PLLSAI2N);
elmot 1:d0dfbce63a89 3659 }
elmot 1:d0dfbce63a89 3660
elmot 1:d0dfbce63a89 3661 /**
elmot 1:d0dfbce63a89 3662 * @brief Get SAI2PLL division factor for PLLSAI2P
elmot 1:d0dfbce63a89 3663 * @note used for PLLSAI2CLK (SAI1 or SAI2 clock).
elmot 1:d0dfbce63a89 3664 * @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP
elmot 1:d0dfbce63a89 3665 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 3666 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
elmot 1:d0dfbce63a89 3667 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
elmot 1:d0dfbce63a89 3668 */
elmot 1:d0dfbce63a89 3669 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
elmot 1:d0dfbce63a89 3670 {
elmot 1:d0dfbce63a89 3671 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P));
elmot 1:d0dfbce63a89 3672 }
elmot 1:d0dfbce63a89 3673
elmot 1:d0dfbce63a89 3674 /**
elmot 1:d0dfbce63a89 3675 * @brief Get SAI2PLL division factor for PLLSAI2R
elmot 1:d0dfbce63a89 3676 * @note used for PLLADC2CLK (ADC clock)
elmot 1:d0dfbce63a89 3677 * @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR
elmot 1:d0dfbce63a89 3678 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 3679 * @arg @ref LL_RCC_PLLSAI2R_DIV_2
elmot 1:d0dfbce63a89 3680 * @arg @ref LL_RCC_PLLSAI2R_DIV_4
elmot 1:d0dfbce63a89 3681 * @arg @ref LL_RCC_PLLSAI2R_DIV_6
elmot 1:d0dfbce63a89 3682 * @arg @ref LL_RCC_PLLSAI2R_DIV_8
elmot 1:d0dfbce63a89 3683 */
elmot 1:d0dfbce63a89 3684 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void)
elmot 1:d0dfbce63a89 3685 {
elmot 1:d0dfbce63a89 3686 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));
elmot 1:d0dfbce63a89 3687 }
elmot 1:d0dfbce63a89 3688
elmot 1:d0dfbce63a89 3689 /**
elmot 1:d0dfbce63a89 3690 * @brief Enable PLLSAI2 output mapped on SAI domain clock
elmot 1:d0dfbce63a89 3691 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI
elmot 1:d0dfbce63a89 3692 * @retval None
elmot 1:d0dfbce63a89 3693 */
elmot 1:d0dfbce63a89 3694 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)
elmot 1:d0dfbce63a89 3695 {
elmot 1:d0dfbce63a89 3696 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
elmot 1:d0dfbce63a89 3697 }
elmot 1:d0dfbce63a89 3698
elmot 1:d0dfbce63a89 3699 /**
elmot 1:d0dfbce63a89 3700 * @brief Disable PLLSAI2 output mapped on SAI domain clock
elmot 1:d0dfbce63a89 3701 * @note In order to save power, when of the PLLSAI2 is
elmot 1:d0dfbce63a89 3702 * not used, should be 0
elmot 1:d0dfbce63a89 3703 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI
elmot 1:d0dfbce63a89 3704 * @retval None
elmot 1:d0dfbce63a89 3705 */
elmot 1:d0dfbce63a89 3706 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)
elmot 1:d0dfbce63a89 3707 {
elmot 1:d0dfbce63a89 3708 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
elmot 1:d0dfbce63a89 3709 }
elmot 1:d0dfbce63a89 3710
elmot 1:d0dfbce63a89 3711 /**
elmot 1:d0dfbce63a89 3712 * @brief Enable PLLSAI2 output mapped on ADC domain clock
elmot 1:d0dfbce63a89 3713 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC
elmot 1:d0dfbce63a89 3714 * @retval None
elmot 1:d0dfbce63a89 3715 */
elmot 1:d0dfbce63a89 3716 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void)
elmot 1:d0dfbce63a89 3717 {
elmot 1:d0dfbce63a89 3718 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
elmot 1:d0dfbce63a89 3719 }
elmot 1:d0dfbce63a89 3720
elmot 1:d0dfbce63a89 3721 /**
elmot 1:d0dfbce63a89 3722 * @brief Disable PLLSAI2 output mapped on ADC domain clock
elmot 1:d0dfbce63a89 3723 * @note In order to save power, when of the PLLSAI2 is
elmot 1:d0dfbce63a89 3724 * not used, Main PLLSAI2 should be 0
elmot 1:d0dfbce63a89 3725 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_ADC
elmot 1:d0dfbce63a89 3726 * @retval None
elmot 1:d0dfbce63a89 3727 */
elmot 1:d0dfbce63a89 3728 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void)
elmot 1:d0dfbce63a89 3729 {
elmot 1:d0dfbce63a89 3730 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
elmot 1:d0dfbce63a89 3731 }
elmot 1:d0dfbce63a89 3732
elmot 1:d0dfbce63a89 3733 /**
elmot 1:d0dfbce63a89 3734 * @}
elmot 1:d0dfbce63a89 3735 */
elmot 1:d0dfbce63a89 3736
elmot 1:d0dfbce63a89 3737 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 3738 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
elmot 1:d0dfbce63a89 3739 * @{
elmot 1:d0dfbce63a89 3740 */
elmot 1:d0dfbce63a89 3741
elmot 1:d0dfbce63a89 3742 /**
elmot 1:d0dfbce63a89 3743 * @brief Clear LSI ready interrupt flag
elmot 1:d0dfbce63a89 3744 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
elmot 1:d0dfbce63a89 3745 * @retval None
elmot 1:d0dfbce63a89 3746 */
elmot 1:d0dfbce63a89 3747 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
elmot 1:d0dfbce63a89 3748 {
elmot 1:d0dfbce63a89 3749 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
elmot 1:d0dfbce63a89 3750 }
elmot 1:d0dfbce63a89 3751
elmot 1:d0dfbce63a89 3752 /**
elmot 1:d0dfbce63a89 3753 * @brief Clear LSE ready interrupt flag
elmot 1:d0dfbce63a89 3754 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
elmot 1:d0dfbce63a89 3755 * @retval None
elmot 1:d0dfbce63a89 3756 */
elmot 1:d0dfbce63a89 3757 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
elmot 1:d0dfbce63a89 3758 {
elmot 1:d0dfbce63a89 3759 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
elmot 1:d0dfbce63a89 3760 }
elmot 1:d0dfbce63a89 3761
elmot 1:d0dfbce63a89 3762 /**
elmot 1:d0dfbce63a89 3763 * @brief Clear MSI ready interrupt flag
elmot 1:d0dfbce63a89 3764 * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
elmot 1:d0dfbce63a89 3765 * @retval None
elmot 1:d0dfbce63a89 3766 */
elmot 1:d0dfbce63a89 3767 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
elmot 1:d0dfbce63a89 3768 {
elmot 1:d0dfbce63a89 3769 SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
elmot 1:d0dfbce63a89 3770 }
elmot 1:d0dfbce63a89 3771
elmot 1:d0dfbce63a89 3772 /**
elmot 1:d0dfbce63a89 3773 * @brief Clear HSI ready interrupt flag
elmot 1:d0dfbce63a89 3774 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
elmot 1:d0dfbce63a89 3775 * @retval None
elmot 1:d0dfbce63a89 3776 */
elmot 1:d0dfbce63a89 3777 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
elmot 1:d0dfbce63a89 3778 {
elmot 1:d0dfbce63a89 3779 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
elmot 1:d0dfbce63a89 3780 }
elmot 1:d0dfbce63a89 3781
elmot 1:d0dfbce63a89 3782 /**
elmot 1:d0dfbce63a89 3783 * @brief Clear HSE ready interrupt flag
elmot 1:d0dfbce63a89 3784 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
elmot 1:d0dfbce63a89 3785 * @retval None
elmot 1:d0dfbce63a89 3786 */
elmot 1:d0dfbce63a89 3787 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
elmot 1:d0dfbce63a89 3788 {
elmot 1:d0dfbce63a89 3789 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
elmot 1:d0dfbce63a89 3790 }
elmot 1:d0dfbce63a89 3791
elmot 1:d0dfbce63a89 3792 /**
elmot 1:d0dfbce63a89 3793 * @brief Clear PLL ready interrupt flag
elmot 1:d0dfbce63a89 3794 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
elmot 1:d0dfbce63a89 3795 * @retval None
elmot 1:d0dfbce63a89 3796 */
elmot 1:d0dfbce63a89 3797 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
elmot 1:d0dfbce63a89 3798 {
elmot 1:d0dfbce63a89 3799 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
elmot 1:d0dfbce63a89 3800 }
elmot 1:d0dfbce63a89 3801
elmot 1:d0dfbce63a89 3802 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 3803 /**
elmot 1:d0dfbce63a89 3804 * @brief Clear HSI48 ready interrupt flag
elmot 1:d0dfbce63a89 3805 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
elmot 1:d0dfbce63a89 3806 * @retval None
elmot 1:d0dfbce63a89 3807 */
elmot 1:d0dfbce63a89 3808 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
elmot 1:d0dfbce63a89 3809 {
elmot 1:d0dfbce63a89 3810 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
elmot 1:d0dfbce63a89 3811 }
elmot 1:d0dfbce63a89 3812 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 3813
elmot 1:d0dfbce63a89 3814 /**
elmot 1:d0dfbce63a89 3815 * @brief Clear PLLSAI1 ready interrupt flag
elmot 1:d0dfbce63a89 3816 * @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY
elmot 1:d0dfbce63a89 3817 * @retval None
elmot 1:d0dfbce63a89 3818 */
elmot 1:d0dfbce63a89 3819 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
elmot 1:d0dfbce63a89 3820 {
elmot 1:d0dfbce63a89 3821 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
elmot 1:d0dfbce63a89 3822 }
elmot 1:d0dfbce63a89 3823
elmot 1:d0dfbce63a89 3824 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 3825 /**
elmot 1:d0dfbce63a89 3826 * @brief Clear PLLSAI1 ready interrupt flag
elmot 1:d0dfbce63a89 3827 * @rmtoll CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY
elmot 1:d0dfbce63a89 3828 * @retval None
elmot 1:d0dfbce63a89 3829 */
elmot 1:d0dfbce63a89 3830 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)
elmot 1:d0dfbce63a89 3831 {
elmot 1:d0dfbce63a89 3832 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC);
elmot 1:d0dfbce63a89 3833 }
elmot 1:d0dfbce63a89 3834
elmot 1:d0dfbce63a89 3835 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 3836 /**
elmot 1:d0dfbce63a89 3837 * @brief Clear Clock security system interrupt flag
elmot 1:d0dfbce63a89 3838 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
elmot 1:d0dfbce63a89 3839 * @retval None
elmot 1:d0dfbce63a89 3840 */
elmot 1:d0dfbce63a89 3841 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
elmot 1:d0dfbce63a89 3842 {
elmot 1:d0dfbce63a89 3843 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
elmot 1:d0dfbce63a89 3844 }
elmot 1:d0dfbce63a89 3845
elmot 1:d0dfbce63a89 3846 /**
elmot 1:d0dfbce63a89 3847 * @brief Clear LSE Clock security system interrupt flag
elmot 1:d0dfbce63a89 3848 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
elmot 1:d0dfbce63a89 3849 * @retval None
elmot 1:d0dfbce63a89 3850 */
elmot 1:d0dfbce63a89 3851 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
elmot 1:d0dfbce63a89 3852 {
elmot 1:d0dfbce63a89 3853 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
elmot 1:d0dfbce63a89 3854 }
elmot 1:d0dfbce63a89 3855
elmot 1:d0dfbce63a89 3856 /**
elmot 1:d0dfbce63a89 3857 * @brief Check if LSI ready interrupt occurred or not
elmot 1:d0dfbce63a89 3858 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
elmot 1:d0dfbce63a89 3859 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 3860 */
elmot 1:d0dfbce63a89 3861 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
elmot 1:d0dfbce63a89 3862 {
elmot 1:d0dfbce63a89 3863 return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF));
elmot 1:d0dfbce63a89 3864 }
elmot 1:d0dfbce63a89 3865
elmot 1:d0dfbce63a89 3866 /**
elmot 1:d0dfbce63a89 3867 * @brief Check if LSE ready interrupt occurred or not
elmot 1:d0dfbce63a89 3868 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
elmot 1:d0dfbce63a89 3869 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 3870 */
elmot 1:d0dfbce63a89 3871 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
elmot 1:d0dfbce63a89 3872 {
elmot 1:d0dfbce63a89 3873 return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF));
elmot 1:d0dfbce63a89 3874 }
elmot 1:d0dfbce63a89 3875
elmot 1:d0dfbce63a89 3876 /**
elmot 1:d0dfbce63a89 3877 * @brief Check if MSI ready interrupt occurred or not
elmot 1:d0dfbce63a89 3878 * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
elmot 1:d0dfbce63a89 3879 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 3880 */
elmot 1:d0dfbce63a89 3881 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
elmot 1:d0dfbce63a89 3882 {
elmot 1:d0dfbce63a89 3883 return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF));
elmot 1:d0dfbce63a89 3884 }
elmot 1:d0dfbce63a89 3885
elmot 1:d0dfbce63a89 3886 /**
elmot 1:d0dfbce63a89 3887 * @brief Check if HSI ready interrupt occurred or not
elmot 1:d0dfbce63a89 3888 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
elmot 1:d0dfbce63a89 3889 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 3890 */
elmot 1:d0dfbce63a89 3891 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
elmot 1:d0dfbce63a89 3892 {
elmot 1:d0dfbce63a89 3893 return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF));
elmot 1:d0dfbce63a89 3894 }
elmot 1:d0dfbce63a89 3895
elmot 1:d0dfbce63a89 3896 /**
elmot 1:d0dfbce63a89 3897 * @brief Check if HSE ready interrupt occurred or not
elmot 1:d0dfbce63a89 3898 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
elmot 1:d0dfbce63a89 3899 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 3900 */
elmot 1:d0dfbce63a89 3901 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
elmot 1:d0dfbce63a89 3902 {
elmot 1:d0dfbce63a89 3903 return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF));
elmot 1:d0dfbce63a89 3904 }
elmot 1:d0dfbce63a89 3905
elmot 1:d0dfbce63a89 3906 /**
elmot 1:d0dfbce63a89 3907 * @brief Check if PLL ready interrupt occurred or not
elmot 1:d0dfbce63a89 3908 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
elmot 1:d0dfbce63a89 3909 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 3910 */
elmot 1:d0dfbce63a89 3911 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
elmot 1:d0dfbce63a89 3912 {
elmot 1:d0dfbce63a89 3913 return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF));
elmot 1:d0dfbce63a89 3914 }
elmot 1:d0dfbce63a89 3915
elmot 1:d0dfbce63a89 3916 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 3917 /**
elmot 1:d0dfbce63a89 3918 * @brief Check if HSI48 ready interrupt occurred or not
elmot 1:d0dfbce63a89 3919 * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
elmot 1:d0dfbce63a89 3920 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 3921 */
elmot 1:d0dfbce63a89 3922 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
elmot 1:d0dfbce63a89 3923 {
elmot 1:d0dfbce63a89 3924 return (READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF));
elmot 1:d0dfbce63a89 3925 }
elmot 1:d0dfbce63a89 3926 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 3927
elmot 1:d0dfbce63a89 3928 /**
elmot 1:d0dfbce63a89 3929 * @brief Check if PLLSAI1 ready interrupt occurred or not
elmot 1:d0dfbce63a89 3930 * @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY
elmot 1:d0dfbce63a89 3931 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 3932 */
elmot 1:d0dfbce63a89 3933 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
elmot 1:d0dfbce63a89 3934 {
elmot 1:d0dfbce63a89 3935 return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF));
elmot 1:d0dfbce63a89 3936 }
elmot 1:d0dfbce63a89 3937
elmot 1:d0dfbce63a89 3938 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 3939 /**
elmot 1:d0dfbce63a89 3940 * @brief Check if PLLSAI1 ready interrupt occurred or not
elmot 1:d0dfbce63a89 3941 * @rmtoll CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY
elmot 1:d0dfbce63a89 3942 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 3943 */
elmot 1:d0dfbce63a89 3944 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)
elmot 1:d0dfbce63a89 3945 {
elmot 1:d0dfbce63a89 3946 return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == (RCC_CIFR_PLLSAI2RDYF));
elmot 1:d0dfbce63a89 3947 }
elmot 1:d0dfbce63a89 3948
elmot 1:d0dfbce63a89 3949 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 3950 /**
elmot 1:d0dfbce63a89 3951 * @brief Check if Clock security system interrupt occurred or not
elmot 1:d0dfbce63a89 3952 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
elmot 1:d0dfbce63a89 3953 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 3954 */
elmot 1:d0dfbce63a89 3955 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
elmot 1:d0dfbce63a89 3956 {
elmot 1:d0dfbce63a89 3957 return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF));
elmot 1:d0dfbce63a89 3958 }
elmot 1:d0dfbce63a89 3959
elmot 1:d0dfbce63a89 3960 /**
elmot 1:d0dfbce63a89 3961 * @brief Check if LSE Clock security system interrupt occurred or not
elmot 1:d0dfbce63a89 3962 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
elmot 1:d0dfbce63a89 3963 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 3964 */
elmot 1:d0dfbce63a89 3965 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
elmot 1:d0dfbce63a89 3966 {
elmot 1:d0dfbce63a89 3967 return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF));
elmot 1:d0dfbce63a89 3968 }
elmot 1:d0dfbce63a89 3969
elmot 1:d0dfbce63a89 3970
elmot 1:d0dfbce63a89 3971 /**
elmot 1:d0dfbce63a89 3972 * @brief Check if RCC flag FW reset is set or not.
elmot 1:d0dfbce63a89 3973 * @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST
elmot 1:d0dfbce63a89 3974 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 3975 */
elmot 1:d0dfbce63a89 3976 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
elmot 1:d0dfbce63a89 3977 {
elmot 1:d0dfbce63a89 3978 return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF));
elmot 1:d0dfbce63a89 3979 }
elmot 1:d0dfbce63a89 3980
elmot 1:d0dfbce63a89 3981 /**
elmot 1:d0dfbce63a89 3982 * @brief Check if RCC flag Independent Watchdog reset is set or not.
elmot 1:d0dfbce63a89 3983 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
elmot 1:d0dfbce63a89 3984 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 3985 */
elmot 1:d0dfbce63a89 3986 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
elmot 1:d0dfbce63a89 3987 {
elmot 1:d0dfbce63a89 3988 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
elmot 1:d0dfbce63a89 3989 }
elmot 1:d0dfbce63a89 3990
elmot 1:d0dfbce63a89 3991 /**
elmot 1:d0dfbce63a89 3992 * @brief Check if RCC flag Low Power reset is set or not.
elmot 1:d0dfbce63a89 3993 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
elmot 1:d0dfbce63a89 3994 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 3995 */
elmot 1:d0dfbce63a89 3996 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
elmot 1:d0dfbce63a89 3997 {
elmot 1:d0dfbce63a89 3998 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
elmot 1:d0dfbce63a89 3999 }
elmot 1:d0dfbce63a89 4000
elmot 1:d0dfbce63a89 4001 /**
elmot 1:d0dfbce63a89 4002 * @brief Check if RCC flag is set or not.
elmot 1:d0dfbce63a89 4003 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
elmot 1:d0dfbce63a89 4004 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 4005 */
elmot 1:d0dfbce63a89 4006 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
elmot 1:d0dfbce63a89 4007 {
elmot 1:d0dfbce63a89 4008 return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
elmot 1:d0dfbce63a89 4009 }
elmot 1:d0dfbce63a89 4010
elmot 1:d0dfbce63a89 4011 /**
elmot 1:d0dfbce63a89 4012 * @brief Check if RCC flag Pin reset is set or not.
elmot 1:d0dfbce63a89 4013 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
elmot 1:d0dfbce63a89 4014 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 4015 */
elmot 1:d0dfbce63a89 4016 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
elmot 1:d0dfbce63a89 4017 {
elmot 1:d0dfbce63a89 4018 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
elmot 1:d0dfbce63a89 4019 }
elmot 1:d0dfbce63a89 4020
elmot 1:d0dfbce63a89 4021 /**
elmot 1:d0dfbce63a89 4022 * @brief Check if RCC flag Software reset is set or not.
elmot 1:d0dfbce63a89 4023 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
elmot 1:d0dfbce63a89 4024 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 4025 */
elmot 1:d0dfbce63a89 4026 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
elmot 1:d0dfbce63a89 4027 {
elmot 1:d0dfbce63a89 4028 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
elmot 1:d0dfbce63a89 4029 }
elmot 1:d0dfbce63a89 4030
elmot 1:d0dfbce63a89 4031 /**
elmot 1:d0dfbce63a89 4032 * @brief Check if RCC flag Window Watchdog reset is set or not.
elmot 1:d0dfbce63a89 4033 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
elmot 1:d0dfbce63a89 4034 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 4035 */
elmot 1:d0dfbce63a89 4036 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
elmot 1:d0dfbce63a89 4037 {
elmot 1:d0dfbce63a89 4038 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
elmot 1:d0dfbce63a89 4039 }
elmot 1:d0dfbce63a89 4040
elmot 1:d0dfbce63a89 4041 /**
elmot 1:d0dfbce63a89 4042 * @brief Check if RCC flag BOR reset is set or not.
elmot 1:d0dfbce63a89 4043 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
elmot 1:d0dfbce63a89 4044 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 4045 */
elmot 1:d0dfbce63a89 4046 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
elmot 1:d0dfbce63a89 4047 {
elmot 1:d0dfbce63a89 4048 return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
elmot 1:d0dfbce63a89 4049 }
elmot 1:d0dfbce63a89 4050
elmot 1:d0dfbce63a89 4051 /**
elmot 1:d0dfbce63a89 4052 * @brief Set RMVF bit to clear the reset flags.
elmot 1:d0dfbce63a89 4053 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
elmot 1:d0dfbce63a89 4054 * @retval None
elmot 1:d0dfbce63a89 4055 */
elmot 1:d0dfbce63a89 4056 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
elmot 1:d0dfbce63a89 4057 {
elmot 1:d0dfbce63a89 4058 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
elmot 1:d0dfbce63a89 4059 }
elmot 1:d0dfbce63a89 4060
elmot 1:d0dfbce63a89 4061 /**
elmot 1:d0dfbce63a89 4062 * @}
elmot 1:d0dfbce63a89 4063 */
elmot 1:d0dfbce63a89 4064
elmot 1:d0dfbce63a89 4065 /** @defgroup RCC_LL_EF_IT_Management IT Management
elmot 1:d0dfbce63a89 4066 * @{
elmot 1:d0dfbce63a89 4067 */
elmot 1:d0dfbce63a89 4068
elmot 1:d0dfbce63a89 4069 /**
elmot 1:d0dfbce63a89 4070 * @brief Enable LSI ready interrupt
elmot 1:d0dfbce63a89 4071 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
elmot 1:d0dfbce63a89 4072 * @retval None
elmot 1:d0dfbce63a89 4073 */
elmot 1:d0dfbce63a89 4074 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
elmot 1:d0dfbce63a89 4075 {
elmot 1:d0dfbce63a89 4076 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
elmot 1:d0dfbce63a89 4077 }
elmot 1:d0dfbce63a89 4078
elmot 1:d0dfbce63a89 4079 /**
elmot 1:d0dfbce63a89 4080 * @brief Enable LSE ready interrupt
elmot 1:d0dfbce63a89 4081 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
elmot 1:d0dfbce63a89 4082 * @retval None
elmot 1:d0dfbce63a89 4083 */
elmot 1:d0dfbce63a89 4084 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
elmot 1:d0dfbce63a89 4085 {
elmot 1:d0dfbce63a89 4086 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
elmot 1:d0dfbce63a89 4087 }
elmot 1:d0dfbce63a89 4088
elmot 1:d0dfbce63a89 4089 /**
elmot 1:d0dfbce63a89 4090 * @brief Enable MSI ready interrupt
elmot 1:d0dfbce63a89 4091 * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
elmot 1:d0dfbce63a89 4092 * @retval None
elmot 1:d0dfbce63a89 4093 */
elmot 1:d0dfbce63a89 4094 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
elmot 1:d0dfbce63a89 4095 {
elmot 1:d0dfbce63a89 4096 SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
elmot 1:d0dfbce63a89 4097 }
elmot 1:d0dfbce63a89 4098
elmot 1:d0dfbce63a89 4099 /**
elmot 1:d0dfbce63a89 4100 * @brief Enable HSI ready interrupt
elmot 1:d0dfbce63a89 4101 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
elmot 1:d0dfbce63a89 4102 * @retval None
elmot 1:d0dfbce63a89 4103 */
elmot 1:d0dfbce63a89 4104 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
elmot 1:d0dfbce63a89 4105 {
elmot 1:d0dfbce63a89 4106 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
elmot 1:d0dfbce63a89 4107 }
elmot 1:d0dfbce63a89 4108
elmot 1:d0dfbce63a89 4109 /**
elmot 1:d0dfbce63a89 4110 * @brief Enable HSE ready interrupt
elmot 1:d0dfbce63a89 4111 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
elmot 1:d0dfbce63a89 4112 * @retval None
elmot 1:d0dfbce63a89 4113 */
elmot 1:d0dfbce63a89 4114 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
elmot 1:d0dfbce63a89 4115 {
elmot 1:d0dfbce63a89 4116 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
elmot 1:d0dfbce63a89 4117 }
elmot 1:d0dfbce63a89 4118
elmot 1:d0dfbce63a89 4119 /**
elmot 1:d0dfbce63a89 4120 * @brief Enable PLL ready interrupt
elmot 1:d0dfbce63a89 4121 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
elmot 1:d0dfbce63a89 4122 * @retval None
elmot 1:d0dfbce63a89 4123 */
elmot 1:d0dfbce63a89 4124 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
elmot 1:d0dfbce63a89 4125 {
elmot 1:d0dfbce63a89 4126 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
elmot 1:d0dfbce63a89 4127 }
elmot 1:d0dfbce63a89 4128
elmot 1:d0dfbce63a89 4129 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 4130 /**
elmot 1:d0dfbce63a89 4131 * @brief Enable HSI48 ready interrupt
elmot 1:d0dfbce63a89 4132 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
elmot 1:d0dfbce63a89 4133 * @retval None
elmot 1:d0dfbce63a89 4134 */
elmot 1:d0dfbce63a89 4135 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
elmot 1:d0dfbce63a89 4136 {
elmot 1:d0dfbce63a89 4137 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
elmot 1:d0dfbce63a89 4138 }
elmot 1:d0dfbce63a89 4139 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 4140
elmot 1:d0dfbce63a89 4141 /**
elmot 1:d0dfbce63a89 4142 * @brief Enable PLLSAI1 ready interrupt
elmot 1:d0dfbce63a89 4143 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY
elmot 1:d0dfbce63a89 4144 * @retval None
elmot 1:d0dfbce63a89 4145 */
elmot 1:d0dfbce63a89 4146 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
elmot 1:d0dfbce63a89 4147 {
elmot 1:d0dfbce63a89 4148 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
elmot 1:d0dfbce63a89 4149 }
elmot 1:d0dfbce63a89 4150
elmot 1:d0dfbce63a89 4151 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 4152 /**
elmot 1:d0dfbce63a89 4153 * @brief Enable PLLSAI2 ready interrupt
elmot 1:d0dfbce63a89 4154 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY
elmot 1:d0dfbce63a89 4155 * @retval None
elmot 1:d0dfbce63a89 4156 */
elmot 1:d0dfbce63a89 4157 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)
elmot 1:d0dfbce63a89 4158 {
elmot 1:d0dfbce63a89 4159 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
elmot 1:d0dfbce63a89 4160 }
elmot 1:d0dfbce63a89 4161
elmot 1:d0dfbce63a89 4162 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 4163 /**
elmot 1:d0dfbce63a89 4164 * @brief Enable LSE clock security system interrupt
elmot 1:d0dfbce63a89 4165 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
elmot 1:d0dfbce63a89 4166 * @retval None
elmot 1:d0dfbce63a89 4167 */
elmot 1:d0dfbce63a89 4168 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
elmot 1:d0dfbce63a89 4169 {
elmot 1:d0dfbce63a89 4170 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
elmot 1:d0dfbce63a89 4171 }
elmot 1:d0dfbce63a89 4172
elmot 1:d0dfbce63a89 4173 /**
elmot 1:d0dfbce63a89 4174 * @brief Disable LSI ready interrupt
elmot 1:d0dfbce63a89 4175 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
elmot 1:d0dfbce63a89 4176 * @retval None
elmot 1:d0dfbce63a89 4177 */
elmot 1:d0dfbce63a89 4178 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
elmot 1:d0dfbce63a89 4179 {
elmot 1:d0dfbce63a89 4180 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
elmot 1:d0dfbce63a89 4181 }
elmot 1:d0dfbce63a89 4182
elmot 1:d0dfbce63a89 4183 /**
elmot 1:d0dfbce63a89 4184 * @brief Disable LSE ready interrupt
elmot 1:d0dfbce63a89 4185 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
elmot 1:d0dfbce63a89 4186 * @retval None
elmot 1:d0dfbce63a89 4187 */
elmot 1:d0dfbce63a89 4188 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
elmot 1:d0dfbce63a89 4189 {
elmot 1:d0dfbce63a89 4190 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
elmot 1:d0dfbce63a89 4191 }
elmot 1:d0dfbce63a89 4192
elmot 1:d0dfbce63a89 4193 /**
elmot 1:d0dfbce63a89 4194 * @brief Disable MSI ready interrupt
elmot 1:d0dfbce63a89 4195 * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
elmot 1:d0dfbce63a89 4196 * @retval None
elmot 1:d0dfbce63a89 4197 */
elmot 1:d0dfbce63a89 4198 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
elmot 1:d0dfbce63a89 4199 {
elmot 1:d0dfbce63a89 4200 CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
elmot 1:d0dfbce63a89 4201 }
elmot 1:d0dfbce63a89 4202
elmot 1:d0dfbce63a89 4203 /**
elmot 1:d0dfbce63a89 4204 * @brief Disable HSI ready interrupt
elmot 1:d0dfbce63a89 4205 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
elmot 1:d0dfbce63a89 4206 * @retval None
elmot 1:d0dfbce63a89 4207 */
elmot 1:d0dfbce63a89 4208 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
elmot 1:d0dfbce63a89 4209 {
elmot 1:d0dfbce63a89 4210 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
elmot 1:d0dfbce63a89 4211 }
elmot 1:d0dfbce63a89 4212
elmot 1:d0dfbce63a89 4213 /**
elmot 1:d0dfbce63a89 4214 * @brief Disable HSE ready interrupt
elmot 1:d0dfbce63a89 4215 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
elmot 1:d0dfbce63a89 4216 * @retval None
elmot 1:d0dfbce63a89 4217 */
elmot 1:d0dfbce63a89 4218 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
elmot 1:d0dfbce63a89 4219 {
elmot 1:d0dfbce63a89 4220 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
elmot 1:d0dfbce63a89 4221 }
elmot 1:d0dfbce63a89 4222
elmot 1:d0dfbce63a89 4223 /**
elmot 1:d0dfbce63a89 4224 * @brief Disable PLL ready interrupt
elmot 1:d0dfbce63a89 4225 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
elmot 1:d0dfbce63a89 4226 * @retval None
elmot 1:d0dfbce63a89 4227 */
elmot 1:d0dfbce63a89 4228 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
elmot 1:d0dfbce63a89 4229 {
elmot 1:d0dfbce63a89 4230 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
elmot 1:d0dfbce63a89 4231 }
elmot 1:d0dfbce63a89 4232
elmot 1:d0dfbce63a89 4233 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 4234 /**
elmot 1:d0dfbce63a89 4235 * @brief Disable HSI48 ready interrupt
elmot 1:d0dfbce63a89 4236 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
elmot 1:d0dfbce63a89 4237 * @retval None
elmot 1:d0dfbce63a89 4238 */
elmot 1:d0dfbce63a89 4239 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
elmot 1:d0dfbce63a89 4240 {
elmot 1:d0dfbce63a89 4241 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
elmot 1:d0dfbce63a89 4242 }
elmot 1:d0dfbce63a89 4243 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 4244
elmot 1:d0dfbce63a89 4245 /**
elmot 1:d0dfbce63a89 4246 * @brief Disable PLLSAI1 ready interrupt
elmot 1:d0dfbce63a89 4247 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY
elmot 1:d0dfbce63a89 4248 * @retval None
elmot 1:d0dfbce63a89 4249 */
elmot 1:d0dfbce63a89 4250 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
elmot 1:d0dfbce63a89 4251 {
elmot 1:d0dfbce63a89 4252 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
elmot 1:d0dfbce63a89 4253 }
elmot 1:d0dfbce63a89 4254
elmot 1:d0dfbce63a89 4255 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 4256 /**
elmot 1:d0dfbce63a89 4257 * @brief Disable PLLSAI2 ready interrupt
elmot 1:d0dfbce63a89 4258 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY
elmot 1:d0dfbce63a89 4259 * @retval None
elmot 1:d0dfbce63a89 4260 */
elmot 1:d0dfbce63a89 4261 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)
elmot 1:d0dfbce63a89 4262 {
elmot 1:d0dfbce63a89 4263 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
elmot 1:d0dfbce63a89 4264 }
elmot 1:d0dfbce63a89 4265
elmot 1:d0dfbce63a89 4266 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 4267 /**
elmot 1:d0dfbce63a89 4268 * @brief Disable LSE clock security system interrupt
elmot 1:d0dfbce63a89 4269 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
elmot 1:d0dfbce63a89 4270 * @retval None
elmot 1:d0dfbce63a89 4271 */
elmot 1:d0dfbce63a89 4272 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
elmot 1:d0dfbce63a89 4273 {
elmot 1:d0dfbce63a89 4274 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
elmot 1:d0dfbce63a89 4275 }
elmot 1:d0dfbce63a89 4276
elmot 1:d0dfbce63a89 4277 /**
elmot 1:d0dfbce63a89 4278 * @brief Checks if LSI ready interrupt source is enabled or disabled.
elmot 1:d0dfbce63a89 4279 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
elmot 1:d0dfbce63a89 4280 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 4281 */
elmot 1:d0dfbce63a89 4282 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
elmot 1:d0dfbce63a89 4283 {
elmot 1:d0dfbce63a89 4284 return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE));
elmot 1:d0dfbce63a89 4285 }
elmot 1:d0dfbce63a89 4286
elmot 1:d0dfbce63a89 4287 /**
elmot 1:d0dfbce63a89 4288 * @brief Checks if LSE ready interrupt source is enabled or disabled.
elmot 1:d0dfbce63a89 4289 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
elmot 1:d0dfbce63a89 4290 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 4291 */
elmot 1:d0dfbce63a89 4292 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
elmot 1:d0dfbce63a89 4293 {
elmot 1:d0dfbce63a89 4294 return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE));
elmot 1:d0dfbce63a89 4295 }
elmot 1:d0dfbce63a89 4296
elmot 1:d0dfbce63a89 4297 /**
elmot 1:d0dfbce63a89 4298 * @brief Checks if MSI ready interrupt source is enabled or disabled.
elmot 1:d0dfbce63a89 4299 * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
elmot 1:d0dfbce63a89 4300 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 4301 */
elmot 1:d0dfbce63a89 4302 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
elmot 1:d0dfbce63a89 4303 {
elmot 1:d0dfbce63a89 4304 return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE));
elmot 1:d0dfbce63a89 4305 }
elmot 1:d0dfbce63a89 4306
elmot 1:d0dfbce63a89 4307 /**
elmot 1:d0dfbce63a89 4308 * @brief Checks if HSI ready interrupt source is enabled or disabled.
elmot 1:d0dfbce63a89 4309 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
elmot 1:d0dfbce63a89 4310 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 4311 */
elmot 1:d0dfbce63a89 4312 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
elmot 1:d0dfbce63a89 4313 {
elmot 1:d0dfbce63a89 4314 return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE));
elmot 1:d0dfbce63a89 4315 }
elmot 1:d0dfbce63a89 4316
elmot 1:d0dfbce63a89 4317 /**
elmot 1:d0dfbce63a89 4318 * @brief Checks if HSE ready interrupt source is enabled or disabled.
elmot 1:d0dfbce63a89 4319 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
elmot 1:d0dfbce63a89 4320 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 4321 */
elmot 1:d0dfbce63a89 4322 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
elmot 1:d0dfbce63a89 4323 {
elmot 1:d0dfbce63a89 4324 return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE));
elmot 1:d0dfbce63a89 4325 }
elmot 1:d0dfbce63a89 4326
elmot 1:d0dfbce63a89 4327 /**
elmot 1:d0dfbce63a89 4328 * @brief Checks if PLL ready interrupt source is enabled or disabled.
elmot 1:d0dfbce63a89 4329 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
elmot 1:d0dfbce63a89 4330 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 4331 */
elmot 1:d0dfbce63a89 4332 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
elmot 1:d0dfbce63a89 4333 {
elmot 1:d0dfbce63a89 4334 return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE));
elmot 1:d0dfbce63a89 4335 }
elmot 1:d0dfbce63a89 4336
elmot 1:d0dfbce63a89 4337 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 4338 /**
elmot 1:d0dfbce63a89 4339 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
elmot 1:d0dfbce63a89 4340 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
elmot 1:d0dfbce63a89 4341 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 4342 */
elmot 1:d0dfbce63a89 4343 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
elmot 1:d0dfbce63a89 4344 {
elmot 1:d0dfbce63a89 4345 return (READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE));
elmot 1:d0dfbce63a89 4346 }
elmot 1:d0dfbce63a89 4347 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 4348
elmot 1:d0dfbce63a89 4349 /**
elmot 1:d0dfbce63a89 4350 * @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled.
elmot 1:d0dfbce63a89 4351 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY
elmot 1:d0dfbce63a89 4352 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 4353 */
elmot 1:d0dfbce63a89 4354 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
elmot 1:d0dfbce63a89 4355 {
elmot 1:d0dfbce63a89 4356 return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE));
elmot 1:d0dfbce63a89 4357 }
elmot 1:d0dfbce63a89 4358
elmot 1:d0dfbce63a89 4359 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 4360 /**
elmot 1:d0dfbce63a89 4361 * @brief Checks if PLLSAI2 ready interrupt source is enabled or disabled.
elmot 1:d0dfbce63a89 4362 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_IsEnabledIT_PLLSAI2RDY
elmot 1:d0dfbce63a89 4363 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 4364 */
elmot 1:d0dfbce63a89 4365 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)
elmot 1:d0dfbce63a89 4366 {
elmot 1:d0dfbce63a89 4367 return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == (RCC_CIER_PLLSAI2RDYIE));
elmot 1:d0dfbce63a89 4368 }
elmot 1:d0dfbce63a89 4369
elmot 1:d0dfbce63a89 4370 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 4371 /**
elmot 1:d0dfbce63a89 4372 * @brief Checks if LSECSS interrupt source is enabled or disabled.
elmot 1:d0dfbce63a89 4373 * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
elmot 1:d0dfbce63a89 4374 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 4375 */
elmot 1:d0dfbce63a89 4376 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
elmot 1:d0dfbce63a89 4377 {
elmot 1:d0dfbce63a89 4378 return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE));
elmot 1:d0dfbce63a89 4379 }
elmot 1:d0dfbce63a89 4380
elmot 1:d0dfbce63a89 4381 /**
elmot 1:d0dfbce63a89 4382 * @}
elmot 1:d0dfbce63a89 4383 */
elmot 1:d0dfbce63a89 4384
elmot 1:d0dfbce63a89 4385 #if defined(USE_FULL_LL_DRIVER)
elmot 1:d0dfbce63a89 4386 /** @defgroup RCC_LL_EF_Init De-initialization function
elmot 1:d0dfbce63a89 4387 * @{
elmot 1:d0dfbce63a89 4388 */
elmot 1:d0dfbce63a89 4389 ErrorStatus LL_RCC_DeInit(void);
elmot 1:d0dfbce63a89 4390 /**
elmot 1:d0dfbce63a89 4391 * @}
elmot 1:d0dfbce63a89 4392 */
elmot 1:d0dfbce63a89 4393
elmot 1:d0dfbce63a89 4394 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
elmot 1:d0dfbce63a89 4395 * @{
elmot 1:d0dfbce63a89 4396 */
elmot 1:d0dfbce63a89 4397 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
elmot 1:d0dfbce63a89 4398 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
elmot 1:d0dfbce63a89 4399 #if defined(UART4) || defined(UART5)
elmot 1:d0dfbce63a89 4400 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
elmot 1:d0dfbce63a89 4401 #endif /* UART4 || UART5 */
elmot 1:d0dfbce63a89 4402 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
elmot 1:d0dfbce63a89 4403 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
elmot 1:d0dfbce63a89 4404 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
elmot 1:d0dfbce63a89 4405 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
elmot 1:d0dfbce63a89 4406 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
elmot 1:d0dfbce63a89 4407 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
elmot 1:d0dfbce63a89 4408 #if defined(USB_OTG_FS) || defined(USB)
elmot 1:d0dfbce63a89 4409 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
elmot 1:d0dfbce63a89 4410 #endif /* USB_OTG_FS || USB */
elmot 1:d0dfbce63a89 4411 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
elmot 1:d0dfbce63a89 4412 uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource);
elmot 1:d0dfbce63a89 4413 #if defined(DFSDM1_Channel0)
elmot 1:d0dfbce63a89 4414 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
elmot 1:d0dfbce63a89 4415 #endif /* DFSDM1_Channel0 */
elmot 1:d0dfbce63a89 4416 /**
elmot 1:d0dfbce63a89 4417 * @}
elmot 1:d0dfbce63a89 4418 */
elmot 1:d0dfbce63a89 4419 #endif /* USE_FULL_LL_DRIVER */
elmot 1:d0dfbce63a89 4420
elmot 1:d0dfbce63a89 4421 /**
elmot 1:d0dfbce63a89 4422 * @}
elmot 1:d0dfbce63a89 4423 */
elmot 1:d0dfbce63a89 4424
elmot 1:d0dfbce63a89 4425 /**
elmot 1:d0dfbce63a89 4426 * @}
elmot 1:d0dfbce63a89 4427 */
elmot 1:d0dfbce63a89 4428
elmot 1:d0dfbce63a89 4429 #endif /* defined(RCC) */
elmot 1:d0dfbce63a89 4430
elmot 1:d0dfbce63a89 4431 /**
elmot 1:d0dfbce63a89 4432 * @}
elmot 1:d0dfbce63a89 4433 */
elmot 1:d0dfbce63a89 4434
elmot 1:d0dfbce63a89 4435 #ifdef __cplusplus
elmot 1:d0dfbce63a89 4436 }
elmot 1:d0dfbce63a89 4437 #endif
elmot 1:d0dfbce63a89 4438
elmot 1:d0dfbce63a89 4439 #endif /* __STM32L4xx_LL_RCC_H */
elmot 1:d0dfbce63a89 4440
elmot 1:d0dfbce63a89 4441 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/