TUKS MCU Introductory course / TUKS-COURSE-TIMER

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

HAL_L476/stm32l4xx_ll_bus.h@1:d0dfbce63a89, 2017-02-24 (annotated)

Committer:
elmot
Date:
Fri Feb 24 21:13:56 2017 +0000
Revision:
1:d0dfbce63a89
Ready-to-copy

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elmot 1:d0dfbce63a89 1 /**
elmot 1:d0dfbce63a89 2 ******************************************************************************
elmot 1:d0dfbce63a89 3 * @file stm32l4xx_ll_bus.h
elmot 1:d0dfbce63a89 4 * @author MCD Application Team
elmot 1:d0dfbce63a89 5 * @version V1.5.1
elmot 1:d0dfbce63a89 6 * @date 31-May-2016
elmot 1:d0dfbce63a89 7 * @brief Header file of BUS LL module.
elmot 1:d0dfbce63a89 8
elmot 1:d0dfbce63a89 9 @verbatim
elmot 1:d0dfbce63a89 10 ##### RCC Limitations #####
elmot 1:d0dfbce63a89 11 ==============================================================================
elmot 1:d0dfbce63a89 12 [..]
elmot 1:d0dfbce63a89 13 A delay between an RCC peripheral clock enable and the effective peripheral
elmot 1:d0dfbce63a89 14 enabling should be taken into account in order to manage the peripheral read/write
elmot 1:d0dfbce63a89 15 from/to registers.
elmot 1:d0dfbce63a89 16 (+) This delay depends on the peripheral mapping.
elmot 1:d0dfbce63a89 17 (++) AHB & APB peripherals, 1 dummy read is necessary
elmot 1:d0dfbce63a89 18
elmot 1:d0dfbce63a89 19 [..]
elmot 1:d0dfbce63a89 20 Workarounds:
elmot 1:d0dfbce63a89 21 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
elmot 1:d0dfbce63a89 22 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
elmot 1:d0dfbce63a89 23
elmot 1:d0dfbce63a89 24 @endverbatim
elmot 1:d0dfbce63a89 25 ******************************************************************************
elmot 1:d0dfbce63a89 26 * @attention
elmot 1:d0dfbce63a89 27 *
elmot 1:d0dfbce63a89 28 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
elmot 1:d0dfbce63a89 29 *
elmot 1:d0dfbce63a89 30 * Redistribution and use in source and binary forms, with or without modification,
elmot 1:d0dfbce63a89 31 * are permitted provided that the following conditions are met:
elmot 1:d0dfbce63a89 32 * 1. Redistributions of source code must retain the above copyright notice,
elmot 1:d0dfbce63a89 33 * this list of conditions and the following disclaimer.
elmot 1:d0dfbce63a89 34 * 2. Redistributions in binary form must reproduce the above copyright notice,
elmot 1:d0dfbce63a89 35 * this list of conditions and the following disclaimer in the documentation
elmot 1:d0dfbce63a89 36 * and/or other materials provided with the distribution.
elmot 1:d0dfbce63a89 37 * 3. Neither the name of STMicroelectronics nor the names of its contributors
elmot 1:d0dfbce63a89 38 * may be used to endorse or promote products derived from this software
elmot 1:d0dfbce63a89 39 * without specific prior written permission.
elmot 1:d0dfbce63a89 40 *
elmot 1:d0dfbce63a89 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elmot 1:d0dfbce63a89 42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elmot 1:d0dfbce63a89 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elmot 1:d0dfbce63a89 44 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
elmot 1:d0dfbce63a89 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
elmot 1:d0dfbce63a89 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
elmot 1:d0dfbce63a89 47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
elmot 1:d0dfbce63a89 48 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
elmot 1:d0dfbce63a89 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
elmot 1:d0dfbce63a89 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elmot 1:d0dfbce63a89 51 *
elmot 1:d0dfbce63a89 52 ******************************************************************************
elmot 1:d0dfbce63a89 53 */
elmot 1:d0dfbce63a89 54
elmot 1:d0dfbce63a89 55 /* Define to prevent recursive inclusion -------------------------------------*/
elmot 1:d0dfbce63a89 56 #ifndef __STM32L4xx_LL_BUS_H
elmot 1:d0dfbce63a89 57 #define __STM32L4xx_LL_BUS_H
elmot 1:d0dfbce63a89 58
elmot 1:d0dfbce63a89 59 #ifdef __cplusplus
elmot 1:d0dfbce63a89 60 extern "C" {
elmot 1:d0dfbce63a89 61 #endif
elmot 1:d0dfbce63a89 62
elmot 1:d0dfbce63a89 63 /* Includes ------------------------------------------------------------------*/
elmot 1:d0dfbce63a89 64 #include "stm32l4xx.h"
elmot 1:d0dfbce63a89 65
elmot 1:d0dfbce63a89 66 /** @addtogroup STM32L4xx_LL_Driver
elmot 1:d0dfbce63a89 67 * @{
elmot 1:d0dfbce63a89 68 */
elmot 1:d0dfbce63a89 69
elmot 1:d0dfbce63a89 70 #if defined(RCC)
elmot 1:d0dfbce63a89 71
elmot 1:d0dfbce63a89 72 /** @defgroup BUS_LL BUS
elmot 1:d0dfbce63a89 73 * @{
elmot 1:d0dfbce63a89 74 */
elmot 1:d0dfbce63a89 75
elmot 1:d0dfbce63a89 76 /* Private types -------------------------------------------------------------*/
elmot 1:d0dfbce63a89 77 /* Private variables ---------------------------------------------------------*/
elmot 1:d0dfbce63a89 78
elmot 1:d0dfbce63a89 79 /* Private constants ---------------------------------------------------------*/
elmot 1:d0dfbce63a89 80
elmot 1:d0dfbce63a89 81 /* Private macros ------------------------------------------------------------*/
elmot 1:d0dfbce63a89 82
elmot 1:d0dfbce63a89 83 /* Exported types ------------------------------------------------------------*/
elmot 1:d0dfbce63a89 84 /* Exported constants --------------------------------------------------------*/
elmot 1:d0dfbce63a89 85 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
elmot 1:d0dfbce63a89 86 * @{
elmot 1:d0dfbce63a89 87 */
elmot 1:d0dfbce63a89 88
elmot 1:d0dfbce63a89 89 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
elmot 1:d0dfbce63a89 90 * @{
elmot 1:d0dfbce63a89 91 */
elmot 1:d0dfbce63a89 92 #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
elmot 1:d0dfbce63a89 93 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
elmot 1:d0dfbce63a89 94 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
elmot 1:d0dfbce63a89 95 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
elmot 1:d0dfbce63a89 96 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
elmot 1:d0dfbce63a89 97 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
elmot 1:d0dfbce63a89 98 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
elmot 1:d0dfbce63a89 99 /**
elmot 1:d0dfbce63a89 100 * @}
elmot 1:d0dfbce63a89 101 */
elmot 1:d0dfbce63a89 102
elmot 1:d0dfbce63a89 103 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
elmot 1:d0dfbce63a89 104 * @{
elmot 1:d0dfbce63a89 105 */
elmot 1:d0dfbce63a89 106 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
elmot 1:d0dfbce63a89 107 #define LL_AHB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
elmot 1:d0dfbce63a89 108 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
elmot 1:d0dfbce63a89 109 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
elmot 1:d0dfbce63a89 110 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
elmot 1:d0dfbce63a89 111 #if defined(GPIOD)
elmot 1:d0dfbce63a89 112 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
elmot 1:d0dfbce63a89 113 #endif /*GPIOD*/
elmot 1:d0dfbce63a89 114 #if defined(GPIOE)
elmot 1:d0dfbce63a89 115 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
elmot 1:d0dfbce63a89 116 #endif /*GPIOE*/
elmot 1:d0dfbce63a89 117 #if defined(GPIOF)
elmot 1:d0dfbce63a89 118 #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
elmot 1:d0dfbce63a89 119 #endif /* GPIOF */
elmot 1:d0dfbce63a89 120 #if defined(GPIOG)
elmot 1:d0dfbce63a89 121 #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
elmot 1:d0dfbce63a89 122 #endif /* GPIOG */
elmot 1:d0dfbce63a89 123 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
elmot 1:d0dfbce63a89 124 #if defined(USB_OTG_FS)
elmot 1:d0dfbce63a89 125 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
elmot 1:d0dfbce63a89 126 #endif /* USB_OTG_FS */
elmot 1:d0dfbce63a89 127 #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
elmot 1:d0dfbce63a89 128 #if defined(AES)
elmot 1:d0dfbce63a89 129 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
elmot 1:d0dfbce63a89 130 #endif /* AES */
elmot 1:d0dfbce63a89 131 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
elmot 1:d0dfbce63a89 132 /**
elmot 1:d0dfbce63a89 133 * @}
elmot 1:d0dfbce63a89 134 */
elmot 1:d0dfbce63a89 135
elmot 1:d0dfbce63a89 136 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
elmot 1:d0dfbce63a89 137 * @{
elmot 1:d0dfbce63a89 138 */
elmot 1:d0dfbce63a89 139 #define LL_AHB3_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
elmot 1:d0dfbce63a89 140 #if defined(FMC_Bank1_R)
elmot 1:d0dfbce63a89 141 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
elmot 1:d0dfbce63a89 142 #endif /* FMC_Bank1_R */
elmot 1:d0dfbce63a89 143 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
elmot 1:d0dfbce63a89 144 /**
elmot 1:d0dfbce63a89 145 * @}
elmot 1:d0dfbce63a89 146 */
elmot 1:d0dfbce63a89 147
elmot 1:d0dfbce63a89 148 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
elmot 1:d0dfbce63a89 149 * @{
elmot 1:d0dfbce63a89 150 */
elmot 1:d0dfbce63a89 151 #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
elmot 1:d0dfbce63a89 152 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
elmot 1:d0dfbce63a89 153 #if defined(TIM3)
elmot 1:d0dfbce63a89 154 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
elmot 1:d0dfbce63a89 155 #endif /* TIM3 */
elmot 1:d0dfbce63a89 156 #if defined(TIM4)
elmot 1:d0dfbce63a89 157 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
elmot 1:d0dfbce63a89 158 #endif /* TIM4 */
elmot 1:d0dfbce63a89 159 #if defined(TIM5)
elmot 1:d0dfbce63a89 160 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
elmot 1:d0dfbce63a89 161 #endif /* TIM5 */
elmot 1:d0dfbce63a89 162 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
elmot 1:d0dfbce63a89 163 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
elmot 1:d0dfbce63a89 164 #if defined(LCD)
elmot 1:d0dfbce63a89 165 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN
elmot 1:d0dfbce63a89 166 #endif /* LCD */
elmot 1:d0dfbce63a89 167 #if defined(RCC_APB1ENR1_RTCAPBEN)
elmot 1:d0dfbce63a89 168 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
elmot 1:d0dfbce63a89 169 #endif /* RCC_APB1ENR1_RTCAPBEN */
elmot 1:d0dfbce63a89 170 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
elmot 1:d0dfbce63a89 171 #if defined(SPI2)
elmot 1:d0dfbce63a89 172 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
elmot 1:d0dfbce63a89 173 #endif /* SPI2 */
elmot 1:d0dfbce63a89 174 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
elmot 1:d0dfbce63a89 175 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
elmot 1:d0dfbce63a89 176 #if defined(USART3)
elmot 1:d0dfbce63a89 177 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
elmot 1:d0dfbce63a89 178 #endif /* USART3 */
elmot 1:d0dfbce63a89 179 #if defined(UART4)
elmot 1:d0dfbce63a89 180 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
elmot 1:d0dfbce63a89 181 #endif /* UART4 */
elmot 1:d0dfbce63a89 182 #if defined(UART5)
elmot 1:d0dfbce63a89 183 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
elmot 1:d0dfbce63a89 184 #endif /* UART5 */
elmot 1:d0dfbce63a89 185 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
elmot 1:d0dfbce63a89 186 #if defined(I2C2)
elmot 1:d0dfbce63a89 187 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
elmot 1:d0dfbce63a89 188 #endif /* I2C2 */
elmot 1:d0dfbce63a89 189 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
elmot 1:d0dfbce63a89 190 #if defined(CRS)
elmot 1:d0dfbce63a89 191 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
elmot 1:d0dfbce63a89 192 #endif /* CRS */
elmot 1:d0dfbce63a89 193 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN
elmot 1:d0dfbce63a89 194 #if defined(USB)
elmot 1:d0dfbce63a89 195 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBFSEN
elmot 1:d0dfbce63a89 196 #endif /* USB */
elmot 1:d0dfbce63a89 197 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
elmot 1:d0dfbce63a89 198 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN
elmot 1:d0dfbce63a89 199 #define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN
elmot 1:d0dfbce63a89 200 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
elmot 1:d0dfbce63a89 201 /**
elmot 1:d0dfbce63a89 202 * @}
elmot 1:d0dfbce63a89 203 */
elmot 1:d0dfbce63a89 204
elmot 1:d0dfbce63a89 205
elmot 1:d0dfbce63a89 206 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
elmot 1:d0dfbce63a89 207 * @{
elmot 1:d0dfbce63a89 208 */
elmot 1:d0dfbce63a89 209 #define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU
elmot 1:d0dfbce63a89 210 #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
elmot 1:d0dfbce63a89 211 #define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN
elmot 1:d0dfbce63a89 212 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
elmot 1:d0dfbce63a89 213 /**
elmot 1:d0dfbce63a89 214 * @}
elmot 1:d0dfbce63a89 215 */
elmot 1:d0dfbce63a89 216
elmot 1:d0dfbce63a89 217 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
elmot 1:d0dfbce63a89 218 * @{
elmot 1:d0dfbce63a89 219 */
elmot 1:d0dfbce63a89 220 #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
elmot 1:d0dfbce63a89 221 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
elmot 1:d0dfbce63a89 222 #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN
elmot 1:d0dfbce63a89 223 #if defined(SDMMC1)
elmot 1:d0dfbce63a89 224 #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN
elmot 1:d0dfbce63a89 225 #endif /* SDMMC1 */
elmot 1:d0dfbce63a89 226 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
elmot 1:d0dfbce63a89 227 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
elmot 1:d0dfbce63a89 228 #if defined(TIM8)
elmot 1:d0dfbce63a89 229 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
elmot 1:d0dfbce63a89 230 #endif /* TIM8 */
elmot 1:d0dfbce63a89 231 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
elmot 1:d0dfbce63a89 232 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
elmot 1:d0dfbce63a89 233 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
elmot 1:d0dfbce63a89 234 #if defined(TIM17)
elmot 1:d0dfbce63a89 235 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
elmot 1:d0dfbce63a89 236 #endif /* TIM17 */
elmot 1:d0dfbce63a89 237 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
elmot 1:d0dfbce63a89 238 #if defined(SAI2)
elmot 1:d0dfbce63a89 239 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
elmot 1:d0dfbce63a89 240 #endif /* SAI2 */
elmot 1:d0dfbce63a89 241 #if defined(DFSDM1_Channel0)
elmot 1:d0dfbce63a89 242 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
elmot 1:d0dfbce63a89 243 #endif /* DFSDM1_Channel0 */
elmot 1:d0dfbce63a89 244 /**
elmot 1:d0dfbce63a89 245 * @}
elmot 1:d0dfbce63a89 246 */
elmot 1:d0dfbce63a89 247
elmot 1:d0dfbce63a89 248 /** Legacy definitions for compatibility purpose
elmot 1:d0dfbce63a89 249 @cond 0
elmot 1:d0dfbce63a89 250 */
elmot 1:d0dfbce63a89 251 #if defined(DFSDM1_Channel0)
elmot 1:d0dfbce63a89 252 #define LL_APB2_GRP1_PERIPH_DFSDM LL_APB2_GRP1_PERIPH_DFSDM1
elmot 1:d0dfbce63a89 253 #endif /* DFSDM1_Channel0 */
elmot 1:d0dfbce63a89 254 /**
elmot 1:d0dfbce63a89 255 @endcond
elmot 1:d0dfbce63a89 256 */
elmot 1:d0dfbce63a89 257
elmot 1:d0dfbce63a89 258 /**
elmot 1:d0dfbce63a89 259 * @}
elmot 1:d0dfbce63a89 260 */
elmot 1:d0dfbce63a89 261
elmot 1:d0dfbce63a89 262 /* Exported macro ------------------------------------------------------------*/
elmot 1:d0dfbce63a89 263 /* Exported functions --------------------------------------------------------*/
elmot 1:d0dfbce63a89 264 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
elmot 1:d0dfbce63a89 265 * @{
elmot 1:d0dfbce63a89 266 */
elmot 1:d0dfbce63a89 267
elmot 1:d0dfbce63a89 268 /** @defgroup BUS_LL_EF_AHB1 AHB1
elmot 1:d0dfbce63a89 269 * @{
elmot 1:d0dfbce63a89 270 */
elmot 1:d0dfbce63a89 271
elmot 1:d0dfbce63a89 272 /**
elmot 1:d0dfbce63a89 273 * @brief Enable AHB1 peripherals clock.
elmot 1:d0dfbce63a89 274 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 275 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 276 * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 277 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 278 * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock
elmot 1:d0dfbce63a89 279 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 280 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
elmot 1:d0dfbce63a89 281 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
elmot 1:d0dfbce63a89 282 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
elmot 1:d0dfbce63a89 283 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
elmot 1:d0dfbce63a89 284 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
elmot 1:d0dfbce63a89 285 *
elmot 1:d0dfbce63a89 286 * @retval None
elmot 1:d0dfbce63a89 287 */
elmot 1:d0dfbce63a89 288 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 289 {
elmot 1:d0dfbce63a89 290 __IO uint32_t tmpreg;
elmot 1:d0dfbce63a89 291 SET_BIT(RCC->AHB1ENR, Periphs);
elmot 1:d0dfbce63a89 292 /* Delay after an RCC peripheral clock enabling */
elmot 1:d0dfbce63a89 293 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
elmot 1:d0dfbce63a89 294 (void)tmpreg;
elmot 1:d0dfbce63a89 295 }
elmot 1:d0dfbce63a89 296
elmot 1:d0dfbce63a89 297 /**
elmot 1:d0dfbce63a89 298 * @brief Check if AHB1 peripheral clock is enabled or not
elmot 1:d0dfbce63a89 299 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 300 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 301 * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 302 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 303 * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock
elmot 1:d0dfbce63a89 304 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 305 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
elmot 1:d0dfbce63a89 306 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
elmot 1:d0dfbce63a89 307 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
elmot 1:d0dfbce63a89 308 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
elmot 1:d0dfbce63a89 309 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
elmot 1:d0dfbce63a89 310 *
elmot 1:d0dfbce63a89 311 * @retval State of Periphs (1 or 0).
elmot 1:d0dfbce63a89 312 */
elmot 1:d0dfbce63a89 313 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 314 {
elmot 1:d0dfbce63a89 315 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
elmot 1:d0dfbce63a89 316 }
elmot 1:d0dfbce63a89 317
elmot 1:d0dfbce63a89 318 /**
elmot 1:d0dfbce63a89 319 * @brief Disable AHB1 peripherals clock.
elmot 1:d0dfbce63a89 320 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 321 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 322 * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 323 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 324 * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock
elmot 1:d0dfbce63a89 325 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 326 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
elmot 1:d0dfbce63a89 327 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
elmot 1:d0dfbce63a89 328 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
elmot 1:d0dfbce63a89 329 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
elmot 1:d0dfbce63a89 330 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
elmot 1:d0dfbce63a89 331 *
elmot 1:d0dfbce63a89 332 * @retval None
elmot 1:d0dfbce63a89 333 */
elmot 1:d0dfbce63a89 334 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 335 {
elmot 1:d0dfbce63a89 336 CLEAR_BIT(RCC->AHB1ENR, Periphs);
elmot 1:d0dfbce63a89 337 }
elmot 1:d0dfbce63a89 338
elmot 1:d0dfbce63a89 339 /**
elmot 1:d0dfbce63a89 340 * @brief Force AHB1 peripherals reset.
elmot 1:d0dfbce63a89 341 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 342 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 343 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 344 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 345 * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset
elmot 1:d0dfbce63a89 346 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 347 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
elmot 1:d0dfbce63a89 348 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
elmot 1:d0dfbce63a89 349 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
elmot 1:d0dfbce63a89 350 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
elmot 1:d0dfbce63a89 351 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
elmot 1:d0dfbce63a89 352 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
elmot 1:d0dfbce63a89 353 *
elmot 1:d0dfbce63a89 354 * @retval None
elmot 1:d0dfbce63a89 355 */
elmot 1:d0dfbce63a89 356 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
elmot 1:d0dfbce63a89 357 {
elmot 1:d0dfbce63a89 358 SET_BIT(RCC->AHB1RSTR, Periphs);
elmot 1:d0dfbce63a89 359 }
elmot 1:d0dfbce63a89 360
elmot 1:d0dfbce63a89 361 /**
elmot 1:d0dfbce63a89 362 * @brief Release AHB1 peripherals reset.
elmot 1:d0dfbce63a89 363 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 364 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 365 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 366 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 367 * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset
elmot 1:d0dfbce63a89 368 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 369 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
elmot 1:d0dfbce63a89 370 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
elmot 1:d0dfbce63a89 371 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
elmot 1:d0dfbce63a89 372 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
elmot 1:d0dfbce63a89 373 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
elmot 1:d0dfbce63a89 374 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
elmot 1:d0dfbce63a89 375 *
elmot 1:d0dfbce63a89 376 * @retval None
elmot 1:d0dfbce63a89 377 */
elmot 1:d0dfbce63a89 378 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
elmot 1:d0dfbce63a89 379 {
elmot 1:d0dfbce63a89 380 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
elmot 1:d0dfbce63a89 381 }
elmot 1:d0dfbce63a89 382
elmot 1:d0dfbce63a89 383 /**
elmot 1:d0dfbce63a89 384 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
elmot 1:d0dfbce63a89 385 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 386 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 387 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 388 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 389 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 390 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep
elmot 1:d0dfbce63a89 391 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 392 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
elmot 1:d0dfbce63a89 393 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
elmot 1:d0dfbce63a89 394 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
elmot 1:d0dfbce63a89 395 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
elmot 1:d0dfbce63a89 396 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
elmot 1:d0dfbce63a89 397 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
elmot 1:d0dfbce63a89 398 *
elmot 1:d0dfbce63a89 399 * @retval None
elmot 1:d0dfbce63a89 400 */
elmot 1:d0dfbce63a89 401 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
elmot 1:d0dfbce63a89 402 {
elmot 1:d0dfbce63a89 403 __IO uint32_t tmpreg;
elmot 1:d0dfbce63a89 404 SET_BIT(RCC->AHB1SMENR, Periphs);
elmot 1:d0dfbce63a89 405 /* Delay after an RCC peripheral clock enabling */
elmot 1:d0dfbce63a89 406 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
elmot 1:d0dfbce63a89 407 (void)tmpreg;
elmot 1:d0dfbce63a89 408 }
elmot 1:d0dfbce63a89 409
elmot 1:d0dfbce63a89 410 /**
elmot 1:d0dfbce63a89 411 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
elmot 1:d0dfbce63a89 412 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 413 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 414 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 415 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 416 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 417 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep
elmot 1:d0dfbce63a89 418 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 419 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
elmot 1:d0dfbce63a89 420 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
elmot 1:d0dfbce63a89 421 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
elmot 1:d0dfbce63a89 422 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
elmot 1:d0dfbce63a89 423 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
elmot 1:d0dfbce63a89 424 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
elmot 1:d0dfbce63a89 425 *
elmot 1:d0dfbce63a89 426 * @retval None
elmot 1:d0dfbce63a89 427 */
elmot 1:d0dfbce63a89 428 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
elmot 1:d0dfbce63a89 429 {
elmot 1:d0dfbce63a89 430 CLEAR_BIT(RCC->AHB1SMENR, Periphs);
elmot 1:d0dfbce63a89 431 }
elmot 1:d0dfbce63a89 432
elmot 1:d0dfbce63a89 433 /**
elmot 1:d0dfbce63a89 434 * @}
elmot 1:d0dfbce63a89 435 */
elmot 1:d0dfbce63a89 436
elmot 1:d0dfbce63a89 437 /** @defgroup BUS_LL_EF_AHB2 AHB2
elmot 1:d0dfbce63a89 438 * @{
elmot 1:d0dfbce63a89 439 */
elmot 1:d0dfbce63a89 440
elmot 1:d0dfbce63a89 441 /**
elmot 1:d0dfbce63a89 442 * @brief Enable AHB2 peripherals clock.
elmot 1:d0dfbce63a89 443 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 444 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 445 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 446 * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 447 * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 448 * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 449 * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 450 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 451 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 452 * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 453 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 454 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock
elmot 1:d0dfbce63a89 455 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 456 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
elmot 1:d0dfbce63a89 457 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
elmot 1:d0dfbce63a89 458 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
elmot 1:d0dfbce63a89 459 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
elmot 1:d0dfbce63a89 460 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
elmot 1:d0dfbce63a89 461 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
elmot 1:d0dfbce63a89 462 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
elmot 1:d0dfbce63a89 463 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
elmot 1:d0dfbce63a89 464 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
elmot 1:d0dfbce63a89 465 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
elmot 1:d0dfbce63a89 466 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
elmot 1:d0dfbce63a89 467 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
elmot 1:d0dfbce63a89 468 *
elmot 1:d0dfbce63a89 469 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 470 * @retval None
elmot 1:d0dfbce63a89 471 */
elmot 1:d0dfbce63a89 472 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 473 {
elmot 1:d0dfbce63a89 474 __IO uint32_t tmpreg;
elmot 1:d0dfbce63a89 475 SET_BIT(RCC->AHB2ENR, Periphs);
elmot 1:d0dfbce63a89 476 /* Delay after an RCC peripheral clock enabling */
elmot 1:d0dfbce63a89 477 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
elmot 1:d0dfbce63a89 478 (void)tmpreg;
elmot 1:d0dfbce63a89 479 }
elmot 1:d0dfbce63a89 480
elmot 1:d0dfbce63a89 481 /**
elmot 1:d0dfbce63a89 482 * @brief Check if AHB2 peripheral clock is enabled or not
elmot 1:d0dfbce63a89 483 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 484 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 485 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 486 * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 487 * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 488 * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 489 * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 490 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 491 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 492 * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 493 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 494 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock
elmot 1:d0dfbce63a89 495 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 496 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
elmot 1:d0dfbce63a89 497 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
elmot 1:d0dfbce63a89 498 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
elmot 1:d0dfbce63a89 499 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
elmot 1:d0dfbce63a89 500 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
elmot 1:d0dfbce63a89 501 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
elmot 1:d0dfbce63a89 502 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
elmot 1:d0dfbce63a89 503 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
elmot 1:d0dfbce63a89 504 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
elmot 1:d0dfbce63a89 505 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
elmot 1:d0dfbce63a89 506 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
elmot 1:d0dfbce63a89 507 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
elmot 1:d0dfbce63a89 508 *
elmot 1:d0dfbce63a89 509 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 510 * @retval State of Periphs (1 or 0).
elmot 1:d0dfbce63a89 511 */
elmot 1:d0dfbce63a89 512 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 513 {
elmot 1:d0dfbce63a89 514 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
elmot 1:d0dfbce63a89 515 }
elmot 1:d0dfbce63a89 516
elmot 1:d0dfbce63a89 517 /**
elmot 1:d0dfbce63a89 518 * @brief Disable AHB2 peripherals clock.
elmot 1:d0dfbce63a89 519 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 520 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 521 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 522 * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 523 * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 524 * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 525 * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 526 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 527 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 528 * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 529 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 530 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock
elmot 1:d0dfbce63a89 531 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 532 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
elmot 1:d0dfbce63a89 533 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
elmot 1:d0dfbce63a89 534 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
elmot 1:d0dfbce63a89 535 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
elmot 1:d0dfbce63a89 536 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
elmot 1:d0dfbce63a89 537 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
elmot 1:d0dfbce63a89 538 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
elmot 1:d0dfbce63a89 539 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
elmot 1:d0dfbce63a89 540 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
elmot 1:d0dfbce63a89 541 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
elmot 1:d0dfbce63a89 542 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
elmot 1:d0dfbce63a89 543 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
elmot 1:d0dfbce63a89 544 *
elmot 1:d0dfbce63a89 545 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 546 * @retval None
elmot 1:d0dfbce63a89 547 */
elmot 1:d0dfbce63a89 548 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 549 {
elmot 1:d0dfbce63a89 550 CLEAR_BIT(RCC->AHB2ENR, Periphs);
elmot 1:d0dfbce63a89 551 }
elmot 1:d0dfbce63a89 552
elmot 1:d0dfbce63a89 553 /**
elmot 1:d0dfbce63a89 554 * @brief Force AHB2 peripherals reset.
elmot 1:d0dfbce63a89 555 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 556 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 557 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 558 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 559 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 560 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 561 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 562 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 563 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 564 * AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 565 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 566 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset
elmot 1:d0dfbce63a89 567 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 568 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
elmot 1:d0dfbce63a89 569 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
elmot 1:d0dfbce63a89 570 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
elmot 1:d0dfbce63a89 571 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
elmot 1:d0dfbce63a89 572 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
elmot 1:d0dfbce63a89 573 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
elmot 1:d0dfbce63a89 574 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
elmot 1:d0dfbce63a89 575 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
elmot 1:d0dfbce63a89 576 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
elmot 1:d0dfbce63a89 577 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
elmot 1:d0dfbce63a89 578 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
elmot 1:d0dfbce63a89 579 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
elmot 1:d0dfbce63a89 580 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
elmot 1:d0dfbce63a89 581 *
elmot 1:d0dfbce63a89 582 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 583 * @retval None
elmot 1:d0dfbce63a89 584 */
elmot 1:d0dfbce63a89 585 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
elmot 1:d0dfbce63a89 586 {
elmot 1:d0dfbce63a89 587 SET_BIT(RCC->AHB2RSTR, Periphs);
elmot 1:d0dfbce63a89 588 }
elmot 1:d0dfbce63a89 589
elmot 1:d0dfbce63a89 590 /**
elmot 1:d0dfbce63a89 591 * @brief Release AHB2 peripherals reset.
elmot 1:d0dfbce63a89 592 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 593 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 594 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 595 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 596 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 597 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 598 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 599 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 600 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 601 * AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 602 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 603 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset
elmot 1:d0dfbce63a89 604 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 605 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
elmot 1:d0dfbce63a89 606 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
elmot 1:d0dfbce63a89 607 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
elmot 1:d0dfbce63a89 608 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
elmot 1:d0dfbce63a89 609 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
elmot 1:d0dfbce63a89 610 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
elmot 1:d0dfbce63a89 611 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
elmot 1:d0dfbce63a89 612 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
elmot 1:d0dfbce63a89 613 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
elmot 1:d0dfbce63a89 614 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
elmot 1:d0dfbce63a89 615 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
elmot 1:d0dfbce63a89 616 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
elmot 1:d0dfbce63a89 617 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
elmot 1:d0dfbce63a89 618 *
elmot 1:d0dfbce63a89 619 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 620 * @retval None
elmot 1:d0dfbce63a89 621 */
elmot 1:d0dfbce63a89 622 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
elmot 1:d0dfbce63a89 623 {
elmot 1:d0dfbce63a89 624 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
elmot 1:d0dfbce63a89 625 }
elmot 1:d0dfbce63a89 626
elmot 1:d0dfbce63a89 627 /**
elmot 1:d0dfbce63a89 628 * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
elmot 1:d0dfbce63a89 629 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 630 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 631 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 632 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 633 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 634 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 635 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 636 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 637 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 638 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 639 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 640 * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 641 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep
elmot 1:d0dfbce63a89 642 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 643 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
elmot 1:d0dfbce63a89 644 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
elmot 1:d0dfbce63a89 645 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
elmot 1:d0dfbce63a89 646 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
elmot 1:d0dfbce63a89 647 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
elmot 1:d0dfbce63a89 648 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
elmot 1:d0dfbce63a89 649 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
elmot 1:d0dfbce63a89 650 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
elmot 1:d0dfbce63a89 651 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
elmot 1:d0dfbce63a89 652 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
elmot 1:d0dfbce63a89 653 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
elmot 1:d0dfbce63a89 654 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
elmot 1:d0dfbce63a89 655 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
elmot 1:d0dfbce63a89 656 *
elmot 1:d0dfbce63a89 657 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 658 * @retval None
elmot 1:d0dfbce63a89 659 */
elmot 1:d0dfbce63a89 660 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
elmot 1:d0dfbce63a89 661 {
elmot 1:d0dfbce63a89 662 __IO uint32_t tmpreg;
elmot 1:d0dfbce63a89 663 SET_BIT(RCC->AHB2SMENR, Periphs);
elmot 1:d0dfbce63a89 664 /* Delay after an RCC peripheral clock enabling */
elmot 1:d0dfbce63a89 665 tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
elmot 1:d0dfbce63a89 666 (void)tmpreg;
elmot 1:d0dfbce63a89 667 }
elmot 1:d0dfbce63a89 668
elmot 1:d0dfbce63a89 669 /**
elmot 1:d0dfbce63a89 670 * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
elmot 1:d0dfbce63a89 671 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 672 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 673 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 674 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 675 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 676 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 677 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 678 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 679 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 680 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 681 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 682 * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 683 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep
elmot 1:d0dfbce63a89 684 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 685 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
elmot 1:d0dfbce63a89 686 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
elmot 1:d0dfbce63a89 687 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
elmot 1:d0dfbce63a89 688 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
elmot 1:d0dfbce63a89 689 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
elmot 1:d0dfbce63a89 690 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
elmot 1:d0dfbce63a89 691 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
elmot 1:d0dfbce63a89 692 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
elmot 1:d0dfbce63a89 693 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
elmot 1:d0dfbce63a89 694 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
elmot 1:d0dfbce63a89 695 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
elmot 1:d0dfbce63a89 696 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
elmot 1:d0dfbce63a89 697 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
elmot 1:d0dfbce63a89 698 *
elmot 1:d0dfbce63a89 699 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 700 * @retval None
elmot 1:d0dfbce63a89 701 */
elmot 1:d0dfbce63a89 702 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
elmot 1:d0dfbce63a89 703 {
elmot 1:d0dfbce63a89 704 CLEAR_BIT(RCC->AHB2SMENR, Periphs);
elmot 1:d0dfbce63a89 705 }
elmot 1:d0dfbce63a89 706
elmot 1:d0dfbce63a89 707 /**
elmot 1:d0dfbce63a89 708 * @}
elmot 1:d0dfbce63a89 709 */
elmot 1:d0dfbce63a89 710
elmot 1:d0dfbce63a89 711 /** @defgroup BUS_LL_EF_AHB3 AHB3
elmot 1:d0dfbce63a89 712 * @{
elmot 1:d0dfbce63a89 713 */
elmot 1:d0dfbce63a89 714
elmot 1:d0dfbce63a89 715 /**
elmot 1:d0dfbce63a89 716 * @brief Enable AHB3 peripherals clock.
elmot 1:d0dfbce63a89 717 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 718 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
elmot 1:d0dfbce63a89 719 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 720 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
elmot 1:d0dfbce63a89 721 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
elmot 1:d0dfbce63a89 722 *
elmot 1:d0dfbce63a89 723 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 724 * @retval None
elmot 1:d0dfbce63a89 725 */
elmot 1:d0dfbce63a89 726 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 727 {
elmot 1:d0dfbce63a89 728 __IO uint32_t tmpreg;
elmot 1:d0dfbce63a89 729 SET_BIT(RCC->AHB3ENR, Periphs);
elmot 1:d0dfbce63a89 730 /* Delay after an RCC peripheral clock enabling */
elmot 1:d0dfbce63a89 731 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
elmot 1:d0dfbce63a89 732 (void)tmpreg;
elmot 1:d0dfbce63a89 733 }
elmot 1:d0dfbce63a89 734
elmot 1:d0dfbce63a89 735 /**
elmot 1:d0dfbce63a89 736 * @brief Check if AHB3 peripheral clock is enabled or not
elmot 1:d0dfbce63a89 737 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 738 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
elmot 1:d0dfbce63a89 739 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 740 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
elmot 1:d0dfbce63a89 741 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
elmot 1:d0dfbce63a89 742 *
elmot 1:d0dfbce63a89 743 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 744 * @retval State of Periphs (1 or 0).
elmot 1:d0dfbce63a89 745 */
elmot 1:d0dfbce63a89 746 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 747 {
elmot 1:d0dfbce63a89 748 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
elmot 1:d0dfbce63a89 749 }
elmot 1:d0dfbce63a89 750
elmot 1:d0dfbce63a89 751 /**
elmot 1:d0dfbce63a89 752 * @brief Disable AHB3 peripherals clock.
elmot 1:d0dfbce63a89 753 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 754 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
elmot 1:d0dfbce63a89 755 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 756 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
elmot 1:d0dfbce63a89 757 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
elmot 1:d0dfbce63a89 758 *
elmot 1:d0dfbce63a89 759 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 760 * @retval None
elmot 1:d0dfbce63a89 761 */
elmot 1:d0dfbce63a89 762 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 763 {
elmot 1:d0dfbce63a89 764 CLEAR_BIT(RCC->AHB3ENR, Periphs);
elmot 1:d0dfbce63a89 765 }
elmot 1:d0dfbce63a89 766
elmot 1:d0dfbce63a89 767 /**
elmot 1:d0dfbce63a89 768 * @brief Force AHB3 peripherals reset.
elmot 1:d0dfbce63a89 769 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 770 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
elmot 1:d0dfbce63a89 771 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 772 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
elmot 1:d0dfbce63a89 773 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
elmot 1:d0dfbce63a89 774 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
elmot 1:d0dfbce63a89 775 *
elmot 1:d0dfbce63a89 776 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 777 * @retval None
elmot 1:d0dfbce63a89 778 */
elmot 1:d0dfbce63a89 779 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
elmot 1:d0dfbce63a89 780 {
elmot 1:d0dfbce63a89 781 SET_BIT(RCC->AHB3RSTR, Periphs);
elmot 1:d0dfbce63a89 782 }
elmot 1:d0dfbce63a89 783
elmot 1:d0dfbce63a89 784 /**
elmot 1:d0dfbce63a89 785 * @brief Release AHB3 peripherals reset.
elmot 1:d0dfbce63a89 786 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 787 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
elmot 1:d0dfbce63a89 788 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 789 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
elmot 1:d0dfbce63a89 790 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
elmot 1:d0dfbce63a89 791 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
elmot 1:d0dfbce63a89 792 *
elmot 1:d0dfbce63a89 793 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 794 * @retval None
elmot 1:d0dfbce63a89 795 */
elmot 1:d0dfbce63a89 796 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
elmot 1:d0dfbce63a89 797 {
elmot 1:d0dfbce63a89 798 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
elmot 1:d0dfbce63a89 799 }
elmot 1:d0dfbce63a89 800
elmot 1:d0dfbce63a89 801 /**
elmot 1:d0dfbce63a89 802 * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
elmot 1:d0dfbce63a89 803 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 804 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep
elmot 1:d0dfbce63a89 805 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 806 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
elmot 1:d0dfbce63a89 807 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
elmot 1:d0dfbce63a89 808 *
elmot 1:d0dfbce63a89 809 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 810 * @retval None
elmot 1:d0dfbce63a89 811 */
elmot 1:d0dfbce63a89 812 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
elmot 1:d0dfbce63a89 813 {
elmot 1:d0dfbce63a89 814 __IO uint32_t tmpreg;
elmot 1:d0dfbce63a89 815 SET_BIT(RCC->AHB3SMENR, Periphs);
elmot 1:d0dfbce63a89 816 /* Delay after an RCC peripheral clock enabling */
elmot 1:d0dfbce63a89 817 tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
elmot 1:d0dfbce63a89 818 (void)tmpreg;
elmot 1:d0dfbce63a89 819 }
elmot 1:d0dfbce63a89 820
elmot 1:d0dfbce63a89 821 /**
elmot 1:d0dfbce63a89 822 * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
elmot 1:d0dfbce63a89 823 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 824 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep
elmot 1:d0dfbce63a89 825 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 826 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
elmot 1:d0dfbce63a89 827 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
elmot 1:d0dfbce63a89 828 *
elmot 1:d0dfbce63a89 829 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 830 * @retval None
elmot 1:d0dfbce63a89 831 */
elmot 1:d0dfbce63a89 832 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
elmot 1:d0dfbce63a89 833 {
elmot 1:d0dfbce63a89 834 CLEAR_BIT(RCC->AHB3SMENR, Periphs);
elmot 1:d0dfbce63a89 835 }
elmot 1:d0dfbce63a89 836
elmot 1:d0dfbce63a89 837 /**
elmot 1:d0dfbce63a89 838 * @}
elmot 1:d0dfbce63a89 839 */
elmot 1:d0dfbce63a89 840
elmot 1:d0dfbce63a89 841 /** @defgroup BUS_LL_EF_APB1 APB1
elmot 1:d0dfbce63a89 842 * @{
elmot 1:d0dfbce63a89 843 */
elmot 1:d0dfbce63a89 844
elmot 1:d0dfbce63a89 845 /**
elmot 1:d0dfbce63a89 846 * @brief Enable APB1 peripherals clock.
elmot 1:d0dfbce63a89 847 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 848 * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 849 * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 850 * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 851 * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 852 * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 853 * APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 854 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 855 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 856 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 857 * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 858 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 859 * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 860 * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 861 * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 862 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 863 * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 864 * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 865 * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 866 * APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 867 * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 868 * APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 869 * APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 870 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
elmot 1:d0dfbce63a89 871 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 872 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
elmot 1:d0dfbce63a89 873 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
elmot 1:d0dfbce63a89 874 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
elmot 1:d0dfbce63a89 875 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
elmot 1:d0dfbce63a89 876 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
elmot 1:d0dfbce63a89 877 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
elmot 1:d0dfbce63a89 878 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
elmot 1:d0dfbce63a89 879 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
elmot 1:d0dfbce63a89 880 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
elmot 1:d0dfbce63a89 881 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
elmot 1:d0dfbce63a89 882 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
elmot 1:d0dfbce63a89 883 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
elmot 1:d0dfbce63a89 884 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
elmot 1:d0dfbce63a89 885 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
elmot 1:d0dfbce63a89 886 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
elmot 1:d0dfbce63a89 887 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
elmot 1:d0dfbce63a89 888 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
elmot 1:d0dfbce63a89 889 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
elmot 1:d0dfbce63a89 890 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
elmot 1:d0dfbce63a89 891 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
elmot 1:d0dfbce63a89 892 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
elmot 1:d0dfbce63a89 893 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
elmot 1:d0dfbce63a89 894 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
elmot 1:d0dfbce63a89 895 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
elmot 1:d0dfbce63a89 896 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
elmot 1:d0dfbce63a89 897 *
elmot 1:d0dfbce63a89 898 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 899 * @retval None
elmot 1:d0dfbce63a89 900 */
elmot 1:d0dfbce63a89 901 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 902 {
elmot 1:d0dfbce63a89 903 __IO uint32_t tmpreg;
elmot 1:d0dfbce63a89 904 SET_BIT(RCC->APB1ENR1, Periphs);
elmot 1:d0dfbce63a89 905 /* Delay after an RCC peripheral clock enabling */
elmot 1:d0dfbce63a89 906 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
elmot 1:d0dfbce63a89 907 (void)tmpreg;
elmot 1:d0dfbce63a89 908 }
elmot 1:d0dfbce63a89 909
elmot 1:d0dfbce63a89 910 /**
elmot 1:d0dfbce63a89 911 * @brief Enable APB1 peripherals clock.
elmot 1:d0dfbce63a89 912 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
elmot 1:d0dfbce63a89 913 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock\n
elmot 1:d0dfbce63a89 914 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
elmot 1:d0dfbce63a89 915 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 916 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
elmot 1:d0dfbce63a89 917 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
elmot 1:d0dfbce63a89 918 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
elmot 1:d0dfbce63a89 919 * @retval None
elmot 1:d0dfbce63a89 920 */
elmot 1:d0dfbce63a89 921 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 922 {
elmot 1:d0dfbce63a89 923 __IO uint32_t tmpreg;
elmot 1:d0dfbce63a89 924 SET_BIT(RCC->APB1ENR2, Periphs);
elmot 1:d0dfbce63a89 925 /* Delay after an RCC peripheral clock enabling */
elmot 1:d0dfbce63a89 926 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
elmot 1:d0dfbce63a89 927 (void)tmpreg;
elmot 1:d0dfbce63a89 928 }
elmot 1:d0dfbce63a89 929
elmot 1:d0dfbce63a89 930 /**
elmot 1:d0dfbce63a89 931 * @brief Check if APB1 peripheral clock is enabled or not
elmot 1:d0dfbce63a89 932 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 933 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 934 * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 935 * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 936 * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 937 * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 938 * APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 939 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 940 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 941 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 942 * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 943 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 944 * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 945 * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 946 * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 947 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 948 * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 949 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 950 * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 951 * APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 952 * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 953 * APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 954 * APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 955 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
elmot 1:d0dfbce63a89 956 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 957 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
elmot 1:d0dfbce63a89 958 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
elmot 1:d0dfbce63a89 959 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
elmot 1:d0dfbce63a89 960 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
elmot 1:d0dfbce63a89 961 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
elmot 1:d0dfbce63a89 962 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
elmot 1:d0dfbce63a89 963 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
elmot 1:d0dfbce63a89 964 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
elmot 1:d0dfbce63a89 965 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
elmot 1:d0dfbce63a89 966 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
elmot 1:d0dfbce63a89 967 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
elmot 1:d0dfbce63a89 968 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
elmot 1:d0dfbce63a89 969 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
elmot 1:d0dfbce63a89 970 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
elmot 1:d0dfbce63a89 971 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
elmot 1:d0dfbce63a89 972 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
elmot 1:d0dfbce63a89 973 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
elmot 1:d0dfbce63a89 974 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
elmot 1:d0dfbce63a89 975 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
elmot 1:d0dfbce63a89 976 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
elmot 1:d0dfbce63a89 977 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
elmot 1:d0dfbce63a89 978 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
elmot 1:d0dfbce63a89 979 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
elmot 1:d0dfbce63a89 980 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
elmot 1:d0dfbce63a89 981 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
elmot 1:d0dfbce63a89 982 *
elmot 1:d0dfbce63a89 983 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 984 * @retval State of Periphs (1 or 0).
elmot 1:d0dfbce63a89 985 */
elmot 1:d0dfbce63a89 986 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 987 {
elmot 1:d0dfbce63a89 988 return (READ_BIT(RCC->APB1ENR1, Periphs) == Periphs);
elmot 1:d0dfbce63a89 989 }
elmot 1:d0dfbce63a89 990
elmot 1:d0dfbce63a89 991 /**
elmot 1:d0dfbce63a89 992 * @brief Check if APB1 peripheral clock is enabled or not
elmot 1:d0dfbce63a89 993 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
elmot 1:d0dfbce63a89 994 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock\n
elmot 1:d0dfbce63a89 995 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
elmot 1:d0dfbce63a89 996 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 997 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
elmot 1:d0dfbce63a89 998 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
elmot 1:d0dfbce63a89 999 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
elmot 1:d0dfbce63a89 1000 * @retval State of Periphs (1 or 0).
elmot 1:d0dfbce63a89 1001 */
elmot 1:d0dfbce63a89 1002 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 1003 {
elmot 1:d0dfbce63a89 1004 return (READ_BIT(RCC->APB1ENR2, Periphs) == Periphs);
elmot 1:d0dfbce63a89 1005 }
elmot 1:d0dfbce63a89 1006
elmot 1:d0dfbce63a89 1007 /**
elmot 1:d0dfbce63a89 1008 * @brief Disable APB1 peripherals clock.
elmot 1:d0dfbce63a89 1009 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1010 * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1011 * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1012 * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1013 * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1014 * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1015 * APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1016 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1017 * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1018 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1019 * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1020 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1021 * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1022 * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1023 * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1024 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1025 * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1026 * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1027 * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1028 * APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1029 * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1030 * APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1031 * APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1032 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
elmot 1:d0dfbce63a89 1033 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1034 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
elmot 1:d0dfbce63a89 1035 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
elmot 1:d0dfbce63a89 1036 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
elmot 1:d0dfbce63a89 1037 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
elmot 1:d0dfbce63a89 1038 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
elmot 1:d0dfbce63a89 1039 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
elmot 1:d0dfbce63a89 1040 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
elmot 1:d0dfbce63a89 1041 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
elmot 1:d0dfbce63a89 1042 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
elmot 1:d0dfbce63a89 1043 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
elmot 1:d0dfbce63a89 1044 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
elmot 1:d0dfbce63a89 1045 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
elmot 1:d0dfbce63a89 1046 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
elmot 1:d0dfbce63a89 1047 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
elmot 1:d0dfbce63a89 1048 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
elmot 1:d0dfbce63a89 1049 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
elmot 1:d0dfbce63a89 1050 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
elmot 1:d0dfbce63a89 1051 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
elmot 1:d0dfbce63a89 1052 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
elmot 1:d0dfbce63a89 1053 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
elmot 1:d0dfbce63a89 1054 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
elmot 1:d0dfbce63a89 1055 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
elmot 1:d0dfbce63a89 1056 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
elmot 1:d0dfbce63a89 1057 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
elmot 1:d0dfbce63a89 1058 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
elmot 1:d0dfbce63a89 1059 *
elmot 1:d0dfbce63a89 1060 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 1061 * @retval None
elmot 1:d0dfbce63a89 1062 */
elmot 1:d0dfbce63a89 1063 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 1064 {
elmot 1:d0dfbce63a89 1065 CLEAR_BIT(RCC->APB1ENR1, Periphs);
elmot 1:d0dfbce63a89 1066 }
elmot 1:d0dfbce63a89 1067
elmot 1:d0dfbce63a89 1068 /**
elmot 1:d0dfbce63a89 1069 * @brief Disable APB1 peripherals clock.
elmot 1:d0dfbce63a89 1070 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
elmot 1:d0dfbce63a89 1071 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock\n
elmot 1:d0dfbce63a89 1072 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
elmot 1:d0dfbce63a89 1073 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1074 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
elmot 1:d0dfbce63a89 1075 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
elmot 1:d0dfbce63a89 1076 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
elmot 1:d0dfbce63a89 1077 * @retval None
elmot 1:d0dfbce63a89 1078 */
elmot 1:d0dfbce63a89 1079 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 1080 {
elmot 1:d0dfbce63a89 1081 CLEAR_BIT(RCC->APB1ENR2, Periphs);
elmot 1:d0dfbce63a89 1082 }
elmot 1:d0dfbce63a89 1083
elmot 1:d0dfbce63a89 1084 /**
elmot 1:d0dfbce63a89 1085 * @brief Force APB1 peripherals reset.
elmot 1:d0dfbce63a89 1086 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1087 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1088 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1089 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1090 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1091 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1092 * APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1093 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1094 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1095 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1096 * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1097 * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1098 * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1099 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1100 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1101 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1102 * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1103 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1104 * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1105 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1106 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1107 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
elmot 1:d0dfbce63a89 1108 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1109 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
elmot 1:d0dfbce63a89 1110 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
elmot 1:d0dfbce63a89 1111 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
elmot 1:d0dfbce63a89 1112 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
elmot 1:d0dfbce63a89 1113 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
elmot 1:d0dfbce63a89 1114 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
elmot 1:d0dfbce63a89 1115 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
elmot 1:d0dfbce63a89 1116 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
elmot 1:d0dfbce63a89 1117 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
elmot 1:d0dfbce63a89 1118 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
elmot 1:d0dfbce63a89 1119 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
elmot 1:d0dfbce63a89 1120 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
elmot 1:d0dfbce63a89 1121 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
elmot 1:d0dfbce63a89 1122 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
elmot 1:d0dfbce63a89 1123 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
elmot 1:d0dfbce63a89 1124 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
elmot 1:d0dfbce63a89 1125 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
elmot 1:d0dfbce63a89 1126 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
elmot 1:d0dfbce63a89 1127 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
elmot 1:d0dfbce63a89 1128 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
elmot 1:d0dfbce63a89 1129 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
elmot 1:d0dfbce63a89 1130 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
elmot 1:d0dfbce63a89 1131 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
elmot 1:d0dfbce63a89 1132 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
elmot 1:d0dfbce63a89 1133 *
elmot 1:d0dfbce63a89 1134 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 1135 * @retval None
elmot 1:d0dfbce63a89 1136 */
elmot 1:d0dfbce63a89 1137 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
elmot 1:d0dfbce63a89 1138 {
elmot 1:d0dfbce63a89 1139 SET_BIT(RCC->APB1RSTR1, Periphs);
elmot 1:d0dfbce63a89 1140 }
elmot 1:d0dfbce63a89 1141
elmot 1:d0dfbce63a89 1142 /**
elmot 1:d0dfbce63a89 1143 * @brief Force APB1 peripherals reset.
elmot 1:d0dfbce63a89 1144 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
elmot 1:d0dfbce63a89 1145 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset\n
elmot 1:d0dfbce63a89 1146 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
elmot 1:d0dfbce63a89 1147 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1148 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
elmot 1:d0dfbce63a89 1149 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
elmot 1:d0dfbce63a89 1150 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
elmot 1:d0dfbce63a89 1151 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
elmot 1:d0dfbce63a89 1152 * @retval None
elmot 1:d0dfbce63a89 1153 */
elmot 1:d0dfbce63a89 1154 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
elmot 1:d0dfbce63a89 1155 {
elmot 1:d0dfbce63a89 1156 SET_BIT(RCC->APB1RSTR2, Periphs);
elmot 1:d0dfbce63a89 1157 }
elmot 1:d0dfbce63a89 1158
elmot 1:d0dfbce63a89 1159 /**
elmot 1:d0dfbce63a89 1160 * @brief Release APB1 peripherals reset.
elmot 1:d0dfbce63a89 1161 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1162 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1163 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1164 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1165 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1166 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1167 * APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1168 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1169 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1170 * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1171 * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1172 * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1173 * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1174 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1175 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1176 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1177 * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1178 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1179 * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1180 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1181 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1182 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
elmot 1:d0dfbce63a89 1183 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1184 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
elmot 1:d0dfbce63a89 1185 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
elmot 1:d0dfbce63a89 1186 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
elmot 1:d0dfbce63a89 1187 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
elmot 1:d0dfbce63a89 1188 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
elmot 1:d0dfbce63a89 1189 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
elmot 1:d0dfbce63a89 1190 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
elmot 1:d0dfbce63a89 1191 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
elmot 1:d0dfbce63a89 1192 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
elmot 1:d0dfbce63a89 1193 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
elmot 1:d0dfbce63a89 1194 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
elmot 1:d0dfbce63a89 1195 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
elmot 1:d0dfbce63a89 1196 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
elmot 1:d0dfbce63a89 1197 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
elmot 1:d0dfbce63a89 1198 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
elmot 1:d0dfbce63a89 1199 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
elmot 1:d0dfbce63a89 1200 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
elmot 1:d0dfbce63a89 1201 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
elmot 1:d0dfbce63a89 1202 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
elmot 1:d0dfbce63a89 1203 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
elmot 1:d0dfbce63a89 1204 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
elmot 1:d0dfbce63a89 1205 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
elmot 1:d0dfbce63a89 1206 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
elmot 1:d0dfbce63a89 1207 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
elmot 1:d0dfbce63a89 1208 *
elmot 1:d0dfbce63a89 1209 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 1210 * @retval None
elmot 1:d0dfbce63a89 1211 */
elmot 1:d0dfbce63a89 1212 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
elmot 1:d0dfbce63a89 1213 {
elmot 1:d0dfbce63a89 1214 CLEAR_BIT(RCC->APB1RSTR1, Periphs);
elmot 1:d0dfbce63a89 1215 }
elmot 1:d0dfbce63a89 1216
elmot 1:d0dfbce63a89 1217 /**
elmot 1:d0dfbce63a89 1218 * @brief Release APB1 peripherals reset.
elmot 1:d0dfbce63a89 1219 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
elmot 1:d0dfbce63a89 1220 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset\n
elmot 1:d0dfbce63a89 1221 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
elmot 1:d0dfbce63a89 1222 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1223 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
elmot 1:d0dfbce63a89 1224 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
elmot 1:d0dfbce63a89 1225 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
elmot 1:d0dfbce63a89 1226 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
elmot 1:d0dfbce63a89 1227 * @retval None
elmot 1:d0dfbce63a89 1228 */
elmot 1:d0dfbce63a89 1229 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
elmot 1:d0dfbce63a89 1230 {
elmot 1:d0dfbce63a89 1231 CLEAR_BIT(RCC->APB1RSTR2, Periphs);
elmot 1:d0dfbce63a89 1232 }
elmot 1:d0dfbce63a89 1233
elmot 1:d0dfbce63a89 1234 /**
elmot 1:d0dfbce63a89 1235 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
elmot 1:d0dfbce63a89 1236 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1237 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1238 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1239 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1240 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1241 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1242 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1243 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1244 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1245 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1246 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1247 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1248 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1249 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1250 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1251 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1252 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1253 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1254 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1255 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1256 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1257 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1258 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1259 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
elmot 1:d0dfbce63a89 1260 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1261 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
elmot 1:d0dfbce63a89 1262 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
elmot 1:d0dfbce63a89 1263 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
elmot 1:d0dfbce63a89 1264 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
elmot 1:d0dfbce63a89 1265 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
elmot 1:d0dfbce63a89 1266 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
elmot 1:d0dfbce63a89 1267 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
elmot 1:d0dfbce63a89 1268 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
elmot 1:d0dfbce63a89 1269 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
elmot 1:d0dfbce63a89 1270 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
elmot 1:d0dfbce63a89 1271 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
elmot 1:d0dfbce63a89 1272 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
elmot 1:d0dfbce63a89 1273 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
elmot 1:d0dfbce63a89 1274 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
elmot 1:d0dfbce63a89 1275 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
elmot 1:d0dfbce63a89 1276 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
elmot 1:d0dfbce63a89 1277 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
elmot 1:d0dfbce63a89 1278 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
elmot 1:d0dfbce63a89 1279 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
elmot 1:d0dfbce63a89 1280 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
elmot 1:d0dfbce63a89 1281 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
elmot 1:d0dfbce63a89 1282 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
elmot 1:d0dfbce63a89 1283 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
elmot 1:d0dfbce63a89 1284 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
elmot 1:d0dfbce63a89 1285 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
elmot 1:d0dfbce63a89 1286 *
elmot 1:d0dfbce63a89 1287 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 1288 * @retval None
elmot 1:d0dfbce63a89 1289 */
elmot 1:d0dfbce63a89 1290 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
elmot 1:d0dfbce63a89 1291 {
elmot 1:d0dfbce63a89 1292 __IO uint32_t tmpreg;
elmot 1:d0dfbce63a89 1293 SET_BIT(RCC->APB1SMENR1, Periphs);
elmot 1:d0dfbce63a89 1294 /* Delay after an RCC peripheral clock enabling */
elmot 1:d0dfbce63a89 1295 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
elmot 1:d0dfbce63a89 1296 (void)tmpreg;
elmot 1:d0dfbce63a89 1297 }
elmot 1:d0dfbce63a89 1298
elmot 1:d0dfbce63a89 1299 /**
elmot 1:d0dfbce63a89 1300 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
elmot 1:d0dfbce63a89 1301 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1302 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1303 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep
elmot 1:d0dfbce63a89 1304 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1305 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
elmot 1:d0dfbce63a89 1306 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
elmot 1:d0dfbce63a89 1307 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
elmot 1:d0dfbce63a89 1308 * @retval None
elmot 1:d0dfbce63a89 1309 */
elmot 1:d0dfbce63a89 1310 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
elmot 1:d0dfbce63a89 1311 {
elmot 1:d0dfbce63a89 1312 __IO uint32_t tmpreg;
elmot 1:d0dfbce63a89 1313 SET_BIT(RCC->APB1SMENR2, Periphs);
elmot 1:d0dfbce63a89 1314 /* Delay after an RCC peripheral clock enabling */
elmot 1:d0dfbce63a89 1315 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
elmot 1:d0dfbce63a89 1316 (void)tmpreg;
elmot 1:d0dfbce63a89 1317 }
elmot 1:d0dfbce63a89 1318
elmot 1:d0dfbce63a89 1319 /**
elmot 1:d0dfbce63a89 1320 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
elmot 1:d0dfbce63a89 1321 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1322 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1323 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1324 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1325 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1326 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1327 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1328 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1329 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1330 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1331 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1332 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1333 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1334 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1335 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1336 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1337 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1338 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1339 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1340 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1341 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1342 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1343 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1344 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
elmot 1:d0dfbce63a89 1345 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1346 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
elmot 1:d0dfbce63a89 1347 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
elmot 1:d0dfbce63a89 1348 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
elmot 1:d0dfbce63a89 1349 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
elmot 1:d0dfbce63a89 1350 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
elmot 1:d0dfbce63a89 1351 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
elmot 1:d0dfbce63a89 1352 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
elmot 1:d0dfbce63a89 1353 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
elmot 1:d0dfbce63a89 1354 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
elmot 1:d0dfbce63a89 1355 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
elmot 1:d0dfbce63a89 1356 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
elmot 1:d0dfbce63a89 1357 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
elmot 1:d0dfbce63a89 1358 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
elmot 1:d0dfbce63a89 1359 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
elmot 1:d0dfbce63a89 1360 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
elmot 1:d0dfbce63a89 1361 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
elmot 1:d0dfbce63a89 1362 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
elmot 1:d0dfbce63a89 1363 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
elmot 1:d0dfbce63a89 1364 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
elmot 1:d0dfbce63a89 1365 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
elmot 1:d0dfbce63a89 1366 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
elmot 1:d0dfbce63a89 1367 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
elmot 1:d0dfbce63a89 1368 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
elmot 1:d0dfbce63a89 1369 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
elmot 1:d0dfbce63a89 1370 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
elmot 1:d0dfbce63a89 1371 *
elmot 1:d0dfbce63a89 1372 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 1373 * @retval None
elmot 1:d0dfbce63a89 1374 */
elmot 1:d0dfbce63a89 1375 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
elmot 1:d0dfbce63a89 1376 {
elmot 1:d0dfbce63a89 1377 CLEAR_BIT(RCC->APB1SMENR1, Periphs);
elmot 1:d0dfbce63a89 1378 }
elmot 1:d0dfbce63a89 1379
elmot 1:d0dfbce63a89 1380 /**
elmot 1:d0dfbce63a89 1381 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
elmot 1:d0dfbce63a89 1382 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1383 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1384 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep
elmot 1:d0dfbce63a89 1385 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1386 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
elmot 1:d0dfbce63a89 1387 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
elmot 1:d0dfbce63a89 1388 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
elmot 1:d0dfbce63a89 1389 * @retval None
elmot 1:d0dfbce63a89 1390 */
elmot 1:d0dfbce63a89 1391 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
elmot 1:d0dfbce63a89 1392 {
elmot 1:d0dfbce63a89 1393 CLEAR_BIT(RCC->APB1SMENR2, Periphs);
elmot 1:d0dfbce63a89 1394 }
elmot 1:d0dfbce63a89 1395
elmot 1:d0dfbce63a89 1396 /**
elmot 1:d0dfbce63a89 1397 * @}
elmot 1:d0dfbce63a89 1398 */
elmot 1:d0dfbce63a89 1399
elmot 1:d0dfbce63a89 1400 /** @defgroup BUS_LL_EF_APB2 APB2
elmot 1:d0dfbce63a89 1401 * @{
elmot 1:d0dfbce63a89 1402 */
elmot 1:d0dfbce63a89 1403
elmot 1:d0dfbce63a89 1404 /**
elmot 1:d0dfbce63a89 1405 * @brief Enable APB2 peripherals clock.
elmot 1:d0dfbce63a89 1406 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 1407 * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 1408 * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 1409 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 1410 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 1411 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 1412 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 1413 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 1414 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 1415 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 1416 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 1417 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
elmot 1:d0dfbce63a89 1418 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock
elmot 1:d0dfbce63a89 1419 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1420 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
elmot 1:d0dfbce63a89 1421 * @arg @ref LL_APB2_GRP1_PERIPH_FW
elmot 1:d0dfbce63a89 1422 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
elmot 1:d0dfbce63a89 1423 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
elmot 1:d0dfbce63a89 1424 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
elmot 1:d0dfbce63a89 1425 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
elmot 1:d0dfbce63a89 1426 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
elmot 1:d0dfbce63a89 1427 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
elmot 1:d0dfbce63a89 1428 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
elmot 1:d0dfbce63a89 1429 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
elmot 1:d0dfbce63a89 1430 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
elmot 1:d0dfbce63a89 1431 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
elmot 1:d0dfbce63a89 1432 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
elmot 1:d0dfbce63a89 1433 *
elmot 1:d0dfbce63a89 1434 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 1435 * @retval None
elmot 1:d0dfbce63a89 1436 */
elmot 1:d0dfbce63a89 1437 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 1438 {
elmot 1:d0dfbce63a89 1439 __IO uint32_t tmpreg;
elmot 1:d0dfbce63a89 1440 SET_BIT(RCC->APB2ENR, Periphs);
elmot 1:d0dfbce63a89 1441 /* Delay after an RCC peripheral clock enabling */
elmot 1:d0dfbce63a89 1442 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
elmot 1:d0dfbce63a89 1443 (void)tmpreg;
elmot 1:d0dfbce63a89 1444 }
elmot 1:d0dfbce63a89 1445
elmot 1:d0dfbce63a89 1446 /**
elmot 1:d0dfbce63a89 1447 * @brief Check if APB2 peripheral clock is enabled or not
elmot 1:d0dfbce63a89 1448 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 1449 * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 1450 * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 1451 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 1452 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 1453 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 1454 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 1455 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 1456 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 1457 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 1458 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 1459 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
elmot 1:d0dfbce63a89 1460 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock
elmot 1:d0dfbce63a89 1461 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1462 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
elmot 1:d0dfbce63a89 1463 * @arg @ref LL_APB2_GRP1_PERIPH_FW
elmot 1:d0dfbce63a89 1464 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
elmot 1:d0dfbce63a89 1465 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
elmot 1:d0dfbce63a89 1466 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
elmot 1:d0dfbce63a89 1467 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
elmot 1:d0dfbce63a89 1468 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
elmot 1:d0dfbce63a89 1469 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
elmot 1:d0dfbce63a89 1470 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
elmot 1:d0dfbce63a89 1471 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
elmot 1:d0dfbce63a89 1472 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
elmot 1:d0dfbce63a89 1473 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
elmot 1:d0dfbce63a89 1474 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
elmot 1:d0dfbce63a89 1475 *
elmot 1:d0dfbce63a89 1476 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 1477 * @retval State of Periphs (1 or 0).
elmot 1:d0dfbce63a89 1478 */
elmot 1:d0dfbce63a89 1479 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 1480 {
elmot 1:d0dfbce63a89 1481 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
elmot 1:d0dfbce63a89 1482 }
elmot 1:d0dfbce63a89 1483
elmot 1:d0dfbce63a89 1484 /**
elmot 1:d0dfbce63a89 1485 * @brief Disable APB2 peripherals clock.
elmot 1:d0dfbce63a89 1486 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1487 * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1488 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1489 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1490 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1491 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1492 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1493 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1494 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1495 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1496 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
elmot 1:d0dfbce63a89 1497 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock
elmot 1:d0dfbce63a89 1498 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1499 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
elmot 1:d0dfbce63a89 1500 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
elmot 1:d0dfbce63a89 1501 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
elmot 1:d0dfbce63a89 1502 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
elmot 1:d0dfbce63a89 1503 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
elmot 1:d0dfbce63a89 1504 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
elmot 1:d0dfbce63a89 1505 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
elmot 1:d0dfbce63a89 1506 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
elmot 1:d0dfbce63a89 1507 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
elmot 1:d0dfbce63a89 1508 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
elmot 1:d0dfbce63a89 1509 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
elmot 1:d0dfbce63a89 1510 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
elmot 1:d0dfbce63a89 1511 *
elmot 1:d0dfbce63a89 1512 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 1513 * @retval None
elmot 1:d0dfbce63a89 1514 */
elmot 1:d0dfbce63a89 1515 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
elmot 1:d0dfbce63a89 1516 {
elmot 1:d0dfbce63a89 1517 CLEAR_BIT(RCC->APB2ENR, Periphs);
elmot 1:d0dfbce63a89 1518 }
elmot 1:d0dfbce63a89 1519
elmot 1:d0dfbce63a89 1520 /**
elmot 1:d0dfbce63a89 1521 * @brief Force APB2 peripherals reset.
elmot 1:d0dfbce63a89 1522 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1523 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1524 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1525 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1526 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1527 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1528 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1529 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1530 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1531 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1532 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
elmot 1:d0dfbce63a89 1533 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset
elmot 1:d0dfbce63a89 1534 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1535 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
elmot 1:d0dfbce63a89 1536 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
elmot 1:d0dfbce63a89 1537 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
elmot 1:d0dfbce63a89 1538 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
elmot 1:d0dfbce63a89 1539 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
elmot 1:d0dfbce63a89 1540 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
elmot 1:d0dfbce63a89 1541 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
elmot 1:d0dfbce63a89 1542 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
elmot 1:d0dfbce63a89 1543 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
elmot 1:d0dfbce63a89 1544 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
elmot 1:d0dfbce63a89 1545 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
elmot 1:d0dfbce63a89 1546 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
elmot 1:d0dfbce63a89 1547 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
elmot 1:d0dfbce63a89 1548 *
elmot 1:d0dfbce63a89 1549 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 1550 * @retval None
elmot 1:d0dfbce63a89 1551 */
elmot 1:d0dfbce63a89 1552 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
elmot 1:d0dfbce63a89 1553 {
elmot 1:d0dfbce63a89 1554 SET_BIT(RCC->APB2RSTR, Periphs);
elmot 1:d0dfbce63a89 1555 }
elmot 1:d0dfbce63a89 1556
elmot 1:d0dfbce63a89 1557 /**
elmot 1:d0dfbce63a89 1558 * @brief Release APB2 peripherals reset.
elmot 1:d0dfbce63a89 1559 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1560 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1561 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1562 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1563 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1564 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1565 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1566 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1567 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1568 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1569 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
elmot 1:d0dfbce63a89 1570 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset
elmot 1:d0dfbce63a89 1571 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1572 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
elmot 1:d0dfbce63a89 1573 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
elmot 1:d0dfbce63a89 1574 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
elmot 1:d0dfbce63a89 1575 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
elmot 1:d0dfbce63a89 1576 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
elmot 1:d0dfbce63a89 1577 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
elmot 1:d0dfbce63a89 1578 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
elmot 1:d0dfbce63a89 1579 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
elmot 1:d0dfbce63a89 1580 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
elmot 1:d0dfbce63a89 1581 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
elmot 1:d0dfbce63a89 1582 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
elmot 1:d0dfbce63a89 1583 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
elmot 1:d0dfbce63a89 1584 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
elmot 1:d0dfbce63a89 1585 *
elmot 1:d0dfbce63a89 1586 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 1587 * @retval None
elmot 1:d0dfbce63a89 1588 */
elmot 1:d0dfbce63a89 1589 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
elmot 1:d0dfbce63a89 1590 {
elmot 1:d0dfbce63a89 1591 CLEAR_BIT(RCC->APB2RSTR, Periphs);
elmot 1:d0dfbce63a89 1592 }
elmot 1:d0dfbce63a89 1593
elmot 1:d0dfbce63a89 1594 /**
elmot 1:d0dfbce63a89 1595 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
elmot 1:d0dfbce63a89 1596 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1597 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1598 * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1599 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1600 * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1601 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1602 * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1603 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1604 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1605 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1606 * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n
elmot 1:d0dfbce63a89 1607 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep
elmot 1:d0dfbce63a89 1608 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1609 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
elmot 1:d0dfbce63a89 1610 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
elmot 1:d0dfbce63a89 1611 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
elmot 1:d0dfbce63a89 1612 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
elmot 1:d0dfbce63a89 1613 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
elmot 1:d0dfbce63a89 1614 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
elmot 1:d0dfbce63a89 1615 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
elmot 1:d0dfbce63a89 1616 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
elmot 1:d0dfbce63a89 1617 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
elmot 1:d0dfbce63a89 1618 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
elmot 1:d0dfbce63a89 1619 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
elmot 1:d0dfbce63a89 1620 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
elmot 1:d0dfbce63a89 1621 *
elmot 1:d0dfbce63a89 1622 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 1623 * @retval None
elmot 1:d0dfbce63a89 1624 */
elmot 1:d0dfbce63a89 1625 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
elmot 1:d0dfbce63a89 1626 {
elmot 1:d0dfbce63a89 1627 __IO uint32_t tmpreg;
elmot 1:d0dfbce63a89 1628 SET_BIT(RCC->APB2SMENR, Periphs);
elmot 1:d0dfbce63a89 1629 /* Delay after an RCC peripheral clock enabling */
elmot 1:d0dfbce63a89 1630 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
elmot 1:d0dfbce63a89 1631 (void)tmpreg;
elmot 1:d0dfbce63a89 1632 }
elmot 1:d0dfbce63a89 1633
elmot 1:d0dfbce63a89 1634 /**
elmot 1:d0dfbce63a89 1635 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
elmot 1:d0dfbce63a89 1636 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1637 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1638 * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1639 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1640 * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1641 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1642 * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1643 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1644 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1645 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1646 * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n
elmot 1:d0dfbce63a89 1647 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep
elmot 1:d0dfbce63a89 1648 * @param Periphs This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 1649 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
elmot 1:d0dfbce63a89 1650 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
elmot 1:d0dfbce63a89 1651 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
elmot 1:d0dfbce63a89 1652 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
elmot 1:d0dfbce63a89 1653 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
elmot 1:d0dfbce63a89 1654 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
elmot 1:d0dfbce63a89 1655 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
elmot 1:d0dfbce63a89 1656 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
elmot 1:d0dfbce63a89 1657 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
elmot 1:d0dfbce63a89 1658 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
elmot 1:d0dfbce63a89 1659 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
elmot 1:d0dfbce63a89 1660 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
elmot 1:d0dfbce63a89 1661 *
elmot 1:d0dfbce63a89 1662 * (*) value not defined in all devices.
elmot 1:d0dfbce63a89 1663 * @retval None
elmot 1:d0dfbce63a89 1664 */
elmot 1:d0dfbce63a89 1665 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
elmot 1:d0dfbce63a89 1666 {
elmot 1:d0dfbce63a89 1667 CLEAR_BIT(RCC->APB2SMENR, Periphs);
elmot 1:d0dfbce63a89 1668 }
elmot 1:d0dfbce63a89 1669
elmot 1:d0dfbce63a89 1670 /**
elmot 1:d0dfbce63a89 1671 * @}
elmot 1:d0dfbce63a89 1672 */
elmot 1:d0dfbce63a89 1673
elmot 1:d0dfbce63a89 1674
elmot 1:d0dfbce63a89 1675 /**
elmot 1:d0dfbce63a89 1676 * @}
elmot 1:d0dfbce63a89 1677 */
elmot 1:d0dfbce63a89 1678
elmot 1:d0dfbce63a89 1679 /**
elmot 1:d0dfbce63a89 1680 * @}
elmot 1:d0dfbce63a89 1681 */
elmot 1:d0dfbce63a89 1682
elmot 1:d0dfbce63a89 1683 #endif /* defined(RCC) */
elmot 1:d0dfbce63a89 1684
elmot 1:d0dfbce63a89 1685 /**
elmot 1:d0dfbce63a89 1686 * @}
elmot 1:d0dfbce63a89 1687 */
elmot 1:d0dfbce63a89 1688
elmot 1:d0dfbce63a89 1689 #ifdef __cplusplus
elmot 1:d0dfbce63a89 1690 }
elmot 1:d0dfbce63a89 1691 #endif
elmot 1:d0dfbce63a89 1692
elmot 1:d0dfbce63a89 1693 #endif /* __STM32L4xx_LL_BUS_H */
elmot 1:d0dfbce63a89 1694
elmot 1:d0dfbce63a89 1695 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/