TUKS MCU Introductory course / TUKS-COURSE-TIMER

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HAL_L476/stm32l4xx_hal_tim.c@1:d0dfbce63a89, 2017-02-24 (annotated)

Committer:
elmot
Date:
Fri Feb 24 21:13:56 2017 +0000
Revision:
1:d0dfbce63a89
Ready-to-copy

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elmot 1:d0dfbce63a89 1 /**
elmot 1:d0dfbce63a89 2 ******************************************************************************
elmot 1:d0dfbce63a89 3 * @file stm32l4xx_hal_tim.c
elmot 1:d0dfbce63a89 4 * @author MCD Application Team
elmot 1:d0dfbce63a89 5 * @version V1.5.1
elmot 1:d0dfbce63a89 6 * @date 31-May-2016
elmot 1:d0dfbce63a89 7 * @brief TIM HAL module driver.
elmot 1:d0dfbce63a89 8 * This file provides firmware functions to manage the following
elmot 1:d0dfbce63a89 9 * functionalities of the Timer (TIM) peripheral:
elmot 1:d0dfbce63a89 10 * + Time Base Initialization
elmot 1:d0dfbce63a89 11 * + Time Base Start
elmot 1:d0dfbce63a89 12 * + Time Base Start Interruption
elmot 1:d0dfbce63a89 13 * + Time Base Start DMA
elmot 1:d0dfbce63a89 14 * + Time Output Compare/PWM Initialization
elmot 1:d0dfbce63a89 15 * + Time Output Compare/PWM Channel Configuration
elmot 1:d0dfbce63a89 16 * + Time Output Compare/PWM Start
elmot 1:d0dfbce63a89 17 * + Time Output Compare/PWM Start Interruption
elmot 1:d0dfbce63a89 18 * + Time Output Compare/PWM Start DMA
elmot 1:d0dfbce63a89 19 * + Time Input Capture Initialization
elmot 1:d0dfbce63a89 20 * + Time Input Capture Channel Configuration
elmot 1:d0dfbce63a89 21 * + Time Input Capture Start
elmot 1:d0dfbce63a89 22 * + Time Input Capture Start Interruption
elmot 1:d0dfbce63a89 23 * + Time Input Capture Start DMA
elmot 1:d0dfbce63a89 24 * + Time One Pulse Initialization
elmot 1:d0dfbce63a89 25 * + Time One Pulse Channel Configuration
elmot 1:d0dfbce63a89 26 * + Time One Pulse Start
elmot 1:d0dfbce63a89 27 * + Time Encoder Interface Initialization
elmot 1:d0dfbce63a89 28 * + Time Encoder Interface Start
elmot 1:d0dfbce63a89 29 * + Time Encoder Interface Start Interruption
elmot 1:d0dfbce63a89 30 * + Time Encoder Interface Start DMA
elmot 1:d0dfbce63a89 31 * + Commutation Event configuration with Interruption and DMA
elmot 1:d0dfbce63a89 32 * + Time OCRef clear configuration
elmot 1:d0dfbce63a89 33 * + Time External Clock configuration
elmot 1:d0dfbce63a89 34 @verbatim
elmot 1:d0dfbce63a89 35 ==============================================================================
elmot 1:d0dfbce63a89 36 ##### TIMER Generic features #####
elmot 1:d0dfbce63a89 37 ==============================================================================
elmot 1:d0dfbce63a89 38 [..] The Timer features include:
elmot 1:d0dfbce63a89 39 (#) 16-bit up, down, up/down auto-reload counter.
elmot 1:d0dfbce63a89 40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
elmot 1:d0dfbce63a89 41 counter clock frequency either by any factor between 1 and 65536.
elmot 1:d0dfbce63a89 42 (#) Up to 4 independent channels for:
elmot 1:d0dfbce63a89 43 (++) Input Capture
elmot 1:d0dfbce63a89 44 (++) Output Compare
elmot 1:d0dfbce63a89 45 (++) PWM generation (Edge and Center-aligned Mode)
elmot 1:d0dfbce63a89 46 (++) One-pulse mode output
elmot 1:d0dfbce63a89 47
elmot 1:d0dfbce63a89 48 ##### How to use this driver #####
elmot 1:d0dfbce63a89 49 ==============================================================================
elmot 1:d0dfbce63a89 50 [..]
elmot 1:d0dfbce63a89 51 (#) Initialize the TIM low level resources by implementing the following functions
elmot 1:d0dfbce63a89 52 depending on the selected feature:
elmot 1:d0dfbce63a89 53 (++) Time Base : HAL_TIM_Base_MspInit()
elmot 1:d0dfbce63a89 54 (++) Input Capture : HAL_TIM_IC_MspInit()
elmot 1:d0dfbce63a89 55 (++) Output Compare : HAL_TIM_OC_MspInit()
elmot 1:d0dfbce63a89 56 (++) PWM generation : HAL_TIM_PWM_MspInit()
elmot 1:d0dfbce63a89 57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
elmot 1:d0dfbce63a89 58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
elmot 1:d0dfbce63a89 59
elmot 1:d0dfbce63a89 60 (#) Initialize the TIM low level resources :
elmot 1:d0dfbce63a89 61 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
elmot 1:d0dfbce63a89 62 (##) TIM pins configuration
elmot 1:d0dfbce63a89 63 (+++) Enable the clock for the TIM GPIOs using the following function:
elmot 1:d0dfbce63a89 64 __HAL_RCC_GPIOx_CLK_ENABLE();
elmot 1:d0dfbce63a89 65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
elmot 1:d0dfbce63a89 66
elmot 1:d0dfbce63a89 67 (#) The external Clock can be configured, if needed (the default clock is the
elmot 1:d0dfbce63a89 68 internal clock from the APBx), using the following function:
elmot 1:d0dfbce63a89 69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
elmot 1:d0dfbce63a89 70 any start function.
elmot 1:d0dfbce63a89 71
elmot 1:d0dfbce63a89 72 (#) Configure the TIM in the desired functioning mode using one of the
elmot 1:d0dfbce63a89 73 Initialization function of this driver:
elmot 1:d0dfbce63a89 74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
elmot 1:d0dfbce63a89 75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
elmot 1:d0dfbce63a89 76 Output Compare signal.
elmot 1:d0dfbce63a89 77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
elmot 1:d0dfbce63a89 78 PWM signal.
elmot 1:d0dfbce63a89 79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
elmot 1:d0dfbce63a89 80 external signal.
elmot 1:d0dfbce63a89 81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
elmot 1:d0dfbce63a89 82 in One Pulse Mode.
elmot 1:d0dfbce63a89 83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
elmot 1:d0dfbce63a89 84
elmot 1:d0dfbce63a89 85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
elmot 1:d0dfbce63a89 86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
elmot 1:d0dfbce63a89 87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
elmot 1:d0dfbce63a89 88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
elmot 1:d0dfbce63a89 89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
elmot 1:d0dfbce63a89 90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
elmot 1:d0dfbce63a89 91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
elmot 1:d0dfbce63a89 92
elmot 1:d0dfbce63a89 93 (#) The DMA Burst is managed with the two following functions:
elmot 1:d0dfbce63a89 94 HAL_TIM_DMABurst_WriteStart()
elmot 1:d0dfbce63a89 95 HAL_TIM_DMABurst_ReadStart()
elmot 1:d0dfbce63a89 96
elmot 1:d0dfbce63a89 97 @endverbatim
elmot 1:d0dfbce63a89 98 ******************************************************************************
elmot 1:d0dfbce63a89 99 * @attention
elmot 1:d0dfbce63a89 100 *
elmot 1:d0dfbce63a89 101 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
elmot 1:d0dfbce63a89 102 *
elmot 1:d0dfbce63a89 103 * Redistribution and use in source and binary forms, with or without modification,
elmot 1:d0dfbce63a89 104 * are permitted provided that the following conditions are met:
elmot 1:d0dfbce63a89 105 * 1. Redistributions of source code must retain the above copyright notice,
elmot 1:d0dfbce63a89 106 * this list of conditions and the following disclaimer.
elmot 1:d0dfbce63a89 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
elmot 1:d0dfbce63a89 108 * this list of conditions and the following disclaimer in the documentation
elmot 1:d0dfbce63a89 109 * and/or other materials provided with the distribution.
elmot 1:d0dfbce63a89 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
elmot 1:d0dfbce63a89 111 * may be used to endorse or promote products derived from this software
elmot 1:d0dfbce63a89 112 * without specific prior written permission.
elmot 1:d0dfbce63a89 113 *
elmot 1:d0dfbce63a89 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elmot 1:d0dfbce63a89 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elmot 1:d0dfbce63a89 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elmot 1:d0dfbce63a89 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
elmot 1:d0dfbce63a89 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
elmot 1:d0dfbce63a89 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
elmot 1:d0dfbce63a89 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
elmot 1:d0dfbce63a89 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
elmot 1:d0dfbce63a89 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
elmot 1:d0dfbce63a89 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elmot 1:d0dfbce63a89 124 *
elmot 1:d0dfbce63a89 125 ******************************************************************************
elmot 1:d0dfbce63a89 126 */
elmot 1:d0dfbce63a89 127
elmot 1:d0dfbce63a89 128 /* Includes ------------------------------------------------------------------*/
elmot 1:d0dfbce63a89 129 #include "stm32l4xx_hal.h"
elmot 1:d0dfbce63a89 130
elmot 1:d0dfbce63a89 131 /** @addtogroup STM32L4xx_HAL_Driver
elmot 1:d0dfbce63a89 132 * @{
elmot 1:d0dfbce63a89 133 */
elmot 1:d0dfbce63a89 134
elmot 1:d0dfbce63a89 135 /** @defgroup TIM TIM
elmot 1:d0dfbce63a89 136 * @brief TIM HAL module driver
elmot 1:d0dfbce63a89 137 * @{
elmot 1:d0dfbce63a89 138 */
elmot 1:d0dfbce63a89 139
elmot 1:d0dfbce63a89 140 #ifdef HAL_TIM_MODULE_ENABLED
elmot 1:d0dfbce63a89 141
elmot 1:d0dfbce63a89 142 /* Private typedef -----------------------------------------------------------*/
elmot 1:d0dfbce63a89 143 /* Private define ------------------------------------------------------------*/
elmot 1:d0dfbce63a89 144 /* Private macro -------------------------------------------------------------*/
elmot 1:d0dfbce63a89 145 /* Private variables ---------------------------------------------------------*/
elmot 1:d0dfbce63a89 146 /* Private function prototypes -----------------------------------------------*/
elmot 1:d0dfbce63a89 147 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
elmot 1:d0dfbce63a89 148 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
elmot 1:d0dfbce63a89 149 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
elmot 1:d0dfbce63a89 150 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
elmot 1:d0dfbce63a89 151 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
elmot 1:d0dfbce63a89 152 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
elmot 1:d0dfbce63a89 153 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
elmot 1:d0dfbce63a89 154 uint32_t TIM_ICFilter);
elmot 1:d0dfbce63a89 155 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
elmot 1:d0dfbce63a89 156 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
elmot 1:d0dfbce63a89 157 uint32_t TIM_ICFilter);
elmot 1:d0dfbce63a89 158 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
elmot 1:d0dfbce63a89 159 uint32_t TIM_ICFilter);
elmot 1:d0dfbce63a89 160 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
elmot 1:d0dfbce63a89 161 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
elmot 1:d0dfbce63a89 162 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
elmot 1:d0dfbce63a89 163 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
elmot 1:d0dfbce63a89 164 TIM_SlaveConfigTypeDef * sSlaveConfig);
elmot 1:d0dfbce63a89 165 /* Exported functions --------------------------------------------------------*/
elmot 1:d0dfbce63a89 166
elmot 1:d0dfbce63a89 167 /** @defgroup TIM_Exported_Functions TIM Exported Functions
elmot 1:d0dfbce63a89 168 * @{
elmot 1:d0dfbce63a89 169 */
elmot 1:d0dfbce63a89 170
elmot 1:d0dfbce63a89 171 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
elmot 1:d0dfbce63a89 172 * @brief Time Base functions
elmot 1:d0dfbce63a89 173 *
elmot 1:d0dfbce63a89 174 @verbatim
elmot 1:d0dfbce63a89 175 ==============================================================================
elmot 1:d0dfbce63a89 176 ##### Time Base functions #####
elmot 1:d0dfbce63a89 177 ==============================================================================
elmot 1:d0dfbce63a89 178 [..]
elmot 1:d0dfbce63a89 179 This section provides functions allowing to:
elmot 1:d0dfbce63a89 180 (+) Initialize and configure the TIM base.
elmot 1:d0dfbce63a89 181 (+) De-initialize the TIM base.
elmot 1:d0dfbce63a89 182 (+) Start the Time Base.
elmot 1:d0dfbce63a89 183 (+) Stop the Time Base.
elmot 1:d0dfbce63a89 184 (+) Start the Time Base and enable interrupt.
elmot 1:d0dfbce63a89 185 (+) Stop the Time Base and disable interrupt.
elmot 1:d0dfbce63a89 186 (+) Start the Time Base and enable DMA transfer.
elmot 1:d0dfbce63a89 187 (+) Stop the Time Base and disable DMA transfer.
elmot 1:d0dfbce63a89 188
elmot 1:d0dfbce63a89 189 @endverbatim
elmot 1:d0dfbce63a89 190 * @{
elmot 1:d0dfbce63a89 191 */
elmot 1:d0dfbce63a89 192 /**
elmot 1:d0dfbce63a89 193 * @brief Initializes the TIM Time base Unit according to the specified
elmot 1:d0dfbce63a89 194 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
elmot 1:d0dfbce63a89 195 * @param htim: TIM Base handle
elmot 1:d0dfbce63a89 196 * @retval HAL status
elmot 1:d0dfbce63a89 197 */
elmot 1:d0dfbce63a89 198 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 199 {
elmot 1:d0dfbce63a89 200 /* Check the TIM handle allocation */
elmot 1:d0dfbce63a89 201 if(htim == NULL)
elmot 1:d0dfbce63a89 202 {
elmot 1:d0dfbce63a89 203 return HAL_ERROR;
elmot 1:d0dfbce63a89 204 }
elmot 1:d0dfbce63a89 205
elmot 1:d0dfbce63a89 206 /* Check the parameters */
elmot 1:d0dfbce63a89 207 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 208 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
elmot 1:d0dfbce63a89 209 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
elmot 1:d0dfbce63a89 210
elmot 1:d0dfbce63a89 211 if(htim->State == HAL_TIM_STATE_RESET)
elmot 1:d0dfbce63a89 212 {
elmot 1:d0dfbce63a89 213 /* Allocate lock resource and initialize it */
elmot 1:d0dfbce63a89 214 htim->Lock = HAL_UNLOCKED;
elmot 1:d0dfbce63a89 215
elmot 1:d0dfbce63a89 216 /* Init the low level hardware : GPIO, CLOCK, NVIC */
elmot 1:d0dfbce63a89 217 HAL_TIM_Base_MspInit(htim);
elmot 1:d0dfbce63a89 218 }
elmot 1:d0dfbce63a89 219
elmot 1:d0dfbce63a89 220 /* Set the TIM state */
elmot 1:d0dfbce63a89 221 htim->State= HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 222
elmot 1:d0dfbce63a89 223 /* Set the Time Base configuration */
elmot 1:d0dfbce63a89 224 TIM_Base_SetConfig(htim->Instance, &htim->Init);
elmot 1:d0dfbce63a89 225
elmot 1:d0dfbce63a89 226 /* Initialize the TIM state*/
elmot 1:d0dfbce63a89 227 htim->State= HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 228
elmot 1:d0dfbce63a89 229 return HAL_OK;
elmot 1:d0dfbce63a89 230 }
elmot 1:d0dfbce63a89 231
elmot 1:d0dfbce63a89 232 /**
elmot 1:d0dfbce63a89 233 * @brief DeInitialize the TIM Base peripheral
elmot 1:d0dfbce63a89 234 * @param htim: TIM Base handle
elmot 1:d0dfbce63a89 235 * @retval HAL status
elmot 1:d0dfbce63a89 236 */
elmot 1:d0dfbce63a89 237 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 238 {
elmot 1:d0dfbce63a89 239 /* Check the parameters */
elmot 1:d0dfbce63a89 240 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 241
elmot 1:d0dfbce63a89 242 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 243
elmot 1:d0dfbce63a89 244 /* Disable the TIM Peripheral Clock */
elmot 1:d0dfbce63a89 245 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 246
elmot 1:d0dfbce63a89 247 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
elmot 1:d0dfbce63a89 248 HAL_TIM_Base_MspDeInit(htim);
elmot 1:d0dfbce63a89 249
elmot 1:d0dfbce63a89 250 /* Change TIM state */
elmot 1:d0dfbce63a89 251 htim->State = HAL_TIM_STATE_RESET;
elmot 1:d0dfbce63a89 252
elmot 1:d0dfbce63a89 253 /* Release Lock */
elmot 1:d0dfbce63a89 254 __HAL_UNLOCK(htim);
elmot 1:d0dfbce63a89 255
elmot 1:d0dfbce63a89 256 return HAL_OK;
elmot 1:d0dfbce63a89 257 }
elmot 1:d0dfbce63a89 258
elmot 1:d0dfbce63a89 259 /**
elmot 1:d0dfbce63a89 260 * @brief Initializes the TIM Base MSP.
elmot 1:d0dfbce63a89 261 * @param htim: TIM handle
elmot 1:d0dfbce63a89 262 * @retval None
elmot 1:d0dfbce63a89 263 */
elmot 1:d0dfbce63a89 264 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 265 {
elmot 1:d0dfbce63a89 266 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 267 UNUSED(htim);
elmot 1:d0dfbce63a89 268
elmot 1:d0dfbce63a89 269 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 270 the HAL_TIM_Base_MspInit could be implemented in the user file
elmot 1:d0dfbce63a89 271 */
elmot 1:d0dfbce63a89 272 }
elmot 1:d0dfbce63a89 273
elmot 1:d0dfbce63a89 274 /**
elmot 1:d0dfbce63a89 275 * @brief DeInitialize TIM Base MSP.
elmot 1:d0dfbce63a89 276 * @param htim: TIM handle
elmot 1:d0dfbce63a89 277 * @retval None
elmot 1:d0dfbce63a89 278 */
elmot 1:d0dfbce63a89 279 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 280 {
elmot 1:d0dfbce63a89 281 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 282 UNUSED(htim);
elmot 1:d0dfbce63a89 283
elmot 1:d0dfbce63a89 284 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 285 the HAL_TIM_Base_MspDeInit could be implemented in the user file
elmot 1:d0dfbce63a89 286 */
elmot 1:d0dfbce63a89 287 }
elmot 1:d0dfbce63a89 288
elmot 1:d0dfbce63a89 289
elmot 1:d0dfbce63a89 290 /**
elmot 1:d0dfbce63a89 291 * @brief Starts the TIM Base generation.
elmot 1:d0dfbce63a89 292 * @param htim : TIM handle
elmot 1:d0dfbce63a89 293 * @retval HAL status
elmot 1:d0dfbce63a89 294 */
elmot 1:d0dfbce63a89 295 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 296 {
elmot 1:d0dfbce63a89 297 /* Check the parameters */
elmot 1:d0dfbce63a89 298 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 299
elmot 1:d0dfbce63a89 300 /* Set the TIM state */
elmot 1:d0dfbce63a89 301 htim->State= HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 302
elmot 1:d0dfbce63a89 303 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 304 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 305
elmot 1:d0dfbce63a89 306 /* Change the TIM state*/
elmot 1:d0dfbce63a89 307 htim->State= HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 308
elmot 1:d0dfbce63a89 309 /* Return function status */
elmot 1:d0dfbce63a89 310 return HAL_OK;
elmot 1:d0dfbce63a89 311 }
elmot 1:d0dfbce63a89 312
elmot 1:d0dfbce63a89 313 /**
elmot 1:d0dfbce63a89 314 * @brief Stops the TIM Base generation.
elmot 1:d0dfbce63a89 315 * @param htim : TIM handle
elmot 1:d0dfbce63a89 316 * @retval HAL status
elmot 1:d0dfbce63a89 317 */
elmot 1:d0dfbce63a89 318 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 319 {
elmot 1:d0dfbce63a89 320 /* Check the parameters */
elmot 1:d0dfbce63a89 321 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 322
elmot 1:d0dfbce63a89 323 /* Set the TIM state */
elmot 1:d0dfbce63a89 324 htim->State= HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 325
elmot 1:d0dfbce63a89 326 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 327 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 328
elmot 1:d0dfbce63a89 329 /* Change the TIM state*/
elmot 1:d0dfbce63a89 330 htim->State= HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 331
elmot 1:d0dfbce63a89 332 /* Return function status */
elmot 1:d0dfbce63a89 333 return HAL_OK;
elmot 1:d0dfbce63a89 334 }
elmot 1:d0dfbce63a89 335
elmot 1:d0dfbce63a89 336 /**
elmot 1:d0dfbce63a89 337 * @brief Starts the TIM Base generation in interrupt mode.
elmot 1:d0dfbce63a89 338 * @param htim : TIM handle
elmot 1:d0dfbce63a89 339 * @retval HAL status
elmot 1:d0dfbce63a89 340 */
elmot 1:d0dfbce63a89 341 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 342 {
elmot 1:d0dfbce63a89 343 /* Check the parameters */
elmot 1:d0dfbce63a89 344 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 345
elmot 1:d0dfbce63a89 346 /* Enable the TIM Update interrupt */
elmot 1:d0dfbce63a89 347 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
elmot 1:d0dfbce63a89 348
elmot 1:d0dfbce63a89 349 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 350 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 351
elmot 1:d0dfbce63a89 352 /* Return function status */
elmot 1:d0dfbce63a89 353 return HAL_OK;
elmot 1:d0dfbce63a89 354 }
elmot 1:d0dfbce63a89 355
elmot 1:d0dfbce63a89 356 /**
elmot 1:d0dfbce63a89 357 * @brief Stops the TIM Base generation in interrupt mode.
elmot 1:d0dfbce63a89 358 * @param htim : TIM handle
elmot 1:d0dfbce63a89 359 * @retval HAL status
elmot 1:d0dfbce63a89 360 */
elmot 1:d0dfbce63a89 361 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 362 {
elmot 1:d0dfbce63a89 363 /* Check the parameters */
elmot 1:d0dfbce63a89 364 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 365 /* Disable the TIM Update interrupt */
elmot 1:d0dfbce63a89 366 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
elmot 1:d0dfbce63a89 367
elmot 1:d0dfbce63a89 368 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 369 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 370
elmot 1:d0dfbce63a89 371 /* Return function status */
elmot 1:d0dfbce63a89 372 return HAL_OK;
elmot 1:d0dfbce63a89 373 }
elmot 1:d0dfbce63a89 374
elmot 1:d0dfbce63a89 375 /**
elmot 1:d0dfbce63a89 376 * @brief Starts the TIM Base generation in DMA mode.
elmot 1:d0dfbce63a89 377 * @param htim : TIM handle
elmot 1:d0dfbce63a89 378 * @param pData: The source Buffer address.
elmot 1:d0dfbce63a89 379 * @param Length: The length of data to be transferred from memory to peripheral.
elmot 1:d0dfbce63a89 380 * @retval HAL status
elmot 1:d0dfbce63a89 381 */
elmot 1:d0dfbce63a89 382 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
elmot 1:d0dfbce63a89 383 {
elmot 1:d0dfbce63a89 384 /* Check the parameters */
elmot 1:d0dfbce63a89 385 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 386
elmot 1:d0dfbce63a89 387 if((htim->State == HAL_TIM_STATE_BUSY))
elmot 1:d0dfbce63a89 388 {
elmot 1:d0dfbce63a89 389 return HAL_BUSY;
elmot 1:d0dfbce63a89 390 }
elmot 1:d0dfbce63a89 391 else if((htim->State == HAL_TIM_STATE_READY))
elmot 1:d0dfbce63a89 392 {
elmot 1:d0dfbce63a89 393 if((pData == 0 ) && (Length > 0))
elmot 1:d0dfbce63a89 394 {
elmot 1:d0dfbce63a89 395 return HAL_ERROR;
elmot 1:d0dfbce63a89 396 }
elmot 1:d0dfbce63a89 397 else
elmot 1:d0dfbce63a89 398 {
elmot 1:d0dfbce63a89 399 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 400 }
elmot 1:d0dfbce63a89 401 }
elmot 1:d0dfbce63a89 402 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 403 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
elmot 1:d0dfbce63a89 404
elmot 1:d0dfbce63a89 405 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 406 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 407
elmot 1:d0dfbce63a89 408 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 409 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
elmot 1:d0dfbce63a89 410
elmot 1:d0dfbce63a89 411 /* Enable the TIM Update DMA request */
elmot 1:d0dfbce63a89 412 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
elmot 1:d0dfbce63a89 413
elmot 1:d0dfbce63a89 414 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 415 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 416
elmot 1:d0dfbce63a89 417 /* Return function status */
elmot 1:d0dfbce63a89 418 return HAL_OK;
elmot 1:d0dfbce63a89 419 }
elmot 1:d0dfbce63a89 420
elmot 1:d0dfbce63a89 421 /**
elmot 1:d0dfbce63a89 422 * @brief Stops the TIM Base generation in DMA mode.
elmot 1:d0dfbce63a89 423 * @param htim : TIM handle
elmot 1:d0dfbce63a89 424 * @retval HAL status
elmot 1:d0dfbce63a89 425 */
elmot 1:d0dfbce63a89 426 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 427 {
elmot 1:d0dfbce63a89 428 /* Check the parameters */
elmot 1:d0dfbce63a89 429 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 430
elmot 1:d0dfbce63a89 431 /* Disable the TIM Update DMA request */
elmot 1:d0dfbce63a89 432 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
elmot 1:d0dfbce63a89 433
elmot 1:d0dfbce63a89 434 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 435 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 436
elmot 1:d0dfbce63a89 437 /* Change the htim state */
elmot 1:d0dfbce63a89 438 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 439
elmot 1:d0dfbce63a89 440 /* Return function status */
elmot 1:d0dfbce63a89 441 return HAL_OK;
elmot 1:d0dfbce63a89 442 }
elmot 1:d0dfbce63a89 443
elmot 1:d0dfbce63a89 444 /**
elmot 1:d0dfbce63a89 445 * @}
elmot 1:d0dfbce63a89 446 */
elmot 1:d0dfbce63a89 447
elmot 1:d0dfbce63a89 448 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
elmot 1:d0dfbce63a89 449 * @brief Time Output Compare functions
elmot 1:d0dfbce63a89 450 *
elmot 1:d0dfbce63a89 451 @verbatim
elmot 1:d0dfbce63a89 452 ==============================================================================
elmot 1:d0dfbce63a89 453 ##### Time Output Compare functions #####
elmot 1:d0dfbce63a89 454 ==============================================================================
elmot 1:d0dfbce63a89 455 [..]
elmot 1:d0dfbce63a89 456 This section provides functions allowing to:
elmot 1:d0dfbce63a89 457 (+) Initialize and configure the TIM Output Compare.
elmot 1:d0dfbce63a89 458 (+) De-initialize the TIM Output Compare.
elmot 1:d0dfbce63a89 459 (+) Start the Time Output Compare.
elmot 1:d0dfbce63a89 460 (+) Stop the Time Output Compare.
elmot 1:d0dfbce63a89 461 (+) Start the Time Output Compare and enable interrupt.
elmot 1:d0dfbce63a89 462 (+) Stop the Time Output Compare and disable interrupt.
elmot 1:d0dfbce63a89 463 (+) Start the Time Output Compare and enable DMA transfer.
elmot 1:d0dfbce63a89 464 (+) Stop the Time Output Compare and disable DMA transfer.
elmot 1:d0dfbce63a89 465
elmot 1:d0dfbce63a89 466 @endverbatim
elmot 1:d0dfbce63a89 467 * @{
elmot 1:d0dfbce63a89 468 */
elmot 1:d0dfbce63a89 469 /**
elmot 1:d0dfbce63a89 470 * @brief Initializes the TIM Output Compare according to the specified
elmot 1:d0dfbce63a89 471 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
elmot 1:d0dfbce63a89 472 * @param htim: TIM Output Compare handle
elmot 1:d0dfbce63a89 473 * @retval HAL status
elmot 1:d0dfbce63a89 474 */
elmot 1:d0dfbce63a89 475 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
elmot 1:d0dfbce63a89 476 {
elmot 1:d0dfbce63a89 477 /* Check the TIM handle allocation */
elmot 1:d0dfbce63a89 478 if(htim == NULL)
elmot 1:d0dfbce63a89 479 {
elmot 1:d0dfbce63a89 480 return HAL_ERROR;
elmot 1:d0dfbce63a89 481 }
elmot 1:d0dfbce63a89 482
elmot 1:d0dfbce63a89 483 /* Check the parameters */
elmot 1:d0dfbce63a89 484 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 485 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
elmot 1:d0dfbce63a89 486 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
elmot 1:d0dfbce63a89 487
elmot 1:d0dfbce63a89 488 if(htim->State == HAL_TIM_STATE_RESET)
elmot 1:d0dfbce63a89 489 {
elmot 1:d0dfbce63a89 490 /* Allocate lock resource and initialize it */
elmot 1:d0dfbce63a89 491 htim->Lock = HAL_UNLOCKED;
elmot 1:d0dfbce63a89 492
elmot 1:d0dfbce63a89 493 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
elmot 1:d0dfbce63a89 494 HAL_TIM_OC_MspInit(htim);
elmot 1:d0dfbce63a89 495 }
elmot 1:d0dfbce63a89 496
elmot 1:d0dfbce63a89 497 /* Set the TIM state */
elmot 1:d0dfbce63a89 498 htim->State= HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 499
elmot 1:d0dfbce63a89 500 /* Init the base time for the Output Compare */
elmot 1:d0dfbce63a89 501 TIM_Base_SetConfig(htim->Instance, &htim->Init);
elmot 1:d0dfbce63a89 502
elmot 1:d0dfbce63a89 503 /* Initialize the TIM state*/
elmot 1:d0dfbce63a89 504 htim->State= HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 505
elmot 1:d0dfbce63a89 506 return HAL_OK;
elmot 1:d0dfbce63a89 507 }
elmot 1:d0dfbce63a89 508
elmot 1:d0dfbce63a89 509 /**
elmot 1:d0dfbce63a89 510 * @brief DeInitialize the TIM peripheral
elmot 1:d0dfbce63a89 511 * @param htim: TIM Output Compare handle
elmot 1:d0dfbce63a89 512 * @retval HAL status
elmot 1:d0dfbce63a89 513 */
elmot 1:d0dfbce63a89 514 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 515 {
elmot 1:d0dfbce63a89 516 /* Check the parameters */
elmot 1:d0dfbce63a89 517 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 518
elmot 1:d0dfbce63a89 519 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 520
elmot 1:d0dfbce63a89 521 /* Disable the TIM Peripheral Clock */
elmot 1:d0dfbce63a89 522 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 523
elmot 1:d0dfbce63a89 524 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
elmot 1:d0dfbce63a89 525 HAL_TIM_OC_MspDeInit(htim);
elmot 1:d0dfbce63a89 526
elmot 1:d0dfbce63a89 527 /* Change TIM state */
elmot 1:d0dfbce63a89 528 htim->State = HAL_TIM_STATE_RESET;
elmot 1:d0dfbce63a89 529
elmot 1:d0dfbce63a89 530 /* Release Lock */
elmot 1:d0dfbce63a89 531 __HAL_UNLOCK(htim);
elmot 1:d0dfbce63a89 532
elmot 1:d0dfbce63a89 533 return HAL_OK;
elmot 1:d0dfbce63a89 534 }
elmot 1:d0dfbce63a89 535
elmot 1:d0dfbce63a89 536 /**
elmot 1:d0dfbce63a89 537 * @brief Initializes the TIM Output Compare MSP.
elmot 1:d0dfbce63a89 538 * @param htim: TIM handle
elmot 1:d0dfbce63a89 539 * @retval None
elmot 1:d0dfbce63a89 540 */
elmot 1:d0dfbce63a89 541 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 542 {
elmot 1:d0dfbce63a89 543 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 544 UNUSED(htim);
elmot 1:d0dfbce63a89 545
elmot 1:d0dfbce63a89 546 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 547 the HAL_TIM_OC_MspInit could be implemented in the user file
elmot 1:d0dfbce63a89 548 */
elmot 1:d0dfbce63a89 549 }
elmot 1:d0dfbce63a89 550
elmot 1:d0dfbce63a89 551 /**
elmot 1:d0dfbce63a89 552 * @brief DeInitialize TIM Output Compare MSP.
elmot 1:d0dfbce63a89 553 * @param htim: TIM handle
elmot 1:d0dfbce63a89 554 * @retval None
elmot 1:d0dfbce63a89 555 */
elmot 1:d0dfbce63a89 556 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 557 {
elmot 1:d0dfbce63a89 558 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 559 UNUSED(htim);
elmot 1:d0dfbce63a89 560
elmot 1:d0dfbce63a89 561 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 562 the HAL_TIM_OC_MspDeInit could be implemented in the user file
elmot 1:d0dfbce63a89 563 */
elmot 1:d0dfbce63a89 564 }
elmot 1:d0dfbce63a89 565
elmot 1:d0dfbce63a89 566 /**
elmot 1:d0dfbce63a89 567 * @brief Starts the TIM Output Compare signal generation.
elmot 1:d0dfbce63a89 568 * @param htim : TIM Output Compare handle
elmot 1:d0dfbce63a89 569 * @param Channel : TIM Channel to be enabled
elmot 1:d0dfbce63a89 570 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 571 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 572 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 573 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 574 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 575 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
elmot 1:d0dfbce63a89 576 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
elmot 1:d0dfbce63a89 577 * @retval HAL status
elmot 1:d0dfbce63a89 578 */
elmot 1:d0dfbce63a89 579 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 580 {
elmot 1:d0dfbce63a89 581 /* Check the parameters */
elmot 1:d0dfbce63a89 582 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 583
elmot 1:d0dfbce63a89 584 /* Enable the Output compare channel */
elmot 1:d0dfbce63a89 585 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 586
elmot 1:d0dfbce63a89 587 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
elmot 1:d0dfbce63a89 588 {
elmot 1:d0dfbce63a89 589 /* Enable the main output */
elmot 1:d0dfbce63a89 590 __HAL_TIM_MOE_ENABLE(htim);
elmot 1:d0dfbce63a89 591 }
elmot 1:d0dfbce63a89 592
elmot 1:d0dfbce63a89 593 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 594 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 595
elmot 1:d0dfbce63a89 596 /* Return function status */
elmot 1:d0dfbce63a89 597 return HAL_OK;
elmot 1:d0dfbce63a89 598 }
elmot 1:d0dfbce63a89 599
elmot 1:d0dfbce63a89 600 /**
elmot 1:d0dfbce63a89 601 * @brief Stops the TIM Output Compare signal generation.
elmot 1:d0dfbce63a89 602 * @param htim : TIM handle
elmot 1:d0dfbce63a89 603 * @param Channel : TIM Channel to be disabled
elmot 1:d0dfbce63a89 604 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 605 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 606 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 607 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 608 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 609 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
elmot 1:d0dfbce63a89 610 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
elmot 1:d0dfbce63a89 611 * @retval HAL status
elmot 1:d0dfbce63a89 612 */
elmot 1:d0dfbce63a89 613 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 614 {
elmot 1:d0dfbce63a89 615 /* Check the parameters */
elmot 1:d0dfbce63a89 616 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 617
elmot 1:d0dfbce63a89 618 /* Disable the Output compare channel */
elmot 1:d0dfbce63a89 619 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 620
elmot 1:d0dfbce63a89 621 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
elmot 1:d0dfbce63a89 622 {
elmot 1:d0dfbce63a89 623 /* Disable the Main Ouput */
elmot 1:d0dfbce63a89 624 __HAL_TIM_MOE_DISABLE(htim);
elmot 1:d0dfbce63a89 625 }
elmot 1:d0dfbce63a89 626
elmot 1:d0dfbce63a89 627 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 628 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 629
elmot 1:d0dfbce63a89 630 /* Return function status */
elmot 1:d0dfbce63a89 631 return HAL_OK;
elmot 1:d0dfbce63a89 632 }
elmot 1:d0dfbce63a89 633
elmot 1:d0dfbce63a89 634 /**
elmot 1:d0dfbce63a89 635 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
elmot 1:d0dfbce63a89 636 * @param htim : TIM OC handle
elmot 1:d0dfbce63a89 637 * @param Channel : TIM Channel to be enabled
elmot 1:d0dfbce63a89 638 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 639 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 640 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 641 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 642 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 643 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
elmot 1:d0dfbce63a89 644 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
elmot 1:d0dfbce63a89 645 * @retval HAL status
elmot 1:d0dfbce63a89 646 */
elmot 1:d0dfbce63a89 647 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 648 {
elmot 1:d0dfbce63a89 649 /* Check the parameters */
elmot 1:d0dfbce63a89 650 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 651
elmot 1:d0dfbce63a89 652 switch (Channel)
elmot 1:d0dfbce63a89 653 {
elmot 1:d0dfbce63a89 654 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 655 {
elmot 1:d0dfbce63a89 656 /* Enable the TIM Capture/Compare 1 interrupt */
elmot 1:d0dfbce63a89 657 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
elmot 1:d0dfbce63a89 658 }
elmot 1:d0dfbce63a89 659 break;
elmot 1:d0dfbce63a89 660
elmot 1:d0dfbce63a89 661 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 662 {
elmot 1:d0dfbce63a89 663 /* Enable the TIM Capture/Compare 2 interrupt */
elmot 1:d0dfbce63a89 664 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
elmot 1:d0dfbce63a89 665 }
elmot 1:d0dfbce63a89 666 break;
elmot 1:d0dfbce63a89 667
elmot 1:d0dfbce63a89 668 case TIM_CHANNEL_3:
elmot 1:d0dfbce63a89 669 {
elmot 1:d0dfbce63a89 670 /* Enable the TIM Capture/Compare 3 interrupt */
elmot 1:d0dfbce63a89 671 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
elmot 1:d0dfbce63a89 672 }
elmot 1:d0dfbce63a89 673 break;
elmot 1:d0dfbce63a89 674
elmot 1:d0dfbce63a89 675 case TIM_CHANNEL_4:
elmot 1:d0dfbce63a89 676 {
elmot 1:d0dfbce63a89 677 /* Enable the TIM Capture/Compare 4 interrupt */
elmot 1:d0dfbce63a89 678 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
elmot 1:d0dfbce63a89 679 }
elmot 1:d0dfbce63a89 680 break;
elmot 1:d0dfbce63a89 681
elmot 1:d0dfbce63a89 682 default:
elmot 1:d0dfbce63a89 683 break;
elmot 1:d0dfbce63a89 684 }
elmot 1:d0dfbce63a89 685
elmot 1:d0dfbce63a89 686 /* Enable the Output compare channel */
elmot 1:d0dfbce63a89 687 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 688
elmot 1:d0dfbce63a89 689 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
elmot 1:d0dfbce63a89 690 {
elmot 1:d0dfbce63a89 691 /* Enable the main output */
elmot 1:d0dfbce63a89 692 __HAL_TIM_MOE_ENABLE(htim);
elmot 1:d0dfbce63a89 693 }
elmot 1:d0dfbce63a89 694
elmot 1:d0dfbce63a89 695 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 696 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 697
elmot 1:d0dfbce63a89 698 /* Return function status */
elmot 1:d0dfbce63a89 699 return HAL_OK;
elmot 1:d0dfbce63a89 700 }
elmot 1:d0dfbce63a89 701
elmot 1:d0dfbce63a89 702 /**
elmot 1:d0dfbce63a89 703 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
elmot 1:d0dfbce63a89 704 * @param htim : TIM Output Compare handle
elmot 1:d0dfbce63a89 705 * @param Channel : TIM Channel to be disabled
elmot 1:d0dfbce63a89 706 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 707 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 708 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 709 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 710 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 711 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
elmot 1:d0dfbce63a89 712 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
elmot 1:d0dfbce63a89 713 * @retval HAL status
elmot 1:d0dfbce63a89 714 */
elmot 1:d0dfbce63a89 715 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 716 {
elmot 1:d0dfbce63a89 717 /* Check the parameters */
elmot 1:d0dfbce63a89 718 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 719
elmot 1:d0dfbce63a89 720 switch (Channel)
elmot 1:d0dfbce63a89 721 {
elmot 1:d0dfbce63a89 722 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 723 {
elmot 1:d0dfbce63a89 724 /* Disable the TIM Capture/Compare 1 interrupt */
elmot 1:d0dfbce63a89 725 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
elmot 1:d0dfbce63a89 726 }
elmot 1:d0dfbce63a89 727 break;
elmot 1:d0dfbce63a89 728
elmot 1:d0dfbce63a89 729 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 730 {
elmot 1:d0dfbce63a89 731 /* Disable the TIM Capture/Compare 2 interrupt */
elmot 1:d0dfbce63a89 732 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
elmot 1:d0dfbce63a89 733 }
elmot 1:d0dfbce63a89 734 break;
elmot 1:d0dfbce63a89 735
elmot 1:d0dfbce63a89 736 case TIM_CHANNEL_3:
elmot 1:d0dfbce63a89 737 {
elmot 1:d0dfbce63a89 738 /* Disable the TIM Capture/Compare 3 interrupt */
elmot 1:d0dfbce63a89 739 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
elmot 1:d0dfbce63a89 740 }
elmot 1:d0dfbce63a89 741 break;
elmot 1:d0dfbce63a89 742
elmot 1:d0dfbce63a89 743 case TIM_CHANNEL_4:
elmot 1:d0dfbce63a89 744 {
elmot 1:d0dfbce63a89 745 /* Disable the TIM Capture/Compare 4 interrupt */
elmot 1:d0dfbce63a89 746 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
elmot 1:d0dfbce63a89 747 }
elmot 1:d0dfbce63a89 748 break;
elmot 1:d0dfbce63a89 749
elmot 1:d0dfbce63a89 750 default:
elmot 1:d0dfbce63a89 751 break;
elmot 1:d0dfbce63a89 752 }
elmot 1:d0dfbce63a89 753
elmot 1:d0dfbce63a89 754 /* Disable the Output compare channel */
elmot 1:d0dfbce63a89 755 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 756
elmot 1:d0dfbce63a89 757 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
elmot 1:d0dfbce63a89 758 {
elmot 1:d0dfbce63a89 759 /* Disable the Main Ouput */
elmot 1:d0dfbce63a89 760 __HAL_TIM_MOE_DISABLE(htim);
elmot 1:d0dfbce63a89 761 }
elmot 1:d0dfbce63a89 762
elmot 1:d0dfbce63a89 763 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 764 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 765
elmot 1:d0dfbce63a89 766 /* Return function status */
elmot 1:d0dfbce63a89 767 return HAL_OK;
elmot 1:d0dfbce63a89 768 }
elmot 1:d0dfbce63a89 769
elmot 1:d0dfbce63a89 770 /**
elmot 1:d0dfbce63a89 771 * @brief Starts the TIM Output Compare signal generation in DMA mode.
elmot 1:d0dfbce63a89 772 * @param htim : TIM Output Compare handle
elmot 1:d0dfbce63a89 773 * @param Channel : TIM Channel to be enabled
elmot 1:d0dfbce63a89 774 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 775 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 776 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 777 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 778 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 779 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
elmot 1:d0dfbce63a89 780 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
elmot 1:d0dfbce63a89 781 * @param pData: The source Buffer address.
elmot 1:d0dfbce63a89 782 * @param Length: The length of data to be transferred from memory to TIM peripheral
elmot 1:d0dfbce63a89 783 * @retval HAL status
elmot 1:d0dfbce63a89 784 */
elmot 1:d0dfbce63a89 785 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
elmot 1:d0dfbce63a89 786 {
elmot 1:d0dfbce63a89 787 /* Check the parameters */
elmot 1:d0dfbce63a89 788 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 789
elmot 1:d0dfbce63a89 790 if((htim->State == HAL_TIM_STATE_BUSY))
elmot 1:d0dfbce63a89 791 {
elmot 1:d0dfbce63a89 792 return HAL_BUSY;
elmot 1:d0dfbce63a89 793 }
elmot 1:d0dfbce63a89 794 else if((htim->State == HAL_TIM_STATE_READY))
elmot 1:d0dfbce63a89 795 {
elmot 1:d0dfbce63a89 796 if(((uint32_t)pData == 0 ) && (Length > 0))
elmot 1:d0dfbce63a89 797 {
elmot 1:d0dfbce63a89 798 return HAL_ERROR;
elmot 1:d0dfbce63a89 799 }
elmot 1:d0dfbce63a89 800 else
elmot 1:d0dfbce63a89 801 {
elmot 1:d0dfbce63a89 802 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 803 }
elmot 1:d0dfbce63a89 804 }
elmot 1:d0dfbce63a89 805 switch (Channel)
elmot 1:d0dfbce63a89 806 {
elmot 1:d0dfbce63a89 807 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 808 {
elmot 1:d0dfbce63a89 809 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 810 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
elmot 1:d0dfbce63a89 811
elmot 1:d0dfbce63a89 812 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 813 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 814
elmot 1:d0dfbce63a89 815 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 816 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
elmot 1:d0dfbce63a89 817
elmot 1:d0dfbce63a89 818 /* Enable the TIM Capture/Compare 1 DMA request */
elmot 1:d0dfbce63a89 819 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
elmot 1:d0dfbce63a89 820 }
elmot 1:d0dfbce63a89 821 break;
elmot 1:d0dfbce63a89 822
elmot 1:d0dfbce63a89 823 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 824 {
elmot 1:d0dfbce63a89 825 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 826 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
elmot 1:d0dfbce63a89 827
elmot 1:d0dfbce63a89 828 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 829 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 830
elmot 1:d0dfbce63a89 831 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 832 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
elmot 1:d0dfbce63a89 833
elmot 1:d0dfbce63a89 834 /* Enable the TIM Capture/Compare 2 DMA request */
elmot 1:d0dfbce63a89 835 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
elmot 1:d0dfbce63a89 836 }
elmot 1:d0dfbce63a89 837 break;
elmot 1:d0dfbce63a89 838
elmot 1:d0dfbce63a89 839 case TIM_CHANNEL_3:
elmot 1:d0dfbce63a89 840 {
elmot 1:d0dfbce63a89 841 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 842 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
elmot 1:d0dfbce63a89 843
elmot 1:d0dfbce63a89 844 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 845 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 846
elmot 1:d0dfbce63a89 847 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 848 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
elmot 1:d0dfbce63a89 849
elmot 1:d0dfbce63a89 850 /* Enable the TIM Capture/Compare 3 DMA request */
elmot 1:d0dfbce63a89 851 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
elmot 1:d0dfbce63a89 852 }
elmot 1:d0dfbce63a89 853 break;
elmot 1:d0dfbce63a89 854
elmot 1:d0dfbce63a89 855 case TIM_CHANNEL_4:
elmot 1:d0dfbce63a89 856 {
elmot 1:d0dfbce63a89 857 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 858 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
elmot 1:d0dfbce63a89 859
elmot 1:d0dfbce63a89 860 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 861 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 862
elmot 1:d0dfbce63a89 863 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 864 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
elmot 1:d0dfbce63a89 865
elmot 1:d0dfbce63a89 866 /* Enable the TIM Capture/Compare 4 DMA request */
elmot 1:d0dfbce63a89 867 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
elmot 1:d0dfbce63a89 868 }
elmot 1:d0dfbce63a89 869 break;
elmot 1:d0dfbce63a89 870
elmot 1:d0dfbce63a89 871 default:
elmot 1:d0dfbce63a89 872 break;
elmot 1:d0dfbce63a89 873 }
elmot 1:d0dfbce63a89 874
elmot 1:d0dfbce63a89 875 /* Enable the Output compare channel */
elmot 1:d0dfbce63a89 876 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 877
elmot 1:d0dfbce63a89 878 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
elmot 1:d0dfbce63a89 879 {
elmot 1:d0dfbce63a89 880 /* Enable the main output */
elmot 1:d0dfbce63a89 881 __HAL_TIM_MOE_ENABLE(htim);
elmot 1:d0dfbce63a89 882 }
elmot 1:d0dfbce63a89 883
elmot 1:d0dfbce63a89 884 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 885 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 886
elmot 1:d0dfbce63a89 887 /* Return function status */
elmot 1:d0dfbce63a89 888 return HAL_OK;
elmot 1:d0dfbce63a89 889 }
elmot 1:d0dfbce63a89 890
elmot 1:d0dfbce63a89 891 /**
elmot 1:d0dfbce63a89 892 * @brief Stops the TIM Output Compare signal generation in DMA mode.
elmot 1:d0dfbce63a89 893 * @param htim : TIM Output Compare handle
elmot 1:d0dfbce63a89 894 * @param Channel : TIM Channel to be disabled
elmot 1:d0dfbce63a89 895 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 896 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 897 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 898 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 899 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 900 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
elmot 1:d0dfbce63a89 901 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
elmot 1:d0dfbce63a89 902 * @retval HAL status
elmot 1:d0dfbce63a89 903 */
elmot 1:d0dfbce63a89 904 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 905 {
elmot 1:d0dfbce63a89 906 /* Check the parameters */
elmot 1:d0dfbce63a89 907 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 908
elmot 1:d0dfbce63a89 909 switch (Channel)
elmot 1:d0dfbce63a89 910 {
elmot 1:d0dfbce63a89 911 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 912 {
elmot 1:d0dfbce63a89 913 /* Disable the TIM Capture/Compare 1 DMA request */
elmot 1:d0dfbce63a89 914 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
elmot 1:d0dfbce63a89 915 }
elmot 1:d0dfbce63a89 916 break;
elmot 1:d0dfbce63a89 917
elmot 1:d0dfbce63a89 918 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 919 {
elmot 1:d0dfbce63a89 920 /* Disable the TIM Capture/Compare 2 DMA request */
elmot 1:d0dfbce63a89 921 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
elmot 1:d0dfbce63a89 922 }
elmot 1:d0dfbce63a89 923 break;
elmot 1:d0dfbce63a89 924
elmot 1:d0dfbce63a89 925 case TIM_CHANNEL_3:
elmot 1:d0dfbce63a89 926 {
elmot 1:d0dfbce63a89 927 /* Disable the TIM Capture/Compare 3 DMA request */
elmot 1:d0dfbce63a89 928 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
elmot 1:d0dfbce63a89 929 }
elmot 1:d0dfbce63a89 930 break;
elmot 1:d0dfbce63a89 931
elmot 1:d0dfbce63a89 932 case TIM_CHANNEL_4:
elmot 1:d0dfbce63a89 933 {
elmot 1:d0dfbce63a89 934 /* Disable the TIM Capture/Compare 4 interrupt */
elmot 1:d0dfbce63a89 935 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
elmot 1:d0dfbce63a89 936 }
elmot 1:d0dfbce63a89 937 break;
elmot 1:d0dfbce63a89 938
elmot 1:d0dfbce63a89 939 default:
elmot 1:d0dfbce63a89 940 break;
elmot 1:d0dfbce63a89 941 }
elmot 1:d0dfbce63a89 942
elmot 1:d0dfbce63a89 943 /* Disable the Output compare channel */
elmot 1:d0dfbce63a89 944 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 945
elmot 1:d0dfbce63a89 946 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
elmot 1:d0dfbce63a89 947 {
elmot 1:d0dfbce63a89 948 /* Disable the Main Ouput */
elmot 1:d0dfbce63a89 949 __HAL_TIM_MOE_DISABLE(htim);
elmot 1:d0dfbce63a89 950 }
elmot 1:d0dfbce63a89 951
elmot 1:d0dfbce63a89 952 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 953 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 954
elmot 1:d0dfbce63a89 955 /* Change the htim state */
elmot 1:d0dfbce63a89 956 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 957
elmot 1:d0dfbce63a89 958 /* Return function status */
elmot 1:d0dfbce63a89 959 return HAL_OK;
elmot 1:d0dfbce63a89 960 }
elmot 1:d0dfbce63a89 961
elmot 1:d0dfbce63a89 962 /**
elmot 1:d0dfbce63a89 963 * @}
elmot 1:d0dfbce63a89 964 */
elmot 1:d0dfbce63a89 965
elmot 1:d0dfbce63a89 966 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
elmot 1:d0dfbce63a89 967 * @brief Time PWM functions
elmot 1:d0dfbce63a89 968 *
elmot 1:d0dfbce63a89 969 @verbatim
elmot 1:d0dfbce63a89 970 ==============================================================================
elmot 1:d0dfbce63a89 971 ##### Time PWM functions #####
elmot 1:d0dfbce63a89 972 ==============================================================================
elmot 1:d0dfbce63a89 973 [..]
elmot 1:d0dfbce63a89 974 This section provides functions allowing to:
elmot 1:d0dfbce63a89 975 (+) Initialize and configure the TIM OPWM.
elmot 1:d0dfbce63a89 976 (+) De-initialize the TIM PWM.
elmot 1:d0dfbce63a89 977 (+) Start the Time PWM.
elmot 1:d0dfbce63a89 978 (+) Stop the Time PWM.
elmot 1:d0dfbce63a89 979 (+) Start the Time PWM and enable interrupt.
elmot 1:d0dfbce63a89 980 (+) Stop the Time PWM and disable interrupt.
elmot 1:d0dfbce63a89 981 (+) Start the Time PWM and enable DMA transfer.
elmot 1:d0dfbce63a89 982 (+) Stop the Time PWM and disable DMA transfer.
elmot 1:d0dfbce63a89 983
elmot 1:d0dfbce63a89 984 @endverbatim
elmot 1:d0dfbce63a89 985 * @{
elmot 1:d0dfbce63a89 986 */
elmot 1:d0dfbce63a89 987 /**
elmot 1:d0dfbce63a89 988 * @brief Initializes the TIM PWM Time Base according to the specified
elmot 1:d0dfbce63a89 989 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
elmot 1:d0dfbce63a89 990 * @param htim: TIM handle
elmot 1:d0dfbce63a89 991 * @retval HAL status
elmot 1:d0dfbce63a89 992 */
elmot 1:d0dfbce63a89 993 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 994 {
elmot 1:d0dfbce63a89 995 /* Check the TIM handle allocation */
elmot 1:d0dfbce63a89 996 if(htim == NULL)
elmot 1:d0dfbce63a89 997 {
elmot 1:d0dfbce63a89 998 return HAL_ERROR;
elmot 1:d0dfbce63a89 999 }
elmot 1:d0dfbce63a89 1000
elmot 1:d0dfbce63a89 1001 /* Check the parameters */
elmot 1:d0dfbce63a89 1002 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 1003 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
elmot 1:d0dfbce63a89 1004 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
elmot 1:d0dfbce63a89 1005
elmot 1:d0dfbce63a89 1006 if(htim->State == HAL_TIM_STATE_RESET)
elmot 1:d0dfbce63a89 1007 {
elmot 1:d0dfbce63a89 1008 /* Allocate lock resource and initialize it */
elmot 1:d0dfbce63a89 1009 htim->Lock = HAL_UNLOCKED;
elmot 1:d0dfbce63a89 1010
elmot 1:d0dfbce63a89 1011 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
elmot 1:d0dfbce63a89 1012 HAL_TIM_PWM_MspInit(htim);
elmot 1:d0dfbce63a89 1013 }
elmot 1:d0dfbce63a89 1014
elmot 1:d0dfbce63a89 1015 /* Set the TIM state */
elmot 1:d0dfbce63a89 1016 htim->State= HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 1017
elmot 1:d0dfbce63a89 1018 /* Init the base time for the PWM */
elmot 1:d0dfbce63a89 1019 TIM_Base_SetConfig(htim->Instance, &htim->Init);
elmot 1:d0dfbce63a89 1020
elmot 1:d0dfbce63a89 1021 /* Initialize the TIM state*/
elmot 1:d0dfbce63a89 1022 htim->State= HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 1023
elmot 1:d0dfbce63a89 1024 return HAL_OK;
elmot 1:d0dfbce63a89 1025 }
elmot 1:d0dfbce63a89 1026
elmot 1:d0dfbce63a89 1027 /**
elmot 1:d0dfbce63a89 1028 * @brief DeInitialize the TIM peripheral
elmot 1:d0dfbce63a89 1029 * @param htim: TIM handle
elmot 1:d0dfbce63a89 1030 * @retval HAL status
elmot 1:d0dfbce63a89 1031 */
elmot 1:d0dfbce63a89 1032 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 1033 {
elmot 1:d0dfbce63a89 1034 /* Check the parameters */
elmot 1:d0dfbce63a89 1035 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 1036
elmot 1:d0dfbce63a89 1037 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 1038
elmot 1:d0dfbce63a89 1039 /* Disable the TIM Peripheral Clock */
elmot 1:d0dfbce63a89 1040 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 1041
elmot 1:d0dfbce63a89 1042 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
elmot 1:d0dfbce63a89 1043 HAL_TIM_PWM_MspDeInit(htim);
elmot 1:d0dfbce63a89 1044
elmot 1:d0dfbce63a89 1045 /* Change TIM state */
elmot 1:d0dfbce63a89 1046 htim->State = HAL_TIM_STATE_RESET;
elmot 1:d0dfbce63a89 1047
elmot 1:d0dfbce63a89 1048 /* Release Lock */
elmot 1:d0dfbce63a89 1049 __HAL_UNLOCK(htim);
elmot 1:d0dfbce63a89 1050
elmot 1:d0dfbce63a89 1051 return HAL_OK;
elmot 1:d0dfbce63a89 1052 }
elmot 1:d0dfbce63a89 1053
elmot 1:d0dfbce63a89 1054 /**
elmot 1:d0dfbce63a89 1055 * @brief Initializes the TIM PWM MSP.
elmot 1:d0dfbce63a89 1056 * @param htim: TIM handle
elmot 1:d0dfbce63a89 1057 * @retval None
elmot 1:d0dfbce63a89 1058 */
elmot 1:d0dfbce63a89 1059 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 1060 {
elmot 1:d0dfbce63a89 1061 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 1062 UNUSED(htim);
elmot 1:d0dfbce63a89 1063
elmot 1:d0dfbce63a89 1064 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 1065 the HAL_TIM_PWM_MspInit could be implemented in the user file
elmot 1:d0dfbce63a89 1066 */
elmot 1:d0dfbce63a89 1067 }
elmot 1:d0dfbce63a89 1068
elmot 1:d0dfbce63a89 1069 /**
elmot 1:d0dfbce63a89 1070 * @brief DeInitialize TIM PWM MSP.
elmot 1:d0dfbce63a89 1071 * @param htim: TIM handle
elmot 1:d0dfbce63a89 1072 * @retval None
elmot 1:d0dfbce63a89 1073 */
elmot 1:d0dfbce63a89 1074 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 1075 {
elmot 1:d0dfbce63a89 1076 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 1077 UNUSED(htim);
elmot 1:d0dfbce63a89 1078
elmot 1:d0dfbce63a89 1079 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 1080 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
elmot 1:d0dfbce63a89 1081 */
elmot 1:d0dfbce63a89 1082 }
elmot 1:d0dfbce63a89 1083
elmot 1:d0dfbce63a89 1084 /**
elmot 1:d0dfbce63a89 1085 * @brief Starts the PWM signal generation.
elmot 1:d0dfbce63a89 1086 * @param htim : TIM handle
elmot 1:d0dfbce63a89 1087 * @param Channel : TIM Channels to be enabled
elmot 1:d0dfbce63a89 1088 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1089 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 1090 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 1091 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 1092 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 1093 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
elmot 1:d0dfbce63a89 1094 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
elmot 1:d0dfbce63a89 1095 * @retval HAL status
elmot 1:d0dfbce63a89 1096 */
elmot 1:d0dfbce63a89 1097 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 1098 {
elmot 1:d0dfbce63a89 1099 /* Check the parameters */
elmot 1:d0dfbce63a89 1100 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 1101
elmot 1:d0dfbce63a89 1102 /* Enable the Capture compare channel */
elmot 1:d0dfbce63a89 1103 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 1104
elmot 1:d0dfbce63a89 1105 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
elmot 1:d0dfbce63a89 1106 {
elmot 1:d0dfbce63a89 1107 /* Enable the main output */
elmot 1:d0dfbce63a89 1108 __HAL_TIM_MOE_ENABLE(htim);
elmot 1:d0dfbce63a89 1109 }
elmot 1:d0dfbce63a89 1110
elmot 1:d0dfbce63a89 1111 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 1112 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 1113
elmot 1:d0dfbce63a89 1114 /* Return function status */
elmot 1:d0dfbce63a89 1115 return HAL_OK;
elmot 1:d0dfbce63a89 1116 }
elmot 1:d0dfbce63a89 1117
elmot 1:d0dfbce63a89 1118 /**
elmot 1:d0dfbce63a89 1119 * @brief Stops the PWM signal generation.
elmot 1:d0dfbce63a89 1120 * @param htim : TIM handle
elmot 1:d0dfbce63a89 1121 * @param Channel : TIM Channels to be disabled
elmot 1:d0dfbce63a89 1122 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1123 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 1124 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 1125 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 1126 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 1127 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
elmot 1:d0dfbce63a89 1128 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
elmot 1:d0dfbce63a89 1129 * @retval HAL status
elmot 1:d0dfbce63a89 1130 */
elmot 1:d0dfbce63a89 1131 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 1132 {
elmot 1:d0dfbce63a89 1133 /* Check the parameters */
elmot 1:d0dfbce63a89 1134 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 1135
elmot 1:d0dfbce63a89 1136 /* Disable the Capture compare channel */
elmot 1:d0dfbce63a89 1137 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 1138
elmot 1:d0dfbce63a89 1139 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
elmot 1:d0dfbce63a89 1140 {
elmot 1:d0dfbce63a89 1141 /* Disable the Main Ouput */
elmot 1:d0dfbce63a89 1142 __HAL_TIM_MOE_DISABLE(htim);
elmot 1:d0dfbce63a89 1143 }
elmot 1:d0dfbce63a89 1144
elmot 1:d0dfbce63a89 1145 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 1146 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 1147
elmot 1:d0dfbce63a89 1148 /* Change the htim state */
elmot 1:d0dfbce63a89 1149 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 1150
elmot 1:d0dfbce63a89 1151 /* Return function status */
elmot 1:d0dfbce63a89 1152 return HAL_OK;
elmot 1:d0dfbce63a89 1153 }
elmot 1:d0dfbce63a89 1154
elmot 1:d0dfbce63a89 1155 /**
elmot 1:d0dfbce63a89 1156 * @brief Starts the PWM signal generation in interrupt mode.
elmot 1:d0dfbce63a89 1157 * @param htim : TIM handle
elmot 1:d0dfbce63a89 1158 * @param Channel : TIM Channel to be enabled
elmot 1:d0dfbce63a89 1159 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1160 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 1161 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 1162 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 1163 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 1164 * @retval HAL status
elmot 1:d0dfbce63a89 1165 */
elmot 1:d0dfbce63a89 1166 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 1167 {
elmot 1:d0dfbce63a89 1168 /* Check the parameters */
elmot 1:d0dfbce63a89 1169 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 1170
elmot 1:d0dfbce63a89 1171 switch (Channel)
elmot 1:d0dfbce63a89 1172 {
elmot 1:d0dfbce63a89 1173 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 1174 {
elmot 1:d0dfbce63a89 1175 /* Enable the TIM Capture/Compare 1 interrupt */
elmot 1:d0dfbce63a89 1176 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
elmot 1:d0dfbce63a89 1177 }
elmot 1:d0dfbce63a89 1178 break;
elmot 1:d0dfbce63a89 1179
elmot 1:d0dfbce63a89 1180 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 1181 {
elmot 1:d0dfbce63a89 1182 /* Enable the TIM Capture/Compare 2 interrupt */
elmot 1:d0dfbce63a89 1183 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
elmot 1:d0dfbce63a89 1184 }
elmot 1:d0dfbce63a89 1185 break;
elmot 1:d0dfbce63a89 1186
elmot 1:d0dfbce63a89 1187 case TIM_CHANNEL_3:
elmot 1:d0dfbce63a89 1188 {
elmot 1:d0dfbce63a89 1189 /* Enable the TIM Capture/Compare 3 interrupt */
elmot 1:d0dfbce63a89 1190 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
elmot 1:d0dfbce63a89 1191 }
elmot 1:d0dfbce63a89 1192 break;
elmot 1:d0dfbce63a89 1193
elmot 1:d0dfbce63a89 1194 case TIM_CHANNEL_4:
elmot 1:d0dfbce63a89 1195 {
elmot 1:d0dfbce63a89 1196 /* Enable the TIM Capture/Compare 4 interrupt */
elmot 1:d0dfbce63a89 1197 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
elmot 1:d0dfbce63a89 1198 }
elmot 1:d0dfbce63a89 1199 break;
elmot 1:d0dfbce63a89 1200
elmot 1:d0dfbce63a89 1201 default:
elmot 1:d0dfbce63a89 1202 break;
elmot 1:d0dfbce63a89 1203 }
elmot 1:d0dfbce63a89 1204
elmot 1:d0dfbce63a89 1205 /* Enable the Capture compare channel */
elmot 1:d0dfbce63a89 1206 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 1207
elmot 1:d0dfbce63a89 1208 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
elmot 1:d0dfbce63a89 1209 {
elmot 1:d0dfbce63a89 1210 /* Enable the main output */
elmot 1:d0dfbce63a89 1211 __HAL_TIM_MOE_ENABLE(htim);
elmot 1:d0dfbce63a89 1212 }
elmot 1:d0dfbce63a89 1213
elmot 1:d0dfbce63a89 1214 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 1215 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 1216
elmot 1:d0dfbce63a89 1217 /* Return function status */
elmot 1:d0dfbce63a89 1218 return HAL_OK;
elmot 1:d0dfbce63a89 1219 }
elmot 1:d0dfbce63a89 1220
elmot 1:d0dfbce63a89 1221 /**
elmot 1:d0dfbce63a89 1222 * @brief Stops the PWM signal generation in interrupt mode.
elmot 1:d0dfbce63a89 1223 * @param htim : TIM handle
elmot 1:d0dfbce63a89 1224 * @param Channel : TIM Channels to be disabled
elmot 1:d0dfbce63a89 1225 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1226 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 1227 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 1228 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 1229 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 1230 * @retval HAL status
elmot 1:d0dfbce63a89 1231 */
elmot 1:d0dfbce63a89 1232 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 1233 {
elmot 1:d0dfbce63a89 1234 /* Check the parameters */
elmot 1:d0dfbce63a89 1235 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 1236
elmot 1:d0dfbce63a89 1237 switch (Channel)
elmot 1:d0dfbce63a89 1238 {
elmot 1:d0dfbce63a89 1239 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 1240 {
elmot 1:d0dfbce63a89 1241 /* Disable the TIM Capture/Compare 1 interrupt */
elmot 1:d0dfbce63a89 1242 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
elmot 1:d0dfbce63a89 1243 }
elmot 1:d0dfbce63a89 1244 break;
elmot 1:d0dfbce63a89 1245
elmot 1:d0dfbce63a89 1246 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 1247 {
elmot 1:d0dfbce63a89 1248 /* Disable the TIM Capture/Compare 2 interrupt */
elmot 1:d0dfbce63a89 1249 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
elmot 1:d0dfbce63a89 1250 }
elmot 1:d0dfbce63a89 1251 break;
elmot 1:d0dfbce63a89 1252
elmot 1:d0dfbce63a89 1253 case TIM_CHANNEL_3:
elmot 1:d0dfbce63a89 1254 {
elmot 1:d0dfbce63a89 1255 /* Disable the TIM Capture/Compare 3 interrupt */
elmot 1:d0dfbce63a89 1256 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
elmot 1:d0dfbce63a89 1257 }
elmot 1:d0dfbce63a89 1258 break;
elmot 1:d0dfbce63a89 1259
elmot 1:d0dfbce63a89 1260 case TIM_CHANNEL_4:
elmot 1:d0dfbce63a89 1261 {
elmot 1:d0dfbce63a89 1262 /* Disable the TIM Capture/Compare 4 interrupt */
elmot 1:d0dfbce63a89 1263 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
elmot 1:d0dfbce63a89 1264 }
elmot 1:d0dfbce63a89 1265 break;
elmot 1:d0dfbce63a89 1266
elmot 1:d0dfbce63a89 1267 default:
elmot 1:d0dfbce63a89 1268 break;
elmot 1:d0dfbce63a89 1269 }
elmot 1:d0dfbce63a89 1270
elmot 1:d0dfbce63a89 1271 /* Disable the Capture compare channel */
elmot 1:d0dfbce63a89 1272 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 1273
elmot 1:d0dfbce63a89 1274 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
elmot 1:d0dfbce63a89 1275 {
elmot 1:d0dfbce63a89 1276 /* Disable the Main Ouput */
elmot 1:d0dfbce63a89 1277 __HAL_TIM_MOE_DISABLE(htim);
elmot 1:d0dfbce63a89 1278 }
elmot 1:d0dfbce63a89 1279
elmot 1:d0dfbce63a89 1280 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 1281 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 1282
elmot 1:d0dfbce63a89 1283 /* Return function status */
elmot 1:d0dfbce63a89 1284 return HAL_OK;
elmot 1:d0dfbce63a89 1285 }
elmot 1:d0dfbce63a89 1286
elmot 1:d0dfbce63a89 1287 /**
elmot 1:d0dfbce63a89 1288 * @brief Starts the TIM PWM signal generation in DMA mode.
elmot 1:d0dfbce63a89 1289 * @param htim : TIM handle
elmot 1:d0dfbce63a89 1290 * @param Channel : TIM Channels to be enabled
elmot 1:d0dfbce63a89 1291 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1292 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 1293 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 1294 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 1295 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 1296 * @param pData: The source Buffer address.
elmot 1:d0dfbce63a89 1297 * @param Length: The length of data to be transferred from memory to TIM peripheral
elmot 1:d0dfbce63a89 1298 * @retval HAL status
elmot 1:d0dfbce63a89 1299 */
elmot 1:d0dfbce63a89 1300 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
elmot 1:d0dfbce63a89 1301 {
elmot 1:d0dfbce63a89 1302 /* Check the parameters */
elmot 1:d0dfbce63a89 1303 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 1304
elmot 1:d0dfbce63a89 1305 if((htim->State == HAL_TIM_STATE_BUSY))
elmot 1:d0dfbce63a89 1306 {
elmot 1:d0dfbce63a89 1307 return HAL_BUSY;
elmot 1:d0dfbce63a89 1308 }
elmot 1:d0dfbce63a89 1309 else if((htim->State == HAL_TIM_STATE_READY))
elmot 1:d0dfbce63a89 1310 {
elmot 1:d0dfbce63a89 1311 if(((uint32_t)pData == 0 ) && (Length > 0))
elmot 1:d0dfbce63a89 1312 {
elmot 1:d0dfbce63a89 1313 return HAL_ERROR;
elmot 1:d0dfbce63a89 1314 }
elmot 1:d0dfbce63a89 1315 else
elmot 1:d0dfbce63a89 1316 {
elmot 1:d0dfbce63a89 1317 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 1318 }
elmot 1:d0dfbce63a89 1319 }
elmot 1:d0dfbce63a89 1320 switch (Channel)
elmot 1:d0dfbce63a89 1321 {
elmot 1:d0dfbce63a89 1322 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 1323 {
elmot 1:d0dfbce63a89 1324 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 1325 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
elmot 1:d0dfbce63a89 1326
elmot 1:d0dfbce63a89 1327 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 1328 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 1329
elmot 1:d0dfbce63a89 1330 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 1331 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
elmot 1:d0dfbce63a89 1332
elmot 1:d0dfbce63a89 1333 /* Enable the TIM Capture/Compare 1 DMA request */
elmot 1:d0dfbce63a89 1334 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
elmot 1:d0dfbce63a89 1335 }
elmot 1:d0dfbce63a89 1336 break;
elmot 1:d0dfbce63a89 1337
elmot 1:d0dfbce63a89 1338 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 1339 {
elmot 1:d0dfbce63a89 1340 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 1341 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
elmot 1:d0dfbce63a89 1342
elmot 1:d0dfbce63a89 1343 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 1344 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 1345
elmot 1:d0dfbce63a89 1346 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 1347 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
elmot 1:d0dfbce63a89 1348
elmot 1:d0dfbce63a89 1349 /* Enable the TIM Capture/Compare 2 DMA request */
elmot 1:d0dfbce63a89 1350 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
elmot 1:d0dfbce63a89 1351 }
elmot 1:d0dfbce63a89 1352 break;
elmot 1:d0dfbce63a89 1353
elmot 1:d0dfbce63a89 1354 case TIM_CHANNEL_3:
elmot 1:d0dfbce63a89 1355 {
elmot 1:d0dfbce63a89 1356 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 1357 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
elmot 1:d0dfbce63a89 1358
elmot 1:d0dfbce63a89 1359 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 1360 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 1361
elmot 1:d0dfbce63a89 1362 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 1363 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
elmot 1:d0dfbce63a89 1364
elmot 1:d0dfbce63a89 1365 /* Enable the TIM Output Capture/Compare 3 request */
elmot 1:d0dfbce63a89 1366 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
elmot 1:d0dfbce63a89 1367 }
elmot 1:d0dfbce63a89 1368 break;
elmot 1:d0dfbce63a89 1369
elmot 1:d0dfbce63a89 1370 case TIM_CHANNEL_4:
elmot 1:d0dfbce63a89 1371 {
elmot 1:d0dfbce63a89 1372 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 1373 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
elmot 1:d0dfbce63a89 1374
elmot 1:d0dfbce63a89 1375 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 1376 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 1377
elmot 1:d0dfbce63a89 1378 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 1379 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
elmot 1:d0dfbce63a89 1380
elmot 1:d0dfbce63a89 1381 /* Enable the TIM Capture/Compare 4 DMA request */
elmot 1:d0dfbce63a89 1382 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
elmot 1:d0dfbce63a89 1383 }
elmot 1:d0dfbce63a89 1384 break;
elmot 1:d0dfbce63a89 1385
elmot 1:d0dfbce63a89 1386 default:
elmot 1:d0dfbce63a89 1387 break;
elmot 1:d0dfbce63a89 1388 }
elmot 1:d0dfbce63a89 1389
elmot 1:d0dfbce63a89 1390 /* Enable the Capture compare channel */
elmot 1:d0dfbce63a89 1391 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 1392
elmot 1:d0dfbce63a89 1393 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
elmot 1:d0dfbce63a89 1394 {
elmot 1:d0dfbce63a89 1395 /* Enable the main output */
elmot 1:d0dfbce63a89 1396 __HAL_TIM_MOE_ENABLE(htim);
elmot 1:d0dfbce63a89 1397 }
elmot 1:d0dfbce63a89 1398
elmot 1:d0dfbce63a89 1399 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 1400 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 1401
elmot 1:d0dfbce63a89 1402 /* Return function status */
elmot 1:d0dfbce63a89 1403 return HAL_OK;
elmot 1:d0dfbce63a89 1404 }
elmot 1:d0dfbce63a89 1405
elmot 1:d0dfbce63a89 1406 /**
elmot 1:d0dfbce63a89 1407 * @brief Stops the TIM PWM signal generation in DMA mode.
elmot 1:d0dfbce63a89 1408 * @param htim : TIM handle
elmot 1:d0dfbce63a89 1409 * @param Channel : TIM Channels to be disabled
elmot 1:d0dfbce63a89 1410 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1411 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 1412 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 1413 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 1414 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 1415 * @retval HAL status
elmot 1:d0dfbce63a89 1416 */
elmot 1:d0dfbce63a89 1417 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 1418 {
elmot 1:d0dfbce63a89 1419 /* Check the parameters */
elmot 1:d0dfbce63a89 1420 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 1421
elmot 1:d0dfbce63a89 1422 switch (Channel)
elmot 1:d0dfbce63a89 1423 {
elmot 1:d0dfbce63a89 1424 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 1425 {
elmot 1:d0dfbce63a89 1426 /* Disable the TIM Capture/Compare 1 DMA request */
elmot 1:d0dfbce63a89 1427 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
elmot 1:d0dfbce63a89 1428 }
elmot 1:d0dfbce63a89 1429 break;
elmot 1:d0dfbce63a89 1430
elmot 1:d0dfbce63a89 1431 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 1432 {
elmot 1:d0dfbce63a89 1433 /* Disable the TIM Capture/Compare 2 DMA request */
elmot 1:d0dfbce63a89 1434 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
elmot 1:d0dfbce63a89 1435 }
elmot 1:d0dfbce63a89 1436 break;
elmot 1:d0dfbce63a89 1437
elmot 1:d0dfbce63a89 1438 case TIM_CHANNEL_3:
elmot 1:d0dfbce63a89 1439 {
elmot 1:d0dfbce63a89 1440 /* Disable the TIM Capture/Compare 3 DMA request */
elmot 1:d0dfbce63a89 1441 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
elmot 1:d0dfbce63a89 1442 }
elmot 1:d0dfbce63a89 1443 break;
elmot 1:d0dfbce63a89 1444
elmot 1:d0dfbce63a89 1445 case TIM_CHANNEL_4:
elmot 1:d0dfbce63a89 1446 {
elmot 1:d0dfbce63a89 1447 /* Disable the TIM Capture/Compare 4 interrupt */
elmot 1:d0dfbce63a89 1448 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
elmot 1:d0dfbce63a89 1449 }
elmot 1:d0dfbce63a89 1450 break;
elmot 1:d0dfbce63a89 1451
elmot 1:d0dfbce63a89 1452 default:
elmot 1:d0dfbce63a89 1453 break;
elmot 1:d0dfbce63a89 1454 }
elmot 1:d0dfbce63a89 1455
elmot 1:d0dfbce63a89 1456 /* Disable the Capture compare channel */
elmot 1:d0dfbce63a89 1457 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 1458
elmot 1:d0dfbce63a89 1459 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
elmot 1:d0dfbce63a89 1460 {
elmot 1:d0dfbce63a89 1461 /* Disable the Main Ouput */
elmot 1:d0dfbce63a89 1462 __HAL_TIM_MOE_DISABLE(htim);
elmot 1:d0dfbce63a89 1463 }
elmot 1:d0dfbce63a89 1464
elmot 1:d0dfbce63a89 1465 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 1466 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 1467
elmot 1:d0dfbce63a89 1468 /* Change the htim state */
elmot 1:d0dfbce63a89 1469 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 1470
elmot 1:d0dfbce63a89 1471 /* Return function status */
elmot 1:d0dfbce63a89 1472 return HAL_OK;
elmot 1:d0dfbce63a89 1473 }
elmot 1:d0dfbce63a89 1474
elmot 1:d0dfbce63a89 1475 /**
elmot 1:d0dfbce63a89 1476 * @}
elmot 1:d0dfbce63a89 1477 */
elmot 1:d0dfbce63a89 1478
elmot 1:d0dfbce63a89 1479 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
elmot 1:d0dfbce63a89 1480 * @brief Time Input Capture functions
elmot 1:d0dfbce63a89 1481 *
elmot 1:d0dfbce63a89 1482 @verbatim
elmot 1:d0dfbce63a89 1483 ==============================================================================
elmot 1:d0dfbce63a89 1484 ##### Time Input Capture functions #####
elmot 1:d0dfbce63a89 1485 ==============================================================================
elmot 1:d0dfbce63a89 1486 [..]
elmot 1:d0dfbce63a89 1487 This section provides functions allowing to:
elmot 1:d0dfbce63a89 1488 (+) Initialize and configure the TIM Input Capture.
elmot 1:d0dfbce63a89 1489 (+) De-initialize the TIM Input Capture.
elmot 1:d0dfbce63a89 1490 (+) Start the Time Input Capture.
elmot 1:d0dfbce63a89 1491 (+) Stop the Time Input Capture.
elmot 1:d0dfbce63a89 1492 (+) Start the Time Input Capture and enable interrupt.
elmot 1:d0dfbce63a89 1493 (+) Stop the Time Input Capture and disable interrupt.
elmot 1:d0dfbce63a89 1494 (+) Start the Time Input Capture and enable DMA transfer.
elmot 1:d0dfbce63a89 1495 (+) Stop the Time Input Capture and disable DMA transfer.
elmot 1:d0dfbce63a89 1496
elmot 1:d0dfbce63a89 1497 @endverbatim
elmot 1:d0dfbce63a89 1498 * @{
elmot 1:d0dfbce63a89 1499 */
elmot 1:d0dfbce63a89 1500 /**
elmot 1:d0dfbce63a89 1501 * @brief Initializes the TIM Input Capture Time base according to the specified
elmot 1:d0dfbce63a89 1502 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
elmot 1:d0dfbce63a89 1503 * @param htim: TIM Input Capture handle
elmot 1:d0dfbce63a89 1504 * @retval HAL status
elmot 1:d0dfbce63a89 1505 */
elmot 1:d0dfbce63a89 1506 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 1507 {
elmot 1:d0dfbce63a89 1508 /* Check the TIM handle allocation */
elmot 1:d0dfbce63a89 1509 if(htim == NULL)
elmot 1:d0dfbce63a89 1510 {
elmot 1:d0dfbce63a89 1511 return HAL_ERROR;
elmot 1:d0dfbce63a89 1512 }
elmot 1:d0dfbce63a89 1513
elmot 1:d0dfbce63a89 1514 /* Check the parameters */
elmot 1:d0dfbce63a89 1515 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 1516 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
elmot 1:d0dfbce63a89 1517 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
elmot 1:d0dfbce63a89 1518
elmot 1:d0dfbce63a89 1519 if(htim->State == HAL_TIM_STATE_RESET)
elmot 1:d0dfbce63a89 1520 {
elmot 1:d0dfbce63a89 1521 /* Allocate lock resource and initialize it */
elmot 1:d0dfbce63a89 1522 htim->Lock = HAL_UNLOCKED;
elmot 1:d0dfbce63a89 1523
elmot 1:d0dfbce63a89 1524 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
elmot 1:d0dfbce63a89 1525 HAL_TIM_IC_MspInit(htim);
elmot 1:d0dfbce63a89 1526 }
elmot 1:d0dfbce63a89 1527
elmot 1:d0dfbce63a89 1528 /* Set the TIM state */
elmot 1:d0dfbce63a89 1529 htim->State= HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 1530
elmot 1:d0dfbce63a89 1531 /* Init the base time for the input capture */
elmot 1:d0dfbce63a89 1532 TIM_Base_SetConfig(htim->Instance, &htim->Init);
elmot 1:d0dfbce63a89 1533
elmot 1:d0dfbce63a89 1534 /* Initialize the TIM state*/
elmot 1:d0dfbce63a89 1535 htim->State= HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 1536
elmot 1:d0dfbce63a89 1537 return HAL_OK;
elmot 1:d0dfbce63a89 1538 }
elmot 1:d0dfbce63a89 1539
elmot 1:d0dfbce63a89 1540 /**
elmot 1:d0dfbce63a89 1541 * @brief DeInitialize the TIM peripheral
elmot 1:d0dfbce63a89 1542 * @param htim: TIM Input Capture handle
elmot 1:d0dfbce63a89 1543 * @retval HAL status
elmot 1:d0dfbce63a89 1544 */
elmot 1:d0dfbce63a89 1545 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 1546 {
elmot 1:d0dfbce63a89 1547 /* Check the parameters */
elmot 1:d0dfbce63a89 1548 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 1549
elmot 1:d0dfbce63a89 1550 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 1551
elmot 1:d0dfbce63a89 1552 /* Disable the TIM Peripheral Clock */
elmot 1:d0dfbce63a89 1553 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 1554
elmot 1:d0dfbce63a89 1555 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
elmot 1:d0dfbce63a89 1556 HAL_TIM_IC_MspDeInit(htim);
elmot 1:d0dfbce63a89 1557
elmot 1:d0dfbce63a89 1558 /* Change TIM state */
elmot 1:d0dfbce63a89 1559 htim->State = HAL_TIM_STATE_RESET;
elmot 1:d0dfbce63a89 1560
elmot 1:d0dfbce63a89 1561 /* Release Lock */
elmot 1:d0dfbce63a89 1562 __HAL_UNLOCK(htim);
elmot 1:d0dfbce63a89 1563
elmot 1:d0dfbce63a89 1564 return HAL_OK;
elmot 1:d0dfbce63a89 1565 }
elmot 1:d0dfbce63a89 1566
elmot 1:d0dfbce63a89 1567 /**
elmot 1:d0dfbce63a89 1568 * @brief Initializes the TIM INput Capture MSP.
elmot 1:d0dfbce63a89 1569 * @param htim: TIM handle
elmot 1:d0dfbce63a89 1570 * @retval None
elmot 1:d0dfbce63a89 1571 */
elmot 1:d0dfbce63a89 1572 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 1573 {
elmot 1:d0dfbce63a89 1574 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 1575 UNUSED(htim);
elmot 1:d0dfbce63a89 1576
elmot 1:d0dfbce63a89 1577 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 1578 the HAL_TIM_IC_MspInit could be implemented in the user file
elmot 1:d0dfbce63a89 1579 */
elmot 1:d0dfbce63a89 1580 }
elmot 1:d0dfbce63a89 1581
elmot 1:d0dfbce63a89 1582 /**
elmot 1:d0dfbce63a89 1583 * @brief DeInitialize TIM Input Capture MSP.
elmot 1:d0dfbce63a89 1584 * @param htim: TIM handle
elmot 1:d0dfbce63a89 1585 * @retval None
elmot 1:d0dfbce63a89 1586 */
elmot 1:d0dfbce63a89 1587 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 1588 {
elmot 1:d0dfbce63a89 1589 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 1590 UNUSED(htim);
elmot 1:d0dfbce63a89 1591
elmot 1:d0dfbce63a89 1592 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 1593 the HAL_TIM_IC_MspDeInit could be implemented in the user file
elmot 1:d0dfbce63a89 1594 */
elmot 1:d0dfbce63a89 1595 }
elmot 1:d0dfbce63a89 1596
elmot 1:d0dfbce63a89 1597 /**
elmot 1:d0dfbce63a89 1598 * @brief Starts the TIM Input Capture measurement.
elmot 1:d0dfbce63a89 1599 * @param htim : TIM Input Capture handle
elmot 1:d0dfbce63a89 1600 * @param Channel : TIM Channels to be enabled
elmot 1:d0dfbce63a89 1601 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1602 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 1603 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 1604 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 1605 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 1606 * @retval HAL status
elmot 1:d0dfbce63a89 1607 */
elmot 1:d0dfbce63a89 1608 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 1609 {
elmot 1:d0dfbce63a89 1610 /* Check the parameters */
elmot 1:d0dfbce63a89 1611 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 1612
elmot 1:d0dfbce63a89 1613 /* Enable the Input Capture channel */
elmot 1:d0dfbce63a89 1614 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 1615
elmot 1:d0dfbce63a89 1616 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 1617 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 1618
elmot 1:d0dfbce63a89 1619 /* Return function status */
elmot 1:d0dfbce63a89 1620 return HAL_OK;
elmot 1:d0dfbce63a89 1621 }
elmot 1:d0dfbce63a89 1622
elmot 1:d0dfbce63a89 1623 /**
elmot 1:d0dfbce63a89 1624 * @brief Stops the TIM Input Capture measurement.
elmot 1:d0dfbce63a89 1625 * @param htim : TIM handle
elmot 1:d0dfbce63a89 1626 * @param Channel : TIM Channels to be disabled
elmot 1:d0dfbce63a89 1627 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1628 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 1629 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 1630 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 1631 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 1632 * @retval HAL status
elmot 1:d0dfbce63a89 1633 */
elmot 1:d0dfbce63a89 1634 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 1635 {
elmot 1:d0dfbce63a89 1636 /* Check the parameters */
elmot 1:d0dfbce63a89 1637 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 1638
elmot 1:d0dfbce63a89 1639 /* Disable the Input Capture channel */
elmot 1:d0dfbce63a89 1640 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 1641
elmot 1:d0dfbce63a89 1642 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 1643 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 1644
elmot 1:d0dfbce63a89 1645 /* Return function status */
elmot 1:d0dfbce63a89 1646 return HAL_OK;
elmot 1:d0dfbce63a89 1647 }
elmot 1:d0dfbce63a89 1648
elmot 1:d0dfbce63a89 1649 /**
elmot 1:d0dfbce63a89 1650 * @brief Starts the TIM Input Capture measurement in interrupt mode.
elmot 1:d0dfbce63a89 1651 * @param htim : TIM Input Capture handle
elmot 1:d0dfbce63a89 1652 * @param Channel : TIM Channels to be enabled
elmot 1:d0dfbce63a89 1653 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1654 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 1655 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 1656 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 1657 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 1658 * @retval HAL status
elmot 1:d0dfbce63a89 1659 */
elmot 1:d0dfbce63a89 1660 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 1661 {
elmot 1:d0dfbce63a89 1662 /* Check the parameters */
elmot 1:d0dfbce63a89 1663 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 1664
elmot 1:d0dfbce63a89 1665 switch (Channel)
elmot 1:d0dfbce63a89 1666 {
elmot 1:d0dfbce63a89 1667 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 1668 {
elmot 1:d0dfbce63a89 1669 /* Enable the TIM Capture/Compare 1 interrupt */
elmot 1:d0dfbce63a89 1670 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
elmot 1:d0dfbce63a89 1671 }
elmot 1:d0dfbce63a89 1672 break;
elmot 1:d0dfbce63a89 1673
elmot 1:d0dfbce63a89 1674 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 1675 {
elmot 1:d0dfbce63a89 1676 /* Enable the TIM Capture/Compare 2 interrupt */
elmot 1:d0dfbce63a89 1677 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
elmot 1:d0dfbce63a89 1678 }
elmot 1:d0dfbce63a89 1679 break;
elmot 1:d0dfbce63a89 1680
elmot 1:d0dfbce63a89 1681 case TIM_CHANNEL_3:
elmot 1:d0dfbce63a89 1682 {
elmot 1:d0dfbce63a89 1683 /* Enable the TIM Capture/Compare 3 interrupt */
elmot 1:d0dfbce63a89 1684 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
elmot 1:d0dfbce63a89 1685 }
elmot 1:d0dfbce63a89 1686 break;
elmot 1:d0dfbce63a89 1687
elmot 1:d0dfbce63a89 1688 case TIM_CHANNEL_4:
elmot 1:d0dfbce63a89 1689 {
elmot 1:d0dfbce63a89 1690 /* Enable the TIM Capture/Compare 4 interrupt */
elmot 1:d0dfbce63a89 1691 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
elmot 1:d0dfbce63a89 1692 }
elmot 1:d0dfbce63a89 1693 break;
elmot 1:d0dfbce63a89 1694
elmot 1:d0dfbce63a89 1695 default:
elmot 1:d0dfbce63a89 1696 break;
elmot 1:d0dfbce63a89 1697 }
elmot 1:d0dfbce63a89 1698 /* Enable the Input Capture channel */
elmot 1:d0dfbce63a89 1699 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 1700
elmot 1:d0dfbce63a89 1701 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 1702 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 1703
elmot 1:d0dfbce63a89 1704 /* Return function status */
elmot 1:d0dfbce63a89 1705 return HAL_OK;
elmot 1:d0dfbce63a89 1706 }
elmot 1:d0dfbce63a89 1707
elmot 1:d0dfbce63a89 1708 /**
elmot 1:d0dfbce63a89 1709 * @brief Stops the TIM Input Capture measurement in interrupt mode.
elmot 1:d0dfbce63a89 1710 * @param htim : TIM handle
elmot 1:d0dfbce63a89 1711 * @param Channel : TIM Channels to be disabled
elmot 1:d0dfbce63a89 1712 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1713 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 1714 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 1715 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 1716 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 1717 * @retval HAL status
elmot 1:d0dfbce63a89 1718 */
elmot 1:d0dfbce63a89 1719 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 1720 {
elmot 1:d0dfbce63a89 1721 /* Check the parameters */
elmot 1:d0dfbce63a89 1722 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 1723
elmot 1:d0dfbce63a89 1724 switch (Channel)
elmot 1:d0dfbce63a89 1725 {
elmot 1:d0dfbce63a89 1726 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 1727 {
elmot 1:d0dfbce63a89 1728 /* Disable the TIM Capture/Compare 1 interrupt */
elmot 1:d0dfbce63a89 1729 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
elmot 1:d0dfbce63a89 1730 }
elmot 1:d0dfbce63a89 1731 break;
elmot 1:d0dfbce63a89 1732
elmot 1:d0dfbce63a89 1733 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 1734 {
elmot 1:d0dfbce63a89 1735 /* Disable the TIM Capture/Compare 2 interrupt */
elmot 1:d0dfbce63a89 1736 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
elmot 1:d0dfbce63a89 1737 }
elmot 1:d0dfbce63a89 1738 break;
elmot 1:d0dfbce63a89 1739
elmot 1:d0dfbce63a89 1740 case TIM_CHANNEL_3:
elmot 1:d0dfbce63a89 1741 {
elmot 1:d0dfbce63a89 1742 /* Disable the TIM Capture/Compare 3 interrupt */
elmot 1:d0dfbce63a89 1743 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
elmot 1:d0dfbce63a89 1744 }
elmot 1:d0dfbce63a89 1745 break;
elmot 1:d0dfbce63a89 1746
elmot 1:d0dfbce63a89 1747 case TIM_CHANNEL_4:
elmot 1:d0dfbce63a89 1748 {
elmot 1:d0dfbce63a89 1749 /* Disable the TIM Capture/Compare 4 interrupt */
elmot 1:d0dfbce63a89 1750 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
elmot 1:d0dfbce63a89 1751 }
elmot 1:d0dfbce63a89 1752 break;
elmot 1:d0dfbce63a89 1753
elmot 1:d0dfbce63a89 1754 default:
elmot 1:d0dfbce63a89 1755 break;
elmot 1:d0dfbce63a89 1756 }
elmot 1:d0dfbce63a89 1757
elmot 1:d0dfbce63a89 1758 /* Disable the Input Capture channel */
elmot 1:d0dfbce63a89 1759 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 1760
elmot 1:d0dfbce63a89 1761 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 1762 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 1763
elmot 1:d0dfbce63a89 1764 /* Return function status */
elmot 1:d0dfbce63a89 1765 return HAL_OK;
elmot 1:d0dfbce63a89 1766 }
elmot 1:d0dfbce63a89 1767
elmot 1:d0dfbce63a89 1768 /**
elmot 1:d0dfbce63a89 1769 * @brief Starts the TIM Input Capture measurement on in DMA mode.
elmot 1:d0dfbce63a89 1770 * @param htim : TIM Input Capture handle
elmot 1:d0dfbce63a89 1771 * @param Channel : TIM Channels to be enabled
elmot 1:d0dfbce63a89 1772 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1773 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 1774 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 1775 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 1776 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 1777 * @param pData: The destination Buffer address.
elmot 1:d0dfbce63a89 1778 * @param Length: The length of data to be transferred from TIM peripheral to memory.
elmot 1:d0dfbce63a89 1779 * @retval HAL status
elmot 1:d0dfbce63a89 1780 */
elmot 1:d0dfbce63a89 1781 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
elmot 1:d0dfbce63a89 1782 {
elmot 1:d0dfbce63a89 1783 /* Check the parameters */
elmot 1:d0dfbce63a89 1784 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 1785 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 1786
elmot 1:d0dfbce63a89 1787 if((htim->State == HAL_TIM_STATE_BUSY))
elmot 1:d0dfbce63a89 1788 {
elmot 1:d0dfbce63a89 1789 return HAL_BUSY;
elmot 1:d0dfbce63a89 1790 }
elmot 1:d0dfbce63a89 1791 else if((htim->State == HAL_TIM_STATE_READY))
elmot 1:d0dfbce63a89 1792 {
elmot 1:d0dfbce63a89 1793 if((pData == 0 ) && (Length > 0))
elmot 1:d0dfbce63a89 1794 {
elmot 1:d0dfbce63a89 1795 return HAL_ERROR;
elmot 1:d0dfbce63a89 1796 }
elmot 1:d0dfbce63a89 1797 else
elmot 1:d0dfbce63a89 1798 {
elmot 1:d0dfbce63a89 1799 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 1800 }
elmot 1:d0dfbce63a89 1801 }
elmot 1:d0dfbce63a89 1802
elmot 1:d0dfbce63a89 1803 switch (Channel)
elmot 1:d0dfbce63a89 1804 {
elmot 1:d0dfbce63a89 1805 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 1806 {
elmot 1:d0dfbce63a89 1807 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 1808 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
elmot 1:d0dfbce63a89 1809
elmot 1:d0dfbce63a89 1810 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 1811 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 1812
elmot 1:d0dfbce63a89 1813 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 1814 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
elmot 1:d0dfbce63a89 1815
elmot 1:d0dfbce63a89 1816 /* Enable the TIM Capture/Compare 1 DMA request */
elmot 1:d0dfbce63a89 1817 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
elmot 1:d0dfbce63a89 1818 }
elmot 1:d0dfbce63a89 1819 break;
elmot 1:d0dfbce63a89 1820
elmot 1:d0dfbce63a89 1821 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 1822 {
elmot 1:d0dfbce63a89 1823 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 1824 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
elmot 1:d0dfbce63a89 1825
elmot 1:d0dfbce63a89 1826 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 1827 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 1828
elmot 1:d0dfbce63a89 1829 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 1830 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
elmot 1:d0dfbce63a89 1831
elmot 1:d0dfbce63a89 1832 /* Enable the TIM Capture/Compare 2 DMA request */
elmot 1:d0dfbce63a89 1833 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
elmot 1:d0dfbce63a89 1834 }
elmot 1:d0dfbce63a89 1835 break;
elmot 1:d0dfbce63a89 1836
elmot 1:d0dfbce63a89 1837 case TIM_CHANNEL_3:
elmot 1:d0dfbce63a89 1838 {
elmot 1:d0dfbce63a89 1839 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 1840 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
elmot 1:d0dfbce63a89 1841
elmot 1:d0dfbce63a89 1842 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 1843 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 1844
elmot 1:d0dfbce63a89 1845 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 1846 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
elmot 1:d0dfbce63a89 1847
elmot 1:d0dfbce63a89 1848 /* Enable the TIM Capture/Compare 3 DMA request */
elmot 1:d0dfbce63a89 1849 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
elmot 1:d0dfbce63a89 1850 }
elmot 1:d0dfbce63a89 1851 break;
elmot 1:d0dfbce63a89 1852
elmot 1:d0dfbce63a89 1853 case TIM_CHANNEL_4:
elmot 1:d0dfbce63a89 1854 {
elmot 1:d0dfbce63a89 1855 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 1856 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
elmot 1:d0dfbce63a89 1857
elmot 1:d0dfbce63a89 1858 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 1859 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 1860
elmot 1:d0dfbce63a89 1861 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 1862 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
elmot 1:d0dfbce63a89 1863
elmot 1:d0dfbce63a89 1864 /* Enable the TIM Capture/Compare 4 DMA request */
elmot 1:d0dfbce63a89 1865 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
elmot 1:d0dfbce63a89 1866 }
elmot 1:d0dfbce63a89 1867 break;
elmot 1:d0dfbce63a89 1868
elmot 1:d0dfbce63a89 1869 default:
elmot 1:d0dfbce63a89 1870 break;
elmot 1:d0dfbce63a89 1871 }
elmot 1:d0dfbce63a89 1872
elmot 1:d0dfbce63a89 1873 /* Enable the Input Capture channel */
elmot 1:d0dfbce63a89 1874 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 1875
elmot 1:d0dfbce63a89 1876 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 1877 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 1878
elmot 1:d0dfbce63a89 1879 /* Return function status */
elmot 1:d0dfbce63a89 1880 return HAL_OK;
elmot 1:d0dfbce63a89 1881 }
elmot 1:d0dfbce63a89 1882
elmot 1:d0dfbce63a89 1883 /**
elmot 1:d0dfbce63a89 1884 * @brief Stops the TIM Input Capture measurement on in DMA mode.
elmot 1:d0dfbce63a89 1885 * @param htim : TIM Input Capture handle
elmot 1:d0dfbce63a89 1886 * @param Channel : TIM Channels to be disabled
elmot 1:d0dfbce63a89 1887 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1888 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 1889 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 1890 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 1891 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 1892 * @retval HAL status
elmot 1:d0dfbce63a89 1893 */
elmot 1:d0dfbce63a89 1894 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 1895 {
elmot 1:d0dfbce63a89 1896 /* Check the parameters */
elmot 1:d0dfbce63a89 1897 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elmot 1:d0dfbce63a89 1898 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 1899
elmot 1:d0dfbce63a89 1900 switch (Channel)
elmot 1:d0dfbce63a89 1901 {
elmot 1:d0dfbce63a89 1902 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 1903 {
elmot 1:d0dfbce63a89 1904 /* Disable the TIM Capture/Compare 1 DMA request */
elmot 1:d0dfbce63a89 1905 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
elmot 1:d0dfbce63a89 1906 }
elmot 1:d0dfbce63a89 1907 break;
elmot 1:d0dfbce63a89 1908
elmot 1:d0dfbce63a89 1909 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 1910 {
elmot 1:d0dfbce63a89 1911 /* Disable the TIM Capture/Compare 2 DMA request */
elmot 1:d0dfbce63a89 1912 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
elmot 1:d0dfbce63a89 1913 }
elmot 1:d0dfbce63a89 1914 break;
elmot 1:d0dfbce63a89 1915
elmot 1:d0dfbce63a89 1916 case TIM_CHANNEL_3:
elmot 1:d0dfbce63a89 1917 {
elmot 1:d0dfbce63a89 1918 /* Disable the TIM Capture/Compare 3 DMA request */
elmot 1:d0dfbce63a89 1919 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
elmot 1:d0dfbce63a89 1920 }
elmot 1:d0dfbce63a89 1921 break;
elmot 1:d0dfbce63a89 1922
elmot 1:d0dfbce63a89 1923 case TIM_CHANNEL_4:
elmot 1:d0dfbce63a89 1924 {
elmot 1:d0dfbce63a89 1925 /* Disable the TIM Capture/Compare 4 DMA request */
elmot 1:d0dfbce63a89 1926 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
elmot 1:d0dfbce63a89 1927 }
elmot 1:d0dfbce63a89 1928 break;
elmot 1:d0dfbce63a89 1929
elmot 1:d0dfbce63a89 1930 default:
elmot 1:d0dfbce63a89 1931 break;
elmot 1:d0dfbce63a89 1932 }
elmot 1:d0dfbce63a89 1933
elmot 1:d0dfbce63a89 1934 /* Disable the Input Capture channel */
elmot 1:d0dfbce63a89 1935 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 1936
elmot 1:d0dfbce63a89 1937 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 1938 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 1939
elmot 1:d0dfbce63a89 1940 /* Change the htim state */
elmot 1:d0dfbce63a89 1941 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 1942
elmot 1:d0dfbce63a89 1943 /* Return function status */
elmot 1:d0dfbce63a89 1944 return HAL_OK;
elmot 1:d0dfbce63a89 1945 }
elmot 1:d0dfbce63a89 1946 /**
elmot 1:d0dfbce63a89 1947 * @}
elmot 1:d0dfbce63a89 1948 */
elmot 1:d0dfbce63a89 1949
elmot 1:d0dfbce63a89 1950 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
elmot 1:d0dfbce63a89 1951 * @brief Time One Pulse functions
elmot 1:d0dfbce63a89 1952 *
elmot 1:d0dfbce63a89 1953 @verbatim
elmot 1:d0dfbce63a89 1954 ==============================================================================
elmot 1:d0dfbce63a89 1955 ##### Time One Pulse functions #####
elmot 1:d0dfbce63a89 1956 ==============================================================================
elmot 1:d0dfbce63a89 1957 [..]
elmot 1:d0dfbce63a89 1958 This section provides functions allowing to:
elmot 1:d0dfbce63a89 1959 (+) Initialize and configure the TIM One Pulse.
elmot 1:d0dfbce63a89 1960 (+) De-initialize the TIM One Pulse.
elmot 1:d0dfbce63a89 1961 (+) Start the Time One Pulse.
elmot 1:d0dfbce63a89 1962 (+) Stop the Time One Pulse.
elmot 1:d0dfbce63a89 1963 (+) Start the Time One Pulse and enable interrupt.
elmot 1:d0dfbce63a89 1964 (+) Stop the Time One Pulse and disable interrupt.
elmot 1:d0dfbce63a89 1965 (+) Start the Time One Pulse and enable DMA transfer.
elmot 1:d0dfbce63a89 1966 (+) Stop the Time One Pulse and disable DMA transfer.
elmot 1:d0dfbce63a89 1967
elmot 1:d0dfbce63a89 1968 @endverbatim
elmot 1:d0dfbce63a89 1969 * @{
elmot 1:d0dfbce63a89 1970 */
elmot 1:d0dfbce63a89 1971 /**
elmot 1:d0dfbce63a89 1972 * @brief Initializes the TIM One Pulse Time Base according to the specified
elmot 1:d0dfbce63a89 1973 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
elmot 1:d0dfbce63a89 1974 * @param htim: TIM OnePulse handle
elmot 1:d0dfbce63a89 1975 * @param OnePulseMode: Select the One pulse mode.
elmot 1:d0dfbce63a89 1976 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1977 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
elmot 1:d0dfbce63a89 1978 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
elmot 1:d0dfbce63a89 1979 * @retval HAL status
elmot 1:d0dfbce63a89 1980 */
elmot 1:d0dfbce63a89 1981 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
elmot 1:d0dfbce63a89 1982 {
elmot 1:d0dfbce63a89 1983 /* Check the TIM handle allocation */
elmot 1:d0dfbce63a89 1984 if(htim == NULL)
elmot 1:d0dfbce63a89 1985 {
elmot 1:d0dfbce63a89 1986 return HAL_ERROR;
elmot 1:d0dfbce63a89 1987 }
elmot 1:d0dfbce63a89 1988
elmot 1:d0dfbce63a89 1989 /* Check the parameters */
elmot 1:d0dfbce63a89 1990 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 1991 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
elmot 1:d0dfbce63a89 1992 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
elmot 1:d0dfbce63a89 1993 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
elmot 1:d0dfbce63a89 1994
elmot 1:d0dfbce63a89 1995 if(htim->State == HAL_TIM_STATE_RESET)
elmot 1:d0dfbce63a89 1996 {
elmot 1:d0dfbce63a89 1997 /* Allocate lock resource and initialize it */
elmot 1:d0dfbce63a89 1998 htim->Lock = HAL_UNLOCKED;
elmot 1:d0dfbce63a89 1999
elmot 1:d0dfbce63a89 2000 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
elmot 1:d0dfbce63a89 2001 HAL_TIM_OnePulse_MspInit(htim);
elmot 1:d0dfbce63a89 2002 }
elmot 1:d0dfbce63a89 2003
elmot 1:d0dfbce63a89 2004 /* Set the TIM state */
elmot 1:d0dfbce63a89 2005 htim->State= HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 2006
elmot 1:d0dfbce63a89 2007 /* Configure the Time base in the One Pulse Mode */
elmot 1:d0dfbce63a89 2008 TIM_Base_SetConfig(htim->Instance, &htim->Init);
elmot 1:d0dfbce63a89 2009
elmot 1:d0dfbce63a89 2010 /* Reset the OPM Bit */
elmot 1:d0dfbce63a89 2011 htim->Instance->CR1 &= ~TIM_CR1_OPM;
elmot 1:d0dfbce63a89 2012
elmot 1:d0dfbce63a89 2013 /* Configure the OPM Mode */
elmot 1:d0dfbce63a89 2014 htim->Instance->CR1 |= OnePulseMode;
elmot 1:d0dfbce63a89 2015
elmot 1:d0dfbce63a89 2016 /* Initialize the TIM state*/
elmot 1:d0dfbce63a89 2017 htim->State= HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 2018
elmot 1:d0dfbce63a89 2019 return HAL_OK;
elmot 1:d0dfbce63a89 2020 }
elmot 1:d0dfbce63a89 2021
elmot 1:d0dfbce63a89 2022 /**
elmot 1:d0dfbce63a89 2023 * @brief DeInitialize the TIM One Pulse
elmot 1:d0dfbce63a89 2024 * @param htim: TIM One Pulse handle
elmot 1:d0dfbce63a89 2025 * @retval HAL status
elmot 1:d0dfbce63a89 2026 */
elmot 1:d0dfbce63a89 2027 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 2028 {
elmot 1:d0dfbce63a89 2029 /* Check the parameters */
elmot 1:d0dfbce63a89 2030 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 2031
elmot 1:d0dfbce63a89 2032 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 2033
elmot 1:d0dfbce63a89 2034 /* Disable the TIM Peripheral Clock */
elmot 1:d0dfbce63a89 2035 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 2036
elmot 1:d0dfbce63a89 2037 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
elmot 1:d0dfbce63a89 2038 HAL_TIM_OnePulse_MspDeInit(htim);
elmot 1:d0dfbce63a89 2039
elmot 1:d0dfbce63a89 2040 /* Change TIM state */
elmot 1:d0dfbce63a89 2041 htim->State = HAL_TIM_STATE_RESET;
elmot 1:d0dfbce63a89 2042
elmot 1:d0dfbce63a89 2043 /* Release Lock */
elmot 1:d0dfbce63a89 2044 __HAL_UNLOCK(htim);
elmot 1:d0dfbce63a89 2045
elmot 1:d0dfbce63a89 2046 return HAL_OK;
elmot 1:d0dfbce63a89 2047 }
elmot 1:d0dfbce63a89 2048
elmot 1:d0dfbce63a89 2049 /**
elmot 1:d0dfbce63a89 2050 * @brief Initializes the TIM One Pulse MSP.
elmot 1:d0dfbce63a89 2051 * @param htim: TIM handle
elmot 1:d0dfbce63a89 2052 * @retval None
elmot 1:d0dfbce63a89 2053 */
elmot 1:d0dfbce63a89 2054 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 2055 {
elmot 1:d0dfbce63a89 2056 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 2057 UNUSED(htim);
elmot 1:d0dfbce63a89 2058
elmot 1:d0dfbce63a89 2059 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 2060 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
elmot 1:d0dfbce63a89 2061 */
elmot 1:d0dfbce63a89 2062 }
elmot 1:d0dfbce63a89 2063
elmot 1:d0dfbce63a89 2064 /**
elmot 1:d0dfbce63a89 2065 * @brief DeInitialize TIM One Pulse MSP.
elmot 1:d0dfbce63a89 2066 * @param htim: TIM handle
elmot 1:d0dfbce63a89 2067 * @retval None
elmot 1:d0dfbce63a89 2068 */
elmot 1:d0dfbce63a89 2069 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 2070 {
elmot 1:d0dfbce63a89 2071 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 2072 UNUSED(htim);
elmot 1:d0dfbce63a89 2073
elmot 1:d0dfbce63a89 2074 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 2075 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
elmot 1:d0dfbce63a89 2076 */
elmot 1:d0dfbce63a89 2077 }
elmot 1:d0dfbce63a89 2078
elmot 1:d0dfbce63a89 2079 /**
elmot 1:d0dfbce63a89 2080 * @brief Starts the TIM One Pulse signal generation.
elmot 1:d0dfbce63a89 2081 * @param htim : TIM One Pulse handle
elmot 1:d0dfbce63a89 2082 * @param OutputChannel : TIM Channels to be enabled
elmot 1:d0dfbce63a89 2083 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2084 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 2085 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 2086 * @retval HAL status
elmot 1:d0dfbce63a89 2087 */
elmot 1:d0dfbce63a89 2088 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
elmot 1:d0dfbce63a89 2089 {
elmot 1:d0dfbce63a89 2090 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 2091 UNUSED(OutputChannel);
elmot 1:d0dfbce63a89 2092
elmot 1:d0dfbce63a89 2093 /* Enable the Capture compare and the Input Capture channels
elmot 1:d0dfbce63a89 2094 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
elmot 1:d0dfbce63a89 2095 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
elmot 1:d0dfbce63a89 2096 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
elmot 1:d0dfbce63a89 2097 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
elmot 1:d0dfbce63a89 2098
elmot 1:d0dfbce63a89 2099 No need to enable the counter, it's enabled automatically by hardware
elmot 1:d0dfbce63a89 2100 (the counter starts in response to a stimulus and generate a pulse */
elmot 1:d0dfbce63a89 2101
elmot 1:d0dfbce63a89 2102 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 2103 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 2104
elmot 1:d0dfbce63a89 2105 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
elmot 1:d0dfbce63a89 2106 {
elmot 1:d0dfbce63a89 2107 /* Enable the main output */
elmot 1:d0dfbce63a89 2108 __HAL_TIM_MOE_ENABLE(htim);
elmot 1:d0dfbce63a89 2109 }
elmot 1:d0dfbce63a89 2110
elmot 1:d0dfbce63a89 2111 /* Return function status */
elmot 1:d0dfbce63a89 2112 return HAL_OK;
elmot 1:d0dfbce63a89 2113 }
elmot 1:d0dfbce63a89 2114
elmot 1:d0dfbce63a89 2115 /**
elmot 1:d0dfbce63a89 2116 * @brief Stops the TIM One Pulse signal generation.
elmot 1:d0dfbce63a89 2117 * @param htim : TIM One Pulse handle
elmot 1:d0dfbce63a89 2118 * @param OutputChannel : TIM Channels to be disable
elmot 1:d0dfbce63a89 2119 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2120 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 2121 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 2122 * @retval HAL status
elmot 1:d0dfbce63a89 2123 */
elmot 1:d0dfbce63a89 2124 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
elmot 1:d0dfbce63a89 2125 {
elmot 1:d0dfbce63a89 2126 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 2127 UNUSED(OutputChannel);
elmot 1:d0dfbce63a89 2128
elmot 1:d0dfbce63a89 2129 /* Disable the Capture compare and the Input Capture channels
elmot 1:d0dfbce63a89 2130 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
elmot 1:d0dfbce63a89 2131 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
elmot 1:d0dfbce63a89 2132 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
elmot 1:d0dfbce63a89 2133 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
elmot 1:d0dfbce63a89 2134
elmot 1:d0dfbce63a89 2135 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 2136 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 2137
elmot 1:d0dfbce63a89 2138 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
elmot 1:d0dfbce63a89 2139 {
elmot 1:d0dfbce63a89 2140 /* Disable the Main Ouput */
elmot 1:d0dfbce63a89 2141 __HAL_TIM_MOE_DISABLE(htim);
elmot 1:d0dfbce63a89 2142 }
elmot 1:d0dfbce63a89 2143
elmot 1:d0dfbce63a89 2144 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 2145 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 2146
elmot 1:d0dfbce63a89 2147 /* Return function status */
elmot 1:d0dfbce63a89 2148 return HAL_OK;
elmot 1:d0dfbce63a89 2149 }
elmot 1:d0dfbce63a89 2150
elmot 1:d0dfbce63a89 2151 /**
elmot 1:d0dfbce63a89 2152 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
elmot 1:d0dfbce63a89 2153 * @param htim : TIM One Pulse handle
elmot 1:d0dfbce63a89 2154 * @param OutputChannel : TIM Channels to be enabled
elmot 1:d0dfbce63a89 2155 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2156 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 2157 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 2158 * @retval HAL status
elmot 1:d0dfbce63a89 2159 */
elmot 1:d0dfbce63a89 2160 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
elmot 1:d0dfbce63a89 2161 {
elmot 1:d0dfbce63a89 2162 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 2163 UNUSED(OutputChannel);
elmot 1:d0dfbce63a89 2164
elmot 1:d0dfbce63a89 2165 /* Enable the Capture compare and the Input Capture channels
elmot 1:d0dfbce63a89 2166 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
elmot 1:d0dfbce63a89 2167 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
elmot 1:d0dfbce63a89 2168 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
elmot 1:d0dfbce63a89 2169 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
elmot 1:d0dfbce63a89 2170
elmot 1:d0dfbce63a89 2171 No need to enable the counter, it's enabled automatically by hardware
elmot 1:d0dfbce63a89 2172 (the counter starts in response to a stimulus and generate a pulse */
elmot 1:d0dfbce63a89 2173
elmot 1:d0dfbce63a89 2174 /* Enable the TIM Capture/Compare 1 interrupt */
elmot 1:d0dfbce63a89 2175 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
elmot 1:d0dfbce63a89 2176
elmot 1:d0dfbce63a89 2177 /* Enable the TIM Capture/Compare 2 interrupt */
elmot 1:d0dfbce63a89 2178 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
elmot 1:d0dfbce63a89 2179
elmot 1:d0dfbce63a89 2180 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 2181 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 2182
elmot 1:d0dfbce63a89 2183 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
elmot 1:d0dfbce63a89 2184 {
elmot 1:d0dfbce63a89 2185 /* Enable the main output */
elmot 1:d0dfbce63a89 2186 __HAL_TIM_MOE_ENABLE(htim);
elmot 1:d0dfbce63a89 2187 }
elmot 1:d0dfbce63a89 2188
elmot 1:d0dfbce63a89 2189 /* Return function status */
elmot 1:d0dfbce63a89 2190 return HAL_OK;
elmot 1:d0dfbce63a89 2191 }
elmot 1:d0dfbce63a89 2192
elmot 1:d0dfbce63a89 2193 /**
elmot 1:d0dfbce63a89 2194 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
elmot 1:d0dfbce63a89 2195 * @param htim : TIM One Pulse handle
elmot 1:d0dfbce63a89 2196 * @param OutputChannel : TIM Channels to be enabled
elmot 1:d0dfbce63a89 2197 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2198 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 2199 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 2200 * @retval HAL status
elmot 1:d0dfbce63a89 2201 */
elmot 1:d0dfbce63a89 2202 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
elmot 1:d0dfbce63a89 2203 {
elmot 1:d0dfbce63a89 2204 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 2205 UNUSED(OutputChannel);
elmot 1:d0dfbce63a89 2206
elmot 1:d0dfbce63a89 2207 /* Disable the TIM Capture/Compare 1 interrupt */
elmot 1:d0dfbce63a89 2208 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
elmot 1:d0dfbce63a89 2209
elmot 1:d0dfbce63a89 2210 /* Disable the TIM Capture/Compare 2 interrupt */
elmot 1:d0dfbce63a89 2211 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
elmot 1:d0dfbce63a89 2212
elmot 1:d0dfbce63a89 2213 /* Disable the Capture compare and the Input Capture channels
elmot 1:d0dfbce63a89 2214 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
elmot 1:d0dfbce63a89 2215 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
elmot 1:d0dfbce63a89 2216 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
elmot 1:d0dfbce63a89 2217 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
elmot 1:d0dfbce63a89 2218 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 2219 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 2220
elmot 1:d0dfbce63a89 2221 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
elmot 1:d0dfbce63a89 2222 {
elmot 1:d0dfbce63a89 2223 /* Disable the Main Ouput */
elmot 1:d0dfbce63a89 2224 __HAL_TIM_MOE_DISABLE(htim);
elmot 1:d0dfbce63a89 2225 }
elmot 1:d0dfbce63a89 2226
elmot 1:d0dfbce63a89 2227 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 2228 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 2229
elmot 1:d0dfbce63a89 2230 /* Return function status */
elmot 1:d0dfbce63a89 2231 return HAL_OK;
elmot 1:d0dfbce63a89 2232 }
elmot 1:d0dfbce63a89 2233
elmot 1:d0dfbce63a89 2234 /**
elmot 1:d0dfbce63a89 2235 * @}
elmot 1:d0dfbce63a89 2236 */
elmot 1:d0dfbce63a89 2237
elmot 1:d0dfbce63a89 2238 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
elmot 1:d0dfbce63a89 2239 * @brief Time Encoder functions
elmot 1:d0dfbce63a89 2240 *
elmot 1:d0dfbce63a89 2241 @verbatim
elmot 1:d0dfbce63a89 2242 ==============================================================================
elmot 1:d0dfbce63a89 2243 ##### Time Encoder functions #####
elmot 1:d0dfbce63a89 2244 ==============================================================================
elmot 1:d0dfbce63a89 2245 [..]
elmot 1:d0dfbce63a89 2246 This section provides functions allowing to:
elmot 1:d0dfbce63a89 2247 (+) Initialize and configure the TIM Encoder.
elmot 1:d0dfbce63a89 2248 (+) De-initialize the TIM Encoder.
elmot 1:d0dfbce63a89 2249 (+) Start the Time Encoder.
elmot 1:d0dfbce63a89 2250 (+) Stop the Time Encoder.
elmot 1:d0dfbce63a89 2251 (+) Start the Time Encoder and enable interrupt.
elmot 1:d0dfbce63a89 2252 (+) Stop the Time Encoder and disable interrupt.
elmot 1:d0dfbce63a89 2253 (+) Start the Time Encoder and enable DMA transfer.
elmot 1:d0dfbce63a89 2254 (+) Stop the Time Encoder and disable DMA transfer.
elmot 1:d0dfbce63a89 2255
elmot 1:d0dfbce63a89 2256 @endverbatim
elmot 1:d0dfbce63a89 2257 * @{
elmot 1:d0dfbce63a89 2258 */
elmot 1:d0dfbce63a89 2259 /**
elmot 1:d0dfbce63a89 2260 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
elmot 1:d0dfbce63a89 2261 * @param htim: TIM Encoder Interface handle
elmot 1:d0dfbce63a89 2262 * @param sConfig: TIM Encoder Interface configuration structure
elmot 1:d0dfbce63a89 2263 * @retval HAL status
elmot 1:d0dfbce63a89 2264 */
elmot 1:d0dfbce63a89 2265 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
elmot 1:d0dfbce63a89 2266 {
elmot 1:d0dfbce63a89 2267 uint32_t tmpsmcr = 0;
elmot 1:d0dfbce63a89 2268 uint32_t tmpccmr1 = 0;
elmot 1:d0dfbce63a89 2269 uint32_t tmpccer = 0;
elmot 1:d0dfbce63a89 2270
elmot 1:d0dfbce63a89 2271 /* Check the TIM handle allocation */
elmot 1:d0dfbce63a89 2272 if(htim == NULL)
elmot 1:d0dfbce63a89 2273 {
elmot 1:d0dfbce63a89 2274 return HAL_ERROR;
elmot 1:d0dfbce63a89 2275 }
elmot 1:d0dfbce63a89 2276
elmot 1:d0dfbce63a89 2277 /* Check the parameters */
elmot 1:d0dfbce63a89 2278 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 2279 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
elmot 1:d0dfbce63a89 2280 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
elmot 1:d0dfbce63a89 2281 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
elmot 1:d0dfbce63a89 2282 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
elmot 1:d0dfbce63a89 2283 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
elmot 1:d0dfbce63a89 2284 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
elmot 1:d0dfbce63a89 2285 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
elmot 1:d0dfbce63a89 2286 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
elmot 1:d0dfbce63a89 2287 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
elmot 1:d0dfbce63a89 2288
elmot 1:d0dfbce63a89 2289 if(htim->State == HAL_TIM_STATE_RESET)
elmot 1:d0dfbce63a89 2290 {
elmot 1:d0dfbce63a89 2291 /* Allocate lock resource and initialize it */
elmot 1:d0dfbce63a89 2292 htim->Lock = HAL_UNLOCKED;
elmot 1:d0dfbce63a89 2293
elmot 1:d0dfbce63a89 2294 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
elmot 1:d0dfbce63a89 2295 HAL_TIM_Encoder_MspInit(htim);
elmot 1:d0dfbce63a89 2296 }
elmot 1:d0dfbce63a89 2297
elmot 1:d0dfbce63a89 2298 /* Set the TIM state */
elmot 1:d0dfbce63a89 2299 htim->State= HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 2300
elmot 1:d0dfbce63a89 2301 /* Reset the SMS bits */
elmot 1:d0dfbce63a89 2302 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
elmot 1:d0dfbce63a89 2303
elmot 1:d0dfbce63a89 2304 /* Configure the Time base in the Encoder Mode */
elmot 1:d0dfbce63a89 2305 TIM_Base_SetConfig(htim->Instance, &htim->Init);
elmot 1:d0dfbce63a89 2306
elmot 1:d0dfbce63a89 2307 /* Get the TIMx SMCR register value */
elmot 1:d0dfbce63a89 2308 tmpsmcr = htim->Instance->SMCR;
elmot 1:d0dfbce63a89 2309
elmot 1:d0dfbce63a89 2310 /* Get the TIMx CCMR1 register value */
elmot 1:d0dfbce63a89 2311 tmpccmr1 = htim->Instance->CCMR1;
elmot 1:d0dfbce63a89 2312
elmot 1:d0dfbce63a89 2313 /* Get the TIMx CCER register value */
elmot 1:d0dfbce63a89 2314 tmpccer = htim->Instance->CCER;
elmot 1:d0dfbce63a89 2315
elmot 1:d0dfbce63a89 2316 /* Set the encoder Mode */
elmot 1:d0dfbce63a89 2317 tmpsmcr |= sConfig->EncoderMode;
elmot 1:d0dfbce63a89 2318
elmot 1:d0dfbce63a89 2319 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
elmot 1:d0dfbce63a89 2320 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
elmot 1:d0dfbce63a89 2321 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
elmot 1:d0dfbce63a89 2322
elmot 1:d0dfbce63a89 2323 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
elmot 1:d0dfbce63a89 2324 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
elmot 1:d0dfbce63a89 2325 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
elmot 1:d0dfbce63a89 2326 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
elmot 1:d0dfbce63a89 2327 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
elmot 1:d0dfbce63a89 2328
elmot 1:d0dfbce63a89 2329 /* Set the TI1 and the TI2 Polarities */
elmot 1:d0dfbce63a89 2330 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
elmot 1:d0dfbce63a89 2331 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
elmot 1:d0dfbce63a89 2332 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
elmot 1:d0dfbce63a89 2333
elmot 1:d0dfbce63a89 2334 /* Write to TIMx SMCR */
elmot 1:d0dfbce63a89 2335 htim->Instance->SMCR = tmpsmcr;
elmot 1:d0dfbce63a89 2336
elmot 1:d0dfbce63a89 2337 /* Write to TIMx CCMR1 */
elmot 1:d0dfbce63a89 2338 htim->Instance->CCMR1 = tmpccmr1;
elmot 1:d0dfbce63a89 2339
elmot 1:d0dfbce63a89 2340 /* Write to TIMx CCER */
elmot 1:d0dfbce63a89 2341 htim->Instance->CCER = tmpccer;
elmot 1:d0dfbce63a89 2342
elmot 1:d0dfbce63a89 2343 /* Initialize the TIM state*/
elmot 1:d0dfbce63a89 2344 htim->State= HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 2345
elmot 1:d0dfbce63a89 2346 return HAL_OK;
elmot 1:d0dfbce63a89 2347 }
elmot 1:d0dfbce63a89 2348
elmot 1:d0dfbce63a89 2349
elmot 1:d0dfbce63a89 2350 /**
elmot 1:d0dfbce63a89 2351 * @brief DeInitialize the TIM Encoder interface
elmot 1:d0dfbce63a89 2352 * @param htim: TIM Encoder handle
elmot 1:d0dfbce63a89 2353 * @retval HAL status
elmot 1:d0dfbce63a89 2354 */
elmot 1:d0dfbce63a89 2355 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 2356 {
elmot 1:d0dfbce63a89 2357 /* Check the parameters */
elmot 1:d0dfbce63a89 2358 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 2359
elmot 1:d0dfbce63a89 2360 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 2361
elmot 1:d0dfbce63a89 2362 /* Disable the TIM Peripheral Clock */
elmot 1:d0dfbce63a89 2363 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 2364
elmot 1:d0dfbce63a89 2365 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
elmot 1:d0dfbce63a89 2366 HAL_TIM_Encoder_MspDeInit(htim);
elmot 1:d0dfbce63a89 2367
elmot 1:d0dfbce63a89 2368 /* Change TIM state */
elmot 1:d0dfbce63a89 2369 htim->State = HAL_TIM_STATE_RESET;
elmot 1:d0dfbce63a89 2370
elmot 1:d0dfbce63a89 2371 /* Release Lock */
elmot 1:d0dfbce63a89 2372 __HAL_UNLOCK(htim);
elmot 1:d0dfbce63a89 2373
elmot 1:d0dfbce63a89 2374 return HAL_OK;
elmot 1:d0dfbce63a89 2375 }
elmot 1:d0dfbce63a89 2376
elmot 1:d0dfbce63a89 2377 /**
elmot 1:d0dfbce63a89 2378 * @brief Initializes the TIM Encoder Interface MSP.
elmot 1:d0dfbce63a89 2379 * @param htim: TIM handle
elmot 1:d0dfbce63a89 2380 * @retval None
elmot 1:d0dfbce63a89 2381 */
elmot 1:d0dfbce63a89 2382 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 2383 {
elmot 1:d0dfbce63a89 2384 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 2385 UNUSED(htim);
elmot 1:d0dfbce63a89 2386
elmot 1:d0dfbce63a89 2387 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 2388 the HAL_TIM_Encoder_MspInit could be implemented in the user file
elmot 1:d0dfbce63a89 2389 */
elmot 1:d0dfbce63a89 2390 }
elmot 1:d0dfbce63a89 2391
elmot 1:d0dfbce63a89 2392 /**
elmot 1:d0dfbce63a89 2393 * @brief DeInitialize TIM Encoder Interface MSP.
elmot 1:d0dfbce63a89 2394 * @param htim: TIM handle
elmot 1:d0dfbce63a89 2395 * @retval None
elmot 1:d0dfbce63a89 2396 */
elmot 1:d0dfbce63a89 2397 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 2398 {
elmot 1:d0dfbce63a89 2399 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 2400 UNUSED(htim);
elmot 1:d0dfbce63a89 2401
elmot 1:d0dfbce63a89 2402 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 2403 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
elmot 1:d0dfbce63a89 2404 */
elmot 1:d0dfbce63a89 2405 }
elmot 1:d0dfbce63a89 2406
elmot 1:d0dfbce63a89 2407 /**
elmot 1:d0dfbce63a89 2408 * @brief Starts the TIM Encoder Interface.
elmot 1:d0dfbce63a89 2409 * @param htim : TIM Encoder Interface handle
elmot 1:d0dfbce63a89 2410 * @param Channel : TIM Channels to be enabled
elmot 1:d0dfbce63a89 2411 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2412 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 2413 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 2414 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
elmot 1:d0dfbce63a89 2415 * @retval HAL status
elmot 1:d0dfbce63a89 2416 */
elmot 1:d0dfbce63a89 2417 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 2418 {
elmot 1:d0dfbce63a89 2419 /* Check the parameters */
elmot 1:d0dfbce63a89 2420 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 2421
elmot 1:d0dfbce63a89 2422 /* Enable the encoder interface channels */
elmot 1:d0dfbce63a89 2423 switch (Channel)
elmot 1:d0dfbce63a89 2424 {
elmot 1:d0dfbce63a89 2425 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 2426 {
elmot 1:d0dfbce63a89 2427 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 2428 }
elmot 1:d0dfbce63a89 2429 break;
elmot 1:d0dfbce63a89 2430
elmot 1:d0dfbce63a89 2431 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 2432 {
elmot 1:d0dfbce63a89 2433 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 2434 }
elmot 1:d0dfbce63a89 2435 break;
elmot 1:d0dfbce63a89 2436
elmot 1:d0dfbce63a89 2437 default :
elmot 1:d0dfbce63a89 2438 {
elmot 1:d0dfbce63a89 2439 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 2440 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 2441 }
elmot 1:d0dfbce63a89 2442 break;
elmot 1:d0dfbce63a89 2443 }
elmot 1:d0dfbce63a89 2444 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 2445 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 2446
elmot 1:d0dfbce63a89 2447 /* Return function status */
elmot 1:d0dfbce63a89 2448 return HAL_OK;
elmot 1:d0dfbce63a89 2449 }
elmot 1:d0dfbce63a89 2450
elmot 1:d0dfbce63a89 2451 /**
elmot 1:d0dfbce63a89 2452 * @brief Stops the TIM Encoder Interface.
elmot 1:d0dfbce63a89 2453 * @param htim : TIM Encoder Interface handle
elmot 1:d0dfbce63a89 2454 * @param Channel : TIM Channels to be disabled
elmot 1:d0dfbce63a89 2455 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2456 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 2457 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 2458 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
elmot 1:d0dfbce63a89 2459 * @retval HAL status
elmot 1:d0dfbce63a89 2460 */
elmot 1:d0dfbce63a89 2461 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 2462 {
elmot 1:d0dfbce63a89 2463 /* Check the parameters */
elmot 1:d0dfbce63a89 2464 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 2465
elmot 1:d0dfbce63a89 2466 /* Disable the Input Capture channels 1 and 2
elmot 1:d0dfbce63a89 2467 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
elmot 1:d0dfbce63a89 2468 switch (Channel)
elmot 1:d0dfbce63a89 2469 {
elmot 1:d0dfbce63a89 2470 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 2471 {
elmot 1:d0dfbce63a89 2472 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 2473 }
elmot 1:d0dfbce63a89 2474 break;
elmot 1:d0dfbce63a89 2475
elmot 1:d0dfbce63a89 2476 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 2477 {
elmot 1:d0dfbce63a89 2478 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 2479 }
elmot 1:d0dfbce63a89 2480 break;
elmot 1:d0dfbce63a89 2481
elmot 1:d0dfbce63a89 2482 default :
elmot 1:d0dfbce63a89 2483 {
elmot 1:d0dfbce63a89 2484 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 2485 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 2486 }
elmot 1:d0dfbce63a89 2487 break;
elmot 1:d0dfbce63a89 2488 }
elmot 1:d0dfbce63a89 2489
elmot 1:d0dfbce63a89 2490 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 2491 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 2492
elmot 1:d0dfbce63a89 2493 /* Return function status */
elmot 1:d0dfbce63a89 2494 return HAL_OK;
elmot 1:d0dfbce63a89 2495 }
elmot 1:d0dfbce63a89 2496
elmot 1:d0dfbce63a89 2497 /**
elmot 1:d0dfbce63a89 2498 * @brief Starts the TIM Encoder Interface in interrupt mode.
elmot 1:d0dfbce63a89 2499 * @param htim : TIM Encoder Interface handle
elmot 1:d0dfbce63a89 2500 * @param Channel : TIM Channels to be enabled
elmot 1:d0dfbce63a89 2501 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2502 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 2503 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 2504 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
elmot 1:d0dfbce63a89 2505 * @retval HAL status
elmot 1:d0dfbce63a89 2506 */
elmot 1:d0dfbce63a89 2507 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 2508 {
elmot 1:d0dfbce63a89 2509 /* Check the parameters */
elmot 1:d0dfbce63a89 2510 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 2511
elmot 1:d0dfbce63a89 2512 /* Enable the encoder interface channels */
elmot 1:d0dfbce63a89 2513 /* Enable the capture compare Interrupts 1 and/or 2 */
elmot 1:d0dfbce63a89 2514 switch (Channel)
elmot 1:d0dfbce63a89 2515 {
elmot 1:d0dfbce63a89 2516 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 2517 {
elmot 1:d0dfbce63a89 2518 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 2519 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
elmot 1:d0dfbce63a89 2520 }
elmot 1:d0dfbce63a89 2521 break;
elmot 1:d0dfbce63a89 2522
elmot 1:d0dfbce63a89 2523 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 2524 {
elmot 1:d0dfbce63a89 2525 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 2526 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
elmot 1:d0dfbce63a89 2527 }
elmot 1:d0dfbce63a89 2528 break;
elmot 1:d0dfbce63a89 2529
elmot 1:d0dfbce63a89 2530 default :
elmot 1:d0dfbce63a89 2531 {
elmot 1:d0dfbce63a89 2532 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 2533 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 2534 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
elmot 1:d0dfbce63a89 2535 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
elmot 1:d0dfbce63a89 2536 }
elmot 1:d0dfbce63a89 2537 break;
elmot 1:d0dfbce63a89 2538 }
elmot 1:d0dfbce63a89 2539
elmot 1:d0dfbce63a89 2540 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 2541 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 2542
elmot 1:d0dfbce63a89 2543 /* Return function status */
elmot 1:d0dfbce63a89 2544 return HAL_OK;
elmot 1:d0dfbce63a89 2545 }
elmot 1:d0dfbce63a89 2546
elmot 1:d0dfbce63a89 2547 /**
elmot 1:d0dfbce63a89 2548 * @brief Stops the TIM Encoder Interface in interrupt mode.
elmot 1:d0dfbce63a89 2549 * @param htim : TIM Encoder Interface handle
elmot 1:d0dfbce63a89 2550 * @param Channel : TIM Channels to be disabled
elmot 1:d0dfbce63a89 2551 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2552 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 2553 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 2554 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
elmot 1:d0dfbce63a89 2555 * @retval HAL status
elmot 1:d0dfbce63a89 2556 */
elmot 1:d0dfbce63a89 2557 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 2558 {
elmot 1:d0dfbce63a89 2559 /* Check the parameters */
elmot 1:d0dfbce63a89 2560 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 2561
elmot 1:d0dfbce63a89 2562 /* Disable the Input Capture channels 1 and 2
elmot 1:d0dfbce63a89 2563 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
elmot 1:d0dfbce63a89 2564 if(Channel == TIM_CHANNEL_1)
elmot 1:d0dfbce63a89 2565 {
elmot 1:d0dfbce63a89 2566 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 2567
elmot 1:d0dfbce63a89 2568 /* Disable the capture compare Interrupts 1 */
elmot 1:d0dfbce63a89 2569 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
elmot 1:d0dfbce63a89 2570 }
elmot 1:d0dfbce63a89 2571 else if(Channel == TIM_CHANNEL_2)
elmot 1:d0dfbce63a89 2572 {
elmot 1:d0dfbce63a89 2573 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 2574
elmot 1:d0dfbce63a89 2575 /* Disable the capture compare Interrupts 2 */
elmot 1:d0dfbce63a89 2576 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
elmot 1:d0dfbce63a89 2577 }
elmot 1:d0dfbce63a89 2578 else
elmot 1:d0dfbce63a89 2579 {
elmot 1:d0dfbce63a89 2580 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 2581 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 2582
elmot 1:d0dfbce63a89 2583 /* Disable the capture compare Interrupts 1 and 2 */
elmot 1:d0dfbce63a89 2584 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
elmot 1:d0dfbce63a89 2585 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
elmot 1:d0dfbce63a89 2586 }
elmot 1:d0dfbce63a89 2587
elmot 1:d0dfbce63a89 2588 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 2589 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 2590
elmot 1:d0dfbce63a89 2591 /* Change the htim state */
elmot 1:d0dfbce63a89 2592 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 2593
elmot 1:d0dfbce63a89 2594 /* Return function status */
elmot 1:d0dfbce63a89 2595 return HAL_OK;
elmot 1:d0dfbce63a89 2596 }
elmot 1:d0dfbce63a89 2597
elmot 1:d0dfbce63a89 2598 /**
elmot 1:d0dfbce63a89 2599 * @brief Starts the TIM Encoder Interface in DMA mode.
elmot 1:d0dfbce63a89 2600 * @param htim : TIM Encoder Interface handle
elmot 1:d0dfbce63a89 2601 * @param Channel : TIM Channels to be enabled
elmot 1:d0dfbce63a89 2602 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2603 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 2604 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 2605 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
elmot 1:d0dfbce63a89 2606 * @param pData1: The destination Buffer address for IC1.
elmot 1:d0dfbce63a89 2607 * @param pData2: The destination Buffer address for IC2.
elmot 1:d0dfbce63a89 2608 * @param Length: The length of data to be transferred from TIM peripheral to memory.
elmot 1:d0dfbce63a89 2609 * @retval HAL status
elmot 1:d0dfbce63a89 2610 */
elmot 1:d0dfbce63a89 2611 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
elmot 1:d0dfbce63a89 2612 {
elmot 1:d0dfbce63a89 2613 /* Check the parameters */
elmot 1:d0dfbce63a89 2614 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 2615
elmot 1:d0dfbce63a89 2616 if((htim->State == HAL_TIM_STATE_BUSY))
elmot 1:d0dfbce63a89 2617 {
elmot 1:d0dfbce63a89 2618 return HAL_BUSY;
elmot 1:d0dfbce63a89 2619 }
elmot 1:d0dfbce63a89 2620 else if((htim->State == HAL_TIM_STATE_READY))
elmot 1:d0dfbce63a89 2621 {
elmot 1:d0dfbce63a89 2622 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
elmot 1:d0dfbce63a89 2623 {
elmot 1:d0dfbce63a89 2624 return HAL_ERROR;
elmot 1:d0dfbce63a89 2625 }
elmot 1:d0dfbce63a89 2626 else
elmot 1:d0dfbce63a89 2627 {
elmot 1:d0dfbce63a89 2628 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 2629 }
elmot 1:d0dfbce63a89 2630 }
elmot 1:d0dfbce63a89 2631
elmot 1:d0dfbce63a89 2632 switch (Channel)
elmot 1:d0dfbce63a89 2633 {
elmot 1:d0dfbce63a89 2634 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 2635 {
elmot 1:d0dfbce63a89 2636 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 2637 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
elmot 1:d0dfbce63a89 2638
elmot 1:d0dfbce63a89 2639 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 2640 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 2641
elmot 1:d0dfbce63a89 2642 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 2643 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
elmot 1:d0dfbce63a89 2644
elmot 1:d0dfbce63a89 2645 /* Enable the TIM Input Capture DMA request */
elmot 1:d0dfbce63a89 2646 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
elmot 1:d0dfbce63a89 2647
elmot 1:d0dfbce63a89 2648 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 2649 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 2650
elmot 1:d0dfbce63a89 2651 /* Enable the Capture compare channel */
elmot 1:d0dfbce63a89 2652 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 2653 }
elmot 1:d0dfbce63a89 2654 break;
elmot 1:d0dfbce63a89 2655
elmot 1:d0dfbce63a89 2656 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 2657 {
elmot 1:d0dfbce63a89 2658 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 2659 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
elmot 1:d0dfbce63a89 2660
elmot 1:d0dfbce63a89 2661 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 2662 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
elmot 1:d0dfbce63a89 2663 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 2664 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
elmot 1:d0dfbce63a89 2665
elmot 1:d0dfbce63a89 2666 /* Enable the TIM Input Capture DMA request */
elmot 1:d0dfbce63a89 2667 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
elmot 1:d0dfbce63a89 2668
elmot 1:d0dfbce63a89 2669 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 2670 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 2671
elmot 1:d0dfbce63a89 2672 /* Enable the Capture compare channel */
elmot 1:d0dfbce63a89 2673 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 2674 }
elmot 1:d0dfbce63a89 2675 break;
elmot 1:d0dfbce63a89 2676
elmot 1:d0dfbce63a89 2677 case TIM_CHANNEL_ALL:
elmot 1:d0dfbce63a89 2678 {
elmot 1:d0dfbce63a89 2679 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 2680 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
elmot 1:d0dfbce63a89 2681
elmot 1:d0dfbce63a89 2682 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 2683 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 2684
elmot 1:d0dfbce63a89 2685 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 2686 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
elmot 1:d0dfbce63a89 2687
elmot 1:d0dfbce63a89 2688 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 2689 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
elmot 1:d0dfbce63a89 2690
elmot 1:d0dfbce63a89 2691 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 2692 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 2693
elmot 1:d0dfbce63a89 2694 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 2695 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
elmot 1:d0dfbce63a89 2696
elmot 1:d0dfbce63a89 2697 /* Enable the Peripheral */
elmot 1:d0dfbce63a89 2698 __HAL_TIM_ENABLE(htim);
elmot 1:d0dfbce63a89 2699
elmot 1:d0dfbce63a89 2700 /* Enable the Capture compare channel */
elmot 1:d0dfbce63a89 2701 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 2702 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
elmot 1:d0dfbce63a89 2703
elmot 1:d0dfbce63a89 2704 /* Enable the TIM Input Capture DMA request */
elmot 1:d0dfbce63a89 2705 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
elmot 1:d0dfbce63a89 2706 /* Enable the TIM Input Capture DMA request */
elmot 1:d0dfbce63a89 2707 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
elmot 1:d0dfbce63a89 2708 }
elmot 1:d0dfbce63a89 2709 break;
elmot 1:d0dfbce63a89 2710
elmot 1:d0dfbce63a89 2711 default:
elmot 1:d0dfbce63a89 2712 break;
elmot 1:d0dfbce63a89 2713 }
elmot 1:d0dfbce63a89 2714 /* Return function status */
elmot 1:d0dfbce63a89 2715 return HAL_OK;
elmot 1:d0dfbce63a89 2716 }
elmot 1:d0dfbce63a89 2717
elmot 1:d0dfbce63a89 2718 /**
elmot 1:d0dfbce63a89 2719 * @brief Stops the TIM Encoder Interface in DMA mode.
elmot 1:d0dfbce63a89 2720 * @param htim : TIM Encoder Interface handle
elmot 1:d0dfbce63a89 2721 * @param Channel : TIM Channels to be enabled
elmot 1:d0dfbce63a89 2722 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2723 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 2724 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 2725 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
elmot 1:d0dfbce63a89 2726 * @retval HAL status
elmot 1:d0dfbce63a89 2727 */
elmot 1:d0dfbce63a89 2728 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 2729 {
elmot 1:d0dfbce63a89 2730 /* Check the parameters */
elmot 1:d0dfbce63a89 2731 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 2732
elmot 1:d0dfbce63a89 2733 /* Disable the Input Capture channels 1 and 2
elmot 1:d0dfbce63a89 2734 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
elmot 1:d0dfbce63a89 2735 if(Channel == TIM_CHANNEL_1)
elmot 1:d0dfbce63a89 2736 {
elmot 1:d0dfbce63a89 2737 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 2738
elmot 1:d0dfbce63a89 2739 /* Disable the capture compare DMA Request 1 */
elmot 1:d0dfbce63a89 2740 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
elmot 1:d0dfbce63a89 2741 }
elmot 1:d0dfbce63a89 2742 else if(Channel == TIM_CHANNEL_2)
elmot 1:d0dfbce63a89 2743 {
elmot 1:d0dfbce63a89 2744 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 2745
elmot 1:d0dfbce63a89 2746 /* Disable the capture compare DMA Request 2 */
elmot 1:d0dfbce63a89 2747 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
elmot 1:d0dfbce63a89 2748 }
elmot 1:d0dfbce63a89 2749 else
elmot 1:d0dfbce63a89 2750 {
elmot 1:d0dfbce63a89 2751 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 2752 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
elmot 1:d0dfbce63a89 2753
elmot 1:d0dfbce63a89 2754 /* Disable the capture compare DMA Request 1 and 2 */
elmot 1:d0dfbce63a89 2755 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
elmot 1:d0dfbce63a89 2756 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
elmot 1:d0dfbce63a89 2757 }
elmot 1:d0dfbce63a89 2758
elmot 1:d0dfbce63a89 2759 /* Disable the Peripheral */
elmot 1:d0dfbce63a89 2760 __HAL_TIM_DISABLE(htim);
elmot 1:d0dfbce63a89 2761
elmot 1:d0dfbce63a89 2762 /* Change the htim state */
elmot 1:d0dfbce63a89 2763 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 2764
elmot 1:d0dfbce63a89 2765 /* Return function status */
elmot 1:d0dfbce63a89 2766 return HAL_OK;
elmot 1:d0dfbce63a89 2767 }
elmot 1:d0dfbce63a89 2768
elmot 1:d0dfbce63a89 2769 /**
elmot 1:d0dfbce63a89 2770 * @}
elmot 1:d0dfbce63a89 2771 */
elmot 1:d0dfbce63a89 2772 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
elmot 1:d0dfbce63a89 2773 * @brief IRQ handler management
elmot 1:d0dfbce63a89 2774 *
elmot 1:d0dfbce63a89 2775 @verbatim
elmot 1:d0dfbce63a89 2776 ==============================================================================
elmot 1:d0dfbce63a89 2777 ##### IRQ handler management #####
elmot 1:d0dfbce63a89 2778 ==============================================================================
elmot 1:d0dfbce63a89 2779 [..]
elmot 1:d0dfbce63a89 2780 This section provides Timer IRQ handler function.
elmot 1:d0dfbce63a89 2781
elmot 1:d0dfbce63a89 2782 @endverbatim
elmot 1:d0dfbce63a89 2783 * @{
elmot 1:d0dfbce63a89 2784 */
elmot 1:d0dfbce63a89 2785 /**
elmot 1:d0dfbce63a89 2786 * @brief This function handles TIM interrupts requests.
elmot 1:d0dfbce63a89 2787 * @param htim: TIM handle
elmot 1:d0dfbce63a89 2788 * @retval None
elmot 1:d0dfbce63a89 2789 */
elmot 1:d0dfbce63a89 2790 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 2791 {
elmot 1:d0dfbce63a89 2792 /* Capture compare 1 event */
elmot 1:d0dfbce63a89 2793 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
elmot 1:d0dfbce63a89 2794 {
elmot 1:d0dfbce63a89 2795 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
elmot 1:d0dfbce63a89 2796 {
elmot 1:d0dfbce63a89 2797 {
elmot 1:d0dfbce63a89 2798 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
elmot 1:d0dfbce63a89 2799 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
elmot 1:d0dfbce63a89 2800
elmot 1:d0dfbce63a89 2801 /* Input capture event */
elmot 1:d0dfbce63a89 2802 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
elmot 1:d0dfbce63a89 2803 {
elmot 1:d0dfbce63a89 2804 HAL_TIM_IC_CaptureCallback(htim);
elmot 1:d0dfbce63a89 2805 }
elmot 1:d0dfbce63a89 2806 /* Output compare event */
elmot 1:d0dfbce63a89 2807 else
elmot 1:d0dfbce63a89 2808 {
elmot 1:d0dfbce63a89 2809 HAL_TIM_OC_DelayElapsedCallback(htim);
elmot 1:d0dfbce63a89 2810 HAL_TIM_PWM_PulseFinishedCallback(htim);
elmot 1:d0dfbce63a89 2811 }
elmot 1:d0dfbce63a89 2812 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
elmot 1:d0dfbce63a89 2813 }
elmot 1:d0dfbce63a89 2814 }
elmot 1:d0dfbce63a89 2815 }
elmot 1:d0dfbce63a89 2816 /* Capture compare 2 event */
elmot 1:d0dfbce63a89 2817 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
elmot 1:d0dfbce63a89 2818 {
elmot 1:d0dfbce63a89 2819 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
elmot 1:d0dfbce63a89 2820 {
elmot 1:d0dfbce63a89 2821 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
elmot 1:d0dfbce63a89 2822 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
elmot 1:d0dfbce63a89 2823 /* Input capture event */
elmot 1:d0dfbce63a89 2824 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
elmot 1:d0dfbce63a89 2825 {
elmot 1:d0dfbce63a89 2826 HAL_TIM_IC_CaptureCallback(htim);
elmot 1:d0dfbce63a89 2827 }
elmot 1:d0dfbce63a89 2828 /* Output compare event */
elmot 1:d0dfbce63a89 2829 else
elmot 1:d0dfbce63a89 2830 {
elmot 1:d0dfbce63a89 2831 HAL_TIM_OC_DelayElapsedCallback(htim);
elmot 1:d0dfbce63a89 2832 HAL_TIM_PWM_PulseFinishedCallback(htim);
elmot 1:d0dfbce63a89 2833 }
elmot 1:d0dfbce63a89 2834 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
elmot 1:d0dfbce63a89 2835 }
elmot 1:d0dfbce63a89 2836 }
elmot 1:d0dfbce63a89 2837 /* Capture compare 3 event */
elmot 1:d0dfbce63a89 2838 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
elmot 1:d0dfbce63a89 2839 {
elmot 1:d0dfbce63a89 2840 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
elmot 1:d0dfbce63a89 2841 {
elmot 1:d0dfbce63a89 2842 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
elmot 1:d0dfbce63a89 2843 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
elmot 1:d0dfbce63a89 2844 /* Input capture event */
elmot 1:d0dfbce63a89 2845 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
elmot 1:d0dfbce63a89 2846 {
elmot 1:d0dfbce63a89 2847 HAL_TIM_IC_CaptureCallback(htim);
elmot 1:d0dfbce63a89 2848 }
elmot 1:d0dfbce63a89 2849 /* Output compare event */
elmot 1:d0dfbce63a89 2850 else
elmot 1:d0dfbce63a89 2851 {
elmot 1:d0dfbce63a89 2852 HAL_TIM_OC_DelayElapsedCallback(htim);
elmot 1:d0dfbce63a89 2853 HAL_TIM_PWM_PulseFinishedCallback(htim);
elmot 1:d0dfbce63a89 2854 }
elmot 1:d0dfbce63a89 2855 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
elmot 1:d0dfbce63a89 2856 }
elmot 1:d0dfbce63a89 2857 }
elmot 1:d0dfbce63a89 2858 /* Capture compare 4 event */
elmot 1:d0dfbce63a89 2859 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
elmot 1:d0dfbce63a89 2860 {
elmot 1:d0dfbce63a89 2861 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
elmot 1:d0dfbce63a89 2862 {
elmot 1:d0dfbce63a89 2863 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
elmot 1:d0dfbce63a89 2864 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
elmot 1:d0dfbce63a89 2865 /* Input capture event */
elmot 1:d0dfbce63a89 2866 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
elmot 1:d0dfbce63a89 2867 {
elmot 1:d0dfbce63a89 2868 HAL_TIM_IC_CaptureCallback(htim);
elmot 1:d0dfbce63a89 2869 }
elmot 1:d0dfbce63a89 2870 /* Output compare event */
elmot 1:d0dfbce63a89 2871 else
elmot 1:d0dfbce63a89 2872 {
elmot 1:d0dfbce63a89 2873 HAL_TIM_OC_DelayElapsedCallback(htim);
elmot 1:d0dfbce63a89 2874 HAL_TIM_PWM_PulseFinishedCallback(htim);
elmot 1:d0dfbce63a89 2875 }
elmot 1:d0dfbce63a89 2876 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
elmot 1:d0dfbce63a89 2877 }
elmot 1:d0dfbce63a89 2878 }
elmot 1:d0dfbce63a89 2879 /* TIM Update event */
elmot 1:d0dfbce63a89 2880 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
elmot 1:d0dfbce63a89 2881 {
elmot 1:d0dfbce63a89 2882 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
elmot 1:d0dfbce63a89 2883 {
elmot 1:d0dfbce63a89 2884 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
elmot 1:d0dfbce63a89 2885 HAL_TIM_PeriodElapsedCallback(htim);
elmot 1:d0dfbce63a89 2886 }
elmot 1:d0dfbce63a89 2887 }
elmot 1:d0dfbce63a89 2888 /* TIM Break input event */
elmot 1:d0dfbce63a89 2889 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
elmot 1:d0dfbce63a89 2890 {
elmot 1:d0dfbce63a89 2891 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
elmot 1:d0dfbce63a89 2892 {
elmot 1:d0dfbce63a89 2893 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
elmot 1:d0dfbce63a89 2894 HAL_TIMEx_BreakCallback(htim);
elmot 1:d0dfbce63a89 2895 }
elmot 1:d0dfbce63a89 2896 }
elmot 1:d0dfbce63a89 2897 /* TIM Trigger detection event */
elmot 1:d0dfbce63a89 2898 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
elmot 1:d0dfbce63a89 2899 {
elmot 1:d0dfbce63a89 2900 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
elmot 1:d0dfbce63a89 2901 {
elmot 1:d0dfbce63a89 2902 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
elmot 1:d0dfbce63a89 2903 HAL_TIM_TriggerCallback(htim);
elmot 1:d0dfbce63a89 2904 }
elmot 1:d0dfbce63a89 2905 }
elmot 1:d0dfbce63a89 2906 /* TIM commutation event */
elmot 1:d0dfbce63a89 2907 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
elmot 1:d0dfbce63a89 2908 {
elmot 1:d0dfbce63a89 2909 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
elmot 1:d0dfbce63a89 2910 {
elmot 1:d0dfbce63a89 2911 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
elmot 1:d0dfbce63a89 2912 HAL_TIMEx_CommutationCallback(htim);
elmot 1:d0dfbce63a89 2913 }
elmot 1:d0dfbce63a89 2914 }
elmot 1:d0dfbce63a89 2915 }
elmot 1:d0dfbce63a89 2916
elmot 1:d0dfbce63a89 2917 /**
elmot 1:d0dfbce63a89 2918 * @}
elmot 1:d0dfbce63a89 2919 */
elmot 1:d0dfbce63a89 2920
elmot 1:d0dfbce63a89 2921 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
elmot 1:d0dfbce63a89 2922 * @brief Peripheral Control functions
elmot 1:d0dfbce63a89 2923 *
elmot 1:d0dfbce63a89 2924 @verbatim
elmot 1:d0dfbce63a89 2925 ==============================================================================
elmot 1:d0dfbce63a89 2926 ##### Peripheral Control functions #####
elmot 1:d0dfbce63a89 2927 ==============================================================================
elmot 1:d0dfbce63a89 2928 [..]
elmot 1:d0dfbce63a89 2929 This section provides functions allowing to:
elmot 1:d0dfbce63a89 2930 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
elmot 1:d0dfbce63a89 2931 (+) Configure External Clock source.
elmot 1:d0dfbce63a89 2932 (+) Configure Complementary channels, break features and dead time.
elmot 1:d0dfbce63a89 2933 (+) Configure Master and the Slave synchronization.
elmot 1:d0dfbce63a89 2934 (+) Configure the DMA Burst Mode.
elmot 1:d0dfbce63a89 2935
elmot 1:d0dfbce63a89 2936 @endverbatim
elmot 1:d0dfbce63a89 2937 * @{
elmot 1:d0dfbce63a89 2938 */
elmot 1:d0dfbce63a89 2939
elmot 1:d0dfbce63a89 2940 /**
elmot 1:d0dfbce63a89 2941 * @brief Initializes the TIM Output Compare Channels according to the specified
elmot 1:d0dfbce63a89 2942 * parameters in the TIM_OC_InitTypeDef.
elmot 1:d0dfbce63a89 2943 * @param htim: TIM Output Compare handle
elmot 1:d0dfbce63a89 2944 * @param sConfig: TIM Output Compare configuration structure
elmot 1:d0dfbce63a89 2945 * @param Channel : TIM Channels to configure
elmot 1:d0dfbce63a89 2946 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2947 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 2948 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 2949 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 2950 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 2951 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
elmot 1:d0dfbce63a89 2952 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
elmot 1:d0dfbce63a89 2953 * @retval HAL status
elmot 1:d0dfbce63a89 2954 */
elmot 1:d0dfbce63a89 2955 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
elmot 1:d0dfbce63a89 2956 TIM_OC_InitTypeDef* sConfig,
elmot 1:d0dfbce63a89 2957 uint32_t Channel)
elmot 1:d0dfbce63a89 2958 {
elmot 1:d0dfbce63a89 2959 /* Check the parameters */
elmot 1:d0dfbce63a89 2960 assert_param(IS_TIM_CHANNELS(Channel));
elmot 1:d0dfbce63a89 2961 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
elmot 1:d0dfbce63a89 2962 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
elmot 1:d0dfbce63a89 2963
elmot 1:d0dfbce63a89 2964 /* Process Locked */
elmot 1:d0dfbce63a89 2965 __HAL_LOCK(htim);
elmot 1:d0dfbce63a89 2966
elmot 1:d0dfbce63a89 2967 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 2968
elmot 1:d0dfbce63a89 2969 switch (Channel)
elmot 1:d0dfbce63a89 2970 {
elmot 1:d0dfbce63a89 2971 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 2972 {
elmot 1:d0dfbce63a89 2973 /* Check the parameters */
elmot 1:d0dfbce63a89 2974 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 2975
elmot 1:d0dfbce63a89 2976 /* Configure the TIM Channel 1 in Output Compare */
elmot 1:d0dfbce63a89 2977 TIM_OC1_SetConfig(htim->Instance, sConfig);
elmot 1:d0dfbce63a89 2978 }
elmot 1:d0dfbce63a89 2979 break;
elmot 1:d0dfbce63a89 2980
elmot 1:d0dfbce63a89 2981 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 2982 {
elmot 1:d0dfbce63a89 2983 /* Check the parameters */
elmot 1:d0dfbce63a89 2984 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 2985
elmot 1:d0dfbce63a89 2986 /* Configure the TIM Channel 2 in Output Compare */
elmot 1:d0dfbce63a89 2987 TIM_OC2_SetConfig(htim->Instance, sConfig);
elmot 1:d0dfbce63a89 2988 }
elmot 1:d0dfbce63a89 2989 break;
elmot 1:d0dfbce63a89 2990
elmot 1:d0dfbce63a89 2991 case TIM_CHANNEL_3:
elmot 1:d0dfbce63a89 2992 {
elmot 1:d0dfbce63a89 2993 /* Check the parameters */
elmot 1:d0dfbce63a89 2994 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 2995
elmot 1:d0dfbce63a89 2996 /* Configure the TIM Channel 3 in Output Compare */
elmot 1:d0dfbce63a89 2997 TIM_OC3_SetConfig(htim->Instance, sConfig);
elmot 1:d0dfbce63a89 2998 }
elmot 1:d0dfbce63a89 2999 break;
elmot 1:d0dfbce63a89 3000
elmot 1:d0dfbce63a89 3001 case TIM_CHANNEL_4:
elmot 1:d0dfbce63a89 3002 {
elmot 1:d0dfbce63a89 3003 /* Check the parameters */
elmot 1:d0dfbce63a89 3004 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3005
elmot 1:d0dfbce63a89 3006 /* Configure the TIM Channel 4 in Output Compare */
elmot 1:d0dfbce63a89 3007 TIM_OC4_SetConfig(htim->Instance, sConfig);
elmot 1:d0dfbce63a89 3008 }
elmot 1:d0dfbce63a89 3009 break;
elmot 1:d0dfbce63a89 3010
elmot 1:d0dfbce63a89 3011 case TIM_CHANNEL_5:
elmot 1:d0dfbce63a89 3012 {
elmot 1:d0dfbce63a89 3013 /* Check the parameters */
elmot 1:d0dfbce63a89 3014 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3015
elmot 1:d0dfbce63a89 3016 /* Configure the TIM Channel 5 in Output Compare */
elmot 1:d0dfbce63a89 3017 TIM_OC5_SetConfig(htim->Instance, sConfig);
elmot 1:d0dfbce63a89 3018 }
elmot 1:d0dfbce63a89 3019 break;
elmot 1:d0dfbce63a89 3020
elmot 1:d0dfbce63a89 3021 case TIM_CHANNEL_6:
elmot 1:d0dfbce63a89 3022 {
elmot 1:d0dfbce63a89 3023 /* Check the parameters */
elmot 1:d0dfbce63a89 3024 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3025
elmot 1:d0dfbce63a89 3026 /* Configure the TIM Channel 6 in Output Compare */
elmot 1:d0dfbce63a89 3027 TIM_OC6_SetConfig(htim->Instance, sConfig);
elmot 1:d0dfbce63a89 3028 }
elmot 1:d0dfbce63a89 3029 break;
elmot 1:d0dfbce63a89 3030
elmot 1:d0dfbce63a89 3031 default:
elmot 1:d0dfbce63a89 3032 break;
elmot 1:d0dfbce63a89 3033 }
elmot 1:d0dfbce63a89 3034
elmot 1:d0dfbce63a89 3035 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 3036
elmot 1:d0dfbce63a89 3037 __HAL_UNLOCK(htim);
elmot 1:d0dfbce63a89 3038
elmot 1:d0dfbce63a89 3039 return HAL_OK;
elmot 1:d0dfbce63a89 3040 }
elmot 1:d0dfbce63a89 3041
elmot 1:d0dfbce63a89 3042 /**
elmot 1:d0dfbce63a89 3043 * @brief Initializes the TIM Input Capture Channels according to the specified
elmot 1:d0dfbce63a89 3044 * parameters in the TIM_IC_InitTypeDef.
elmot 1:d0dfbce63a89 3045 * @param htim: TIM IC handle
elmot 1:d0dfbce63a89 3046 * @param sConfig: TIM Input Capture configuration structure
elmot 1:d0dfbce63a89 3047 * @param Channel : TIM Channels to be enabled
elmot 1:d0dfbce63a89 3048 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3049 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 3050 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 3051 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 3052 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 3053 * @retval HAL status
elmot 1:d0dfbce63a89 3054 */
elmot 1:d0dfbce63a89 3055 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
elmot 1:d0dfbce63a89 3056 {
elmot 1:d0dfbce63a89 3057 /* Check the parameters */
elmot 1:d0dfbce63a89 3058 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3059 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
elmot 1:d0dfbce63a89 3060 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
elmot 1:d0dfbce63a89 3061 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
elmot 1:d0dfbce63a89 3062 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
elmot 1:d0dfbce63a89 3063
elmot 1:d0dfbce63a89 3064 /* Process Locked */
elmot 1:d0dfbce63a89 3065 __HAL_LOCK(htim);
elmot 1:d0dfbce63a89 3066
elmot 1:d0dfbce63a89 3067 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 3068
elmot 1:d0dfbce63a89 3069 if (Channel == TIM_CHANNEL_1)
elmot 1:d0dfbce63a89 3070 {
elmot 1:d0dfbce63a89 3071 /* TI1 Configuration */
elmot 1:d0dfbce63a89 3072 TIM_TI1_SetConfig(htim->Instance,
elmot 1:d0dfbce63a89 3073 sConfig->ICPolarity,
elmot 1:d0dfbce63a89 3074 sConfig->ICSelection,
elmot 1:d0dfbce63a89 3075 sConfig->ICFilter);
elmot 1:d0dfbce63a89 3076
elmot 1:d0dfbce63a89 3077 /* Reset the IC1PSC Bits */
elmot 1:d0dfbce63a89 3078 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
elmot 1:d0dfbce63a89 3079
elmot 1:d0dfbce63a89 3080 /* Set the IC1PSC value */
elmot 1:d0dfbce63a89 3081 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
elmot 1:d0dfbce63a89 3082 }
elmot 1:d0dfbce63a89 3083 else if (Channel == TIM_CHANNEL_2)
elmot 1:d0dfbce63a89 3084 {
elmot 1:d0dfbce63a89 3085 /* TI2 Configuration */
elmot 1:d0dfbce63a89 3086 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3087
elmot 1:d0dfbce63a89 3088 TIM_TI2_SetConfig(htim->Instance,
elmot 1:d0dfbce63a89 3089 sConfig->ICPolarity,
elmot 1:d0dfbce63a89 3090 sConfig->ICSelection,
elmot 1:d0dfbce63a89 3091 sConfig->ICFilter);
elmot 1:d0dfbce63a89 3092
elmot 1:d0dfbce63a89 3093 /* Reset the IC2PSC Bits */
elmot 1:d0dfbce63a89 3094 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
elmot 1:d0dfbce63a89 3095
elmot 1:d0dfbce63a89 3096 /* Set the IC2PSC value */
elmot 1:d0dfbce63a89 3097 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
elmot 1:d0dfbce63a89 3098 }
elmot 1:d0dfbce63a89 3099 else if (Channel == TIM_CHANNEL_3)
elmot 1:d0dfbce63a89 3100 {
elmot 1:d0dfbce63a89 3101 /* TI3 Configuration */
elmot 1:d0dfbce63a89 3102 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3103
elmot 1:d0dfbce63a89 3104 TIM_TI3_SetConfig(htim->Instance,
elmot 1:d0dfbce63a89 3105 sConfig->ICPolarity,
elmot 1:d0dfbce63a89 3106 sConfig->ICSelection,
elmot 1:d0dfbce63a89 3107 sConfig->ICFilter);
elmot 1:d0dfbce63a89 3108
elmot 1:d0dfbce63a89 3109 /* Reset the IC3PSC Bits */
elmot 1:d0dfbce63a89 3110 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
elmot 1:d0dfbce63a89 3111
elmot 1:d0dfbce63a89 3112 /* Set the IC3PSC value */
elmot 1:d0dfbce63a89 3113 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
elmot 1:d0dfbce63a89 3114 }
elmot 1:d0dfbce63a89 3115 else
elmot 1:d0dfbce63a89 3116 {
elmot 1:d0dfbce63a89 3117 /* TI4 Configuration */
elmot 1:d0dfbce63a89 3118 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3119
elmot 1:d0dfbce63a89 3120 TIM_TI4_SetConfig(htim->Instance,
elmot 1:d0dfbce63a89 3121 sConfig->ICPolarity,
elmot 1:d0dfbce63a89 3122 sConfig->ICSelection,
elmot 1:d0dfbce63a89 3123 sConfig->ICFilter);
elmot 1:d0dfbce63a89 3124
elmot 1:d0dfbce63a89 3125 /* Reset the IC4PSC Bits */
elmot 1:d0dfbce63a89 3126 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
elmot 1:d0dfbce63a89 3127
elmot 1:d0dfbce63a89 3128 /* Set the IC4PSC value */
elmot 1:d0dfbce63a89 3129 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
elmot 1:d0dfbce63a89 3130 }
elmot 1:d0dfbce63a89 3131
elmot 1:d0dfbce63a89 3132 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 3133
elmot 1:d0dfbce63a89 3134 __HAL_UNLOCK(htim);
elmot 1:d0dfbce63a89 3135
elmot 1:d0dfbce63a89 3136 return HAL_OK;
elmot 1:d0dfbce63a89 3137 }
elmot 1:d0dfbce63a89 3138
elmot 1:d0dfbce63a89 3139 /**
elmot 1:d0dfbce63a89 3140 * @brief Initializes the TIM PWM channels according to the specified
elmot 1:d0dfbce63a89 3141 * parameters in the TIM_OC_InitTypeDef.
elmot 1:d0dfbce63a89 3142 * @param htim: TIM PWM handle
elmot 1:d0dfbce63a89 3143 * @param sConfig: TIM PWM configuration structure
elmot 1:d0dfbce63a89 3144 * @param Channel : TIM Channels to be configured
elmot 1:d0dfbce63a89 3145 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3146 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 3147 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 3148 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 3149 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 3150 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
elmot 1:d0dfbce63a89 3151 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
elmot 1:d0dfbce63a89 3152 * @retval HAL status
elmot 1:d0dfbce63a89 3153 */
elmot 1:d0dfbce63a89 3154 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
elmot 1:d0dfbce63a89 3155 TIM_OC_InitTypeDef* sConfig,
elmot 1:d0dfbce63a89 3156 uint32_t Channel)
elmot 1:d0dfbce63a89 3157 {
elmot 1:d0dfbce63a89 3158 /* Check the parameters */
elmot 1:d0dfbce63a89 3159 assert_param(IS_TIM_CHANNELS(Channel));
elmot 1:d0dfbce63a89 3160 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
elmot 1:d0dfbce63a89 3161 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
elmot 1:d0dfbce63a89 3162 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
elmot 1:d0dfbce63a89 3163
elmot 1:d0dfbce63a89 3164 /* Process Locked */
elmot 1:d0dfbce63a89 3165 __HAL_LOCK(htim);
elmot 1:d0dfbce63a89 3166
elmot 1:d0dfbce63a89 3167 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 3168
elmot 1:d0dfbce63a89 3169 switch (Channel)
elmot 1:d0dfbce63a89 3170 {
elmot 1:d0dfbce63a89 3171 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 3172 {
elmot 1:d0dfbce63a89 3173 /* Check the parameters */
elmot 1:d0dfbce63a89 3174 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3175
elmot 1:d0dfbce63a89 3176 /* Configure the Channel 1 in PWM mode */
elmot 1:d0dfbce63a89 3177 TIM_OC1_SetConfig(htim->Instance, sConfig);
elmot 1:d0dfbce63a89 3178
elmot 1:d0dfbce63a89 3179 /* Set the Preload enable bit for channel1 */
elmot 1:d0dfbce63a89 3180 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
elmot 1:d0dfbce63a89 3181
elmot 1:d0dfbce63a89 3182 /* Configure the Output Fast mode */
elmot 1:d0dfbce63a89 3183 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
elmot 1:d0dfbce63a89 3184 htim->Instance->CCMR1 |= sConfig->OCFastMode;
elmot 1:d0dfbce63a89 3185 }
elmot 1:d0dfbce63a89 3186 break;
elmot 1:d0dfbce63a89 3187
elmot 1:d0dfbce63a89 3188 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 3189 {
elmot 1:d0dfbce63a89 3190 /* Check the parameters */
elmot 1:d0dfbce63a89 3191 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3192
elmot 1:d0dfbce63a89 3193 /* Configure the Channel 2 in PWM mode */
elmot 1:d0dfbce63a89 3194 TIM_OC2_SetConfig(htim->Instance, sConfig);
elmot 1:d0dfbce63a89 3195
elmot 1:d0dfbce63a89 3196 /* Set the Preload enable bit for channel2 */
elmot 1:d0dfbce63a89 3197 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
elmot 1:d0dfbce63a89 3198
elmot 1:d0dfbce63a89 3199 /* Configure the Output Fast mode */
elmot 1:d0dfbce63a89 3200 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
elmot 1:d0dfbce63a89 3201 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
elmot 1:d0dfbce63a89 3202 }
elmot 1:d0dfbce63a89 3203 break;
elmot 1:d0dfbce63a89 3204
elmot 1:d0dfbce63a89 3205 case TIM_CHANNEL_3:
elmot 1:d0dfbce63a89 3206 {
elmot 1:d0dfbce63a89 3207 /* Check the parameters */
elmot 1:d0dfbce63a89 3208 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3209
elmot 1:d0dfbce63a89 3210 /* Configure the Channel 3 in PWM mode */
elmot 1:d0dfbce63a89 3211 TIM_OC3_SetConfig(htim->Instance, sConfig);
elmot 1:d0dfbce63a89 3212
elmot 1:d0dfbce63a89 3213 /* Set the Preload enable bit for channel3 */
elmot 1:d0dfbce63a89 3214 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
elmot 1:d0dfbce63a89 3215
elmot 1:d0dfbce63a89 3216 /* Configure the Output Fast mode */
elmot 1:d0dfbce63a89 3217 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
elmot 1:d0dfbce63a89 3218 htim->Instance->CCMR2 |= sConfig->OCFastMode;
elmot 1:d0dfbce63a89 3219 }
elmot 1:d0dfbce63a89 3220 break;
elmot 1:d0dfbce63a89 3221
elmot 1:d0dfbce63a89 3222 case TIM_CHANNEL_4:
elmot 1:d0dfbce63a89 3223 {
elmot 1:d0dfbce63a89 3224 /* Check the parameters */
elmot 1:d0dfbce63a89 3225 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3226
elmot 1:d0dfbce63a89 3227 /* Configure the Channel 4 in PWM mode */
elmot 1:d0dfbce63a89 3228 TIM_OC4_SetConfig(htim->Instance, sConfig);
elmot 1:d0dfbce63a89 3229
elmot 1:d0dfbce63a89 3230 /* Set the Preload enable bit for channel4 */
elmot 1:d0dfbce63a89 3231 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
elmot 1:d0dfbce63a89 3232
elmot 1:d0dfbce63a89 3233 /* Configure the Output Fast mode */
elmot 1:d0dfbce63a89 3234 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
elmot 1:d0dfbce63a89 3235 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
elmot 1:d0dfbce63a89 3236 }
elmot 1:d0dfbce63a89 3237 break;
elmot 1:d0dfbce63a89 3238
elmot 1:d0dfbce63a89 3239 case TIM_CHANNEL_5:
elmot 1:d0dfbce63a89 3240 {
elmot 1:d0dfbce63a89 3241 /* Check the parameters */
elmot 1:d0dfbce63a89 3242 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3243
elmot 1:d0dfbce63a89 3244 /* Configure the Channel 5 in PWM mode */
elmot 1:d0dfbce63a89 3245 TIM_OC5_SetConfig(htim->Instance, sConfig);
elmot 1:d0dfbce63a89 3246
elmot 1:d0dfbce63a89 3247 /* Set the Preload enable bit for channel5*/
elmot 1:d0dfbce63a89 3248 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
elmot 1:d0dfbce63a89 3249
elmot 1:d0dfbce63a89 3250 /* Configure the Output Fast mode */
elmot 1:d0dfbce63a89 3251 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
elmot 1:d0dfbce63a89 3252 htim->Instance->CCMR3 |= sConfig->OCFastMode;
elmot 1:d0dfbce63a89 3253 }
elmot 1:d0dfbce63a89 3254 break;
elmot 1:d0dfbce63a89 3255
elmot 1:d0dfbce63a89 3256 case TIM_CHANNEL_6:
elmot 1:d0dfbce63a89 3257 {
elmot 1:d0dfbce63a89 3258 /* Check the parameters */
elmot 1:d0dfbce63a89 3259 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3260
elmot 1:d0dfbce63a89 3261 /* Configure the Channel 5 in PWM mode */
elmot 1:d0dfbce63a89 3262 TIM_OC6_SetConfig(htim->Instance, sConfig);
elmot 1:d0dfbce63a89 3263
elmot 1:d0dfbce63a89 3264 /* Set the Preload enable bit for channel6 */
elmot 1:d0dfbce63a89 3265 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
elmot 1:d0dfbce63a89 3266
elmot 1:d0dfbce63a89 3267 /* Configure the Output Fast mode */
elmot 1:d0dfbce63a89 3268 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
elmot 1:d0dfbce63a89 3269 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
elmot 1:d0dfbce63a89 3270 }
elmot 1:d0dfbce63a89 3271 break;
elmot 1:d0dfbce63a89 3272
elmot 1:d0dfbce63a89 3273 default:
elmot 1:d0dfbce63a89 3274 break;
elmot 1:d0dfbce63a89 3275 }
elmot 1:d0dfbce63a89 3276
elmot 1:d0dfbce63a89 3277 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 3278
elmot 1:d0dfbce63a89 3279 __HAL_UNLOCK(htim);
elmot 1:d0dfbce63a89 3280
elmot 1:d0dfbce63a89 3281 return HAL_OK;
elmot 1:d0dfbce63a89 3282 }
elmot 1:d0dfbce63a89 3283
elmot 1:d0dfbce63a89 3284 /**
elmot 1:d0dfbce63a89 3285 * @brief Initializes the TIM One Pulse Channels according to the specified
elmot 1:d0dfbce63a89 3286 * parameters in the TIM_OnePulse_InitTypeDef.
elmot 1:d0dfbce63a89 3287 * @param htim: TIM One Pulse handle
elmot 1:d0dfbce63a89 3288 * @param sConfig: TIM One Pulse configuration structure
elmot 1:d0dfbce63a89 3289 * @param OutputChannel : TIM Channels to be enabled
elmot 1:d0dfbce63a89 3290 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3291 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 3292 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 3293 * @param InputChannel : TIM Channels to be enabled
elmot 1:d0dfbce63a89 3294 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3295 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 3296 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 3297 * @retval HAL status
elmot 1:d0dfbce63a89 3298 */
elmot 1:d0dfbce63a89 3299 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
elmot 1:d0dfbce63a89 3300 {
elmot 1:d0dfbce63a89 3301 TIM_OC_InitTypeDef temp1;
elmot 1:d0dfbce63a89 3302
elmot 1:d0dfbce63a89 3303 /* Check the parameters */
elmot 1:d0dfbce63a89 3304 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
elmot 1:d0dfbce63a89 3305 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
elmot 1:d0dfbce63a89 3306
elmot 1:d0dfbce63a89 3307 if(OutputChannel != InputChannel)
elmot 1:d0dfbce63a89 3308 {
elmot 1:d0dfbce63a89 3309 /* Process Locked */
elmot 1:d0dfbce63a89 3310 __HAL_LOCK(htim);
elmot 1:d0dfbce63a89 3311
elmot 1:d0dfbce63a89 3312 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 3313
elmot 1:d0dfbce63a89 3314 /* Extract the Ouput compare configuration from sConfig structure */
elmot 1:d0dfbce63a89 3315 temp1.OCMode = sConfig->OCMode;
elmot 1:d0dfbce63a89 3316 temp1.Pulse = sConfig->Pulse;
elmot 1:d0dfbce63a89 3317 temp1.OCPolarity = sConfig->OCPolarity;
elmot 1:d0dfbce63a89 3318 temp1.OCNPolarity = sConfig->OCNPolarity;
elmot 1:d0dfbce63a89 3319 temp1.OCIdleState = sConfig->OCIdleState;
elmot 1:d0dfbce63a89 3320 temp1.OCNIdleState = sConfig->OCNIdleState;
elmot 1:d0dfbce63a89 3321
elmot 1:d0dfbce63a89 3322 switch (OutputChannel)
elmot 1:d0dfbce63a89 3323 {
elmot 1:d0dfbce63a89 3324 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 3325 {
elmot 1:d0dfbce63a89 3326 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3327
elmot 1:d0dfbce63a89 3328 TIM_OC1_SetConfig(htim->Instance, &temp1);
elmot 1:d0dfbce63a89 3329 }
elmot 1:d0dfbce63a89 3330 break;
elmot 1:d0dfbce63a89 3331 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 3332 {
elmot 1:d0dfbce63a89 3333 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3334
elmot 1:d0dfbce63a89 3335 TIM_OC2_SetConfig(htim->Instance, &temp1);
elmot 1:d0dfbce63a89 3336 }
elmot 1:d0dfbce63a89 3337 break;
elmot 1:d0dfbce63a89 3338 default:
elmot 1:d0dfbce63a89 3339 break;
elmot 1:d0dfbce63a89 3340 }
elmot 1:d0dfbce63a89 3341 switch (InputChannel)
elmot 1:d0dfbce63a89 3342 {
elmot 1:d0dfbce63a89 3343 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 3344 {
elmot 1:d0dfbce63a89 3345 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3346
elmot 1:d0dfbce63a89 3347 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
elmot 1:d0dfbce63a89 3348 sConfig->ICSelection, sConfig->ICFilter);
elmot 1:d0dfbce63a89 3349
elmot 1:d0dfbce63a89 3350 /* Reset the IC1PSC Bits */
elmot 1:d0dfbce63a89 3351 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
elmot 1:d0dfbce63a89 3352
elmot 1:d0dfbce63a89 3353 /* Select the Trigger source */
elmot 1:d0dfbce63a89 3354 htim->Instance->SMCR &= ~TIM_SMCR_TS;
elmot 1:d0dfbce63a89 3355 htim->Instance->SMCR |= TIM_TS_TI1FP1;
elmot 1:d0dfbce63a89 3356
elmot 1:d0dfbce63a89 3357 /* Select the Slave Mode */
elmot 1:d0dfbce63a89 3358 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
elmot 1:d0dfbce63a89 3359 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
elmot 1:d0dfbce63a89 3360 }
elmot 1:d0dfbce63a89 3361 break;
elmot 1:d0dfbce63a89 3362 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 3363 {
elmot 1:d0dfbce63a89 3364 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3365
elmot 1:d0dfbce63a89 3366 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
elmot 1:d0dfbce63a89 3367 sConfig->ICSelection, sConfig->ICFilter);
elmot 1:d0dfbce63a89 3368
elmot 1:d0dfbce63a89 3369 /* Reset the IC2PSC Bits */
elmot 1:d0dfbce63a89 3370 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
elmot 1:d0dfbce63a89 3371
elmot 1:d0dfbce63a89 3372 /* Select the Trigger source */
elmot 1:d0dfbce63a89 3373 htim->Instance->SMCR &= ~TIM_SMCR_TS;
elmot 1:d0dfbce63a89 3374 htim->Instance->SMCR |= TIM_TS_TI2FP2;
elmot 1:d0dfbce63a89 3375
elmot 1:d0dfbce63a89 3376 /* Select the Slave Mode */
elmot 1:d0dfbce63a89 3377 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
elmot 1:d0dfbce63a89 3378 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
elmot 1:d0dfbce63a89 3379 }
elmot 1:d0dfbce63a89 3380 break;
elmot 1:d0dfbce63a89 3381
elmot 1:d0dfbce63a89 3382 default:
elmot 1:d0dfbce63a89 3383 break;
elmot 1:d0dfbce63a89 3384 }
elmot 1:d0dfbce63a89 3385
elmot 1:d0dfbce63a89 3386 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 3387
elmot 1:d0dfbce63a89 3388 __HAL_UNLOCK(htim);
elmot 1:d0dfbce63a89 3389
elmot 1:d0dfbce63a89 3390 return HAL_OK;
elmot 1:d0dfbce63a89 3391 }
elmot 1:d0dfbce63a89 3392 else
elmot 1:d0dfbce63a89 3393 {
elmot 1:d0dfbce63a89 3394 return HAL_ERROR;
elmot 1:d0dfbce63a89 3395 }
elmot 1:d0dfbce63a89 3396 }
elmot 1:d0dfbce63a89 3397
elmot 1:d0dfbce63a89 3398 /**
elmot 1:d0dfbce63a89 3399 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
elmot 1:d0dfbce63a89 3400 * @param htim: TIM handle
elmot 1:d0dfbce63a89 3401 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write
elmot 1:d0dfbce63a89 3402 * This parameters can be on of the following values:
elmot 1:d0dfbce63a89 3403 * @arg TIM_DMABASE_CR1
elmot 1:d0dfbce63a89 3404 * @arg TIM_DMABASE_CR2
elmot 1:d0dfbce63a89 3405 * @arg TIM_DMABASE_SMCR
elmot 1:d0dfbce63a89 3406 * @arg TIM_DMABASE_DIER
elmot 1:d0dfbce63a89 3407 * @arg TIM_DMABASE_SR
elmot 1:d0dfbce63a89 3408 * @arg TIM_DMABASE_EGR
elmot 1:d0dfbce63a89 3409 * @arg TIM_DMABASE_CCMR1
elmot 1:d0dfbce63a89 3410 * @arg TIM_DMABASE_CCMR2
elmot 1:d0dfbce63a89 3411 * @arg TIM_DMABASE_CCER
elmot 1:d0dfbce63a89 3412 * @arg TIM_DMABASE_CNT
elmot 1:d0dfbce63a89 3413 * @arg TIM_DMABASE_PSC
elmot 1:d0dfbce63a89 3414 * @arg TIM_DMABASE_ARR
elmot 1:d0dfbce63a89 3415 * @arg TIM_DMABASE_RCR
elmot 1:d0dfbce63a89 3416 * @arg TIM_DMABASE_CCR1
elmot 1:d0dfbce63a89 3417 * @arg TIM_DMABASE_CCR2
elmot 1:d0dfbce63a89 3418 * @arg TIM_DMABASE_CCR3
elmot 1:d0dfbce63a89 3419 * @arg TIM_DMABASE_CCR4
elmot 1:d0dfbce63a89 3420 * @arg TIM_DMABASE_BDTR
elmot 1:d0dfbce63a89 3421 * @arg TIM_DMABASE_DCR
elmot 1:d0dfbce63a89 3422 * @param BurstRequestSrc: TIM DMA Request sources
elmot 1:d0dfbce63a89 3423 * This parameters can be on of the following values:
elmot 1:d0dfbce63a89 3424 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
elmot 1:d0dfbce63a89 3425 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
elmot 1:d0dfbce63a89 3426 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
elmot 1:d0dfbce63a89 3427 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
elmot 1:d0dfbce63a89 3428 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
elmot 1:d0dfbce63a89 3429 * @arg TIM_DMA_COM: TIM Commutation DMA source
elmot 1:d0dfbce63a89 3430 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
elmot 1:d0dfbce63a89 3431 * @param BurstBuffer: The Buffer address.
elmot 1:d0dfbce63a89 3432 * @param BurstLength: DMA Burst length. This parameter can be one value
elmot 1:d0dfbce63a89 3433 * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
elmot 1:d0dfbce63a89 3434 * @retval HAL status
elmot 1:d0dfbce63a89 3435 */
elmot 1:d0dfbce63a89 3436 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
elmot 1:d0dfbce63a89 3437 uint32_t* BurstBuffer, uint32_t BurstLength)
elmot 1:d0dfbce63a89 3438 {
elmot 1:d0dfbce63a89 3439 /* Check the parameters */
elmot 1:d0dfbce63a89 3440 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3441 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
elmot 1:d0dfbce63a89 3442 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
elmot 1:d0dfbce63a89 3443 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
elmot 1:d0dfbce63a89 3444
elmot 1:d0dfbce63a89 3445 if((htim->State == HAL_TIM_STATE_BUSY))
elmot 1:d0dfbce63a89 3446 {
elmot 1:d0dfbce63a89 3447 return HAL_BUSY;
elmot 1:d0dfbce63a89 3448 }
elmot 1:d0dfbce63a89 3449 else if((htim->State == HAL_TIM_STATE_READY))
elmot 1:d0dfbce63a89 3450 {
elmot 1:d0dfbce63a89 3451 if((BurstBuffer == 0 ) && (BurstLength > 0))
elmot 1:d0dfbce63a89 3452 {
elmot 1:d0dfbce63a89 3453 return HAL_ERROR;
elmot 1:d0dfbce63a89 3454 }
elmot 1:d0dfbce63a89 3455 else
elmot 1:d0dfbce63a89 3456 {
elmot 1:d0dfbce63a89 3457 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 3458 }
elmot 1:d0dfbce63a89 3459 }
elmot 1:d0dfbce63a89 3460 switch(BurstRequestSrc)
elmot 1:d0dfbce63a89 3461 {
elmot 1:d0dfbce63a89 3462 case TIM_DMA_UPDATE:
elmot 1:d0dfbce63a89 3463 {
elmot 1:d0dfbce63a89 3464 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 3465 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
elmot 1:d0dfbce63a89 3466
elmot 1:d0dfbce63a89 3467 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 3468 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 3469
elmot 1:d0dfbce63a89 3470 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 3471 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
elmot 1:d0dfbce63a89 3472 }
elmot 1:d0dfbce63a89 3473 break;
elmot 1:d0dfbce63a89 3474 case TIM_DMA_CC1:
elmot 1:d0dfbce63a89 3475 {
elmot 1:d0dfbce63a89 3476 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 3477 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
elmot 1:d0dfbce63a89 3478
elmot 1:d0dfbce63a89 3479 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 3480 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 3481
elmot 1:d0dfbce63a89 3482 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 3483 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
elmot 1:d0dfbce63a89 3484 }
elmot 1:d0dfbce63a89 3485 break;
elmot 1:d0dfbce63a89 3486 case TIM_DMA_CC2:
elmot 1:d0dfbce63a89 3487 {
elmot 1:d0dfbce63a89 3488 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 3489 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
elmot 1:d0dfbce63a89 3490
elmot 1:d0dfbce63a89 3491 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 3492 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 3493
elmot 1:d0dfbce63a89 3494 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 3495 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
elmot 1:d0dfbce63a89 3496 }
elmot 1:d0dfbce63a89 3497 break;
elmot 1:d0dfbce63a89 3498 case TIM_DMA_CC3:
elmot 1:d0dfbce63a89 3499 {
elmot 1:d0dfbce63a89 3500 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 3501 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
elmot 1:d0dfbce63a89 3502
elmot 1:d0dfbce63a89 3503 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 3504 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 3505
elmot 1:d0dfbce63a89 3506 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 3507 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
elmot 1:d0dfbce63a89 3508 }
elmot 1:d0dfbce63a89 3509 break;
elmot 1:d0dfbce63a89 3510 case TIM_DMA_CC4:
elmot 1:d0dfbce63a89 3511 {
elmot 1:d0dfbce63a89 3512 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 3513 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
elmot 1:d0dfbce63a89 3514
elmot 1:d0dfbce63a89 3515 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 3516 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 3517
elmot 1:d0dfbce63a89 3518 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 3519 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
elmot 1:d0dfbce63a89 3520 }
elmot 1:d0dfbce63a89 3521 break;
elmot 1:d0dfbce63a89 3522 case TIM_DMA_COM:
elmot 1:d0dfbce63a89 3523 {
elmot 1:d0dfbce63a89 3524 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 3525 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
elmot 1:d0dfbce63a89 3526
elmot 1:d0dfbce63a89 3527 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 3528 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 3529
elmot 1:d0dfbce63a89 3530 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 3531 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
elmot 1:d0dfbce63a89 3532 }
elmot 1:d0dfbce63a89 3533 break;
elmot 1:d0dfbce63a89 3534 case TIM_DMA_TRIGGER:
elmot 1:d0dfbce63a89 3535 {
elmot 1:d0dfbce63a89 3536 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 3537 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
elmot 1:d0dfbce63a89 3538
elmot 1:d0dfbce63a89 3539 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 3540 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 3541
elmot 1:d0dfbce63a89 3542 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 3543 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
elmot 1:d0dfbce63a89 3544 }
elmot 1:d0dfbce63a89 3545 break;
elmot 1:d0dfbce63a89 3546 default:
elmot 1:d0dfbce63a89 3547 break;
elmot 1:d0dfbce63a89 3548 }
elmot 1:d0dfbce63a89 3549 /* configure the DMA Burst Mode */
elmot 1:d0dfbce63a89 3550 htim->Instance->DCR = BurstBaseAddress | BurstLength;
elmot 1:d0dfbce63a89 3551
elmot 1:d0dfbce63a89 3552 /* Enable the TIM DMA Request */
elmot 1:d0dfbce63a89 3553 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
elmot 1:d0dfbce63a89 3554
elmot 1:d0dfbce63a89 3555 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 3556
elmot 1:d0dfbce63a89 3557 /* Return function status */
elmot 1:d0dfbce63a89 3558 return HAL_OK;
elmot 1:d0dfbce63a89 3559 }
elmot 1:d0dfbce63a89 3560
elmot 1:d0dfbce63a89 3561 /**
elmot 1:d0dfbce63a89 3562 * @brief Stops the TIM DMA Burst mode
elmot 1:d0dfbce63a89 3563 * @param htim: TIM handle
elmot 1:d0dfbce63a89 3564 * @param BurstRequestSrc: TIM DMA Request sources to disable
elmot 1:d0dfbce63a89 3565 * @retval HAL status
elmot 1:d0dfbce63a89 3566 */
elmot 1:d0dfbce63a89 3567 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
elmot 1:d0dfbce63a89 3568 {
elmot 1:d0dfbce63a89 3569 /* Check the parameters */
elmot 1:d0dfbce63a89 3570 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
elmot 1:d0dfbce63a89 3571
elmot 1:d0dfbce63a89 3572 /* Abort the DMA transfer (at least disable the DMA channel) */
elmot 1:d0dfbce63a89 3573 switch(BurstRequestSrc)
elmot 1:d0dfbce63a89 3574 {
elmot 1:d0dfbce63a89 3575 case TIM_DMA_UPDATE:
elmot 1:d0dfbce63a89 3576 {
elmot 1:d0dfbce63a89 3577 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
elmot 1:d0dfbce63a89 3578 }
elmot 1:d0dfbce63a89 3579 break;
elmot 1:d0dfbce63a89 3580 case TIM_DMA_CC1:
elmot 1:d0dfbce63a89 3581 {
elmot 1:d0dfbce63a89 3582 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
elmot 1:d0dfbce63a89 3583 }
elmot 1:d0dfbce63a89 3584 break;
elmot 1:d0dfbce63a89 3585 case TIM_DMA_CC2:
elmot 1:d0dfbce63a89 3586 {
elmot 1:d0dfbce63a89 3587 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
elmot 1:d0dfbce63a89 3588 }
elmot 1:d0dfbce63a89 3589 break;
elmot 1:d0dfbce63a89 3590 case TIM_DMA_CC3:
elmot 1:d0dfbce63a89 3591 {
elmot 1:d0dfbce63a89 3592 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
elmot 1:d0dfbce63a89 3593 }
elmot 1:d0dfbce63a89 3594 break;
elmot 1:d0dfbce63a89 3595 case TIM_DMA_CC4:
elmot 1:d0dfbce63a89 3596 {
elmot 1:d0dfbce63a89 3597 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
elmot 1:d0dfbce63a89 3598 }
elmot 1:d0dfbce63a89 3599 break;
elmot 1:d0dfbce63a89 3600 case TIM_DMA_COM:
elmot 1:d0dfbce63a89 3601 {
elmot 1:d0dfbce63a89 3602 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
elmot 1:d0dfbce63a89 3603 }
elmot 1:d0dfbce63a89 3604 break;
elmot 1:d0dfbce63a89 3605 case TIM_DMA_TRIGGER:
elmot 1:d0dfbce63a89 3606 {
elmot 1:d0dfbce63a89 3607 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
elmot 1:d0dfbce63a89 3608 }
elmot 1:d0dfbce63a89 3609 break;
elmot 1:d0dfbce63a89 3610 default:
elmot 1:d0dfbce63a89 3611 break;
elmot 1:d0dfbce63a89 3612 }
elmot 1:d0dfbce63a89 3613
elmot 1:d0dfbce63a89 3614 /* Disable the TIM Update DMA request */
elmot 1:d0dfbce63a89 3615 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
elmot 1:d0dfbce63a89 3616
elmot 1:d0dfbce63a89 3617 /* Return function status */
elmot 1:d0dfbce63a89 3618 return HAL_OK;
elmot 1:d0dfbce63a89 3619 }
elmot 1:d0dfbce63a89 3620
elmot 1:d0dfbce63a89 3621 /**
elmot 1:d0dfbce63a89 3622 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
elmot 1:d0dfbce63a89 3623 * @param htim: TIM handle
elmot 1:d0dfbce63a89 3624 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read
elmot 1:d0dfbce63a89 3625 * This parameters can be on of the following values:
elmot 1:d0dfbce63a89 3626 * @arg TIM_DMABASE_CR1
elmot 1:d0dfbce63a89 3627 * @arg TIM_DMABASE_CR2
elmot 1:d0dfbce63a89 3628 * @arg TIM_DMABASE_SMCR
elmot 1:d0dfbce63a89 3629 * @arg TIM_DMABASE_DIER
elmot 1:d0dfbce63a89 3630 * @arg TIM_DMABASE_SR
elmot 1:d0dfbce63a89 3631 * @arg TIM_DMABASE_EGR
elmot 1:d0dfbce63a89 3632 * @arg TIM_DMABASE_CCMR1
elmot 1:d0dfbce63a89 3633 * @arg TIM_DMABASE_CCMR2
elmot 1:d0dfbce63a89 3634 * @arg TIM_DMABASE_CCER
elmot 1:d0dfbce63a89 3635 * @arg TIM_DMABASE_CNT
elmot 1:d0dfbce63a89 3636 * @arg TIM_DMABASE_PSC
elmot 1:d0dfbce63a89 3637 * @arg TIM_DMABASE_ARR
elmot 1:d0dfbce63a89 3638 * @arg TIM_DMABASE_RCR
elmot 1:d0dfbce63a89 3639 * @arg TIM_DMABASE_CCR1
elmot 1:d0dfbce63a89 3640 * @arg TIM_DMABASE_CCR2
elmot 1:d0dfbce63a89 3641 * @arg TIM_DMABASE_CCR3
elmot 1:d0dfbce63a89 3642 * @arg TIM_DMABASE_CCR4
elmot 1:d0dfbce63a89 3643 * @arg TIM_DMABASE_BDTR
elmot 1:d0dfbce63a89 3644 * @arg TIM_DMABASE_DCR
elmot 1:d0dfbce63a89 3645 * @param BurstRequestSrc: TIM DMA Request sources
elmot 1:d0dfbce63a89 3646 * This parameters can be on of the following values:
elmot 1:d0dfbce63a89 3647 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
elmot 1:d0dfbce63a89 3648 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
elmot 1:d0dfbce63a89 3649 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
elmot 1:d0dfbce63a89 3650 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
elmot 1:d0dfbce63a89 3651 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
elmot 1:d0dfbce63a89 3652 * @arg TIM_DMA_COM: TIM Commutation DMA source
elmot 1:d0dfbce63a89 3653 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
elmot 1:d0dfbce63a89 3654 * @param BurstBuffer: The Buffer address.
elmot 1:d0dfbce63a89 3655 * @param BurstLength: DMA Burst length. This parameter can be one value
elmot 1:d0dfbce63a89 3656 * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
elmot 1:d0dfbce63a89 3657 * @retval HAL status
elmot 1:d0dfbce63a89 3658 */
elmot 1:d0dfbce63a89 3659 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
elmot 1:d0dfbce63a89 3660 uint32_t *BurstBuffer, uint32_t BurstLength)
elmot 1:d0dfbce63a89 3661 {
elmot 1:d0dfbce63a89 3662 /* Check the parameters */
elmot 1:d0dfbce63a89 3663 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3664 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
elmot 1:d0dfbce63a89 3665 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
elmot 1:d0dfbce63a89 3666 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
elmot 1:d0dfbce63a89 3667
elmot 1:d0dfbce63a89 3668 if((htim->State == HAL_TIM_STATE_BUSY))
elmot 1:d0dfbce63a89 3669 {
elmot 1:d0dfbce63a89 3670 return HAL_BUSY;
elmot 1:d0dfbce63a89 3671 }
elmot 1:d0dfbce63a89 3672 else if((htim->State == HAL_TIM_STATE_READY))
elmot 1:d0dfbce63a89 3673 {
elmot 1:d0dfbce63a89 3674 if((BurstBuffer == 0 ) && (BurstLength > 0))
elmot 1:d0dfbce63a89 3675 {
elmot 1:d0dfbce63a89 3676 return HAL_ERROR;
elmot 1:d0dfbce63a89 3677 }
elmot 1:d0dfbce63a89 3678 else
elmot 1:d0dfbce63a89 3679 {
elmot 1:d0dfbce63a89 3680 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 3681 }
elmot 1:d0dfbce63a89 3682 }
elmot 1:d0dfbce63a89 3683 switch(BurstRequestSrc)
elmot 1:d0dfbce63a89 3684 {
elmot 1:d0dfbce63a89 3685 case TIM_DMA_UPDATE:
elmot 1:d0dfbce63a89 3686 {
elmot 1:d0dfbce63a89 3687 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 3688 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
elmot 1:d0dfbce63a89 3689
elmot 1:d0dfbce63a89 3690 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 3691 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 3692
elmot 1:d0dfbce63a89 3693 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 3694 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
elmot 1:d0dfbce63a89 3695 }
elmot 1:d0dfbce63a89 3696 break;
elmot 1:d0dfbce63a89 3697 case TIM_DMA_CC1:
elmot 1:d0dfbce63a89 3698 {
elmot 1:d0dfbce63a89 3699 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 3700 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
elmot 1:d0dfbce63a89 3701
elmot 1:d0dfbce63a89 3702 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 3703 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 3704
elmot 1:d0dfbce63a89 3705 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 3706 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
elmot 1:d0dfbce63a89 3707 }
elmot 1:d0dfbce63a89 3708 break;
elmot 1:d0dfbce63a89 3709 case TIM_DMA_CC2:
elmot 1:d0dfbce63a89 3710 {
elmot 1:d0dfbce63a89 3711 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 3712 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
elmot 1:d0dfbce63a89 3713
elmot 1:d0dfbce63a89 3714 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 3715 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 3716
elmot 1:d0dfbce63a89 3717 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 3718 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
elmot 1:d0dfbce63a89 3719 }
elmot 1:d0dfbce63a89 3720 break;
elmot 1:d0dfbce63a89 3721 case TIM_DMA_CC3:
elmot 1:d0dfbce63a89 3722 {
elmot 1:d0dfbce63a89 3723 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 3724 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
elmot 1:d0dfbce63a89 3725
elmot 1:d0dfbce63a89 3726 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 3727 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 3728
elmot 1:d0dfbce63a89 3729 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 3730 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
elmot 1:d0dfbce63a89 3731 }
elmot 1:d0dfbce63a89 3732 break;
elmot 1:d0dfbce63a89 3733 case TIM_DMA_CC4:
elmot 1:d0dfbce63a89 3734 {
elmot 1:d0dfbce63a89 3735 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 3736 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
elmot 1:d0dfbce63a89 3737
elmot 1:d0dfbce63a89 3738 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 3739 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 3740
elmot 1:d0dfbce63a89 3741 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 3742 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
elmot 1:d0dfbce63a89 3743 }
elmot 1:d0dfbce63a89 3744 break;
elmot 1:d0dfbce63a89 3745 case TIM_DMA_COM:
elmot 1:d0dfbce63a89 3746 {
elmot 1:d0dfbce63a89 3747 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 3748 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
elmot 1:d0dfbce63a89 3749
elmot 1:d0dfbce63a89 3750 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 3751 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 3752
elmot 1:d0dfbce63a89 3753 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 3754 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
elmot 1:d0dfbce63a89 3755 }
elmot 1:d0dfbce63a89 3756 break;
elmot 1:d0dfbce63a89 3757 case TIM_DMA_TRIGGER:
elmot 1:d0dfbce63a89 3758 {
elmot 1:d0dfbce63a89 3759 /* Set the DMA Period elapsed callback */
elmot 1:d0dfbce63a89 3760 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
elmot 1:d0dfbce63a89 3761
elmot 1:d0dfbce63a89 3762 /* Set the DMA error callback */
elmot 1:d0dfbce63a89 3763 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
elmot 1:d0dfbce63a89 3764
elmot 1:d0dfbce63a89 3765 /* Enable the DMA channel */
elmot 1:d0dfbce63a89 3766 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
elmot 1:d0dfbce63a89 3767 }
elmot 1:d0dfbce63a89 3768 break;
elmot 1:d0dfbce63a89 3769 default:
elmot 1:d0dfbce63a89 3770 break;
elmot 1:d0dfbce63a89 3771 }
elmot 1:d0dfbce63a89 3772
elmot 1:d0dfbce63a89 3773 /* configure the DMA Burst Mode */
elmot 1:d0dfbce63a89 3774 htim->Instance->DCR = BurstBaseAddress | BurstLength;
elmot 1:d0dfbce63a89 3775
elmot 1:d0dfbce63a89 3776 /* Enable the TIM DMA Request */
elmot 1:d0dfbce63a89 3777 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
elmot 1:d0dfbce63a89 3778
elmot 1:d0dfbce63a89 3779 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 3780
elmot 1:d0dfbce63a89 3781 /* Return function status */
elmot 1:d0dfbce63a89 3782 return HAL_OK;
elmot 1:d0dfbce63a89 3783 }
elmot 1:d0dfbce63a89 3784
elmot 1:d0dfbce63a89 3785 /**
elmot 1:d0dfbce63a89 3786 * @brief Stop the DMA burst reading
elmot 1:d0dfbce63a89 3787 * @param htim: TIM handle
elmot 1:d0dfbce63a89 3788 * @param BurstRequestSrc: TIM DMA Request sources to disable.
elmot 1:d0dfbce63a89 3789 * @retval HAL status
elmot 1:d0dfbce63a89 3790 */
elmot 1:d0dfbce63a89 3791 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
elmot 1:d0dfbce63a89 3792 {
elmot 1:d0dfbce63a89 3793 /* Check the parameters */
elmot 1:d0dfbce63a89 3794 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
elmot 1:d0dfbce63a89 3795
elmot 1:d0dfbce63a89 3796 /* Abort the DMA transfer (at least disable the DMA channel) */
elmot 1:d0dfbce63a89 3797 switch(BurstRequestSrc)
elmot 1:d0dfbce63a89 3798 {
elmot 1:d0dfbce63a89 3799 case TIM_DMA_UPDATE:
elmot 1:d0dfbce63a89 3800 {
elmot 1:d0dfbce63a89 3801 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
elmot 1:d0dfbce63a89 3802 }
elmot 1:d0dfbce63a89 3803 break;
elmot 1:d0dfbce63a89 3804 case TIM_DMA_CC1:
elmot 1:d0dfbce63a89 3805 {
elmot 1:d0dfbce63a89 3806 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
elmot 1:d0dfbce63a89 3807 }
elmot 1:d0dfbce63a89 3808 break;
elmot 1:d0dfbce63a89 3809 case TIM_DMA_CC2:
elmot 1:d0dfbce63a89 3810 {
elmot 1:d0dfbce63a89 3811 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
elmot 1:d0dfbce63a89 3812 }
elmot 1:d0dfbce63a89 3813 break;
elmot 1:d0dfbce63a89 3814 case TIM_DMA_CC3:
elmot 1:d0dfbce63a89 3815 {
elmot 1:d0dfbce63a89 3816 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
elmot 1:d0dfbce63a89 3817 }
elmot 1:d0dfbce63a89 3818 break;
elmot 1:d0dfbce63a89 3819 case TIM_DMA_CC4:
elmot 1:d0dfbce63a89 3820 {
elmot 1:d0dfbce63a89 3821 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
elmot 1:d0dfbce63a89 3822 }
elmot 1:d0dfbce63a89 3823 break;
elmot 1:d0dfbce63a89 3824 case TIM_DMA_COM:
elmot 1:d0dfbce63a89 3825 {
elmot 1:d0dfbce63a89 3826 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
elmot 1:d0dfbce63a89 3827 }
elmot 1:d0dfbce63a89 3828 break;
elmot 1:d0dfbce63a89 3829 case TIM_DMA_TRIGGER:
elmot 1:d0dfbce63a89 3830 {
elmot 1:d0dfbce63a89 3831 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
elmot 1:d0dfbce63a89 3832 }
elmot 1:d0dfbce63a89 3833 break;
elmot 1:d0dfbce63a89 3834 default:
elmot 1:d0dfbce63a89 3835 break;
elmot 1:d0dfbce63a89 3836 }
elmot 1:d0dfbce63a89 3837
elmot 1:d0dfbce63a89 3838 /* Disable the TIM Update DMA request */
elmot 1:d0dfbce63a89 3839 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
elmot 1:d0dfbce63a89 3840
elmot 1:d0dfbce63a89 3841 /* Return function status */
elmot 1:d0dfbce63a89 3842 return HAL_OK;
elmot 1:d0dfbce63a89 3843 }
elmot 1:d0dfbce63a89 3844
elmot 1:d0dfbce63a89 3845 /**
elmot 1:d0dfbce63a89 3846 * @brief Generate a software event
elmot 1:d0dfbce63a89 3847 * @param htim: TIM handle
elmot 1:d0dfbce63a89 3848 * @param EventSource: specifies the event source.
elmot 1:d0dfbce63a89 3849 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3850 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
elmot 1:d0dfbce63a89 3851 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
elmot 1:d0dfbce63a89 3852 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
elmot 1:d0dfbce63a89 3853 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
elmot 1:d0dfbce63a89 3854 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
elmot 1:d0dfbce63a89 3855 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
elmot 1:d0dfbce63a89 3856 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
elmot 1:d0dfbce63a89 3857 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
elmot 1:d0dfbce63a89 3858 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
elmot 1:d0dfbce63a89 3859 * @retval None
elmot 1:d0dfbce63a89 3860 */
elmot 1:d0dfbce63a89 3861
elmot 1:d0dfbce63a89 3862 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
elmot 1:d0dfbce63a89 3863 {
elmot 1:d0dfbce63a89 3864 /* Check the parameters */
elmot 1:d0dfbce63a89 3865 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3866 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
elmot 1:d0dfbce63a89 3867
elmot 1:d0dfbce63a89 3868 /* Process Locked */
elmot 1:d0dfbce63a89 3869 __HAL_LOCK(htim);
elmot 1:d0dfbce63a89 3870
elmot 1:d0dfbce63a89 3871 /* Change the TIM state */
elmot 1:d0dfbce63a89 3872 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 3873
elmot 1:d0dfbce63a89 3874 /* Set the event sources */
elmot 1:d0dfbce63a89 3875 htim->Instance->EGR = EventSource;
elmot 1:d0dfbce63a89 3876
elmot 1:d0dfbce63a89 3877 /* Change the TIM state */
elmot 1:d0dfbce63a89 3878 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 3879
elmot 1:d0dfbce63a89 3880 __HAL_UNLOCK(htim);
elmot 1:d0dfbce63a89 3881
elmot 1:d0dfbce63a89 3882 /* Return function status */
elmot 1:d0dfbce63a89 3883 return HAL_OK;
elmot 1:d0dfbce63a89 3884 }
elmot 1:d0dfbce63a89 3885
elmot 1:d0dfbce63a89 3886 /**
elmot 1:d0dfbce63a89 3887 * @brief Configures the OCRef clear feature
elmot 1:d0dfbce63a89 3888 * @param htim: TIM handle
elmot 1:d0dfbce63a89 3889 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
elmot 1:d0dfbce63a89 3890 * contains the OCREF clear feature and parameters for the TIM peripheral.
elmot 1:d0dfbce63a89 3891 * @param Channel: specifies the TIM Channel
elmot 1:d0dfbce63a89 3892 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 3893 * @arg TIM_Channel_1: TIM Channel 1
elmot 1:d0dfbce63a89 3894 * @arg TIM_Channel_2: TIM Channel 2
elmot 1:d0dfbce63a89 3895 * @arg TIM_Channel_3: TIM Channel 3
elmot 1:d0dfbce63a89 3896 * @arg TIM_Channel_4: TIM Channel 4
elmot 1:d0dfbce63a89 3897 * @arg TIM_Channel_5: TIM Channel 5
elmot 1:d0dfbce63a89 3898 * @arg TIM_Channel_6: TIM Channel 6
elmot 1:d0dfbce63a89 3899 * @retval None
elmot 1:d0dfbce63a89 3900 */
elmot 1:d0dfbce63a89 3901 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
elmot 1:d0dfbce63a89 3902 TIM_ClearInputConfigTypeDef *sClearInputConfig,
elmot 1:d0dfbce63a89 3903 uint32_t Channel)
elmot 1:d0dfbce63a89 3904 {
elmot 1:d0dfbce63a89 3905 uint32_t tmpsmcr = 0;
elmot 1:d0dfbce63a89 3906
elmot 1:d0dfbce63a89 3907 /* Check the parameters */
elmot 1:d0dfbce63a89 3908 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 3909 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
elmot 1:d0dfbce63a89 3910
elmot 1:d0dfbce63a89 3911 /* Process Locked */
elmot 1:d0dfbce63a89 3912 __HAL_LOCK(htim);
elmot 1:d0dfbce63a89 3913
elmot 1:d0dfbce63a89 3914 switch (sClearInputConfig->ClearInputSource)
elmot 1:d0dfbce63a89 3915 {
elmot 1:d0dfbce63a89 3916 case TIM_CLEARINPUTSOURCE_NONE:
elmot 1:d0dfbce63a89 3917 {
elmot 1:d0dfbce63a89 3918 /* Get the TIMx SMCR register value */
elmot 1:d0dfbce63a89 3919 tmpsmcr = htim->Instance->SMCR;
elmot 1:d0dfbce63a89 3920
elmot 1:d0dfbce63a89 3921 /* Clear the OCREF clear selection bit */
elmot 1:d0dfbce63a89 3922 tmpsmcr &= ~TIM_SMCR_OCCS;
elmot 1:d0dfbce63a89 3923
elmot 1:d0dfbce63a89 3924 /* Clear the ETR Bits */
elmot 1:d0dfbce63a89 3925 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
elmot 1:d0dfbce63a89 3926
elmot 1:d0dfbce63a89 3927 /* Set TIMx_SMCR */
elmot 1:d0dfbce63a89 3928 htim->Instance->SMCR = tmpsmcr;
elmot 1:d0dfbce63a89 3929 }
elmot 1:d0dfbce63a89 3930 break;
elmot 1:d0dfbce63a89 3931
elmot 1:d0dfbce63a89 3932 case TIM_CLEARINPUTSOURCE_OCREFCLR:
elmot 1:d0dfbce63a89 3933 {
elmot 1:d0dfbce63a89 3934 /* Clear the OCREF clear selection bit */
elmot 1:d0dfbce63a89 3935 htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
elmot 1:d0dfbce63a89 3936 }
elmot 1:d0dfbce63a89 3937 break;
elmot 1:d0dfbce63a89 3938
elmot 1:d0dfbce63a89 3939 case TIM_CLEARINPUTSOURCE_ETR:
elmot 1:d0dfbce63a89 3940 {
elmot 1:d0dfbce63a89 3941 /* Check the parameters */
elmot 1:d0dfbce63a89 3942 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
elmot 1:d0dfbce63a89 3943 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
elmot 1:d0dfbce63a89 3944 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
elmot 1:d0dfbce63a89 3945
elmot 1:d0dfbce63a89 3946 TIM_ETR_SetConfig(htim->Instance,
elmot 1:d0dfbce63a89 3947 sClearInputConfig->ClearInputPrescaler,
elmot 1:d0dfbce63a89 3948 sClearInputConfig->ClearInputPolarity,
elmot 1:d0dfbce63a89 3949 sClearInputConfig->ClearInputFilter);
elmot 1:d0dfbce63a89 3950
elmot 1:d0dfbce63a89 3951 /* Set the OCREF clear selection bit */
elmot 1:d0dfbce63a89 3952 htim->Instance->SMCR |= TIM_SMCR_OCCS;
elmot 1:d0dfbce63a89 3953 }
elmot 1:d0dfbce63a89 3954 break;
elmot 1:d0dfbce63a89 3955
elmot 1:d0dfbce63a89 3956 default:
elmot 1:d0dfbce63a89 3957 break;
elmot 1:d0dfbce63a89 3958 }
elmot 1:d0dfbce63a89 3959
elmot 1:d0dfbce63a89 3960 switch (Channel)
elmot 1:d0dfbce63a89 3961 {
elmot 1:d0dfbce63a89 3962 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 3963 {
elmot 1:d0dfbce63a89 3964 if(sClearInputConfig->ClearInputState != RESET)
elmot 1:d0dfbce63a89 3965 {
elmot 1:d0dfbce63a89 3966 /* Enable the OCREF clear feature for Channel 1 */
elmot 1:d0dfbce63a89 3967 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
elmot 1:d0dfbce63a89 3968 }
elmot 1:d0dfbce63a89 3969 else
elmot 1:d0dfbce63a89 3970 {
elmot 1:d0dfbce63a89 3971 /* Disable the OCREF clear feature for Channel 1 */
elmot 1:d0dfbce63a89 3972 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
elmot 1:d0dfbce63a89 3973 }
elmot 1:d0dfbce63a89 3974 }
elmot 1:d0dfbce63a89 3975 break;
elmot 1:d0dfbce63a89 3976 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 3977 {
elmot 1:d0dfbce63a89 3978 if(sClearInputConfig->ClearInputState != RESET)
elmot 1:d0dfbce63a89 3979 {
elmot 1:d0dfbce63a89 3980 /* Enable the OCREF clear feature for Channel 2 */
elmot 1:d0dfbce63a89 3981 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
elmot 1:d0dfbce63a89 3982 }
elmot 1:d0dfbce63a89 3983 else
elmot 1:d0dfbce63a89 3984 {
elmot 1:d0dfbce63a89 3985 /* Disable the OCREF clear feature for Channel 2 */
elmot 1:d0dfbce63a89 3986 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
elmot 1:d0dfbce63a89 3987 }
elmot 1:d0dfbce63a89 3988 }
elmot 1:d0dfbce63a89 3989 break;
elmot 1:d0dfbce63a89 3990 case TIM_CHANNEL_3:
elmot 1:d0dfbce63a89 3991 {
elmot 1:d0dfbce63a89 3992 if(sClearInputConfig->ClearInputState != RESET)
elmot 1:d0dfbce63a89 3993 {
elmot 1:d0dfbce63a89 3994 /* Enable the OCREF clear feature for Channel 3 */
elmot 1:d0dfbce63a89 3995 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
elmot 1:d0dfbce63a89 3996 }
elmot 1:d0dfbce63a89 3997 else
elmot 1:d0dfbce63a89 3998 {
elmot 1:d0dfbce63a89 3999 /* Disable the OCREF clear feature for Channel 3 */
elmot 1:d0dfbce63a89 4000 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
elmot 1:d0dfbce63a89 4001 }
elmot 1:d0dfbce63a89 4002 }
elmot 1:d0dfbce63a89 4003 break;
elmot 1:d0dfbce63a89 4004 case TIM_CHANNEL_4:
elmot 1:d0dfbce63a89 4005 {
elmot 1:d0dfbce63a89 4006 if(sClearInputConfig->ClearInputState != RESET)
elmot 1:d0dfbce63a89 4007 {
elmot 1:d0dfbce63a89 4008 /* Enable the OCREF clear feature for Channel 4 */
elmot 1:d0dfbce63a89 4009 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
elmot 1:d0dfbce63a89 4010 }
elmot 1:d0dfbce63a89 4011 else
elmot 1:d0dfbce63a89 4012 {
elmot 1:d0dfbce63a89 4013 /* Disable the OCREF clear feature for Channel 4 */
elmot 1:d0dfbce63a89 4014 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
elmot 1:d0dfbce63a89 4015 }
elmot 1:d0dfbce63a89 4016 }
elmot 1:d0dfbce63a89 4017 break;
elmot 1:d0dfbce63a89 4018 case TIM_CHANNEL_5:
elmot 1:d0dfbce63a89 4019 {
elmot 1:d0dfbce63a89 4020 if(sClearInputConfig->ClearInputState != RESET)
elmot 1:d0dfbce63a89 4021 {
elmot 1:d0dfbce63a89 4022 /* Enable the OCREF clear feature for Channel 1 */
elmot 1:d0dfbce63a89 4023 htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
elmot 1:d0dfbce63a89 4024 }
elmot 1:d0dfbce63a89 4025 else
elmot 1:d0dfbce63a89 4026 {
elmot 1:d0dfbce63a89 4027 /* Disable the OCREF clear feature for Channel 1 */
elmot 1:d0dfbce63a89 4028 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
elmot 1:d0dfbce63a89 4029 }
elmot 1:d0dfbce63a89 4030 }
elmot 1:d0dfbce63a89 4031 break;
elmot 1:d0dfbce63a89 4032 case TIM_CHANNEL_6:
elmot 1:d0dfbce63a89 4033 {
elmot 1:d0dfbce63a89 4034 if(sClearInputConfig->ClearInputState != RESET)
elmot 1:d0dfbce63a89 4035 {
elmot 1:d0dfbce63a89 4036 /* Enable the OCREF clear feature for Channel 1 */
elmot 1:d0dfbce63a89 4037 htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
elmot 1:d0dfbce63a89 4038 }
elmot 1:d0dfbce63a89 4039 else
elmot 1:d0dfbce63a89 4040 {
elmot 1:d0dfbce63a89 4041 /* Disable the OCREF clear feature for Channel 1 */
elmot 1:d0dfbce63a89 4042 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
elmot 1:d0dfbce63a89 4043 }
elmot 1:d0dfbce63a89 4044 }
elmot 1:d0dfbce63a89 4045 break;
elmot 1:d0dfbce63a89 4046 default:
elmot 1:d0dfbce63a89 4047 break;
elmot 1:d0dfbce63a89 4048 }
elmot 1:d0dfbce63a89 4049
elmot 1:d0dfbce63a89 4050 __HAL_UNLOCK(htim);
elmot 1:d0dfbce63a89 4051
elmot 1:d0dfbce63a89 4052 return HAL_OK;
elmot 1:d0dfbce63a89 4053 }
elmot 1:d0dfbce63a89 4054
elmot 1:d0dfbce63a89 4055 /**
elmot 1:d0dfbce63a89 4056 * @brief Configures the clock source to be used
elmot 1:d0dfbce63a89 4057 * @param htim: TIM handle
elmot 1:d0dfbce63a89 4058 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
elmot 1:d0dfbce63a89 4059 * contains the clock source information for the TIM peripheral.
elmot 1:d0dfbce63a89 4060 * @retval HAL status
elmot 1:d0dfbce63a89 4061 */
elmot 1:d0dfbce63a89 4062 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
elmot 1:d0dfbce63a89 4063 {
elmot 1:d0dfbce63a89 4064 uint32_t tmpsmcr = 0;
elmot 1:d0dfbce63a89 4065
elmot 1:d0dfbce63a89 4066 /* Process Locked */
elmot 1:d0dfbce63a89 4067 __HAL_LOCK(htim);
elmot 1:d0dfbce63a89 4068
elmot 1:d0dfbce63a89 4069 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 4070
elmot 1:d0dfbce63a89 4071 /* Check the parameters */
elmot 1:d0dfbce63a89 4072 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
elmot 1:d0dfbce63a89 4073
elmot 1:d0dfbce63a89 4074 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
elmot 1:d0dfbce63a89 4075 tmpsmcr = htim->Instance->SMCR;
elmot 1:d0dfbce63a89 4076 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
elmot 1:d0dfbce63a89 4077 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
elmot 1:d0dfbce63a89 4078 htim->Instance->SMCR = tmpsmcr;
elmot 1:d0dfbce63a89 4079
elmot 1:d0dfbce63a89 4080 switch (sClockSourceConfig->ClockSource)
elmot 1:d0dfbce63a89 4081 {
elmot 1:d0dfbce63a89 4082 case TIM_CLOCKSOURCE_INTERNAL:
elmot 1:d0dfbce63a89 4083 {
elmot 1:d0dfbce63a89 4084 assert_param(IS_TIM_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4085 /* Disable slave mode to clock the prescaler directly with the internal clock */
elmot 1:d0dfbce63a89 4086 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
elmot 1:d0dfbce63a89 4087 }
elmot 1:d0dfbce63a89 4088 break;
elmot 1:d0dfbce63a89 4089
elmot 1:d0dfbce63a89 4090 case TIM_CLOCKSOURCE_ETRMODE1:
elmot 1:d0dfbce63a89 4091 {
elmot 1:d0dfbce63a89 4092 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
elmot 1:d0dfbce63a89 4093 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4094
elmot 1:d0dfbce63a89 4095 /* Check ETR input conditioning related parameters */
elmot 1:d0dfbce63a89 4096 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
elmot 1:d0dfbce63a89 4097 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
elmot 1:d0dfbce63a89 4098 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
elmot 1:d0dfbce63a89 4099
elmot 1:d0dfbce63a89 4100 /* Configure the ETR Clock source */
elmot 1:d0dfbce63a89 4101 TIM_ETR_SetConfig(htim->Instance,
elmot 1:d0dfbce63a89 4102 sClockSourceConfig->ClockPrescaler,
elmot 1:d0dfbce63a89 4103 sClockSourceConfig->ClockPolarity,
elmot 1:d0dfbce63a89 4104 sClockSourceConfig->ClockFilter);
elmot 1:d0dfbce63a89 4105 /* Get the TIMx SMCR register value */
elmot 1:d0dfbce63a89 4106 tmpsmcr = htim->Instance->SMCR;
elmot 1:d0dfbce63a89 4107 /* Reset the SMS and TS Bits */
elmot 1:d0dfbce63a89 4108 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
elmot 1:d0dfbce63a89 4109 /* Select the External clock mode1 and the ETRF trigger */
elmot 1:d0dfbce63a89 4110 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
elmot 1:d0dfbce63a89 4111 /* Write to TIMx SMCR */
elmot 1:d0dfbce63a89 4112 htim->Instance->SMCR = tmpsmcr;
elmot 1:d0dfbce63a89 4113 }
elmot 1:d0dfbce63a89 4114 break;
elmot 1:d0dfbce63a89 4115
elmot 1:d0dfbce63a89 4116 case TIM_CLOCKSOURCE_ETRMODE2:
elmot 1:d0dfbce63a89 4117 {
elmot 1:d0dfbce63a89 4118 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
elmot 1:d0dfbce63a89 4119 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4120
elmot 1:d0dfbce63a89 4121 /* Check ETR input conditioning related parameters */
elmot 1:d0dfbce63a89 4122 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
elmot 1:d0dfbce63a89 4123 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
elmot 1:d0dfbce63a89 4124 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
elmot 1:d0dfbce63a89 4125
elmot 1:d0dfbce63a89 4126 /* Configure the ETR Clock source */
elmot 1:d0dfbce63a89 4127 TIM_ETR_SetConfig(htim->Instance,
elmot 1:d0dfbce63a89 4128 sClockSourceConfig->ClockPrescaler,
elmot 1:d0dfbce63a89 4129 sClockSourceConfig->ClockPolarity,
elmot 1:d0dfbce63a89 4130 sClockSourceConfig->ClockFilter);
elmot 1:d0dfbce63a89 4131 /* Enable the External clock mode2 */
elmot 1:d0dfbce63a89 4132 htim->Instance->SMCR |= TIM_SMCR_ECE;
elmot 1:d0dfbce63a89 4133 }
elmot 1:d0dfbce63a89 4134 break;
elmot 1:d0dfbce63a89 4135
elmot 1:d0dfbce63a89 4136 case TIM_CLOCKSOURCE_TI1:
elmot 1:d0dfbce63a89 4137 {
elmot 1:d0dfbce63a89 4138 /* Check whether or not the timer instance supports external clock mode 1 */
elmot 1:d0dfbce63a89 4139 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4140
elmot 1:d0dfbce63a89 4141 /* Check TI1 input conditioning related parameters */
elmot 1:d0dfbce63a89 4142 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
elmot 1:d0dfbce63a89 4143 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
elmot 1:d0dfbce63a89 4144
elmot 1:d0dfbce63a89 4145 TIM_TI1_ConfigInputStage(htim->Instance,
elmot 1:d0dfbce63a89 4146 sClockSourceConfig->ClockPolarity,
elmot 1:d0dfbce63a89 4147 sClockSourceConfig->ClockFilter);
elmot 1:d0dfbce63a89 4148 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
elmot 1:d0dfbce63a89 4149 }
elmot 1:d0dfbce63a89 4150 break;
elmot 1:d0dfbce63a89 4151
elmot 1:d0dfbce63a89 4152 case TIM_CLOCKSOURCE_TI2:
elmot 1:d0dfbce63a89 4153 {
elmot 1:d0dfbce63a89 4154 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
elmot 1:d0dfbce63a89 4155 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4156
elmot 1:d0dfbce63a89 4157 /* Check TI2 input conditioning related parameters */
elmot 1:d0dfbce63a89 4158 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
elmot 1:d0dfbce63a89 4159 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
elmot 1:d0dfbce63a89 4160
elmot 1:d0dfbce63a89 4161 TIM_TI2_ConfigInputStage(htim->Instance,
elmot 1:d0dfbce63a89 4162 sClockSourceConfig->ClockPolarity,
elmot 1:d0dfbce63a89 4163 sClockSourceConfig->ClockFilter);
elmot 1:d0dfbce63a89 4164 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
elmot 1:d0dfbce63a89 4165 }
elmot 1:d0dfbce63a89 4166 break;
elmot 1:d0dfbce63a89 4167
elmot 1:d0dfbce63a89 4168 case TIM_CLOCKSOURCE_TI1ED:
elmot 1:d0dfbce63a89 4169 {
elmot 1:d0dfbce63a89 4170 /* Check whether or not the timer instance supports external clock mode 1 */
elmot 1:d0dfbce63a89 4171 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4172
elmot 1:d0dfbce63a89 4173 /* Check TI1 input conditioning related parameters */
elmot 1:d0dfbce63a89 4174 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
elmot 1:d0dfbce63a89 4175 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
elmot 1:d0dfbce63a89 4176
elmot 1:d0dfbce63a89 4177 TIM_TI1_ConfigInputStage(htim->Instance,
elmot 1:d0dfbce63a89 4178 sClockSourceConfig->ClockPolarity,
elmot 1:d0dfbce63a89 4179 sClockSourceConfig->ClockFilter);
elmot 1:d0dfbce63a89 4180 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
elmot 1:d0dfbce63a89 4181 }
elmot 1:d0dfbce63a89 4182 break;
elmot 1:d0dfbce63a89 4183
elmot 1:d0dfbce63a89 4184 case TIM_CLOCKSOURCE_ITR0:
elmot 1:d0dfbce63a89 4185 {
elmot 1:d0dfbce63a89 4186 /* Check whether or not the timer instance supports internal trigger input */
elmot 1:d0dfbce63a89 4187 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4188
elmot 1:d0dfbce63a89 4189 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
elmot 1:d0dfbce63a89 4190 }
elmot 1:d0dfbce63a89 4191 break;
elmot 1:d0dfbce63a89 4192
elmot 1:d0dfbce63a89 4193 case TIM_CLOCKSOURCE_ITR1:
elmot 1:d0dfbce63a89 4194 {
elmot 1:d0dfbce63a89 4195 /* Check whether or not the timer instance supports internal trigger input */
elmot 1:d0dfbce63a89 4196 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4197
elmot 1:d0dfbce63a89 4198 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
elmot 1:d0dfbce63a89 4199 }
elmot 1:d0dfbce63a89 4200 break;
elmot 1:d0dfbce63a89 4201
elmot 1:d0dfbce63a89 4202 case TIM_CLOCKSOURCE_ITR2:
elmot 1:d0dfbce63a89 4203 {
elmot 1:d0dfbce63a89 4204 /* Check whether or not the timer instance supports internal trigger input */
elmot 1:d0dfbce63a89 4205 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4206
elmot 1:d0dfbce63a89 4207 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
elmot 1:d0dfbce63a89 4208 }
elmot 1:d0dfbce63a89 4209 break;
elmot 1:d0dfbce63a89 4210
elmot 1:d0dfbce63a89 4211 case TIM_CLOCKSOURCE_ITR3:
elmot 1:d0dfbce63a89 4212 {
elmot 1:d0dfbce63a89 4213 /* Check whether or not the timer instance supports internal trigger input */
elmot 1:d0dfbce63a89 4214 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4215
elmot 1:d0dfbce63a89 4216 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
elmot 1:d0dfbce63a89 4217 }
elmot 1:d0dfbce63a89 4218 break;
elmot 1:d0dfbce63a89 4219
elmot 1:d0dfbce63a89 4220 default:
elmot 1:d0dfbce63a89 4221 break;
elmot 1:d0dfbce63a89 4222 }
elmot 1:d0dfbce63a89 4223 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 4224
elmot 1:d0dfbce63a89 4225 __HAL_UNLOCK(htim);
elmot 1:d0dfbce63a89 4226
elmot 1:d0dfbce63a89 4227 return HAL_OK;
elmot 1:d0dfbce63a89 4228 }
elmot 1:d0dfbce63a89 4229
elmot 1:d0dfbce63a89 4230 /**
elmot 1:d0dfbce63a89 4231 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
elmot 1:d0dfbce63a89 4232 * or a XOR combination between CH1_input, CH2_input & CH3_input
elmot 1:d0dfbce63a89 4233 * @param htim: TIM handle.
elmot 1:d0dfbce63a89 4234 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
elmot 1:d0dfbce63a89 4235 * output of a XOR gate.
elmot 1:d0dfbce63a89 4236 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 4237 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
elmot 1:d0dfbce63a89 4238 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
elmot 1:d0dfbce63a89 4239 * pins are connected to the TI1 input (XOR combination)
elmot 1:d0dfbce63a89 4240 * @retval HAL status
elmot 1:d0dfbce63a89 4241 */
elmot 1:d0dfbce63a89 4242 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
elmot 1:d0dfbce63a89 4243 {
elmot 1:d0dfbce63a89 4244 uint32_t tmpcr2 = 0;
elmot 1:d0dfbce63a89 4245
elmot 1:d0dfbce63a89 4246 /* Check the parameters */
elmot 1:d0dfbce63a89 4247 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4248 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
elmot 1:d0dfbce63a89 4249
elmot 1:d0dfbce63a89 4250 /* Get the TIMx CR2 register value */
elmot 1:d0dfbce63a89 4251 tmpcr2 = htim->Instance->CR2;
elmot 1:d0dfbce63a89 4252
elmot 1:d0dfbce63a89 4253 /* Reset the TI1 selection */
elmot 1:d0dfbce63a89 4254 tmpcr2 &= ~TIM_CR2_TI1S;
elmot 1:d0dfbce63a89 4255
elmot 1:d0dfbce63a89 4256 /* Set the TI1 selection */
elmot 1:d0dfbce63a89 4257 tmpcr2 |= TI1_Selection;
elmot 1:d0dfbce63a89 4258
elmot 1:d0dfbce63a89 4259 /* Write to TIMxCR2 */
elmot 1:d0dfbce63a89 4260 htim->Instance->CR2 = tmpcr2;
elmot 1:d0dfbce63a89 4261
elmot 1:d0dfbce63a89 4262 return HAL_OK;
elmot 1:d0dfbce63a89 4263 }
elmot 1:d0dfbce63a89 4264
elmot 1:d0dfbce63a89 4265 /**
elmot 1:d0dfbce63a89 4266 * @brief Configures the TIM in Slave mode
elmot 1:d0dfbce63a89 4267 * @param htim: TIM handle.
elmot 1:d0dfbce63a89 4268 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
elmot 1:d0dfbce63a89 4269 * contains the selected trigger (internal trigger input, filtered
elmot 1:d0dfbce63a89 4270 * timer input or external trigger input) and the ) and the Slave
elmot 1:d0dfbce63a89 4271 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
elmot 1:d0dfbce63a89 4272 * @retval HAL status
elmot 1:d0dfbce63a89 4273 */
elmot 1:d0dfbce63a89 4274 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
elmot 1:d0dfbce63a89 4275 {
elmot 1:d0dfbce63a89 4276 /* Check the parameters */
elmot 1:d0dfbce63a89 4277 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4278 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
elmot 1:d0dfbce63a89 4279 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
elmot 1:d0dfbce63a89 4280
elmot 1:d0dfbce63a89 4281 __HAL_LOCK(htim);
elmot 1:d0dfbce63a89 4282
elmot 1:d0dfbce63a89 4283 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 4284
elmot 1:d0dfbce63a89 4285 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
elmot 1:d0dfbce63a89 4286
elmot 1:d0dfbce63a89 4287 /* Disable Trigger Interrupt */
elmot 1:d0dfbce63a89 4288 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
elmot 1:d0dfbce63a89 4289
elmot 1:d0dfbce63a89 4290 /* Disable Trigger DMA request */
elmot 1:d0dfbce63a89 4291 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
elmot 1:d0dfbce63a89 4292
elmot 1:d0dfbce63a89 4293 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 4294
elmot 1:d0dfbce63a89 4295 __HAL_UNLOCK(htim);
elmot 1:d0dfbce63a89 4296
elmot 1:d0dfbce63a89 4297 return HAL_OK;
elmot 1:d0dfbce63a89 4298 }
elmot 1:d0dfbce63a89 4299
elmot 1:d0dfbce63a89 4300 /**
elmot 1:d0dfbce63a89 4301 * @brief Configures the TIM in Slave mode in interrupt mode
elmot 1:d0dfbce63a89 4302 * @param htim: TIM handle.
elmot 1:d0dfbce63a89 4303 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
elmot 1:d0dfbce63a89 4304 * contains the selected trigger (internal trigger input, filtered
elmot 1:d0dfbce63a89 4305 * timer input or external trigger input) and the ) and the Slave
elmot 1:d0dfbce63a89 4306 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
elmot 1:d0dfbce63a89 4307 * @retval HAL status
elmot 1:d0dfbce63a89 4308 */
elmot 1:d0dfbce63a89 4309 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
elmot 1:d0dfbce63a89 4310 TIM_SlaveConfigTypeDef * sSlaveConfig)
elmot 1:d0dfbce63a89 4311 {
elmot 1:d0dfbce63a89 4312 /* Check the parameters */
elmot 1:d0dfbce63a89 4313 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4314 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
elmot 1:d0dfbce63a89 4315 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
elmot 1:d0dfbce63a89 4316
elmot 1:d0dfbce63a89 4317 __HAL_LOCK(htim);
elmot 1:d0dfbce63a89 4318
elmot 1:d0dfbce63a89 4319 htim->State = HAL_TIM_STATE_BUSY;
elmot 1:d0dfbce63a89 4320
elmot 1:d0dfbce63a89 4321 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
elmot 1:d0dfbce63a89 4322
elmot 1:d0dfbce63a89 4323 /* Enable Trigger Interrupt */
elmot 1:d0dfbce63a89 4324 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
elmot 1:d0dfbce63a89 4325
elmot 1:d0dfbce63a89 4326 /* Disable Trigger DMA request */
elmot 1:d0dfbce63a89 4327 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
elmot 1:d0dfbce63a89 4328
elmot 1:d0dfbce63a89 4329 htim->State = HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 4330
elmot 1:d0dfbce63a89 4331 __HAL_UNLOCK(htim);
elmot 1:d0dfbce63a89 4332
elmot 1:d0dfbce63a89 4333 return HAL_OK;
elmot 1:d0dfbce63a89 4334 }
elmot 1:d0dfbce63a89 4335
elmot 1:d0dfbce63a89 4336 /**
elmot 1:d0dfbce63a89 4337 * @brief Read the captured value from Capture Compare unit
elmot 1:d0dfbce63a89 4338 * @param htim: TIM handle.
elmot 1:d0dfbce63a89 4339 * @param Channel : TIM Channels to be enabled
elmot 1:d0dfbce63a89 4340 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 4341 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
elmot 1:d0dfbce63a89 4342 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
elmot 1:d0dfbce63a89 4343 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
elmot 1:d0dfbce63a89 4344 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
elmot 1:d0dfbce63a89 4345 * @retval Captured value
elmot 1:d0dfbce63a89 4346 */
elmot 1:d0dfbce63a89 4347 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
elmot 1:d0dfbce63a89 4348 {
elmot 1:d0dfbce63a89 4349 uint32_t tmpreg = 0;
elmot 1:d0dfbce63a89 4350
elmot 1:d0dfbce63a89 4351 __HAL_LOCK(htim);
elmot 1:d0dfbce63a89 4352
elmot 1:d0dfbce63a89 4353 switch (Channel)
elmot 1:d0dfbce63a89 4354 {
elmot 1:d0dfbce63a89 4355 case TIM_CHANNEL_1:
elmot 1:d0dfbce63a89 4356 {
elmot 1:d0dfbce63a89 4357 /* Check the parameters */
elmot 1:d0dfbce63a89 4358 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4359
elmot 1:d0dfbce63a89 4360 /* Return the capture 1 value */
elmot 1:d0dfbce63a89 4361 tmpreg = htim->Instance->CCR1;
elmot 1:d0dfbce63a89 4362
elmot 1:d0dfbce63a89 4363 break;
elmot 1:d0dfbce63a89 4364 }
elmot 1:d0dfbce63a89 4365 case TIM_CHANNEL_2:
elmot 1:d0dfbce63a89 4366 {
elmot 1:d0dfbce63a89 4367 /* Check the parameters */
elmot 1:d0dfbce63a89 4368 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4369
elmot 1:d0dfbce63a89 4370 /* Return the capture 2 value */
elmot 1:d0dfbce63a89 4371 tmpreg = htim->Instance->CCR2;
elmot 1:d0dfbce63a89 4372
elmot 1:d0dfbce63a89 4373 break;
elmot 1:d0dfbce63a89 4374 }
elmot 1:d0dfbce63a89 4375
elmot 1:d0dfbce63a89 4376 case TIM_CHANNEL_3:
elmot 1:d0dfbce63a89 4377 {
elmot 1:d0dfbce63a89 4378 /* Check the parameters */
elmot 1:d0dfbce63a89 4379 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4380
elmot 1:d0dfbce63a89 4381 /* Return the capture 3 value */
elmot 1:d0dfbce63a89 4382 tmpreg = htim->Instance->CCR3;
elmot 1:d0dfbce63a89 4383
elmot 1:d0dfbce63a89 4384 break;
elmot 1:d0dfbce63a89 4385 }
elmot 1:d0dfbce63a89 4386
elmot 1:d0dfbce63a89 4387 case TIM_CHANNEL_4:
elmot 1:d0dfbce63a89 4388 {
elmot 1:d0dfbce63a89 4389 /* Check the parameters */
elmot 1:d0dfbce63a89 4390 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 4391
elmot 1:d0dfbce63a89 4392 /* Return the capture 4 value */
elmot 1:d0dfbce63a89 4393 tmpreg = htim->Instance->CCR4;
elmot 1:d0dfbce63a89 4394
elmot 1:d0dfbce63a89 4395 break;
elmot 1:d0dfbce63a89 4396 }
elmot 1:d0dfbce63a89 4397
elmot 1:d0dfbce63a89 4398 default:
elmot 1:d0dfbce63a89 4399 break;
elmot 1:d0dfbce63a89 4400 }
elmot 1:d0dfbce63a89 4401
elmot 1:d0dfbce63a89 4402 __HAL_UNLOCK(htim);
elmot 1:d0dfbce63a89 4403 return tmpreg;
elmot 1:d0dfbce63a89 4404 }
elmot 1:d0dfbce63a89 4405
elmot 1:d0dfbce63a89 4406 /**
elmot 1:d0dfbce63a89 4407 * @}
elmot 1:d0dfbce63a89 4408 */
elmot 1:d0dfbce63a89 4409
elmot 1:d0dfbce63a89 4410 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
elmot 1:d0dfbce63a89 4411 * @brief TIM Callbacks functions
elmot 1:d0dfbce63a89 4412 *
elmot 1:d0dfbce63a89 4413 @verbatim
elmot 1:d0dfbce63a89 4414 ==============================================================================
elmot 1:d0dfbce63a89 4415 ##### TIM Callbacks functions #####
elmot 1:d0dfbce63a89 4416 ==============================================================================
elmot 1:d0dfbce63a89 4417 [..]
elmot 1:d0dfbce63a89 4418 This section provides TIM callback functions:
elmot 1:d0dfbce63a89 4419 (+) Timer Period elapsed callback
elmot 1:d0dfbce63a89 4420 (+) Timer Output Compare callback
elmot 1:d0dfbce63a89 4421 (+) Timer Input capture callback
elmot 1:d0dfbce63a89 4422 (+) Timer Trigger callback
elmot 1:d0dfbce63a89 4423 (+) Timer Error callback
elmot 1:d0dfbce63a89 4424
elmot 1:d0dfbce63a89 4425 @endverbatim
elmot 1:d0dfbce63a89 4426 * @{
elmot 1:d0dfbce63a89 4427 */
elmot 1:d0dfbce63a89 4428
elmot 1:d0dfbce63a89 4429 /**
elmot 1:d0dfbce63a89 4430 * @brief Period elapsed callback in non-blocking mode
elmot 1:d0dfbce63a89 4431 * @param htim : TIM handle
elmot 1:d0dfbce63a89 4432 * @retval None
elmot 1:d0dfbce63a89 4433 */
elmot 1:d0dfbce63a89 4434 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 4435 {
elmot 1:d0dfbce63a89 4436 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 4437 UNUSED(htim);
elmot 1:d0dfbce63a89 4438
elmot 1:d0dfbce63a89 4439 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 4440 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
elmot 1:d0dfbce63a89 4441 */
elmot 1:d0dfbce63a89 4442
elmot 1:d0dfbce63a89 4443 }
elmot 1:d0dfbce63a89 4444 /**
elmot 1:d0dfbce63a89 4445 * @brief Output Compare callback in non-blocking mode
elmot 1:d0dfbce63a89 4446 * @param htim : TIM OC handle
elmot 1:d0dfbce63a89 4447 * @retval None
elmot 1:d0dfbce63a89 4448 */
elmot 1:d0dfbce63a89 4449 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 4450 {
elmot 1:d0dfbce63a89 4451 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 4452 UNUSED(htim);
elmot 1:d0dfbce63a89 4453
elmot 1:d0dfbce63a89 4454 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 4455 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
elmot 1:d0dfbce63a89 4456 */
elmot 1:d0dfbce63a89 4457 }
elmot 1:d0dfbce63a89 4458 /**
elmot 1:d0dfbce63a89 4459 * @brief Input Capture callback in non-blocking mode
elmot 1:d0dfbce63a89 4460 * @param htim : TIM IC handle
elmot 1:d0dfbce63a89 4461 * @retval None
elmot 1:d0dfbce63a89 4462 */
elmot 1:d0dfbce63a89 4463 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 4464 {
elmot 1:d0dfbce63a89 4465 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 4466 UNUSED(htim);
elmot 1:d0dfbce63a89 4467
elmot 1:d0dfbce63a89 4468 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 4469 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
elmot 1:d0dfbce63a89 4470 */
elmot 1:d0dfbce63a89 4471 }
elmot 1:d0dfbce63a89 4472
elmot 1:d0dfbce63a89 4473 /**
elmot 1:d0dfbce63a89 4474 * @brief PWM Pulse finished callback in non-blocking mode
elmot 1:d0dfbce63a89 4475 * @param htim : TIM handle
elmot 1:d0dfbce63a89 4476 * @retval None
elmot 1:d0dfbce63a89 4477 */
elmot 1:d0dfbce63a89 4478 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 4479 {
elmot 1:d0dfbce63a89 4480 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 4481 UNUSED(htim);
elmot 1:d0dfbce63a89 4482
elmot 1:d0dfbce63a89 4483 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 4484 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
elmot 1:d0dfbce63a89 4485 */
elmot 1:d0dfbce63a89 4486 }
elmot 1:d0dfbce63a89 4487
elmot 1:d0dfbce63a89 4488 /**
elmot 1:d0dfbce63a89 4489 * @brief Hall Trigger detection callback in non-blocking mode
elmot 1:d0dfbce63a89 4490 * @param htim : TIM handle
elmot 1:d0dfbce63a89 4491 * @retval None
elmot 1:d0dfbce63a89 4492 */
elmot 1:d0dfbce63a89 4493 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 4494 {
elmot 1:d0dfbce63a89 4495 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 4496 UNUSED(htim);
elmot 1:d0dfbce63a89 4497
elmot 1:d0dfbce63a89 4498 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 4499 the HAL_TIM_TriggerCallback could be implemented in the user file
elmot 1:d0dfbce63a89 4500 */
elmot 1:d0dfbce63a89 4501 }
elmot 1:d0dfbce63a89 4502
elmot 1:d0dfbce63a89 4503 /**
elmot 1:d0dfbce63a89 4504 * @brief Timer error callback in non-blocking mode
elmot 1:d0dfbce63a89 4505 * @param htim : TIM handle
elmot 1:d0dfbce63a89 4506 * @retval None
elmot 1:d0dfbce63a89 4507 */
elmot 1:d0dfbce63a89 4508 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 4509 {
elmot 1:d0dfbce63a89 4510 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 4511 UNUSED(htim);
elmot 1:d0dfbce63a89 4512
elmot 1:d0dfbce63a89 4513 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 4514 the HAL_TIM_ErrorCallback could be implemented in the user file
elmot 1:d0dfbce63a89 4515 */
elmot 1:d0dfbce63a89 4516 }
elmot 1:d0dfbce63a89 4517
elmot 1:d0dfbce63a89 4518 /**
elmot 1:d0dfbce63a89 4519 * @}
elmot 1:d0dfbce63a89 4520 */
elmot 1:d0dfbce63a89 4521
elmot 1:d0dfbce63a89 4522 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
elmot 1:d0dfbce63a89 4523 * @brief Peripheral State functions
elmot 1:d0dfbce63a89 4524 *
elmot 1:d0dfbce63a89 4525 @verbatim
elmot 1:d0dfbce63a89 4526 ==============================================================================
elmot 1:d0dfbce63a89 4527 ##### Peripheral State functions #####
elmot 1:d0dfbce63a89 4528 ==============================================================================
elmot 1:d0dfbce63a89 4529 [..]
elmot 1:d0dfbce63a89 4530 This subsection permits to get in run-time the status of the peripheral
elmot 1:d0dfbce63a89 4531 and the data flow.
elmot 1:d0dfbce63a89 4532
elmot 1:d0dfbce63a89 4533 @endverbatim
elmot 1:d0dfbce63a89 4534 * @{
elmot 1:d0dfbce63a89 4535 */
elmot 1:d0dfbce63a89 4536
elmot 1:d0dfbce63a89 4537 /**
elmot 1:d0dfbce63a89 4538 * @brief Return the TIM Base handle state.
elmot 1:d0dfbce63a89 4539 * @param htim: TIM Base handle
elmot 1:d0dfbce63a89 4540 * @retval HAL state
elmot 1:d0dfbce63a89 4541 */
elmot 1:d0dfbce63a89 4542 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 4543 {
elmot 1:d0dfbce63a89 4544 return htim->State;
elmot 1:d0dfbce63a89 4545 }
elmot 1:d0dfbce63a89 4546
elmot 1:d0dfbce63a89 4547 /**
elmot 1:d0dfbce63a89 4548 * @brief Return the TIM OC handle state.
elmot 1:d0dfbce63a89 4549 * @param htim: TIM Ouput Compare handle
elmot 1:d0dfbce63a89 4550 * @retval HAL state
elmot 1:d0dfbce63a89 4551 */
elmot 1:d0dfbce63a89 4552 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 4553 {
elmot 1:d0dfbce63a89 4554 return htim->State;
elmot 1:d0dfbce63a89 4555 }
elmot 1:d0dfbce63a89 4556
elmot 1:d0dfbce63a89 4557 /**
elmot 1:d0dfbce63a89 4558 * @brief Return the TIM PWM handle state.
elmot 1:d0dfbce63a89 4559 * @param htim: TIM handle
elmot 1:d0dfbce63a89 4560 * @retval HAL state
elmot 1:d0dfbce63a89 4561 */
elmot 1:d0dfbce63a89 4562 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 4563 {
elmot 1:d0dfbce63a89 4564 return htim->State;
elmot 1:d0dfbce63a89 4565 }
elmot 1:d0dfbce63a89 4566
elmot 1:d0dfbce63a89 4567 /**
elmot 1:d0dfbce63a89 4568 * @brief Return the TIM Input Capture handle state.
elmot 1:d0dfbce63a89 4569 * @param htim: TIM IC handle
elmot 1:d0dfbce63a89 4570 * @retval HAL state
elmot 1:d0dfbce63a89 4571 */
elmot 1:d0dfbce63a89 4572 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 4573 {
elmot 1:d0dfbce63a89 4574 return htim->State;
elmot 1:d0dfbce63a89 4575 }
elmot 1:d0dfbce63a89 4576
elmot 1:d0dfbce63a89 4577 /**
elmot 1:d0dfbce63a89 4578 * @brief Return the TIM One Pulse Mode handle state.
elmot 1:d0dfbce63a89 4579 * @param htim: TIM OPM handle
elmot 1:d0dfbce63a89 4580 * @retval HAL state
elmot 1:d0dfbce63a89 4581 */
elmot 1:d0dfbce63a89 4582 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 4583 {
elmot 1:d0dfbce63a89 4584 return htim->State;
elmot 1:d0dfbce63a89 4585 }
elmot 1:d0dfbce63a89 4586
elmot 1:d0dfbce63a89 4587 /**
elmot 1:d0dfbce63a89 4588 * @brief Return the TIM Encoder Mode handle state.
elmot 1:d0dfbce63a89 4589 * @param htim: TIM Encoder handle
elmot 1:d0dfbce63a89 4590 * @retval HAL state
elmot 1:d0dfbce63a89 4591 */
elmot 1:d0dfbce63a89 4592 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
elmot 1:d0dfbce63a89 4593 {
elmot 1:d0dfbce63a89 4594 return htim->State;
elmot 1:d0dfbce63a89 4595 }
elmot 1:d0dfbce63a89 4596
elmot 1:d0dfbce63a89 4597 /**
elmot 1:d0dfbce63a89 4598 * @}
elmot 1:d0dfbce63a89 4599 */
elmot 1:d0dfbce63a89 4600
elmot 1:d0dfbce63a89 4601 /**
elmot 1:d0dfbce63a89 4602 * @brief TIM DMA error callback
elmot 1:d0dfbce63a89 4603 * @param hdma : pointer to DMA handle.
elmot 1:d0dfbce63a89 4604 * @retval None
elmot 1:d0dfbce63a89 4605 */
elmot 1:d0dfbce63a89 4606 void TIM_DMAError(DMA_HandleTypeDef *hdma)
elmot 1:d0dfbce63a89 4607 {
elmot 1:d0dfbce63a89 4608 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elmot 1:d0dfbce63a89 4609
elmot 1:d0dfbce63a89 4610 htim->State= HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 4611
elmot 1:d0dfbce63a89 4612 HAL_TIM_ErrorCallback(htim);
elmot 1:d0dfbce63a89 4613 }
elmot 1:d0dfbce63a89 4614
elmot 1:d0dfbce63a89 4615 /**
elmot 1:d0dfbce63a89 4616 * @brief TIM DMA Delay Pulse complete callback.
elmot 1:d0dfbce63a89 4617 * @param hdma : pointer to DMA handle.
elmot 1:d0dfbce63a89 4618 * @retval None
elmot 1:d0dfbce63a89 4619 */
elmot 1:d0dfbce63a89 4620 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
elmot 1:d0dfbce63a89 4621 {
elmot 1:d0dfbce63a89 4622 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elmot 1:d0dfbce63a89 4623
elmot 1:d0dfbce63a89 4624 htim->State= HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 4625
elmot 1:d0dfbce63a89 4626 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
elmot 1:d0dfbce63a89 4627 {
elmot 1:d0dfbce63a89 4628 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
elmot 1:d0dfbce63a89 4629 }
elmot 1:d0dfbce63a89 4630 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
elmot 1:d0dfbce63a89 4631 {
elmot 1:d0dfbce63a89 4632 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
elmot 1:d0dfbce63a89 4633 }
elmot 1:d0dfbce63a89 4634 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
elmot 1:d0dfbce63a89 4635 {
elmot 1:d0dfbce63a89 4636 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
elmot 1:d0dfbce63a89 4637 }
elmot 1:d0dfbce63a89 4638 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
elmot 1:d0dfbce63a89 4639 {
elmot 1:d0dfbce63a89 4640 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
elmot 1:d0dfbce63a89 4641 }
elmot 1:d0dfbce63a89 4642
elmot 1:d0dfbce63a89 4643 HAL_TIM_PWM_PulseFinishedCallback(htim);
elmot 1:d0dfbce63a89 4644
elmot 1:d0dfbce63a89 4645 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
elmot 1:d0dfbce63a89 4646 }
elmot 1:d0dfbce63a89 4647 /**
elmot 1:d0dfbce63a89 4648 * @brief TIM DMA Capture complete callback.
elmot 1:d0dfbce63a89 4649 * @param hdma : pointer to DMA handle.
elmot 1:d0dfbce63a89 4650 * @retval None
elmot 1:d0dfbce63a89 4651 */
elmot 1:d0dfbce63a89 4652 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
elmot 1:d0dfbce63a89 4653 {
elmot 1:d0dfbce63a89 4654 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elmot 1:d0dfbce63a89 4655
elmot 1:d0dfbce63a89 4656 htim->State= HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 4657
elmot 1:d0dfbce63a89 4658 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
elmot 1:d0dfbce63a89 4659 {
elmot 1:d0dfbce63a89 4660 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
elmot 1:d0dfbce63a89 4661 }
elmot 1:d0dfbce63a89 4662 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
elmot 1:d0dfbce63a89 4663 {
elmot 1:d0dfbce63a89 4664 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
elmot 1:d0dfbce63a89 4665 }
elmot 1:d0dfbce63a89 4666 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
elmot 1:d0dfbce63a89 4667 {
elmot 1:d0dfbce63a89 4668 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
elmot 1:d0dfbce63a89 4669 }
elmot 1:d0dfbce63a89 4670 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
elmot 1:d0dfbce63a89 4671 {
elmot 1:d0dfbce63a89 4672 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
elmot 1:d0dfbce63a89 4673 }
elmot 1:d0dfbce63a89 4674
elmot 1:d0dfbce63a89 4675 HAL_TIM_IC_CaptureCallback(htim);
elmot 1:d0dfbce63a89 4676
elmot 1:d0dfbce63a89 4677 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
elmot 1:d0dfbce63a89 4678 }
elmot 1:d0dfbce63a89 4679
elmot 1:d0dfbce63a89 4680 /**
elmot 1:d0dfbce63a89 4681 * @brief TIM DMA Period Elapse complete callback.
elmot 1:d0dfbce63a89 4682 * @param hdma : pointer to DMA handle.
elmot 1:d0dfbce63a89 4683 * @retval None
elmot 1:d0dfbce63a89 4684 */
elmot 1:d0dfbce63a89 4685 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
elmot 1:d0dfbce63a89 4686 {
elmot 1:d0dfbce63a89 4687 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elmot 1:d0dfbce63a89 4688
elmot 1:d0dfbce63a89 4689 htim->State= HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 4690
elmot 1:d0dfbce63a89 4691 HAL_TIM_PeriodElapsedCallback(htim);
elmot 1:d0dfbce63a89 4692 }
elmot 1:d0dfbce63a89 4693
elmot 1:d0dfbce63a89 4694 /**
elmot 1:d0dfbce63a89 4695 * @brief TIM DMA Trigger callback.
elmot 1:d0dfbce63a89 4696 * @param hdma : pointer to DMA handle.
elmot 1:d0dfbce63a89 4697 * @retval None
elmot 1:d0dfbce63a89 4698 */
elmot 1:d0dfbce63a89 4699 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
elmot 1:d0dfbce63a89 4700 {
elmot 1:d0dfbce63a89 4701 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elmot 1:d0dfbce63a89 4702
elmot 1:d0dfbce63a89 4703 htim->State= HAL_TIM_STATE_READY;
elmot 1:d0dfbce63a89 4704
elmot 1:d0dfbce63a89 4705 HAL_TIM_TriggerCallback(htim);
elmot 1:d0dfbce63a89 4706 }
elmot 1:d0dfbce63a89 4707
elmot 1:d0dfbce63a89 4708 /**
elmot 1:d0dfbce63a89 4709 * @brief Time Base configuration
elmot 1:d0dfbce63a89 4710 * @param TIMx: TIM peripheral
elmot 1:d0dfbce63a89 4711 * @param Structure: TIM Base configuration structure
elmot 1:d0dfbce63a89 4712 * @retval None
elmot 1:d0dfbce63a89 4713 */
elmot 1:d0dfbce63a89 4714 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
elmot 1:d0dfbce63a89 4715 {
elmot 1:d0dfbce63a89 4716 uint32_t tmpcr1 = 0;
elmot 1:d0dfbce63a89 4717 tmpcr1 = TIMx->CR1;
elmot 1:d0dfbce63a89 4718
elmot 1:d0dfbce63a89 4719 /* Set TIM Time Base Unit parameters ---------------------------------------*/
elmot 1:d0dfbce63a89 4720 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
elmot 1:d0dfbce63a89 4721 {
elmot 1:d0dfbce63a89 4722 /* Select the Counter Mode */
elmot 1:d0dfbce63a89 4723 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
elmot 1:d0dfbce63a89 4724 tmpcr1 |= Structure->CounterMode;
elmot 1:d0dfbce63a89 4725 }
elmot 1:d0dfbce63a89 4726
elmot 1:d0dfbce63a89 4727 if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
elmot 1:d0dfbce63a89 4728 {
elmot 1:d0dfbce63a89 4729 /* Set the clock division */
elmot 1:d0dfbce63a89 4730 tmpcr1 &= ~TIM_CR1_CKD;
elmot 1:d0dfbce63a89 4731 tmpcr1 |= (uint32_t)Structure->ClockDivision;
elmot 1:d0dfbce63a89 4732 }
elmot 1:d0dfbce63a89 4733
elmot 1:d0dfbce63a89 4734 TIMx->CR1 = tmpcr1;
elmot 1:d0dfbce63a89 4735
elmot 1:d0dfbce63a89 4736 /* Set the Autoreload value */
elmot 1:d0dfbce63a89 4737 TIMx->ARR = (uint32_t)Structure->Period ;
elmot 1:d0dfbce63a89 4738
elmot 1:d0dfbce63a89 4739 /* Set the Prescaler value */
elmot 1:d0dfbce63a89 4740 TIMx->PSC = (uint32_t)Structure->Prescaler;
elmot 1:d0dfbce63a89 4741
elmot 1:d0dfbce63a89 4742 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
elmot 1:d0dfbce63a89 4743 {
elmot 1:d0dfbce63a89 4744 /* Set the Repetition Counter value */
elmot 1:d0dfbce63a89 4745 TIMx->RCR = Structure->RepetitionCounter;
elmot 1:d0dfbce63a89 4746 }
elmot 1:d0dfbce63a89 4747
elmot 1:d0dfbce63a89 4748 /* Generate an update event to reload the Prescaler
elmot 1:d0dfbce63a89 4749 and the repetition counter(only for TIM1 and TIM8) value immediately */
elmot 1:d0dfbce63a89 4750 TIMx->EGR = TIM_EGR_UG;
elmot 1:d0dfbce63a89 4751 }
elmot 1:d0dfbce63a89 4752
elmot 1:d0dfbce63a89 4753 /**
elmot 1:d0dfbce63a89 4754 * @brief Time Ouput Compare 1 configuration
elmot 1:d0dfbce63a89 4755 * @param TIMx to select the TIM peripheral
elmot 1:d0dfbce63a89 4756 * @param OC_Config: The ouput configuration structure
elmot 1:d0dfbce63a89 4757 * @retval None
elmot 1:d0dfbce63a89 4758 */
elmot 1:d0dfbce63a89 4759 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
elmot 1:d0dfbce63a89 4760 {
elmot 1:d0dfbce63a89 4761 uint32_t tmpccmrx = 0;
elmot 1:d0dfbce63a89 4762 uint32_t tmpccer = 0;
elmot 1:d0dfbce63a89 4763 uint32_t tmpcr2 = 0;
elmot 1:d0dfbce63a89 4764
elmot 1:d0dfbce63a89 4765 /* Disable the Channel 1: Reset the CC1E Bit */
elmot 1:d0dfbce63a89 4766 TIMx->CCER &= ~TIM_CCER_CC1E;
elmot 1:d0dfbce63a89 4767
elmot 1:d0dfbce63a89 4768 /* Get the TIMx CCER register value */
elmot 1:d0dfbce63a89 4769 tmpccer = TIMx->CCER;
elmot 1:d0dfbce63a89 4770 /* Get the TIMx CR2 register value */
elmot 1:d0dfbce63a89 4771 tmpcr2 = TIMx->CR2;
elmot 1:d0dfbce63a89 4772
elmot 1:d0dfbce63a89 4773 /* Get the TIMx CCMR1 register value */
elmot 1:d0dfbce63a89 4774 tmpccmrx = TIMx->CCMR1;
elmot 1:d0dfbce63a89 4775
elmot 1:d0dfbce63a89 4776 /* Reset the Output Compare Mode Bits */
elmot 1:d0dfbce63a89 4777 tmpccmrx &= ~TIM_CCMR1_OC1M;
elmot 1:d0dfbce63a89 4778 tmpccmrx &= ~TIM_CCMR1_CC1S;
elmot 1:d0dfbce63a89 4779 /* Select the Output Compare Mode */
elmot 1:d0dfbce63a89 4780 tmpccmrx |= OC_Config->OCMode;
elmot 1:d0dfbce63a89 4781
elmot 1:d0dfbce63a89 4782 /* Reset the Output Polarity level */
elmot 1:d0dfbce63a89 4783 tmpccer &= ~TIM_CCER_CC1P;
elmot 1:d0dfbce63a89 4784 /* Set the Output Compare Polarity */
elmot 1:d0dfbce63a89 4785 tmpccer |= OC_Config->OCPolarity;
elmot 1:d0dfbce63a89 4786
elmot 1:d0dfbce63a89 4787 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
elmot 1:d0dfbce63a89 4788 {
elmot 1:d0dfbce63a89 4789 /* Check parameters */
elmot 1:d0dfbce63a89 4790 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
elmot 1:d0dfbce63a89 4791
elmot 1:d0dfbce63a89 4792 /* Reset the Output N Polarity level */
elmot 1:d0dfbce63a89 4793 tmpccer &= ~TIM_CCER_CC1NP;
elmot 1:d0dfbce63a89 4794 /* Set the Output N Polarity */
elmot 1:d0dfbce63a89 4795 tmpccer |= OC_Config->OCNPolarity;
elmot 1:d0dfbce63a89 4796 /* Reset the Output N State */
elmot 1:d0dfbce63a89 4797 tmpccer &= ~TIM_CCER_CC1NE;
elmot 1:d0dfbce63a89 4798 }
elmot 1:d0dfbce63a89 4799
elmot 1:d0dfbce63a89 4800 if(IS_TIM_BREAK_INSTANCE(TIMx))
elmot 1:d0dfbce63a89 4801 {
elmot 1:d0dfbce63a89 4802 /* Check parameters */
elmot 1:d0dfbce63a89 4803 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
elmot 1:d0dfbce63a89 4804 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
elmot 1:d0dfbce63a89 4805
elmot 1:d0dfbce63a89 4806 /* Reset the Output Compare and Output Compare N IDLE State */
elmot 1:d0dfbce63a89 4807 tmpcr2 &= ~TIM_CR2_OIS1;
elmot 1:d0dfbce63a89 4808 tmpcr2 &= ~TIM_CR2_OIS1N;
elmot 1:d0dfbce63a89 4809 /* Set the Output Idle state */
elmot 1:d0dfbce63a89 4810 tmpcr2 |= OC_Config->OCIdleState;
elmot 1:d0dfbce63a89 4811 /* Set the Output N Idle state */
elmot 1:d0dfbce63a89 4812 tmpcr2 |= OC_Config->OCNIdleState;
elmot 1:d0dfbce63a89 4813 }
elmot 1:d0dfbce63a89 4814 /* Write to TIMx CR2 */
elmot 1:d0dfbce63a89 4815 TIMx->CR2 = tmpcr2;
elmot 1:d0dfbce63a89 4816
elmot 1:d0dfbce63a89 4817 /* Write to TIMx CCMR1 */
elmot 1:d0dfbce63a89 4818 TIMx->CCMR1 = tmpccmrx;
elmot 1:d0dfbce63a89 4819
elmot 1:d0dfbce63a89 4820 /* Set the Capture Compare Register value */
elmot 1:d0dfbce63a89 4821 TIMx->CCR1 = OC_Config->Pulse;
elmot 1:d0dfbce63a89 4822
elmot 1:d0dfbce63a89 4823 /* Write to TIMx CCER */
elmot 1:d0dfbce63a89 4824 TIMx->CCER = tmpccer;
elmot 1:d0dfbce63a89 4825 }
elmot 1:d0dfbce63a89 4826
elmot 1:d0dfbce63a89 4827 /**
elmot 1:d0dfbce63a89 4828 * @brief Time Ouput Compare 2 configuration
elmot 1:d0dfbce63a89 4829 * @param TIMx to select the TIM peripheral
elmot 1:d0dfbce63a89 4830 * @param OC_Config: The ouput configuration structure
elmot 1:d0dfbce63a89 4831 * @retval None
elmot 1:d0dfbce63a89 4832 */
elmot 1:d0dfbce63a89 4833 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
elmot 1:d0dfbce63a89 4834 {
elmot 1:d0dfbce63a89 4835 uint32_t tmpccmrx = 0;
elmot 1:d0dfbce63a89 4836 uint32_t tmpccer = 0;
elmot 1:d0dfbce63a89 4837 uint32_t tmpcr2 = 0;
elmot 1:d0dfbce63a89 4838
elmot 1:d0dfbce63a89 4839 /* Disable the Channel 2: Reset the CC2E Bit */
elmot 1:d0dfbce63a89 4840 TIMx->CCER &= ~TIM_CCER_CC2E;
elmot 1:d0dfbce63a89 4841
elmot 1:d0dfbce63a89 4842 /* Get the TIMx CCER register value */
elmot 1:d0dfbce63a89 4843 tmpccer = TIMx->CCER;
elmot 1:d0dfbce63a89 4844 /* Get the TIMx CR2 register value */
elmot 1:d0dfbce63a89 4845 tmpcr2 = TIMx->CR2;
elmot 1:d0dfbce63a89 4846
elmot 1:d0dfbce63a89 4847 /* Get the TIMx CCMR1 register value */
elmot 1:d0dfbce63a89 4848 tmpccmrx = TIMx->CCMR1;
elmot 1:d0dfbce63a89 4849
elmot 1:d0dfbce63a89 4850 /* Reset the Output Compare mode and Capture/Compare selection Bits */
elmot 1:d0dfbce63a89 4851 tmpccmrx &= ~TIM_CCMR1_OC2M;
elmot 1:d0dfbce63a89 4852 tmpccmrx &= ~TIM_CCMR1_CC2S;
elmot 1:d0dfbce63a89 4853
elmot 1:d0dfbce63a89 4854 /* Select the Output Compare Mode */
elmot 1:d0dfbce63a89 4855 tmpccmrx |= (OC_Config->OCMode << 8);
elmot 1:d0dfbce63a89 4856
elmot 1:d0dfbce63a89 4857 /* Reset the Output Polarity level */
elmot 1:d0dfbce63a89 4858 tmpccer &= ~TIM_CCER_CC2P;
elmot 1:d0dfbce63a89 4859 /* Set the Output Compare Polarity */
elmot 1:d0dfbce63a89 4860 tmpccer |= (OC_Config->OCPolarity << 4);
elmot 1:d0dfbce63a89 4861
elmot 1:d0dfbce63a89 4862 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
elmot 1:d0dfbce63a89 4863 {
elmot 1:d0dfbce63a89 4864 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
elmot 1:d0dfbce63a89 4865
elmot 1:d0dfbce63a89 4866 /* Reset the Output N Polarity level */
elmot 1:d0dfbce63a89 4867 tmpccer &= ~TIM_CCER_CC2NP;
elmot 1:d0dfbce63a89 4868 /* Set the Output N Polarity */
elmot 1:d0dfbce63a89 4869 tmpccer |= (OC_Config->OCNPolarity << 4);
elmot 1:d0dfbce63a89 4870 /* Reset the Output N State */
elmot 1:d0dfbce63a89 4871 tmpccer &= ~TIM_CCER_CC2NE;
elmot 1:d0dfbce63a89 4872
elmot 1:d0dfbce63a89 4873 }
elmot 1:d0dfbce63a89 4874
elmot 1:d0dfbce63a89 4875 if(IS_TIM_BREAK_INSTANCE(TIMx))
elmot 1:d0dfbce63a89 4876 {
elmot 1:d0dfbce63a89 4877 /* Check parameters */
elmot 1:d0dfbce63a89 4878 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
elmot 1:d0dfbce63a89 4879 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
elmot 1:d0dfbce63a89 4880
elmot 1:d0dfbce63a89 4881 /* Reset the Output Compare and Output Compare N IDLE State */
elmot 1:d0dfbce63a89 4882 tmpcr2 &= ~TIM_CR2_OIS2;
elmot 1:d0dfbce63a89 4883 tmpcr2 &= ~TIM_CR2_OIS2N;
elmot 1:d0dfbce63a89 4884 /* Set the Output Idle state */
elmot 1:d0dfbce63a89 4885 tmpcr2 |= (OC_Config->OCIdleState << 2);
elmot 1:d0dfbce63a89 4886 /* Set the Output N Idle state */
elmot 1:d0dfbce63a89 4887 tmpcr2 |= (OC_Config->OCNIdleState << 2);
elmot 1:d0dfbce63a89 4888 }
elmot 1:d0dfbce63a89 4889
elmot 1:d0dfbce63a89 4890 /* Write to TIMx CR2 */
elmot 1:d0dfbce63a89 4891 TIMx->CR2 = tmpcr2;
elmot 1:d0dfbce63a89 4892
elmot 1:d0dfbce63a89 4893 /* Write to TIMx CCMR1 */
elmot 1:d0dfbce63a89 4894 TIMx->CCMR1 = tmpccmrx;
elmot 1:d0dfbce63a89 4895
elmot 1:d0dfbce63a89 4896 /* Set the Capture Compare Register value */
elmot 1:d0dfbce63a89 4897 TIMx->CCR2 = OC_Config->Pulse;
elmot 1:d0dfbce63a89 4898
elmot 1:d0dfbce63a89 4899 /* Write to TIMx CCER */
elmot 1:d0dfbce63a89 4900 TIMx->CCER = tmpccer;
elmot 1:d0dfbce63a89 4901 }
elmot 1:d0dfbce63a89 4902
elmot 1:d0dfbce63a89 4903 /**
elmot 1:d0dfbce63a89 4904 * @brief Time Ouput Compare 3 configuration
elmot 1:d0dfbce63a89 4905 * @param TIMx to select the TIM peripheral
elmot 1:d0dfbce63a89 4906 * @param OC_Config: The ouput configuration structure
elmot 1:d0dfbce63a89 4907 * @retval None
elmot 1:d0dfbce63a89 4908 */
elmot 1:d0dfbce63a89 4909 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
elmot 1:d0dfbce63a89 4910 {
elmot 1:d0dfbce63a89 4911 uint32_t tmpccmrx = 0;
elmot 1:d0dfbce63a89 4912 uint32_t tmpccer = 0;
elmot 1:d0dfbce63a89 4913 uint32_t tmpcr2 = 0;
elmot 1:d0dfbce63a89 4914
elmot 1:d0dfbce63a89 4915 /* Disable the Channel 3: Reset the CC2E Bit */
elmot 1:d0dfbce63a89 4916 TIMx->CCER &= ~TIM_CCER_CC3E;
elmot 1:d0dfbce63a89 4917
elmot 1:d0dfbce63a89 4918 /* Get the TIMx CCER register value */
elmot 1:d0dfbce63a89 4919 tmpccer = TIMx->CCER;
elmot 1:d0dfbce63a89 4920 /* Get the TIMx CR2 register value */
elmot 1:d0dfbce63a89 4921 tmpcr2 = TIMx->CR2;
elmot 1:d0dfbce63a89 4922
elmot 1:d0dfbce63a89 4923 /* Get the TIMx CCMR2 register value */
elmot 1:d0dfbce63a89 4924 tmpccmrx = TIMx->CCMR2;
elmot 1:d0dfbce63a89 4925
elmot 1:d0dfbce63a89 4926 /* Reset the Output Compare mode and Capture/Compare selection Bits */
elmot 1:d0dfbce63a89 4927 tmpccmrx &= ~TIM_CCMR2_OC3M;
elmot 1:d0dfbce63a89 4928 tmpccmrx &= ~TIM_CCMR2_CC3S;
elmot 1:d0dfbce63a89 4929 /* Select the Output Compare Mode */
elmot 1:d0dfbce63a89 4930 tmpccmrx |= OC_Config->OCMode;
elmot 1:d0dfbce63a89 4931
elmot 1:d0dfbce63a89 4932 /* Reset the Output Polarity level */
elmot 1:d0dfbce63a89 4933 tmpccer &= ~TIM_CCER_CC3P;
elmot 1:d0dfbce63a89 4934 /* Set the Output Compare Polarity */
elmot 1:d0dfbce63a89 4935 tmpccer |= (OC_Config->OCPolarity << 8);
elmot 1:d0dfbce63a89 4936
elmot 1:d0dfbce63a89 4937 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
elmot 1:d0dfbce63a89 4938 {
elmot 1:d0dfbce63a89 4939 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
elmot 1:d0dfbce63a89 4940
elmot 1:d0dfbce63a89 4941 /* Reset the Output N Polarity level */
elmot 1:d0dfbce63a89 4942 tmpccer &= ~TIM_CCER_CC3NP;
elmot 1:d0dfbce63a89 4943 /* Set the Output N Polarity */
elmot 1:d0dfbce63a89 4944 tmpccer |= (OC_Config->OCNPolarity << 8);
elmot 1:d0dfbce63a89 4945 /* Reset the Output N State */
elmot 1:d0dfbce63a89 4946 tmpccer &= ~TIM_CCER_CC3NE;
elmot 1:d0dfbce63a89 4947 }
elmot 1:d0dfbce63a89 4948
elmot 1:d0dfbce63a89 4949 if(IS_TIM_BREAK_INSTANCE(TIMx))
elmot 1:d0dfbce63a89 4950 {
elmot 1:d0dfbce63a89 4951 /* Check parameters */
elmot 1:d0dfbce63a89 4952 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
elmot 1:d0dfbce63a89 4953 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
elmot 1:d0dfbce63a89 4954
elmot 1:d0dfbce63a89 4955 /* Reset the Output Compare and Output Compare N IDLE State */
elmot 1:d0dfbce63a89 4956 tmpcr2 &= ~TIM_CR2_OIS3;
elmot 1:d0dfbce63a89 4957 tmpcr2 &= ~TIM_CR2_OIS3N;
elmot 1:d0dfbce63a89 4958 /* Set the Output Idle state */
elmot 1:d0dfbce63a89 4959 tmpcr2 |= (OC_Config->OCIdleState << 4);
elmot 1:d0dfbce63a89 4960 /* Set the Output N Idle state */
elmot 1:d0dfbce63a89 4961 tmpcr2 |= (OC_Config->OCNIdleState << 4);
elmot 1:d0dfbce63a89 4962 }
elmot 1:d0dfbce63a89 4963
elmot 1:d0dfbce63a89 4964 /* Write to TIMx CR2 */
elmot 1:d0dfbce63a89 4965 TIMx->CR2 = tmpcr2;
elmot 1:d0dfbce63a89 4966
elmot 1:d0dfbce63a89 4967 /* Write to TIMx CCMR2 */
elmot 1:d0dfbce63a89 4968 TIMx->CCMR2 = tmpccmrx;
elmot 1:d0dfbce63a89 4969
elmot 1:d0dfbce63a89 4970 /* Set the Capture Compare Register value */
elmot 1:d0dfbce63a89 4971 TIMx->CCR3 = OC_Config->Pulse;
elmot 1:d0dfbce63a89 4972
elmot 1:d0dfbce63a89 4973 /* Write to TIMx CCER */
elmot 1:d0dfbce63a89 4974 TIMx->CCER = tmpccer;
elmot 1:d0dfbce63a89 4975 }
elmot 1:d0dfbce63a89 4976
elmot 1:d0dfbce63a89 4977 /**
elmot 1:d0dfbce63a89 4978 * @brief Time Ouput Compare 4 configuration
elmot 1:d0dfbce63a89 4979 * @param TIMx to select the TIM peripheral
elmot 1:d0dfbce63a89 4980 * @param OC_Config: The ouput configuration structure
elmot 1:d0dfbce63a89 4981 * @retval None
elmot 1:d0dfbce63a89 4982 */
elmot 1:d0dfbce63a89 4983 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
elmot 1:d0dfbce63a89 4984 {
elmot 1:d0dfbce63a89 4985 uint32_t tmpccmrx = 0;
elmot 1:d0dfbce63a89 4986 uint32_t tmpccer = 0;
elmot 1:d0dfbce63a89 4987 uint32_t tmpcr2 = 0;
elmot 1:d0dfbce63a89 4988
elmot 1:d0dfbce63a89 4989 /* Disable the Channel 4: Reset the CC4E Bit */
elmot 1:d0dfbce63a89 4990 TIMx->CCER &= ~TIM_CCER_CC4E;
elmot 1:d0dfbce63a89 4991
elmot 1:d0dfbce63a89 4992 /* Get the TIMx CCER register value */
elmot 1:d0dfbce63a89 4993 tmpccer = TIMx->CCER;
elmot 1:d0dfbce63a89 4994 /* Get the TIMx CR2 register value */
elmot 1:d0dfbce63a89 4995 tmpcr2 = TIMx->CR2;
elmot 1:d0dfbce63a89 4996
elmot 1:d0dfbce63a89 4997 /* Get the TIMx CCMR2 register value */
elmot 1:d0dfbce63a89 4998 tmpccmrx = TIMx->CCMR2;
elmot 1:d0dfbce63a89 4999
elmot 1:d0dfbce63a89 5000 /* Reset the Output Compare mode and Capture/Compare selection Bits */
elmot 1:d0dfbce63a89 5001 tmpccmrx &= ~TIM_CCMR2_OC4M;
elmot 1:d0dfbce63a89 5002 tmpccmrx &= ~TIM_CCMR2_CC4S;
elmot 1:d0dfbce63a89 5003
elmot 1:d0dfbce63a89 5004 /* Select the Output Compare Mode */
elmot 1:d0dfbce63a89 5005 tmpccmrx |= (OC_Config->OCMode << 8);
elmot 1:d0dfbce63a89 5006
elmot 1:d0dfbce63a89 5007 /* Reset the Output Polarity level */
elmot 1:d0dfbce63a89 5008 tmpccer &= ~TIM_CCER_CC4P;
elmot 1:d0dfbce63a89 5009 /* Set the Output Compare Polarity */
elmot 1:d0dfbce63a89 5010 tmpccer |= (OC_Config->OCPolarity << 12);
elmot 1:d0dfbce63a89 5011
elmot 1:d0dfbce63a89 5012 if(IS_TIM_BREAK_INSTANCE(TIMx))
elmot 1:d0dfbce63a89 5013 {
elmot 1:d0dfbce63a89 5014 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
elmot 1:d0dfbce63a89 5015
elmot 1:d0dfbce63a89 5016 /* Reset the Output Compare IDLE State */
elmot 1:d0dfbce63a89 5017 tmpcr2 &= ~TIM_CR2_OIS4;
elmot 1:d0dfbce63a89 5018 /* Set the Output Idle state */
elmot 1:d0dfbce63a89 5019 tmpcr2 |= (OC_Config->OCIdleState << 6);
elmot 1:d0dfbce63a89 5020 }
elmot 1:d0dfbce63a89 5021
elmot 1:d0dfbce63a89 5022 /* Write to TIMx CR2 */
elmot 1:d0dfbce63a89 5023 TIMx->CR2 = tmpcr2;
elmot 1:d0dfbce63a89 5024
elmot 1:d0dfbce63a89 5025 /* Write to TIMx CCMR2 */
elmot 1:d0dfbce63a89 5026 TIMx->CCMR2 = tmpccmrx;
elmot 1:d0dfbce63a89 5027
elmot 1:d0dfbce63a89 5028 /* Set the Capture Compare Register value */
elmot 1:d0dfbce63a89 5029 TIMx->CCR4 = OC_Config->Pulse;
elmot 1:d0dfbce63a89 5030
elmot 1:d0dfbce63a89 5031 /* Write to TIMx CCER */
elmot 1:d0dfbce63a89 5032 TIMx->CCER = tmpccer;
elmot 1:d0dfbce63a89 5033 }
elmot 1:d0dfbce63a89 5034
elmot 1:d0dfbce63a89 5035 /**
elmot 1:d0dfbce63a89 5036 * @brief Timer Ouput Compare 5 configuration
elmot 1:d0dfbce63a89 5037 * @param TIMx to select the TIM peripheral
elmot 1:d0dfbce63a89 5038 * @param OC_Config: The ouput configuration structure
elmot 1:d0dfbce63a89 5039 * @retval None
elmot 1:d0dfbce63a89 5040 */
elmot 1:d0dfbce63a89 5041 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
elmot 1:d0dfbce63a89 5042 TIM_OC_InitTypeDef *OC_Config)
elmot 1:d0dfbce63a89 5043 {
elmot 1:d0dfbce63a89 5044 uint32_t tmpccmrx = 0;
elmot 1:d0dfbce63a89 5045 uint32_t tmpccer = 0;
elmot 1:d0dfbce63a89 5046 uint32_t tmpcr2 = 0;
elmot 1:d0dfbce63a89 5047
elmot 1:d0dfbce63a89 5048 /* Disable the output: Reset the CCxE Bit */
elmot 1:d0dfbce63a89 5049 TIMx->CCER &= ~TIM_CCER_CC5E;
elmot 1:d0dfbce63a89 5050
elmot 1:d0dfbce63a89 5051 /* Get the TIMx CCER register value */
elmot 1:d0dfbce63a89 5052 tmpccer = TIMx->CCER;
elmot 1:d0dfbce63a89 5053 /* Get the TIMx CR2 register value */
elmot 1:d0dfbce63a89 5054 tmpcr2 = TIMx->CR2;
elmot 1:d0dfbce63a89 5055 /* Get the TIMx CCMR1 register value */
elmot 1:d0dfbce63a89 5056 tmpccmrx = TIMx->CCMR3;
elmot 1:d0dfbce63a89 5057
elmot 1:d0dfbce63a89 5058 /* Reset the Output Compare Mode Bits */
elmot 1:d0dfbce63a89 5059 tmpccmrx &= ~(TIM_CCMR3_OC5M);
elmot 1:d0dfbce63a89 5060 /* Select the Output Compare Mode */
elmot 1:d0dfbce63a89 5061 tmpccmrx |= OC_Config->OCMode;
elmot 1:d0dfbce63a89 5062
elmot 1:d0dfbce63a89 5063 /* Reset the Output Polarity level */
elmot 1:d0dfbce63a89 5064 tmpccer &= ~TIM_CCER_CC5P;
elmot 1:d0dfbce63a89 5065 /* Set the Output Compare Polarity */
elmot 1:d0dfbce63a89 5066 tmpccer |= (OC_Config->OCPolarity << 16);
elmot 1:d0dfbce63a89 5067
elmot 1:d0dfbce63a89 5068 if(IS_TIM_BREAK_INSTANCE(TIMx))
elmot 1:d0dfbce63a89 5069 {
elmot 1:d0dfbce63a89 5070 /* Reset the Output Compare IDLE State */
elmot 1:d0dfbce63a89 5071 tmpcr2 &= ~TIM_CR2_OIS5;
elmot 1:d0dfbce63a89 5072 /* Set the Output Idle state */
elmot 1:d0dfbce63a89 5073 tmpcr2 |= (OC_Config->OCIdleState << 8);
elmot 1:d0dfbce63a89 5074 }
elmot 1:d0dfbce63a89 5075 /* Write to TIMx CR2 */
elmot 1:d0dfbce63a89 5076 TIMx->CR2 = tmpcr2;
elmot 1:d0dfbce63a89 5077
elmot 1:d0dfbce63a89 5078 /* Write to TIMx CCMR3 */
elmot 1:d0dfbce63a89 5079 TIMx->CCMR3 = tmpccmrx;
elmot 1:d0dfbce63a89 5080
elmot 1:d0dfbce63a89 5081 /* Set the Capture Compare Register value */
elmot 1:d0dfbce63a89 5082 TIMx->CCR5 = OC_Config->Pulse;
elmot 1:d0dfbce63a89 5083
elmot 1:d0dfbce63a89 5084 /* Write to TIMx CCER */
elmot 1:d0dfbce63a89 5085 TIMx->CCER = tmpccer;
elmot 1:d0dfbce63a89 5086 }
elmot 1:d0dfbce63a89 5087
elmot 1:d0dfbce63a89 5088 /**
elmot 1:d0dfbce63a89 5089 * @brief Timer Ouput Compare 6 configuration
elmot 1:d0dfbce63a89 5090 * @param TIMx to select the TIM peripheral
elmot 1:d0dfbce63a89 5091 * @param OC_Config: The ouput configuration structure
elmot 1:d0dfbce63a89 5092 * @retval None
elmot 1:d0dfbce63a89 5093 */
elmot 1:d0dfbce63a89 5094 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
elmot 1:d0dfbce63a89 5095 TIM_OC_InitTypeDef *OC_Config)
elmot 1:d0dfbce63a89 5096 {
elmot 1:d0dfbce63a89 5097 uint32_t tmpccmrx = 0;
elmot 1:d0dfbce63a89 5098 uint32_t tmpccer = 0;
elmot 1:d0dfbce63a89 5099 uint32_t tmpcr2 = 0;
elmot 1:d0dfbce63a89 5100
elmot 1:d0dfbce63a89 5101 /* Disable the output: Reset the CCxE Bit */
elmot 1:d0dfbce63a89 5102 TIMx->CCER &= ~TIM_CCER_CC6E;
elmot 1:d0dfbce63a89 5103
elmot 1:d0dfbce63a89 5104 /* Get the TIMx CCER register value */
elmot 1:d0dfbce63a89 5105 tmpccer = TIMx->CCER;
elmot 1:d0dfbce63a89 5106 /* Get the TIMx CR2 register value */
elmot 1:d0dfbce63a89 5107 tmpcr2 = TIMx->CR2;
elmot 1:d0dfbce63a89 5108 /* Get the TIMx CCMR1 register value */
elmot 1:d0dfbce63a89 5109 tmpccmrx = TIMx->CCMR3;
elmot 1:d0dfbce63a89 5110
elmot 1:d0dfbce63a89 5111 /* Reset the Output Compare Mode Bits */
elmot 1:d0dfbce63a89 5112 tmpccmrx &= ~(TIM_CCMR3_OC6M);
elmot 1:d0dfbce63a89 5113 /* Select the Output Compare Mode */
elmot 1:d0dfbce63a89 5114 tmpccmrx |= (OC_Config->OCMode << 8);
elmot 1:d0dfbce63a89 5115
elmot 1:d0dfbce63a89 5116 /* Reset the Output Polarity level */
elmot 1:d0dfbce63a89 5117 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
elmot 1:d0dfbce63a89 5118 /* Set the Output Compare Polarity */
elmot 1:d0dfbce63a89 5119 tmpccer |= (OC_Config->OCPolarity << 20);
elmot 1:d0dfbce63a89 5120
elmot 1:d0dfbce63a89 5121 if(IS_TIM_BREAK_INSTANCE(TIMx))
elmot 1:d0dfbce63a89 5122 {
elmot 1:d0dfbce63a89 5123 /* Reset the Output Compare IDLE State */
elmot 1:d0dfbce63a89 5124 tmpcr2 &= ~TIM_CR2_OIS6;
elmot 1:d0dfbce63a89 5125 /* Set the Output Idle state */
elmot 1:d0dfbce63a89 5126 tmpcr2 |= (OC_Config->OCIdleState << 10);
elmot 1:d0dfbce63a89 5127 }
elmot 1:d0dfbce63a89 5128
elmot 1:d0dfbce63a89 5129 /* Write to TIMx CR2 */
elmot 1:d0dfbce63a89 5130 TIMx->CR2 = tmpcr2;
elmot 1:d0dfbce63a89 5131
elmot 1:d0dfbce63a89 5132 /* Write to TIMx CCMR3 */
elmot 1:d0dfbce63a89 5133 TIMx->CCMR3 = tmpccmrx;
elmot 1:d0dfbce63a89 5134
elmot 1:d0dfbce63a89 5135 /* Set the Capture Compare Register value */
elmot 1:d0dfbce63a89 5136 TIMx->CCR6 = OC_Config->Pulse;
elmot 1:d0dfbce63a89 5137
elmot 1:d0dfbce63a89 5138 /* Write to TIMx CCER */
elmot 1:d0dfbce63a89 5139 TIMx->CCER = tmpccer;
elmot 1:d0dfbce63a89 5140 }
elmot 1:d0dfbce63a89 5141
elmot 1:d0dfbce63a89 5142 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
elmot 1:d0dfbce63a89 5143 TIM_SlaveConfigTypeDef * sSlaveConfig)
elmot 1:d0dfbce63a89 5144 {
elmot 1:d0dfbce63a89 5145 uint32_t tmpsmcr = 0;
elmot 1:d0dfbce63a89 5146 uint32_t tmpccmr1 = 0;
elmot 1:d0dfbce63a89 5147 uint32_t tmpccer = 0;
elmot 1:d0dfbce63a89 5148
elmot 1:d0dfbce63a89 5149 /* Get the TIMx SMCR register value */
elmot 1:d0dfbce63a89 5150 tmpsmcr = htim->Instance->SMCR;
elmot 1:d0dfbce63a89 5151
elmot 1:d0dfbce63a89 5152 /* Reset the Trigger Selection Bits */
elmot 1:d0dfbce63a89 5153 tmpsmcr &= ~TIM_SMCR_TS;
elmot 1:d0dfbce63a89 5154 /* Set the Input Trigger source */
elmot 1:d0dfbce63a89 5155 tmpsmcr |= sSlaveConfig->InputTrigger;
elmot 1:d0dfbce63a89 5156
elmot 1:d0dfbce63a89 5157 /* Reset the slave mode Bits */
elmot 1:d0dfbce63a89 5158 tmpsmcr &= ~TIM_SMCR_SMS;
elmot 1:d0dfbce63a89 5159 /* Set the slave mode */
elmot 1:d0dfbce63a89 5160 tmpsmcr |= sSlaveConfig->SlaveMode;
elmot 1:d0dfbce63a89 5161
elmot 1:d0dfbce63a89 5162 /* Write to TIMx SMCR */
elmot 1:d0dfbce63a89 5163 htim->Instance->SMCR = tmpsmcr;
elmot 1:d0dfbce63a89 5164
elmot 1:d0dfbce63a89 5165 /* Configure the trigger prescaler, filter, and polarity */
elmot 1:d0dfbce63a89 5166 switch (sSlaveConfig->InputTrigger)
elmot 1:d0dfbce63a89 5167 {
elmot 1:d0dfbce63a89 5168 case TIM_TS_ETRF:
elmot 1:d0dfbce63a89 5169 {
elmot 1:d0dfbce63a89 5170 /* Check the parameters */
elmot 1:d0dfbce63a89 5171 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 5172 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
elmot 1:d0dfbce63a89 5173 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
elmot 1:d0dfbce63a89 5174 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
elmot 1:d0dfbce63a89 5175 /* Configure the ETR Trigger source */
elmot 1:d0dfbce63a89 5176 TIM_ETR_SetConfig(htim->Instance,
elmot 1:d0dfbce63a89 5177 sSlaveConfig->TriggerPrescaler,
elmot 1:d0dfbce63a89 5178 sSlaveConfig->TriggerPolarity,
elmot 1:d0dfbce63a89 5179 sSlaveConfig->TriggerFilter);
elmot 1:d0dfbce63a89 5180 }
elmot 1:d0dfbce63a89 5181 break;
elmot 1:d0dfbce63a89 5182
elmot 1:d0dfbce63a89 5183 case TIM_TS_TI1F_ED:
elmot 1:d0dfbce63a89 5184 {
elmot 1:d0dfbce63a89 5185 /* Check the parameters */
elmot 1:d0dfbce63a89 5186 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 5187 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
elmot 1:d0dfbce63a89 5188
elmot 1:d0dfbce63a89 5189 /* Disable the Channel 1: Reset the CC1E Bit */
elmot 1:d0dfbce63a89 5190 tmpccer = htim->Instance->CCER;
elmot 1:d0dfbce63a89 5191 htim->Instance->CCER &= ~TIM_CCER_CC1E;
elmot 1:d0dfbce63a89 5192 tmpccmr1 = htim->Instance->CCMR1;
elmot 1:d0dfbce63a89 5193
elmot 1:d0dfbce63a89 5194 /* Set the filter */
elmot 1:d0dfbce63a89 5195 tmpccmr1 &= ~TIM_CCMR1_IC1F;
elmot 1:d0dfbce63a89 5196 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
elmot 1:d0dfbce63a89 5197
elmot 1:d0dfbce63a89 5198 /* Write to TIMx CCMR1 and CCER registers */
elmot 1:d0dfbce63a89 5199 htim->Instance->CCMR1 = tmpccmr1;
elmot 1:d0dfbce63a89 5200 htim->Instance->CCER = tmpccer;
elmot 1:d0dfbce63a89 5201
elmot 1:d0dfbce63a89 5202 }
elmot 1:d0dfbce63a89 5203 break;
elmot 1:d0dfbce63a89 5204
elmot 1:d0dfbce63a89 5205 case TIM_TS_TI1FP1:
elmot 1:d0dfbce63a89 5206 {
elmot 1:d0dfbce63a89 5207 /* Check the parameters */
elmot 1:d0dfbce63a89 5208 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 5209 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
elmot 1:d0dfbce63a89 5210 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
elmot 1:d0dfbce63a89 5211
elmot 1:d0dfbce63a89 5212 /* Configure TI1 Filter and Polarity */
elmot 1:d0dfbce63a89 5213 TIM_TI1_ConfigInputStage(htim->Instance,
elmot 1:d0dfbce63a89 5214 sSlaveConfig->TriggerPolarity,
elmot 1:d0dfbce63a89 5215 sSlaveConfig->TriggerFilter);
elmot 1:d0dfbce63a89 5216 }
elmot 1:d0dfbce63a89 5217 break;
elmot 1:d0dfbce63a89 5218
elmot 1:d0dfbce63a89 5219 case TIM_TS_TI2FP2:
elmot 1:d0dfbce63a89 5220 {
elmot 1:d0dfbce63a89 5221 /* Check the parameters */
elmot 1:d0dfbce63a89 5222 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 5223 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
elmot 1:d0dfbce63a89 5224 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
elmot 1:d0dfbce63a89 5225
elmot 1:d0dfbce63a89 5226 /* Configure TI2 Filter and Polarity */
elmot 1:d0dfbce63a89 5227 TIM_TI2_ConfigInputStage(htim->Instance,
elmot 1:d0dfbce63a89 5228 sSlaveConfig->TriggerPolarity,
elmot 1:d0dfbce63a89 5229 sSlaveConfig->TriggerFilter);
elmot 1:d0dfbce63a89 5230 }
elmot 1:d0dfbce63a89 5231 break;
elmot 1:d0dfbce63a89 5232
elmot 1:d0dfbce63a89 5233 case TIM_TS_ITR0:
elmot 1:d0dfbce63a89 5234 {
elmot 1:d0dfbce63a89 5235 /* Check the parameter */
elmot 1:d0dfbce63a89 5236 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 5237 }
elmot 1:d0dfbce63a89 5238 break;
elmot 1:d0dfbce63a89 5239
elmot 1:d0dfbce63a89 5240 case TIM_TS_ITR1:
elmot 1:d0dfbce63a89 5241 {
elmot 1:d0dfbce63a89 5242 /* Check the parameter */
elmot 1:d0dfbce63a89 5243 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 5244 }
elmot 1:d0dfbce63a89 5245 break;
elmot 1:d0dfbce63a89 5246
elmot 1:d0dfbce63a89 5247 case TIM_TS_ITR2:
elmot 1:d0dfbce63a89 5248 {
elmot 1:d0dfbce63a89 5249 /* Check the parameter */
elmot 1:d0dfbce63a89 5250 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 5251 }
elmot 1:d0dfbce63a89 5252 break;
elmot 1:d0dfbce63a89 5253
elmot 1:d0dfbce63a89 5254 case TIM_TS_ITR3:
elmot 1:d0dfbce63a89 5255 {
elmot 1:d0dfbce63a89 5256 /* Check the parameter */
elmot 1:d0dfbce63a89 5257 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elmot 1:d0dfbce63a89 5258 }
elmot 1:d0dfbce63a89 5259 break;
elmot 1:d0dfbce63a89 5260
elmot 1:d0dfbce63a89 5261 default:
elmot 1:d0dfbce63a89 5262 break;
elmot 1:d0dfbce63a89 5263 }
elmot 1:d0dfbce63a89 5264 }
elmot 1:d0dfbce63a89 5265
elmot 1:d0dfbce63a89 5266 /**
elmot 1:d0dfbce63a89 5267 * @brief Configure the TI1 as Input.
elmot 1:d0dfbce63a89 5268 * @param TIMx to select the TIM peripheral.
elmot 1:d0dfbce63a89 5269 * @param TIM_ICPolarity : The Input Polarity.
elmot 1:d0dfbce63a89 5270 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 5271 * @arg TIM_ICPolarity_Rising
elmot 1:d0dfbce63a89 5272 * @arg TIM_ICPolarity_Falling
elmot 1:d0dfbce63a89 5273 * @arg TIM_ICPolarity_BothEdge
elmot 1:d0dfbce63a89 5274 * @param TIM_ICSelection: specifies the input to be used.
elmot 1:d0dfbce63a89 5275 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 5276 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
elmot 1:d0dfbce63a89 5277 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
elmot 1:d0dfbce63a89 5278 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
elmot 1:d0dfbce63a89 5279 * @param TIM_ICFilter: Specifies the Input Capture Filter.
elmot 1:d0dfbce63a89 5280 * This parameter must be a value between 0x00 and 0x0F.
elmot 1:d0dfbce63a89 5281 * @retval None
elmot 1:d0dfbce63a89 5282 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
elmot 1:d0dfbce63a89 5283 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
elmot 1:d0dfbce63a89 5284 * protected against un-initialized filter and polarity values.
elmot 1:d0dfbce63a89 5285 */
elmot 1:d0dfbce63a89 5286 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
elmot 1:d0dfbce63a89 5287 uint32_t TIM_ICFilter)
elmot 1:d0dfbce63a89 5288 {
elmot 1:d0dfbce63a89 5289 uint32_t tmpccmr1 = 0;
elmot 1:d0dfbce63a89 5290 uint32_t tmpccer = 0;
elmot 1:d0dfbce63a89 5291
elmot 1:d0dfbce63a89 5292 /* Disable the Channel 1: Reset the CC1E Bit */
elmot 1:d0dfbce63a89 5293 TIMx->CCER &= ~TIM_CCER_CC1E;
elmot 1:d0dfbce63a89 5294 tmpccmr1 = TIMx->CCMR1;
elmot 1:d0dfbce63a89 5295 tmpccer = TIMx->CCER;
elmot 1:d0dfbce63a89 5296
elmot 1:d0dfbce63a89 5297 /* Select the Input */
elmot 1:d0dfbce63a89 5298 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
elmot 1:d0dfbce63a89 5299 {
elmot 1:d0dfbce63a89 5300 tmpccmr1 &= ~TIM_CCMR1_CC1S;
elmot 1:d0dfbce63a89 5301 tmpccmr1 |= TIM_ICSelection;
elmot 1:d0dfbce63a89 5302 }
elmot 1:d0dfbce63a89 5303 else
elmot 1:d0dfbce63a89 5304 {
elmot 1:d0dfbce63a89 5305 tmpccmr1 |= TIM_CCMR1_CC1S_0;
elmot 1:d0dfbce63a89 5306 }
elmot 1:d0dfbce63a89 5307
elmot 1:d0dfbce63a89 5308 /* Set the filter */
elmot 1:d0dfbce63a89 5309 tmpccmr1 &= ~TIM_CCMR1_IC1F;
elmot 1:d0dfbce63a89 5310 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
elmot 1:d0dfbce63a89 5311
elmot 1:d0dfbce63a89 5312 /* Select the Polarity and set the CC1E Bit */
elmot 1:d0dfbce63a89 5313 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
elmot 1:d0dfbce63a89 5314 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
elmot 1:d0dfbce63a89 5315
elmot 1:d0dfbce63a89 5316 /* Write to TIMx CCMR1 and CCER registers */
elmot 1:d0dfbce63a89 5317 TIMx->CCMR1 = tmpccmr1;
elmot 1:d0dfbce63a89 5318 TIMx->CCER = tmpccer;
elmot 1:d0dfbce63a89 5319 }
elmot 1:d0dfbce63a89 5320
elmot 1:d0dfbce63a89 5321 /**
elmot 1:d0dfbce63a89 5322 * @brief Configure the Polarity and Filter for TI1.
elmot 1:d0dfbce63a89 5323 * @param TIMx to select the TIM peripheral.
elmot 1:d0dfbce63a89 5324 * @param TIM_ICPolarity : The Input Polarity.
elmot 1:d0dfbce63a89 5325 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 5326 * @arg TIM_ICPolarity_Rising
elmot 1:d0dfbce63a89 5327 * @arg TIM_ICPolarity_Falling
elmot 1:d0dfbce63a89 5328 * @arg TIM_ICPolarity_BothEdge
elmot 1:d0dfbce63a89 5329 * @param TIM_ICFilter: Specifies the Input Capture Filter.
elmot 1:d0dfbce63a89 5330 * This parameter must be a value between 0x00 and 0x0F.
elmot 1:d0dfbce63a89 5331 * @retval None
elmot 1:d0dfbce63a89 5332 */
elmot 1:d0dfbce63a89 5333 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
elmot 1:d0dfbce63a89 5334 {
elmot 1:d0dfbce63a89 5335 uint32_t tmpccmr1 = 0;
elmot 1:d0dfbce63a89 5336 uint32_t tmpccer = 0;
elmot 1:d0dfbce63a89 5337
elmot 1:d0dfbce63a89 5338 /* Disable the Channel 1: Reset the CC1E Bit */
elmot 1:d0dfbce63a89 5339 tmpccer = TIMx->CCER;
elmot 1:d0dfbce63a89 5340 TIMx->CCER &= ~TIM_CCER_CC1E;
elmot 1:d0dfbce63a89 5341 tmpccmr1 = TIMx->CCMR1;
elmot 1:d0dfbce63a89 5342
elmot 1:d0dfbce63a89 5343 /* Set the filter */
elmot 1:d0dfbce63a89 5344 tmpccmr1 &= ~TIM_CCMR1_IC1F;
elmot 1:d0dfbce63a89 5345 tmpccmr1 |= (TIM_ICFilter << 4);
elmot 1:d0dfbce63a89 5346
elmot 1:d0dfbce63a89 5347 /* Select the Polarity and set the CC1E Bit */
elmot 1:d0dfbce63a89 5348 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
elmot 1:d0dfbce63a89 5349 tmpccer |= TIM_ICPolarity;
elmot 1:d0dfbce63a89 5350
elmot 1:d0dfbce63a89 5351 /* Write to TIMx CCMR1 and CCER registers */
elmot 1:d0dfbce63a89 5352 TIMx->CCMR1 = tmpccmr1;
elmot 1:d0dfbce63a89 5353 TIMx->CCER = tmpccer;
elmot 1:d0dfbce63a89 5354 }
elmot 1:d0dfbce63a89 5355
elmot 1:d0dfbce63a89 5356 /**
elmot 1:d0dfbce63a89 5357 * @brief Configure the TI2 as Input.
elmot 1:d0dfbce63a89 5358 * @param TIMx to select the TIM peripheral
elmot 1:d0dfbce63a89 5359 * @param TIM_ICPolarity : The Input Polarity.
elmot 1:d0dfbce63a89 5360 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 5361 * @arg TIM_ICPolarity_Rising
elmot 1:d0dfbce63a89 5362 * @arg TIM_ICPolarity_Falling
elmot 1:d0dfbce63a89 5363 * @arg TIM_ICPolarity_BothEdge
elmot 1:d0dfbce63a89 5364 * @param TIM_ICSelection: specifies the input to be used.
elmot 1:d0dfbce63a89 5365 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 5366 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
elmot 1:d0dfbce63a89 5367 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
elmot 1:d0dfbce63a89 5368 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
elmot 1:d0dfbce63a89 5369 * @param TIM_ICFilter: Specifies the Input Capture Filter.
elmot 1:d0dfbce63a89 5370 * This parameter must be a value between 0x00 and 0x0F.
elmot 1:d0dfbce63a89 5371 * @retval None
elmot 1:d0dfbce63a89 5372 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
elmot 1:d0dfbce63a89 5373 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
elmot 1:d0dfbce63a89 5374 * protected against un-initialized filter and polarity values.
elmot 1:d0dfbce63a89 5375 */
elmot 1:d0dfbce63a89 5376 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
elmot 1:d0dfbce63a89 5377 uint32_t TIM_ICFilter)
elmot 1:d0dfbce63a89 5378 {
elmot 1:d0dfbce63a89 5379 uint32_t tmpccmr1 = 0;
elmot 1:d0dfbce63a89 5380 uint32_t tmpccer = 0;
elmot 1:d0dfbce63a89 5381
elmot 1:d0dfbce63a89 5382 /* Disable the Channel 2: Reset the CC2E Bit */
elmot 1:d0dfbce63a89 5383 TIMx->CCER &= ~TIM_CCER_CC2E;
elmot 1:d0dfbce63a89 5384 tmpccmr1 = TIMx->CCMR1;
elmot 1:d0dfbce63a89 5385 tmpccer = TIMx->CCER;
elmot 1:d0dfbce63a89 5386
elmot 1:d0dfbce63a89 5387 /* Select the Input */
elmot 1:d0dfbce63a89 5388 tmpccmr1 &= ~TIM_CCMR1_CC2S;
elmot 1:d0dfbce63a89 5389 tmpccmr1 |= (TIM_ICSelection << 8);
elmot 1:d0dfbce63a89 5390
elmot 1:d0dfbce63a89 5391 /* Set the filter */
elmot 1:d0dfbce63a89 5392 tmpccmr1 &= ~TIM_CCMR1_IC2F;
elmot 1:d0dfbce63a89 5393 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
elmot 1:d0dfbce63a89 5394
elmot 1:d0dfbce63a89 5395 /* Select the Polarity and set the CC2E Bit */
elmot 1:d0dfbce63a89 5396 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
elmot 1:d0dfbce63a89 5397 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
elmot 1:d0dfbce63a89 5398
elmot 1:d0dfbce63a89 5399 /* Write to TIMx CCMR1 and CCER registers */
elmot 1:d0dfbce63a89 5400 TIMx->CCMR1 = tmpccmr1 ;
elmot 1:d0dfbce63a89 5401 TIMx->CCER = tmpccer;
elmot 1:d0dfbce63a89 5402 }
elmot 1:d0dfbce63a89 5403
elmot 1:d0dfbce63a89 5404 /**
elmot 1:d0dfbce63a89 5405 * @brief Configure the Polarity and Filter for TI2.
elmot 1:d0dfbce63a89 5406 * @param TIMx to select the TIM peripheral.
elmot 1:d0dfbce63a89 5407 * @param TIM_ICPolarity : The Input Polarity.
elmot 1:d0dfbce63a89 5408 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 5409 * @arg TIM_ICPolarity_Rising
elmot 1:d0dfbce63a89 5410 * @arg TIM_ICPolarity_Falling
elmot 1:d0dfbce63a89 5411 * @arg TIM_ICPolarity_BothEdge
elmot 1:d0dfbce63a89 5412 * @param TIM_ICFilter: Specifies the Input Capture Filter.
elmot 1:d0dfbce63a89 5413 * This parameter must be a value between 0x00 and 0x0F.
elmot 1:d0dfbce63a89 5414 * @retval None
elmot 1:d0dfbce63a89 5415 */
elmot 1:d0dfbce63a89 5416 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
elmot 1:d0dfbce63a89 5417 {
elmot 1:d0dfbce63a89 5418 uint32_t tmpccmr1 = 0;
elmot 1:d0dfbce63a89 5419 uint32_t tmpccer = 0;
elmot 1:d0dfbce63a89 5420
elmot 1:d0dfbce63a89 5421 /* Disable the Channel 2: Reset the CC2E Bit */
elmot 1:d0dfbce63a89 5422 TIMx->CCER &= ~TIM_CCER_CC2E;
elmot 1:d0dfbce63a89 5423 tmpccmr1 = TIMx->CCMR1;
elmot 1:d0dfbce63a89 5424 tmpccer = TIMx->CCER;
elmot 1:d0dfbce63a89 5425
elmot 1:d0dfbce63a89 5426 /* Set the filter */
elmot 1:d0dfbce63a89 5427 tmpccmr1 &= ~TIM_CCMR1_IC2F;
elmot 1:d0dfbce63a89 5428 tmpccmr1 |= (TIM_ICFilter << 12);
elmot 1:d0dfbce63a89 5429
elmot 1:d0dfbce63a89 5430 /* Select the Polarity and set the CC2E Bit */
elmot 1:d0dfbce63a89 5431 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
elmot 1:d0dfbce63a89 5432 tmpccer |= (TIM_ICPolarity << 4);
elmot 1:d0dfbce63a89 5433
elmot 1:d0dfbce63a89 5434 /* Write to TIMx CCMR1 and CCER registers */
elmot 1:d0dfbce63a89 5435 TIMx->CCMR1 = tmpccmr1 ;
elmot 1:d0dfbce63a89 5436 TIMx->CCER = tmpccer;
elmot 1:d0dfbce63a89 5437 }
elmot 1:d0dfbce63a89 5438
elmot 1:d0dfbce63a89 5439 /**
elmot 1:d0dfbce63a89 5440 * @brief Configure the TI3 as Input.
elmot 1:d0dfbce63a89 5441 * @param TIMx to select the TIM peripheral
elmot 1:d0dfbce63a89 5442 * @param TIM_ICPolarity : The Input Polarity.
elmot 1:d0dfbce63a89 5443 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 5444 * @arg TIM_ICPolarity_Rising
elmot 1:d0dfbce63a89 5445 * @arg TIM_ICPolarity_Falling
elmot 1:d0dfbce63a89 5446 * @arg TIM_ICPolarity_BothEdge
elmot 1:d0dfbce63a89 5447 * @param TIM_ICSelection: specifies the input to be used.
elmot 1:d0dfbce63a89 5448 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 5449 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
elmot 1:d0dfbce63a89 5450 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
elmot 1:d0dfbce63a89 5451 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
elmot 1:d0dfbce63a89 5452 * @param TIM_ICFilter: Specifies the Input Capture Filter.
elmot 1:d0dfbce63a89 5453 * This parameter must be a value between 0x00 and 0x0F.
elmot 1:d0dfbce63a89 5454 * @retval None
elmot 1:d0dfbce63a89 5455 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
elmot 1:d0dfbce63a89 5456 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
elmot 1:d0dfbce63a89 5457 * protected against un-initialized filter and polarity values.
elmot 1:d0dfbce63a89 5458 */
elmot 1:d0dfbce63a89 5459 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
elmot 1:d0dfbce63a89 5460 uint32_t TIM_ICFilter)
elmot 1:d0dfbce63a89 5461 {
elmot 1:d0dfbce63a89 5462 uint32_t tmpccmr2 = 0;
elmot 1:d0dfbce63a89 5463 uint32_t tmpccer = 0;
elmot 1:d0dfbce63a89 5464
elmot 1:d0dfbce63a89 5465 /* Disable the Channel 3: Reset the CC3E Bit */
elmot 1:d0dfbce63a89 5466 TIMx->CCER &= ~TIM_CCER_CC3E;
elmot 1:d0dfbce63a89 5467 tmpccmr2 = TIMx->CCMR2;
elmot 1:d0dfbce63a89 5468 tmpccer = TIMx->CCER;
elmot 1:d0dfbce63a89 5469
elmot 1:d0dfbce63a89 5470 /* Select the Input */
elmot 1:d0dfbce63a89 5471 tmpccmr2 &= ~TIM_CCMR2_CC3S;
elmot 1:d0dfbce63a89 5472 tmpccmr2 |= TIM_ICSelection;
elmot 1:d0dfbce63a89 5473
elmot 1:d0dfbce63a89 5474 /* Set the filter */
elmot 1:d0dfbce63a89 5475 tmpccmr2 &= ~TIM_CCMR2_IC3F;
elmot 1:d0dfbce63a89 5476 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
elmot 1:d0dfbce63a89 5477
elmot 1:d0dfbce63a89 5478 /* Select the Polarity and set the CC3E Bit */
elmot 1:d0dfbce63a89 5479 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
elmot 1:d0dfbce63a89 5480 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
elmot 1:d0dfbce63a89 5481
elmot 1:d0dfbce63a89 5482 /* Write to TIMx CCMR2 and CCER registers */
elmot 1:d0dfbce63a89 5483 TIMx->CCMR2 = tmpccmr2;
elmot 1:d0dfbce63a89 5484 TIMx->CCER = tmpccer;
elmot 1:d0dfbce63a89 5485 }
elmot 1:d0dfbce63a89 5486
elmot 1:d0dfbce63a89 5487 /**
elmot 1:d0dfbce63a89 5488 * @brief Configure the TI4 as Input.
elmot 1:d0dfbce63a89 5489 * @param TIMx to select the TIM peripheral
elmot 1:d0dfbce63a89 5490 * @param TIM_ICPolarity : The Input Polarity.
elmot 1:d0dfbce63a89 5491 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 5492 * @arg TIM_ICPolarity_Rising
elmot 1:d0dfbce63a89 5493 * @arg TIM_ICPolarity_Falling
elmot 1:d0dfbce63a89 5494 * @arg TIM_ICPolarity_BothEdge
elmot 1:d0dfbce63a89 5495 * @param TIM_ICSelection: specifies the input to be used.
elmot 1:d0dfbce63a89 5496 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 5497 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
elmot 1:d0dfbce63a89 5498 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
elmot 1:d0dfbce63a89 5499 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
elmot 1:d0dfbce63a89 5500 * @param TIM_ICFilter: Specifies the Input Capture Filter.
elmot 1:d0dfbce63a89 5501 * This parameter must be a value between 0x00 and 0x0F.
elmot 1:d0dfbce63a89 5502 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
elmot 1:d0dfbce63a89 5503 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
elmot 1:d0dfbce63a89 5504 * protected against un-initialized filter and polarity values.
elmot 1:d0dfbce63a89 5505 * @retval None
elmot 1:d0dfbce63a89 5506 */
elmot 1:d0dfbce63a89 5507 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
elmot 1:d0dfbce63a89 5508 uint32_t TIM_ICFilter)
elmot 1:d0dfbce63a89 5509 {
elmot 1:d0dfbce63a89 5510 uint32_t tmpccmr2 = 0;
elmot 1:d0dfbce63a89 5511 uint32_t tmpccer = 0;
elmot 1:d0dfbce63a89 5512
elmot 1:d0dfbce63a89 5513 /* Disable the Channel 4: Reset the CC4E Bit */
elmot 1:d0dfbce63a89 5514 TIMx->CCER &= ~TIM_CCER_CC4E;
elmot 1:d0dfbce63a89 5515 tmpccmr2 = TIMx->CCMR2;
elmot 1:d0dfbce63a89 5516 tmpccer = TIMx->CCER;
elmot 1:d0dfbce63a89 5517
elmot 1:d0dfbce63a89 5518 /* Select the Input */
elmot 1:d0dfbce63a89 5519 tmpccmr2 &= ~TIM_CCMR2_CC4S;
elmot 1:d0dfbce63a89 5520 tmpccmr2 |= (TIM_ICSelection << 8);
elmot 1:d0dfbce63a89 5521
elmot 1:d0dfbce63a89 5522 /* Set the filter */
elmot 1:d0dfbce63a89 5523 tmpccmr2 &= ~TIM_CCMR2_IC4F;
elmot 1:d0dfbce63a89 5524 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
elmot 1:d0dfbce63a89 5525
elmot 1:d0dfbce63a89 5526 /* Select the Polarity and set the CC4E Bit */
elmot 1:d0dfbce63a89 5527 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
elmot 1:d0dfbce63a89 5528 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
elmot 1:d0dfbce63a89 5529
elmot 1:d0dfbce63a89 5530 /* Write to TIMx CCMR2 and CCER registers */
elmot 1:d0dfbce63a89 5531 TIMx->CCMR2 = tmpccmr2;
elmot 1:d0dfbce63a89 5532 TIMx->CCER = tmpccer ;
elmot 1:d0dfbce63a89 5533 }
elmot 1:d0dfbce63a89 5534
elmot 1:d0dfbce63a89 5535 /**
elmot 1:d0dfbce63a89 5536 * @brief Selects the Input Trigger source
elmot 1:d0dfbce63a89 5537 * @param TIMx to select the TIM peripheral
elmot 1:d0dfbce63a89 5538 * @param InputTriggerSource: The Input Trigger source.
elmot 1:d0dfbce63a89 5539 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 5540 * @arg TIM_TS_ITR0: Internal Trigger 0
elmot 1:d0dfbce63a89 5541 * @arg TIM_TS_ITR1: Internal Trigger 1
elmot 1:d0dfbce63a89 5542 * @arg TIM_TS_ITR2: Internal Trigger 2
elmot 1:d0dfbce63a89 5543 * @arg TIM_TS_ITR3: Internal Trigger 3
elmot 1:d0dfbce63a89 5544 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
elmot 1:d0dfbce63a89 5545 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
elmot 1:d0dfbce63a89 5546 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
elmot 1:d0dfbce63a89 5547 * @arg TIM_TS_ETRF: External Trigger input
elmot 1:d0dfbce63a89 5548 * @retval None
elmot 1:d0dfbce63a89 5549 */
elmot 1:d0dfbce63a89 5550 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
elmot 1:d0dfbce63a89 5551 {
elmot 1:d0dfbce63a89 5552 uint32_t tmpsmcr = 0;
elmot 1:d0dfbce63a89 5553
elmot 1:d0dfbce63a89 5554 /* Get the TIMx SMCR register value */
elmot 1:d0dfbce63a89 5555 tmpsmcr = TIMx->SMCR;
elmot 1:d0dfbce63a89 5556 /* Reset the TS Bits */
elmot 1:d0dfbce63a89 5557 tmpsmcr &= ~TIM_SMCR_TS;
elmot 1:d0dfbce63a89 5558 /* Set the Input Trigger source and the slave mode*/
elmot 1:d0dfbce63a89 5559 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
elmot 1:d0dfbce63a89 5560 /* Write to TIMx SMCR */
elmot 1:d0dfbce63a89 5561 TIMx->SMCR = tmpsmcr;
elmot 1:d0dfbce63a89 5562 }
elmot 1:d0dfbce63a89 5563 /**
elmot 1:d0dfbce63a89 5564 * @brief Configures the TIMx External Trigger (ETR).
elmot 1:d0dfbce63a89 5565 * @param TIMx to select the TIM peripheral
elmot 1:d0dfbce63a89 5566 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
elmot 1:d0dfbce63a89 5567 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 5568 * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
elmot 1:d0dfbce63a89 5569 * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
elmot 1:d0dfbce63a89 5570 * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
elmot 1:d0dfbce63a89 5571 * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
elmot 1:d0dfbce63a89 5572 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
elmot 1:d0dfbce63a89 5573 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 5574 * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
elmot 1:d0dfbce63a89 5575 * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
elmot 1:d0dfbce63a89 5576 * @param ExtTRGFilter: External Trigger Filter.
elmot 1:d0dfbce63a89 5577 * This parameter must be a value between 0x00 and 0x0F
elmot 1:d0dfbce63a89 5578 * @retval None
elmot 1:d0dfbce63a89 5579 */
elmot 1:d0dfbce63a89 5580 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
elmot 1:d0dfbce63a89 5581 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
elmot 1:d0dfbce63a89 5582 {
elmot 1:d0dfbce63a89 5583 uint32_t tmpsmcr = 0;
elmot 1:d0dfbce63a89 5584
elmot 1:d0dfbce63a89 5585 tmpsmcr = TIMx->SMCR;
elmot 1:d0dfbce63a89 5586
elmot 1:d0dfbce63a89 5587 /* Reset the ETR Bits */
elmot 1:d0dfbce63a89 5588 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
elmot 1:d0dfbce63a89 5589
elmot 1:d0dfbce63a89 5590 /* Set the Prescaler, the Filter value and the Polarity */
elmot 1:d0dfbce63a89 5591 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
elmot 1:d0dfbce63a89 5592
elmot 1:d0dfbce63a89 5593 /* Write to TIMx SMCR */
elmot 1:d0dfbce63a89 5594 TIMx->SMCR = tmpsmcr;
elmot 1:d0dfbce63a89 5595 }
elmot 1:d0dfbce63a89 5596
elmot 1:d0dfbce63a89 5597 /**
elmot 1:d0dfbce63a89 5598 * @brief Enables or disables the TIM Capture Compare Channel x.
elmot 1:d0dfbce63a89 5599 * @param TIMx to select the TIM peripheral
elmot 1:d0dfbce63a89 5600 * @param Channel: specifies the TIM Channel
elmot 1:d0dfbce63a89 5601 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 5602 * @arg TIM_CHANNEL_1: TIM Channel 1
elmot 1:d0dfbce63a89 5603 * @arg TIM_CHANNEL_2: TIM Channel 2
elmot 1:d0dfbce63a89 5604 * @arg TIM_CHANNEL_3: TIM Channel 3
elmot 1:d0dfbce63a89 5605 * @arg TIM_CHANNEL_4: TIM Channel 4
elmot 1:d0dfbce63a89 5606 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
elmot 1:d0dfbce63a89 5607 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
elmot 1:d0dfbce63a89 5608 * @retval None
elmot 1:d0dfbce63a89 5609 */
elmot 1:d0dfbce63a89 5610 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
elmot 1:d0dfbce63a89 5611 {
elmot 1:d0dfbce63a89 5612 uint32_t tmp = 0;
elmot 1:d0dfbce63a89 5613
elmot 1:d0dfbce63a89 5614 /* Check the parameters */
elmot 1:d0dfbce63a89 5615 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
elmot 1:d0dfbce63a89 5616 assert_param(IS_TIM_CHANNELS(Channel));
elmot 1:d0dfbce63a89 5617
elmot 1:d0dfbce63a89 5618 tmp = TIM_CCER_CC1E << Channel;
elmot 1:d0dfbce63a89 5619
elmot 1:d0dfbce63a89 5620 /* Reset the CCxE Bit */
elmot 1:d0dfbce63a89 5621 TIMx->CCER &= ~tmp;
elmot 1:d0dfbce63a89 5622
elmot 1:d0dfbce63a89 5623 /* Set or reset the CCxE Bit */
elmot 1:d0dfbce63a89 5624 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
elmot 1:d0dfbce63a89 5625 }
elmot 1:d0dfbce63a89 5626
elmot 1:d0dfbce63a89 5627
elmot 1:d0dfbce63a89 5628 /**
elmot 1:d0dfbce63a89 5629 * @}
elmot 1:d0dfbce63a89 5630 */
elmot 1:d0dfbce63a89 5631
elmot 1:d0dfbce63a89 5632 #endif /* HAL_TIM_MODULE_ENABLED */
elmot 1:d0dfbce63a89 5633 /**
elmot 1:d0dfbce63a89 5634 * @}
elmot 1:d0dfbce63a89 5635 */
elmot 1:d0dfbce63a89 5636
elmot 1:d0dfbce63a89 5637 /**
elmot 1:d0dfbce63a89 5638 * @}
elmot 1:d0dfbce63a89 5639 */
elmot 1:d0dfbce63a89 5640 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/