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HAL_L476/stm32l4xx_hal_qspi.c@1:d0dfbce63a89, 2017-02-24 (annotated)

Committer:: elmot
Date:: Fri Feb 24 21:13:56 2017 +0000
Revision:: 1:d0dfbce63a89

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elmot	1:d0dfbce63a89	1	/**
elmot	1:d0dfbce63a89	2	******************************************************************************
elmot	1:d0dfbce63a89	3	* @file stm32l4xx_hal_qspi.c
elmot	1:d0dfbce63a89	4	* @author MCD Application Team
elmot	1:d0dfbce63a89	5	* @version V1.5.1
elmot	1:d0dfbce63a89	6	* @date 31-May-2016
elmot	1:d0dfbce63a89	7	* @brief QSPI HAL module driver.
elmot	1:d0dfbce63a89	8	* This file provides firmware functions to manage the following
elmot	1:d0dfbce63a89	9	* functionalities of the QuadSPI interface (QSPI).
elmot	1:d0dfbce63a89	10	* + Initialization and de-initialization functions
elmot	1:d0dfbce63a89	11	* + Indirect functional mode management
elmot	1:d0dfbce63a89	12	* + Memory-mapped functional mode management
elmot	1:d0dfbce63a89	13	* + Auto-polling functional mode management
elmot	1:d0dfbce63a89	14	* + Interrupts and flags management
elmot	1:d0dfbce63a89	15	* + DMA channel configuration for indirect functional mode
elmot	1:d0dfbce63a89	16	* + Errors management and abort functionality
elmot	1:d0dfbce63a89	17	*
elmot	1:d0dfbce63a89	18	*
elmot	1:d0dfbce63a89	19	@verbatim
elmot	1:d0dfbce63a89	20	===============================================================================
elmot	1:d0dfbce63a89	21	##### How to use this driver #####
elmot	1:d0dfbce63a89	22	===============================================================================
elmot	1:d0dfbce63a89	23	[..]
elmot	1:d0dfbce63a89	24	* Initialization *
elmot	1:d0dfbce63a89	25	======================
elmot	1:d0dfbce63a89	26	[..]
elmot	1:d0dfbce63a89	27	(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
elmot	1:d0dfbce63a89	28	(++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
elmot	1:d0dfbce63a89	29	(++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
elmot	1:d0dfbce63a89	30	(++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
elmot	1:d0dfbce63a89	31	(++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
elmot	1:d0dfbce63a89	32	(++) If interrupt mode is used, enable and configure QuadSPI global
elmot	1:d0dfbce63a89	33	interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
elmot	1:d0dfbce63a89	34	(++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
elmot	1:d0dfbce63a89	35	with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
elmot	1:d0dfbce63a89	36	link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
elmot	1:d0dfbce63a89	37	DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
elmot	1:d0dfbce63a89	38	(#) Configure the flash size, the clock prescaler, the fifo threshold, the
elmot	1:d0dfbce63a89	39	clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
elmot	1:d0dfbce63a89	40
elmot	1:d0dfbce63a89	41	* Indirect functional mode *
elmot	1:d0dfbce63a89	42	================================
elmot	1:d0dfbce63a89	43	[..]
elmot	1:d0dfbce63a89	44	(#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
elmot	1:d0dfbce63a89	45	functions :
elmot	1:d0dfbce63a89	46	(++) Instruction phase : the mode used and if present the instruction opcode.
elmot	1:d0dfbce63a89	47	(++) Address phase : the mode used and if present the size and the address value.
elmot	1:d0dfbce63a89	48	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
elmot	1:d0dfbce63a89	49	bytes values.
elmot	1:d0dfbce63a89	50	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
elmot	1:d0dfbce63a89	51	(++) Data phase : the mode used and if present the number of bytes.
elmot	1:d0dfbce63a89	52	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
elmot	1:d0dfbce63a89	53	if activated.
elmot	1:d0dfbce63a89	54	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
elmot	1:d0dfbce63a89	55	(#) If no data is required for the command, it is sent directly to the memory :
elmot	1:d0dfbce63a89	56	(++) In polling mode, the output of the function is done when the transfer is complete.
elmot	1:d0dfbce63a89	57	(++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
elmot	1:d0dfbce63a89	58	(#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
elmot	1:d0dfbce63a89	59	HAL_QSPI_Transmit_IT() after the command configuration :
elmot	1:d0dfbce63a89	60	(++) In polling mode, the output of the function is done when the transfer is complete.
elmot	1:d0dfbce63a89	61	(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
elmot	1:d0dfbce63a89	62	is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
elmot	1:d0dfbce63a89	63	(++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
elmot	1:d0dfbce63a89	64	HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
elmot	1:d0dfbce63a89	65	(#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
elmot	1:d0dfbce63a89	66	HAL_QSPI_Receive_IT() after the command configuration :
elmot	1:d0dfbce63a89	67	(++) In polling mode, the output of the function is done when the transfer is complete.
elmot	1:d0dfbce63a89	68	(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
elmot	1:d0dfbce63a89	69	is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
elmot	1:d0dfbce63a89	70	(++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
elmot	1:d0dfbce63a89	71	HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
elmot	1:d0dfbce63a89	72
elmot	1:d0dfbce63a89	73	* Auto-polling functional mode *
elmot	1:d0dfbce63a89	74	====================================
elmot	1:d0dfbce63a89	75	[..]
elmot	1:d0dfbce63a89	76	(#) Configure the command sequence and the auto-polling functional mode using the
elmot	1:d0dfbce63a89	77	HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
elmot	1:d0dfbce63a89	78	(++) Instruction phase : the mode used and if present the instruction opcode.
elmot	1:d0dfbce63a89	79	(++) Address phase : the mode used and if present the size and the address value.
elmot	1:d0dfbce63a89	80	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
elmot	1:d0dfbce63a89	81	bytes values.
elmot	1:d0dfbce63a89	82	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
elmot	1:d0dfbce63a89	83	(++) Data phase : the mode used.
elmot	1:d0dfbce63a89	84	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
elmot	1:d0dfbce63a89	85	if activated.
elmot	1:d0dfbce63a89	86	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
elmot	1:d0dfbce63a89	87	(++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
elmot	1:d0dfbce63a89	88	the polling interval and the automatic stop activation.
elmot	1:d0dfbce63a89	89	(#) After the configuration :
elmot	1:d0dfbce63a89	90	(++) In polling mode, the output of the function is done when the status match is reached. The
elmot	1:d0dfbce63a89	91	automatic stop is activated to avoid an infinite loop.
elmot	1:d0dfbce63a89	92	(++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
elmot	1:d0dfbce63a89	93
elmot	1:d0dfbce63a89	94	* Memory-mapped functional mode *
elmot	1:d0dfbce63a89	95	=====================================
elmot	1:d0dfbce63a89	96	[..]
elmot	1:d0dfbce63a89	97	(#) Configure the command sequence and the memory-mapped functional mode using the
elmot	1:d0dfbce63a89	98	HAL_QSPI_MemoryMapped() functions :
elmot	1:d0dfbce63a89	99	(++) Instruction phase : the mode used and if present the instruction opcode.
elmot	1:d0dfbce63a89	100	(++) Address phase : the mode used and the size.
elmot	1:d0dfbce63a89	101	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
elmot	1:d0dfbce63a89	102	bytes values.
elmot	1:d0dfbce63a89	103	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
elmot	1:d0dfbce63a89	104	(++) Data phase : the mode used.
elmot	1:d0dfbce63a89	105	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
elmot	1:d0dfbce63a89	106	if activated.
elmot	1:d0dfbce63a89	107	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
elmot	1:d0dfbce63a89	108	(++) The timeout activation and the timeout period.
elmot	1:d0dfbce63a89	109	(#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
elmot	1:d0dfbce63a89	110	the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
elmot	1:d0dfbce63a89	111
elmot	1:d0dfbce63a89	112	* Errors management and abort functionality *
elmot	1:d0dfbce63a89	113	=================================================
elmot	1:d0dfbce63a89	114	[..]
elmot	1:d0dfbce63a89	115	(#) HAL_QSPI_GetError() function gives the error raised during the last operation.
elmot	1:d0dfbce63a89	116	(#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
elmot	1:d0dfbce63a89	117	flushes the fifo :
elmot	1:d0dfbce63a89	118	(++) In polling mode, the output of the function is done when the transfer
elmot	1:d0dfbce63a89	119	complete bit is set and the busy bit cleared.
elmot	1:d0dfbce63a89	120	(++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
elmot	1:d0dfbce63a89	121	the transfer complete bi is set.
elmot	1:d0dfbce63a89	122
elmot	1:d0dfbce63a89	123	* Control functions *
elmot	1:d0dfbce63a89	124	=========================
elmot	1:d0dfbce63a89	125	[..]
elmot	1:d0dfbce63a89	126	(#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
elmot	1:d0dfbce63a89	127	(#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
elmot	1:d0dfbce63a89	128	(#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
elmot	1:d0dfbce63a89	129	(#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
elmot	1:d0dfbce63a89	130
elmot	1:d0dfbce63a89	131	* Workarounds linked to Silicon Limitation *
elmot	1:d0dfbce63a89	132	====================================================
elmot	1:d0dfbce63a89	133	[..]
elmot	1:d0dfbce63a89	134	(#) Workarounds Implemented inside HAL Driver
elmot	1:d0dfbce63a89	135	(++) Extra data written in the FIFO at the end of a read transfer
elmot	1:d0dfbce63a89	136
elmot	1:d0dfbce63a89	137	@endverbatim
elmot	1:d0dfbce63a89	138	******************************************************************************
elmot	1:d0dfbce63a89	139	* @attention
elmot	1:d0dfbce63a89	140	*
elmot	1:d0dfbce63a89	141	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
elmot	1:d0dfbce63a89	142	*
elmot	1:d0dfbce63a89	143	* Redistribution and use in source and binary forms, with or without modification,
elmot	1:d0dfbce63a89	144	* are permitted provided that the following conditions are met:
elmot	1:d0dfbce63a89	145	* 1. Redistributions of source code must retain the above copyright notice,
elmot	1:d0dfbce63a89	146	* this list of conditions and the following disclaimer.
elmot	1:d0dfbce63a89	147	* 2. Redistributions in binary form must reproduce the above copyright notice,
elmot	1:d0dfbce63a89	148	* this list of conditions and the following disclaimer in the documentation
elmot	1:d0dfbce63a89	149	* and/or other materials provided with the distribution.
elmot	1:d0dfbce63a89	150	* 3. Neither the name of STMicroelectronics nor the names of its contributors
elmot	1:d0dfbce63a89	151	* may be used to endorse or promote products derived from this software
elmot	1:d0dfbce63a89	152	* without specific prior written permission.
elmot	1:d0dfbce63a89	153	*
elmot	1:d0dfbce63a89	154	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elmot	1:d0dfbce63a89	155	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elmot	1:d0dfbce63a89	156	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elmot	1:d0dfbce63a89	157	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
elmot	1:d0dfbce63a89	158	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
elmot	1:d0dfbce63a89	159	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
elmot	1:d0dfbce63a89	160	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
elmot	1:d0dfbce63a89	161	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
elmot	1:d0dfbce63a89	162	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
elmot	1:d0dfbce63a89	163	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elmot	1:d0dfbce63a89	164	*
elmot	1:d0dfbce63a89	165	******************************************************************************
elmot	1:d0dfbce63a89	166	*/
elmot	1:d0dfbce63a89	167
elmot	1:d0dfbce63a89	168	/* Includes ------------------------------------------------------------------*/
elmot	1:d0dfbce63a89	169	#include "stm32l4xx_hal.h"
elmot	1:d0dfbce63a89	170
elmot	1:d0dfbce63a89	171	/** @addtogroup STM32L4xx_HAL_Driver
elmot	1:d0dfbce63a89	172	* @{
elmot	1:d0dfbce63a89	173	*/
elmot	1:d0dfbce63a89	174
elmot	1:d0dfbce63a89	175	/** @defgroup QSPI QSPI
elmot	1:d0dfbce63a89	176	* @brief QSPI HAL module driver
elmot	1:d0dfbce63a89	177	* @{
elmot	1:d0dfbce63a89	178	*/
elmot	1:d0dfbce63a89	179	#ifdef HAL_QSPI_MODULE_ENABLED
elmot	1:d0dfbce63a89	180
elmot	1:d0dfbce63a89	181	/* Private typedef -----------------------------------------------------------*/
elmot	1:d0dfbce63a89	182
elmot	1:d0dfbce63a89	183	/* Private define ------------------------------------------------------------*/
elmot	1:d0dfbce63a89	184	/** @defgroup QSPI_Private_Constants QSPI Private Constants
elmot	1:d0dfbce63a89	185	* @{
elmot	1:d0dfbce63a89	186	*/
elmot	1:d0dfbce63a89	187	#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /!<Indirect write mode/
elmot	1:d0dfbce63a89	188	#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /!<Indirect read mode/
elmot	1:d0dfbce63a89	189	#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /!<Automatic polling mode/
elmot	1:d0dfbce63a89	190	#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /!<Memory-mapped mode/
elmot	1:d0dfbce63a89	191	/**
elmot	1:d0dfbce63a89	192	* @}
elmot	1:d0dfbce63a89	193	*/
elmot	1:d0dfbce63a89	194
elmot	1:d0dfbce63a89	195	/* Private macro -------------------------------------------------------------*/
elmot	1:d0dfbce63a89	196	/** @defgroup QSPI_Private_Macros QSPI Private Macros
elmot	1:d0dfbce63a89	197	* @{
elmot	1:d0dfbce63a89	198	*/
elmot	1:d0dfbce63a89	199	#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) \|\| \
elmot	1:d0dfbce63a89	200	((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) \|\| \
elmot	1:d0dfbce63a89	201	((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) \|\| \
elmot	1:d0dfbce63a89	202	((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
elmot	1:d0dfbce63a89	203	/**
elmot	1:d0dfbce63a89	204	* @}
elmot	1:d0dfbce63a89	205	*/
elmot	1:d0dfbce63a89	206
elmot	1:d0dfbce63a89	207	/* Private variables ---------------------------------------------------------*/
elmot	1:d0dfbce63a89	208
elmot	1:d0dfbce63a89	209	/* Private function prototypes -----------------------------------------------*/
elmot	1:d0dfbce63a89	210	static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
elmot	1:d0dfbce63a89	211	static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
elmot	1:d0dfbce63a89	212	static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
elmot	1:d0dfbce63a89	213	static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
elmot	1:d0dfbce63a89	214	static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
elmot	1:d0dfbce63a89	215	static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
elmot	1:d0dfbce63a89	216	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);
elmot	1:d0dfbce63a89	217	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode);
elmot	1:d0dfbce63a89	218
elmot	1:d0dfbce63a89	219	/* Exported functions --------------------------------------------------------*/
elmot	1:d0dfbce63a89	220
elmot	1:d0dfbce63a89	221	/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
elmot	1:d0dfbce63a89	222	* @{
elmot	1:d0dfbce63a89	223	*/
elmot	1:d0dfbce63a89	224
elmot	1:d0dfbce63a89	225	/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
elmot	1:d0dfbce63a89	226	* @brief Initialization and Configuration functions
elmot	1:d0dfbce63a89	227	*
elmot	1:d0dfbce63a89	228	@verbatim
elmot	1:d0dfbce63a89	229	===============================================================================
elmot	1:d0dfbce63a89	230	##### Initialization and Configuration functions #####
elmot	1:d0dfbce63a89	231	===============================================================================
elmot	1:d0dfbce63a89	232	[..]
elmot	1:d0dfbce63a89	233	This subsection provides a set of functions allowing to :
elmot	1:d0dfbce63a89	234	(+) Initialize the QuadSPI.
elmot	1:d0dfbce63a89	235	(+) De-initialize the QuadSPI.
elmot	1:d0dfbce63a89	236
elmot	1:d0dfbce63a89	237	@endverbatim
elmot	1:d0dfbce63a89	238	* @{
elmot	1:d0dfbce63a89	239	*/
elmot	1:d0dfbce63a89	240
elmot	1:d0dfbce63a89	241	/**
elmot	1:d0dfbce63a89	242	* @brief Initialize the QSPI mode according to the specified parameters
elmot	1:d0dfbce63a89	243	* in the QSPI_InitTypeDef and initialize the associated handle.
elmot	1:d0dfbce63a89	244	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	245	* @retval HAL status
elmot	1:d0dfbce63a89	246	*/
elmot	1:d0dfbce63a89	247	HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	248	{
elmot	1:d0dfbce63a89	249	HAL_StatusTypeDef status = HAL_ERROR;
elmot	1:d0dfbce63a89	250	uint32_t tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	251
elmot	1:d0dfbce63a89	252	/* Check the QSPI handle allocation */
elmot	1:d0dfbce63a89	253	if(hqspi == NULL)
elmot	1:d0dfbce63a89	254	{
elmot	1:d0dfbce63a89	255	return HAL_ERROR;
elmot	1:d0dfbce63a89	256	}
elmot	1:d0dfbce63a89	257
elmot	1:d0dfbce63a89	258	/* Check the parameters */
elmot	1:d0dfbce63a89	259	assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
elmot	1:d0dfbce63a89	260	assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
elmot	1:d0dfbce63a89	261	assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
elmot	1:d0dfbce63a89	262	assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
elmot	1:d0dfbce63a89	263	assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
elmot	1:d0dfbce63a89	264	assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
elmot	1:d0dfbce63a89	265	assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
elmot	1:d0dfbce63a89	266	#if defined(STM32L431xx) \|\| defined(STM32L432xx) \|\| defined(STM32L433xx) \|\| defined(STM32L442xx) \|\| defined(STM32L443xx)
elmot	1:d0dfbce63a89	267	assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
elmot	1:d0dfbce63a89	268
elmot	1:d0dfbce63a89	269	if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
elmot	1:d0dfbce63a89	270	{
elmot	1:d0dfbce63a89	271	assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
elmot	1:d0dfbce63a89	272	}
elmot	1:d0dfbce63a89	273	#endif
elmot	1:d0dfbce63a89	274
elmot	1:d0dfbce63a89	275	/* Process locked */
elmot	1:d0dfbce63a89	276	__HAL_LOCK(hqspi);
elmot	1:d0dfbce63a89	277
elmot	1:d0dfbce63a89	278	if(hqspi->State == HAL_QSPI_STATE_RESET)
elmot	1:d0dfbce63a89	279	{
elmot	1:d0dfbce63a89	280	/* Allocate lock resource and initialize it */
elmot	1:d0dfbce63a89	281	hqspi->Lock = HAL_UNLOCKED;
elmot	1:d0dfbce63a89	282
elmot	1:d0dfbce63a89	283	/* Init the low level hardware : GPIO, CLOCK */
elmot	1:d0dfbce63a89	284	HAL_QSPI_MspInit(hqspi);
elmot	1:d0dfbce63a89	285
elmot	1:d0dfbce63a89	286	/* Configure the default timeout for the QSPI memory access */
elmot	1:d0dfbce63a89	287	HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
elmot	1:d0dfbce63a89	288	}
elmot	1:d0dfbce63a89	289
elmot	1:d0dfbce63a89	290	/* Configure QSPI FIFO Threshold */
elmot	1:d0dfbce63a89	291	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
elmot	1:d0dfbce63a89	292	((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
elmot	1:d0dfbce63a89	293
elmot	1:d0dfbce63a89	294	/* Wait till BUSY flag reset */
elmot	1:d0dfbce63a89	295	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
elmot	1:d0dfbce63a89	296
elmot	1:d0dfbce63a89	297	if(status == HAL_OK)
elmot	1:d0dfbce63a89	298	{
elmot	1:d0dfbce63a89	299	/* Configure QSPI Clock Prescaler and Sample Shift */
elmot	1:d0dfbce63a89	300	#if defined(STM32L431xx) \|\| defined(STM32L432xx) \|\| defined(STM32L433xx) \|\| defined(STM32L442xx) \|\| defined(STM32L443xx)
elmot	1:d0dfbce63a89	301	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER \| QUADSPI_CR_SSHIFT \| QUADSPI_CR_FSEL \| QUADSPI_CR_DFM),
elmot	1:d0dfbce63a89	302	((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) \|
elmot	1:d0dfbce63a89	303	hqspi->Init.SampleShifting \| hqspi->Init.FlashID \| hqspi->Init.DualFlash));
elmot	1:d0dfbce63a89	304	#else
elmot	1:d0dfbce63a89	305	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER \| QUADSPI_CR_SSHIFT),
elmot	1:d0dfbce63a89	306	((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) \|
elmot	1:d0dfbce63a89	307	hqspi->Init.SampleShifting));
elmot	1:d0dfbce63a89	308	#endif
elmot	1:d0dfbce63a89	309
elmot	1:d0dfbce63a89	310	/* Configure QSPI Flash Size, CS High Time and Clock Mode */
elmot	1:d0dfbce63a89	311	MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE \| QUADSPI_DCR_CSHT \| QUADSPI_DCR_CKMODE),
elmot	1:d0dfbce63a89	312	((hqspi->Init.FlashSize << POSITION_VAL(QUADSPI_DCR_FSIZE)) \|
elmot	1:d0dfbce63a89	313	hqspi->Init.ChipSelectHighTime \| hqspi->Init.ClockMode));
elmot	1:d0dfbce63a89	314
elmot	1:d0dfbce63a89	315	/* Enable the QSPI peripheral */
elmot	1:d0dfbce63a89	316	__HAL_QSPI_ENABLE(hqspi);
elmot	1:d0dfbce63a89	317
elmot	1:d0dfbce63a89	318	/* Set QSPI error code to none */
elmot	1:d0dfbce63a89	319	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
elmot	1:d0dfbce63a89	320
elmot	1:d0dfbce63a89	321	/* Initialize the QSPI state */
elmot	1:d0dfbce63a89	322	hqspi->State = HAL_QSPI_STATE_READY;
elmot	1:d0dfbce63a89	323	}
elmot	1:d0dfbce63a89	324
elmot	1:d0dfbce63a89	325	/* Release Lock */
elmot	1:d0dfbce63a89	326	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	327
elmot	1:d0dfbce63a89	328	/* Return function status */
elmot	1:d0dfbce63a89	329	return status;
elmot	1:d0dfbce63a89	330	}
elmot	1:d0dfbce63a89	331
elmot	1:d0dfbce63a89	332	/**
elmot	1:d0dfbce63a89	333	* @brief De-Initialize the QSPI peripheral.
elmot	1:d0dfbce63a89	334	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	335	* @retval HAL status
elmot	1:d0dfbce63a89	336	*/
elmot	1:d0dfbce63a89	337	HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	338	{
elmot	1:d0dfbce63a89	339	/* Check the QSPI handle allocation */
elmot	1:d0dfbce63a89	340	if(hqspi == NULL)
elmot	1:d0dfbce63a89	341	{
elmot	1:d0dfbce63a89	342	return HAL_ERROR;
elmot	1:d0dfbce63a89	343	}
elmot	1:d0dfbce63a89	344
elmot	1:d0dfbce63a89	345	/* Process locked */
elmot	1:d0dfbce63a89	346	__HAL_LOCK(hqspi);
elmot	1:d0dfbce63a89	347
elmot	1:d0dfbce63a89	348	/* Disable the QSPI Peripheral Clock */
elmot	1:d0dfbce63a89	349	__HAL_QSPI_DISABLE(hqspi);
elmot	1:d0dfbce63a89	350
elmot	1:d0dfbce63a89	351	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
elmot	1:d0dfbce63a89	352	HAL_QSPI_MspDeInit(hqspi);
elmot	1:d0dfbce63a89	353
elmot	1:d0dfbce63a89	354	/* Set QSPI error code to none */
elmot	1:d0dfbce63a89	355	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
elmot	1:d0dfbce63a89	356
elmot	1:d0dfbce63a89	357	/* Initialize the QSPI state */
elmot	1:d0dfbce63a89	358	hqspi->State = HAL_QSPI_STATE_RESET;
elmot	1:d0dfbce63a89	359
elmot	1:d0dfbce63a89	360	/* Release Lock */
elmot	1:d0dfbce63a89	361	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	362
elmot	1:d0dfbce63a89	363	return HAL_OK;
elmot	1:d0dfbce63a89	364	}
elmot	1:d0dfbce63a89	365
elmot	1:d0dfbce63a89	366	/**
elmot	1:d0dfbce63a89	367	* @brief Initialize the QSPI MSP.
elmot	1:d0dfbce63a89	368	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	369	* @retval None
elmot	1:d0dfbce63a89	370	*/
elmot	1:d0dfbce63a89	371	__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	372	{
elmot	1:d0dfbce63a89	373	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	374	UNUSED(hqspi);
elmot	1:d0dfbce63a89	375
elmot	1:d0dfbce63a89	376	/* NOTE : This function should not be modified, when the callback is needed,
elmot	1:d0dfbce63a89	377	the HAL_QSPI_MspInit can be implemented in the user file
elmot	1:d0dfbce63a89	378	*/
elmot	1:d0dfbce63a89	379	}
elmot	1:d0dfbce63a89	380
elmot	1:d0dfbce63a89	381	/**
elmot	1:d0dfbce63a89	382	* @brief DeInitialize the QSPI MSP.
elmot	1:d0dfbce63a89	383	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	384	* @retval None
elmot	1:d0dfbce63a89	385	*/
elmot	1:d0dfbce63a89	386	__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	387	{
elmot	1:d0dfbce63a89	388	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	389	UNUSED(hqspi);
elmot	1:d0dfbce63a89	390
elmot	1:d0dfbce63a89	391	/* NOTE : This function should not be modified, when the callback is needed,
elmot	1:d0dfbce63a89	392	the HAL_QSPI_MspDeInit can be implemented in the user file
elmot	1:d0dfbce63a89	393	*/
elmot	1:d0dfbce63a89	394	}
elmot	1:d0dfbce63a89	395
elmot	1:d0dfbce63a89	396	/**
elmot	1:d0dfbce63a89	397	* @}
elmot	1:d0dfbce63a89	398	*/
elmot	1:d0dfbce63a89	399
elmot	1:d0dfbce63a89	400	/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
elmot	1:d0dfbce63a89	401	* @brief QSPI Transmit/Receive functions
elmot	1:d0dfbce63a89	402	*
elmot	1:d0dfbce63a89	403	@verbatim
elmot	1:d0dfbce63a89	404	===============================================================================
elmot	1:d0dfbce63a89	405	##### IO operation functions #####
elmot	1:d0dfbce63a89	406	===============================================================================
elmot	1:d0dfbce63a89	407	[..]
elmot	1:d0dfbce63a89	408	This subsection provides a set of functions allowing to :
elmot	1:d0dfbce63a89	409	(+) Handle the interrupts.
elmot	1:d0dfbce63a89	410	(+) Handle the command sequence.
elmot	1:d0dfbce63a89	411	(+) Transmit data in blocking, interrupt or DMA mode.
elmot	1:d0dfbce63a89	412	(+) Receive data in blocking, interrupt or DMA mode.
elmot	1:d0dfbce63a89	413	(+) Manage the auto-polling functional mode.
elmot	1:d0dfbce63a89	414	(+) Manage the memory-mapped functional mode.
elmot	1:d0dfbce63a89	415
elmot	1:d0dfbce63a89	416	@endverbatim
elmot	1:d0dfbce63a89	417	* @{
elmot	1:d0dfbce63a89	418	*/
elmot	1:d0dfbce63a89	419
elmot	1:d0dfbce63a89	420	/**
elmot	1:d0dfbce63a89	421	* @brief Handle QSPI interrupt request.
elmot	1:d0dfbce63a89	422	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	423	* @retval None
elmot	1:d0dfbce63a89	424	*/
elmot	1:d0dfbce63a89	425	void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	426	{
elmot	1:d0dfbce63a89	427	__IO uint32_t *data_reg;
elmot	1:d0dfbce63a89	428	uint32_t flag = READ_REG(hqspi->Instance->SR);
elmot	1:d0dfbce63a89	429	uint32_t itsource = READ_REG(hqspi->Instance->CR);
elmot	1:d0dfbce63a89	430
elmot	1:d0dfbce63a89	431	/* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
elmot	1:d0dfbce63a89	432	if((flag & QSPI_FLAG_FT) && (itsource & QSPI_IT_FT))
elmot	1:d0dfbce63a89	433	{
elmot	1:d0dfbce63a89	434	data_reg = &hqspi->Instance->DR;
elmot	1:d0dfbce63a89	435
elmot	1:d0dfbce63a89	436	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
elmot	1:d0dfbce63a89	437	{
elmot	1:d0dfbce63a89	438	/* Transmission process */
elmot	1:d0dfbce63a89	439	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
elmot	1:d0dfbce63a89	440	{
elmot	1:d0dfbce63a89	441	if (hqspi->TxXferCount > 0)
elmot	1:d0dfbce63a89	442	{
elmot	1:d0dfbce63a89	443	/* Fill the FIFO until the threshold is reached */
elmot	1:d0dfbce63a89	444	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr++;
elmot	1:d0dfbce63a89	445	hqspi->TxXferCount--;
elmot	1:d0dfbce63a89	446	}
elmot	1:d0dfbce63a89	447	else
elmot	1:d0dfbce63a89	448	{
elmot	1:d0dfbce63a89	449	/* No more data available for the transfer */
elmot	1:d0dfbce63a89	450	/* Disable the QSPI FIFO Threshold Interrupt */
elmot	1:d0dfbce63a89	451	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
elmot	1:d0dfbce63a89	452	break;
elmot	1:d0dfbce63a89	453	}
elmot	1:d0dfbce63a89	454	}
elmot	1:d0dfbce63a89	455	}
elmot	1:d0dfbce63a89	456	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
elmot	1:d0dfbce63a89	457	{
elmot	1:d0dfbce63a89	458	/* Receiving Process */
elmot	1:d0dfbce63a89	459	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
elmot	1:d0dfbce63a89	460	{
elmot	1:d0dfbce63a89	461	if (hqspi->RxXferCount > 0)
elmot	1:d0dfbce63a89	462	{
elmot	1:d0dfbce63a89	463	/* Read the FIFO until the threshold is reached */
elmot	1:d0dfbce63a89	464	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
elmot	1:d0dfbce63a89	465	hqspi->RxXferCount--;
elmot	1:d0dfbce63a89	466	}
elmot	1:d0dfbce63a89	467	else
elmot	1:d0dfbce63a89	468	{
elmot	1:d0dfbce63a89	469	/* All data have been received for the transfer */
elmot	1:d0dfbce63a89	470	/* Disable the QSPI FIFO Threshold Interrupt */
elmot	1:d0dfbce63a89	471	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
elmot	1:d0dfbce63a89	472	break;
elmot	1:d0dfbce63a89	473	}
elmot	1:d0dfbce63a89	474	}
elmot	1:d0dfbce63a89	475	}
elmot	1:d0dfbce63a89	476
elmot	1:d0dfbce63a89	477	/* FIFO Threshold callback */
elmot	1:d0dfbce63a89	478	HAL_QSPI_FifoThresholdCallback(hqspi);
elmot	1:d0dfbce63a89	479	}
elmot	1:d0dfbce63a89	480
elmot	1:d0dfbce63a89	481	/* QSPI Transfer Complete interrupt occurred -------------------------------*/
elmot	1:d0dfbce63a89	482	else if((flag & QSPI_FLAG_TC) && (itsource & QSPI_IT_TC))
elmot	1:d0dfbce63a89	483	{
elmot	1:d0dfbce63a89	484	/* Clear interrupt */
elmot	1:d0dfbce63a89	485	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
elmot	1:d0dfbce63a89	486
elmot	1:d0dfbce63a89	487	/* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
elmot	1:d0dfbce63a89	488	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
elmot	1:d0dfbce63a89	489
elmot	1:d0dfbce63a89	490	/* Transfer complete callback */
elmot	1:d0dfbce63a89	491	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
elmot	1:d0dfbce63a89	492	{
elmot	1:d0dfbce63a89	493	if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
elmot	1:d0dfbce63a89	494	{
elmot	1:d0dfbce63a89	495	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
elmot	1:d0dfbce63a89	496	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
elmot	1:d0dfbce63a89	497
elmot	1:d0dfbce63a89	498	/* Disable the DMA channel */
elmot	1:d0dfbce63a89	499	__HAL_DMA_DISABLE(hqspi->hdma);
elmot	1:d0dfbce63a89	500	}
elmot	1:d0dfbce63a89	501
elmot	1:d0dfbce63a89	502	#if defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
elmot	1:d0dfbce63a89	503	/* Clear Busy bit */
elmot	1:d0dfbce63a89	504	HAL_QSPI_Abort_IT(hqspi);
elmot	1:d0dfbce63a89	505	#endif
elmot	1:d0dfbce63a89	506
elmot	1:d0dfbce63a89	507	/* Change state of QSPI */
elmot	1:d0dfbce63a89	508	hqspi->State = HAL_QSPI_STATE_READY;
elmot	1:d0dfbce63a89	509
elmot	1:d0dfbce63a89	510	/* TX Complete callback */
elmot	1:d0dfbce63a89	511	HAL_QSPI_TxCpltCallback(hqspi);
elmot	1:d0dfbce63a89	512	}
elmot	1:d0dfbce63a89	513	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
elmot	1:d0dfbce63a89	514	{
elmot	1:d0dfbce63a89	515	if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
elmot	1:d0dfbce63a89	516	{
elmot	1:d0dfbce63a89	517	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
elmot	1:d0dfbce63a89	518	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
elmot	1:d0dfbce63a89	519
elmot	1:d0dfbce63a89	520	/* Disable the DMA channel */
elmot	1:d0dfbce63a89	521	__HAL_DMA_DISABLE(hqspi->hdma);
elmot	1:d0dfbce63a89	522	}
elmot	1:d0dfbce63a89	523	else
elmot	1:d0dfbce63a89	524	{
elmot	1:d0dfbce63a89	525	data_reg = &hqspi->Instance->DR;
elmot	1:d0dfbce63a89	526	while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
elmot	1:d0dfbce63a89	527	{
elmot	1:d0dfbce63a89	528	if (hqspi->RxXferCount > 0)
elmot	1:d0dfbce63a89	529	{
elmot	1:d0dfbce63a89	530	/* Read the last data received in the FIFO until it is empty */
elmot	1:d0dfbce63a89	531	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
elmot	1:d0dfbce63a89	532	hqspi->RxXferCount--;
elmot	1:d0dfbce63a89	533	}
elmot	1:d0dfbce63a89	534	else
elmot	1:d0dfbce63a89	535	{
elmot	1:d0dfbce63a89	536	/* All data have been received for the transfer */
elmot	1:d0dfbce63a89	537	break;
elmot	1:d0dfbce63a89	538	}
elmot	1:d0dfbce63a89	539	}
elmot	1:d0dfbce63a89	540	}
elmot	1:d0dfbce63a89	541
elmot	1:d0dfbce63a89	542	#if defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
elmot	1:d0dfbce63a89	543	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
elmot	1:d0dfbce63a89	544	HAL_QSPI_Abort_IT(hqspi);
elmot	1:d0dfbce63a89	545	#endif
elmot	1:d0dfbce63a89	546
elmot	1:d0dfbce63a89	547	/* Change state of QSPI */
elmot	1:d0dfbce63a89	548	hqspi->State = HAL_QSPI_STATE_READY;
elmot	1:d0dfbce63a89	549
elmot	1:d0dfbce63a89	550	/* RX Complete callback */
elmot	1:d0dfbce63a89	551	HAL_QSPI_RxCpltCallback(hqspi);
elmot	1:d0dfbce63a89	552	}
elmot	1:d0dfbce63a89	553	else if(hqspi->State == HAL_QSPI_STATE_BUSY)
elmot	1:d0dfbce63a89	554	{
elmot	1:d0dfbce63a89	555	/* Change state of QSPI */
elmot	1:d0dfbce63a89	556	hqspi->State = HAL_QSPI_STATE_READY;
elmot	1:d0dfbce63a89	557
elmot	1:d0dfbce63a89	558	/* Command Complete callback */
elmot	1:d0dfbce63a89	559	HAL_QSPI_CmdCpltCallback(hqspi);
elmot	1:d0dfbce63a89	560	}
elmot	1:d0dfbce63a89	561	else if(hqspi->State == HAL_QSPI_STATE_ABORT)
elmot	1:d0dfbce63a89	562	{
elmot	1:d0dfbce63a89	563	/* Change state of QSPI */
elmot	1:d0dfbce63a89	564	hqspi->State = HAL_QSPI_STATE_READY;
elmot	1:d0dfbce63a89	565
elmot	1:d0dfbce63a89	566	if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
elmot	1:d0dfbce63a89	567	{
elmot	1:d0dfbce63a89	568	/* Abort called by the user */
elmot	1:d0dfbce63a89	569
elmot	1:d0dfbce63a89	570	/* Abort Complete callback */
elmot	1:d0dfbce63a89	571	HAL_QSPI_AbortCpltCallback(hqspi);
elmot	1:d0dfbce63a89	572	}
elmot	1:d0dfbce63a89	573	else
elmot	1:d0dfbce63a89	574	{
elmot	1:d0dfbce63a89	575	/* Abort due to an error (eg : DMA error) */
elmot	1:d0dfbce63a89	576
elmot	1:d0dfbce63a89	577	/* Error callback */
elmot	1:d0dfbce63a89	578	HAL_QSPI_ErrorCallback(hqspi);
elmot	1:d0dfbce63a89	579	}
elmot	1:d0dfbce63a89	580	}
elmot	1:d0dfbce63a89	581	}
elmot	1:d0dfbce63a89	582
elmot	1:d0dfbce63a89	583	/* QSPI Status Match interrupt occurred ------------------------------------*/
elmot	1:d0dfbce63a89	584	else if((flag & QSPI_FLAG_SM) && (itsource & QSPI_IT_SM))
elmot	1:d0dfbce63a89	585	{
elmot	1:d0dfbce63a89	586	/* Clear interrupt */
elmot	1:d0dfbce63a89	587	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
elmot	1:d0dfbce63a89	588
elmot	1:d0dfbce63a89	589	/* Check if the automatic poll mode stop is activated */
elmot	1:d0dfbce63a89	590	if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
elmot	1:d0dfbce63a89	591	{
elmot	1:d0dfbce63a89	592	/* Disable the QSPI Transfer Error and Status Match Interrupts */
elmot	1:d0dfbce63a89	593	__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM \| QSPI_IT_TE));
elmot	1:d0dfbce63a89	594
elmot	1:d0dfbce63a89	595	/* Change state of QSPI */
elmot	1:d0dfbce63a89	596	hqspi->State = HAL_QSPI_STATE_READY;
elmot	1:d0dfbce63a89	597	}
elmot	1:d0dfbce63a89	598
elmot	1:d0dfbce63a89	599	/* Status match callback */
elmot	1:d0dfbce63a89	600	HAL_QSPI_StatusMatchCallback(hqspi);
elmot	1:d0dfbce63a89	601	}
elmot	1:d0dfbce63a89	602
elmot	1:d0dfbce63a89	603	/* QSPI Transfer Error interrupt occurred ----------------------------------*/
elmot	1:d0dfbce63a89	604	else if((flag & QSPI_FLAG_TE) && (itsource & QSPI_IT_TE))
elmot	1:d0dfbce63a89	605	{
elmot	1:d0dfbce63a89	606	/* Clear interrupt */
elmot	1:d0dfbce63a89	607	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
elmot	1:d0dfbce63a89	608
elmot	1:d0dfbce63a89	609	/* Disable all the QSPI Interrupts */
elmot	1:d0dfbce63a89	610	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM \| QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
elmot	1:d0dfbce63a89	611
elmot	1:d0dfbce63a89	612	/* Set error code */
elmot	1:d0dfbce63a89	613	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TRANSFER;
elmot	1:d0dfbce63a89	614
elmot	1:d0dfbce63a89	615	if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
elmot	1:d0dfbce63a89	616	{
elmot	1:d0dfbce63a89	617	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
elmot	1:d0dfbce63a89	618	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
elmot	1:d0dfbce63a89	619
elmot	1:d0dfbce63a89	620	/* Disable the DMA channel */
elmot	1:d0dfbce63a89	621	hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
elmot	1:d0dfbce63a89	622	HAL_DMA_Abort_IT(hqspi->hdma);
elmot	1:d0dfbce63a89	623	}
elmot	1:d0dfbce63a89	624	else
elmot	1:d0dfbce63a89	625	{
elmot	1:d0dfbce63a89	626	/* Change state of QSPI */
elmot	1:d0dfbce63a89	627	hqspi->State = HAL_QSPI_STATE_READY;
elmot	1:d0dfbce63a89	628
elmot	1:d0dfbce63a89	629	/* Error callback */
elmot	1:d0dfbce63a89	630	HAL_QSPI_ErrorCallback(hqspi);
elmot	1:d0dfbce63a89	631	}
elmot	1:d0dfbce63a89	632	}
elmot	1:d0dfbce63a89	633
elmot	1:d0dfbce63a89	634	/* QSPI Timeout interrupt occurred -----------------------------------------*/
elmot	1:d0dfbce63a89	635	else if((flag & QSPI_FLAG_TO) && (itsource & QSPI_IT_TO))
elmot	1:d0dfbce63a89	636	{
elmot	1:d0dfbce63a89	637	/* Clear interrupt */
elmot	1:d0dfbce63a89	638	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
elmot	1:d0dfbce63a89	639
elmot	1:d0dfbce63a89	640	/* Timeout callback */
elmot	1:d0dfbce63a89	641	HAL_QSPI_TimeOutCallback(hqspi);
elmot	1:d0dfbce63a89	642	}
elmot	1:d0dfbce63a89	643	}
elmot	1:d0dfbce63a89	644
elmot	1:d0dfbce63a89	645	/**
elmot	1:d0dfbce63a89	646	* @brief Set the command configuration.
elmot	1:d0dfbce63a89	647	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	648	* @param cmd : structure that contains the command configuration information
elmot	1:d0dfbce63a89	649	* @param Timeout : Timeout duration
elmot	1:d0dfbce63a89	650	* @note This function is used only in Indirect Read or Write Modes
elmot	1:d0dfbce63a89	651	* @retval HAL status
elmot	1:d0dfbce63a89	652	*/
elmot	1:d0dfbce63a89	653	HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t Timeout)
elmot	1:d0dfbce63a89	654	{
elmot	1:d0dfbce63a89	655	HAL_StatusTypeDef status = HAL_ERROR;
elmot	1:d0dfbce63a89	656	uint32_t tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	657
elmot	1:d0dfbce63a89	658	/* Check the parameters */
elmot	1:d0dfbce63a89	659	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
elmot	1:d0dfbce63a89	660	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
elmot	1:d0dfbce63a89	661	{
elmot	1:d0dfbce63a89	662	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
elmot	1:d0dfbce63a89	663	}
elmot	1:d0dfbce63a89	664
elmot	1:d0dfbce63a89	665	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
elmot	1:d0dfbce63a89	666	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
elmot	1:d0dfbce63a89	667	{
elmot	1:d0dfbce63a89	668	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
elmot	1:d0dfbce63a89	669	}
elmot	1:d0dfbce63a89	670
elmot	1:d0dfbce63a89	671	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
elmot	1:d0dfbce63a89	672	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
elmot	1:d0dfbce63a89	673	{
elmot	1:d0dfbce63a89	674	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
elmot	1:d0dfbce63a89	675	}
elmot	1:d0dfbce63a89	676
elmot	1:d0dfbce63a89	677	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
elmot	1:d0dfbce63a89	678	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
elmot	1:d0dfbce63a89	679
elmot	1:d0dfbce63a89	680	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
elmot	1:d0dfbce63a89	681	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
elmot	1:d0dfbce63a89	682	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
elmot	1:d0dfbce63a89	683
elmot	1:d0dfbce63a89	684	/* Process locked */
elmot	1:d0dfbce63a89	685	__HAL_LOCK(hqspi);
elmot	1:d0dfbce63a89	686
elmot	1:d0dfbce63a89	687	if(hqspi->State == HAL_QSPI_STATE_READY)
elmot	1:d0dfbce63a89	688	{
elmot	1:d0dfbce63a89	689	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
elmot	1:d0dfbce63a89	690
elmot	1:d0dfbce63a89	691	/* Update QSPI state */
elmot	1:d0dfbce63a89	692	hqspi->State = HAL_QSPI_STATE_BUSY;
elmot	1:d0dfbce63a89	693
elmot	1:d0dfbce63a89	694	/* Wait till BUSY flag reset */
elmot	1:d0dfbce63a89	695	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
elmot	1:d0dfbce63a89	696
elmot	1:d0dfbce63a89	697	if (status == HAL_OK)
elmot	1:d0dfbce63a89	698	{
elmot	1:d0dfbce63a89	699	/* Call the configuration function */
elmot	1:d0dfbce63a89	700	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
elmot	1:d0dfbce63a89	701
elmot	1:d0dfbce63a89	702	if (cmd->DataMode == QSPI_DATA_NONE)
elmot	1:d0dfbce63a89	703	{
elmot	1:d0dfbce63a89	704	/* When there is no data phase, the transfer start as soon as the configuration is done
elmot	1:d0dfbce63a89	705	so wait until TC flag is set to go back in idle state */
elmot	1:d0dfbce63a89	706	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
elmot	1:d0dfbce63a89	707
elmot	1:d0dfbce63a89	708	if (status == HAL_OK)
elmot	1:d0dfbce63a89	709	{
elmot	1:d0dfbce63a89	710	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
elmot	1:d0dfbce63a89	711
elmot	1:d0dfbce63a89	712	/* Update QSPI state */
elmot	1:d0dfbce63a89	713	hqspi->State = HAL_QSPI_STATE_READY;
elmot	1:d0dfbce63a89	714	}
elmot	1:d0dfbce63a89	715	}
elmot	1:d0dfbce63a89	716	else
elmot	1:d0dfbce63a89	717	{
elmot	1:d0dfbce63a89	718	/* Update QSPI state */
elmot	1:d0dfbce63a89	719	hqspi->State = HAL_QSPI_STATE_READY;
elmot	1:d0dfbce63a89	720	}
elmot	1:d0dfbce63a89	721	}
elmot	1:d0dfbce63a89	722	}
elmot	1:d0dfbce63a89	723	else
elmot	1:d0dfbce63a89	724	{
elmot	1:d0dfbce63a89	725	status = HAL_BUSY;
elmot	1:d0dfbce63a89	726	}
elmot	1:d0dfbce63a89	727
elmot	1:d0dfbce63a89	728	/* Process unlocked */
elmot	1:d0dfbce63a89	729	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	730
elmot	1:d0dfbce63a89	731	/* Return function status */
elmot	1:d0dfbce63a89	732	return status;
elmot	1:d0dfbce63a89	733	}
elmot	1:d0dfbce63a89	734
elmot	1:d0dfbce63a89	735	/**
elmot	1:d0dfbce63a89	736	* @brief Set the command configuration in interrupt mode.
elmot	1:d0dfbce63a89	737	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	738	* @param cmd : structure that contains the command configuration information
elmot	1:d0dfbce63a89	739	* @note This function is used only in Indirect Read or Write Modes
elmot	1:d0dfbce63a89	740	* @retval HAL status
elmot	1:d0dfbce63a89	741	*/
elmot	1:d0dfbce63a89	742	HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd)
elmot	1:d0dfbce63a89	743	{
elmot	1:d0dfbce63a89	744	HAL_StatusTypeDef status = HAL_ERROR;
elmot	1:d0dfbce63a89	745	uint32_t tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	746
elmot	1:d0dfbce63a89	747	/* Check the parameters */
elmot	1:d0dfbce63a89	748	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
elmot	1:d0dfbce63a89	749	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
elmot	1:d0dfbce63a89	750	{
elmot	1:d0dfbce63a89	751	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
elmot	1:d0dfbce63a89	752	}
elmot	1:d0dfbce63a89	753
elmot	1:d0dfbce63a89	754	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
elmot	1:d0dfbce63a89	755	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
elmot	1:d0dfbce63a89	756	{
elmot	1:d0dfbce63a89	757	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
elmot	1:d0dfbce63a89	758	}
elmot	1:d0dfbce63a89	759
elmot	1:d0dfbce63a89	760	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
elmot	1:d0dfbce63a89	761	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
elmot	1:d0dfbce63a89	762	{
elmot	1:d0dfbce63a89	763	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
elmot	1:d0dfbce63a89	764	}
elmot	1:d0dfbce63a89	765
elmot	1:d0dfbce63a89	766	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
elmot	1:d0dfbce63a89	767	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
elmot	1:d0dfbce63a89	768
elmot	1:d0dfbce63a89	769	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
elmot	1:d0dfbce63a89	770	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
elmot	1:d0dfbce63a89	771	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
elmot	1:d0dfbce63a89	772
elmot	1:d0dfbce63a89	773	/* Process locked */
elmot	1:d0dfbce63a89	774	__HAL_LOCK(hqspi);
elmot	1:d0dfbce63a89	775
elmot	1:d0dfbce63a89	776	if(hqspi->State == HAL_QSPI_STATE_READY)
elmot	1:d0dfbce63a89	777	{
elmot	1:d0dfbce63a89	778	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
elmot	1:d0dfbce63a89	779
elmot	1:d0dfbce63a89	780	/* Update QSPI state */
elmot	1:d0dfbce63a89	781	hqspi->State = HAL_QSPI_STATE_BUSY;
elmot	1:d0dfbce63a89	782
elmot	1:d0dfbce63a89	783	/* Wait till BUSY flag reset */
elmot	1:d0dfbce63a89	784	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
elmot	1:d0dfbce63a89	785
elmot	1:d0dfbce63a89	786	if (status == HAL_OK)
elmot	1:d0dfbce63a89	787	{
elmot	1:d0dfbce63a89	788	if (cmd->DataMode == QSPI_DATA_NONE)
elmot	1:d0dfbce63a89	789	{
elmot	1:d0dfbce63a89	790	/* Clear interrupt */
elmot	1:d0dfbce63a89	791	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_TC);
elmot	1:d0dfbce63a89	792	}
elmot	1:d0dfbce63a89	793
elmot	1:d0dfbce63a89	794	/* Call the configuration function */
elmot	1:d0dfbce63a89	795	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
elmot	1:d0dfbce63a89	796
elmot	1:d0dfbce63a89	797	if (cmd->DataMode == QSPI_DATA_NONE)
elmot	1:d0dfbce63a89	798	{
elmot	1:d0dfbce63a89	799	/* When there is no data phase, the transfer start as soon as the configuration is done
elmot	1:d0dfbce63a89	800	so activate TC and TE interrupts */
elmot	1:d0dfbce63a89	801	/* Process unlocked */
elmot	1:d0dfbce63a89	802	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	803
elmot	1:d0dfbce63a89	804	/* Enable the QSPI Transfer Error Interrupt */
elmot	1:d0dfbce63a89	805	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_TC);
elmot	1:d0dfbce63a89	806	}
elmot	1:d0dfbce63a89	807	else
elmot	1:d0dfbce63a89	808	{
elmot	1:d0dfbce63a89	809	/* Update QSPI state */
elmot	1:d0dfbce63a89	810	hqspi->State = HAL_QSPI_STATE_READY;
elmot	1:d0dfbce63a89	811
elmot	1:d0dfbce63a89	812	/* Process unlocked */
elmot	1:d0dfbce63a89	813	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	814	}
elmot	1:d0dfbce63a89	815	}
elmot	1:d0dfbce63a89	816	else
elmot	1:d0dfbce63a89	817	{
elmot	1:d0dfbce63a89	818	/* Process unlocked */
elmot	1:d0dfbce63a89	819	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	820	}
elmot	1:d0dfbce63a89	821	}
elmot	1:d0dfbce63a89	822	else
elmot	1:d0dfbce63a89	823	{
elmot	1:d0dfbce63a89	824	status = HAL_BUSY;
elmot	1:d0dfbce63a89	825
elmot	1:d0dfbce63a89	826	/* Process unlocked */
elmot	1:d0dfbce63a89	827	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	828	}
elmot	1:d0dfbce63a89	829
elmot	1:d0dfbce63a89	830	/* Return function status */
elmot	1:d0dfbce63a89	831	return status;
elmot	1:d0dfbce63a89	832	}
elmot	1:d0dfbce63a89	833
elmot	1:d0dfbce63a89	834	/**
elmot	1:d0dfbce63a89	835	* @brief Transmit an amount of data in blocking mode.
elmot	1:d0dfbce63a89	836	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	837	* @param pData: pointer to data buffer
elmot	1:d0dfbce63a89	838	* @param Timeout : Timeout duration
elmot	1:d0dfbce63a89	839	* @note This function is used only in Indirect Write Mode
elmot	1:d0dfbce63a89	840	* @retval HAL status
elmot	1:d0dfbce63a89	841	*/
elmot	1:d0dfbce63a89	842	HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
elmot	1:d0dfbce63a89	843	{
elmot	1:d0dfbce63a89	844	HAL_StatusTypeDef status = HAL_OK;
elmot	1:d0dfbce63a89	845	uint32_t tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	846	__IO uint32_t *data_reg = &hqspi->Instance->DR;
elmot	1:d0dfbce63a89	847
elmot	1:d0dfbce63a89	848	/* Process locked */
elmot	1:d0dfbce63a89	849	__HAL_LOCK(hqspi);
elmot	1:d0dfbce63a89	850
elmot	1:d0dfbce63a89	851	if(hqspi->State == HAL_QSPI_STATE_READY)
elmot	1:d0dfbce63a89	852	{
elmot	1:d0dfbce63a89	853	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
elmot	1:d0dfbce63a89	854
elmot	1:d0dfbce63a89	855	if(pData != NULL )
elmot	1:d0dfbce63a89	856	{
elmot	1:d0dfbce63a89	857	/* Update state */
elmot	1:d0dfbce63a89	858	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
elmot	1:d0dfbce63a89	859
elmot	1:d0dfbce63a89	860	/* Configure counters and size of the handle */
elmot	1:d0dfbce63a89	861	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
elmot	1:d0dfbce63a89	862	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
elmot	1:d0dfbce63a89	863	hqspi->pTxBuffPtr = pData;
elmot	1:d0dfbce63a89	864
elmot	1:d0dfbce63a89	865	/* Configure QSPI: CCR register with functional as indirect write */
elmot	1:d0dfbce63a89	866	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
elmot	1:d0dfbce63a89	867
elmot	1:d0dfbce63a89	868	while(hqspi->TxXferCount > 0)
elmot	1:d0dfbce63a89	869	{
elmot	1:d0dfbce63a89	870	/* Wait until FT flag is set to send data */
elmot	1:d0dfbce63a89	871	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
elmot	1:d0dfbce63a89	872
elmot	1:d0dfbce63a89	873	if (status != HAL_OK)
elmot	1:d0dfbce63a89	874	{
elmot	1:d0dfbce63a89	875	break;
elmot	1:d0dfbce63a89	876	}
elmot	1:d0dfbce63a89	877
elmot	1:d0dfbce63a89	878	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr++;
elmot	1:d0dfbce63a89	879	hqspi->TxXferCount--;
elmot	1:d0dfbce63a89	880	}
elmot	1:d0dfbce63a89	881
elmot	1:d0dfbce63a89	882	if (status == HAL_OK)
elmot	1:d0dfbce63a89	883	{
elmot	1:d0dfbce63a89	884	/* Wait until TC flag is set to go back in idle state */
elmot	1:d0dfbce63a89	885	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
elmot	1:d0dfbce63a89	886
elmot	1:d0dfbce63a89	887	if (status == HAL_OK)
elmot	1:d0dfbce63a89	888	{
elmot	1:d0dfbce63a89	889	/* Clear Transfer Complete bit */
elmot	1:d0dfbce63a89	890	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
elmot	1:d0dfbce63a89	891
elmot	1:d0dfbce63a89	892	#if defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
elmot	1:d0dfbce63a89	893	/* Clear Busy bit */
elmot	1:d0dfbce63a89	894	status = HAL_QSPI_Abort(hqspi);
elmot	1:d0dfbce63a89	895	#endif
elmot	1:d0dfbce63a89	896	}
elmot	1:d0dfbce63a89	897	}
elmot	1:d0dfbce63a89	898
elmot	1:d0dfbce63a89	899	/* Update QSPI state */
elmot	1:d0dfbce63a89	900	hqspi->State = HAL_QSPI_STATE_READY;
elmot	1:d0dfbce63a89	901	}
elmot	1:d0dfbce63a89	902	else
elmot	1:d0dfbce63a89	903	{
elmot	1:d0dfbce63a89	904	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
elmot	1:d0dfbce63a89	905	status = HAL_ERROR;
elmot	1:d0dfbce63a89	906	}
elmot	1:d0dfbce63a89	907	}
elmot	1:d0dfbce63a89	908	else
elmot	1:d0dfbce63a89	909	{
elmot	1:d0dfbce63a89	910	status = HAL_BUSY;
elmot	1:d0dfbce63a89	911	}
elmot	1:d0dfbce63a89	912
elmot	1:d0dfbce63a89	913	/* Process unlocked */
elmot	1:d0dfbce63a89	914	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	915
elmot	1:d0dfbce63a89	916	return status;
elmot	1:d0dfbce63a89	917	}
elmot	1:d0dfbce63a89	918
elmot	1:d0dfbce63a89	919
elmot	1:d0dfbce63a89	920	/**
elmot	1:d0dfbce63a89	921	* @brief Receive an amount of data in blocking mode.
elmot	1:d0dfbce63a89	922	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	923	* @param pData: pointer to data buffer
elmot	1:d0dfbce63a89	924	* @param Timeout : Timeout duration
elmot	1:d0dfbce63a89	925	* @note This function is used only in Indirect Read Mode
elmot	1:d0dfbce63a89	926	* @retval HAL status
elmot	1:d0dfbce63a89	927	*/
elmot	1:d0dfbce63a89	928	HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
elmot	1:d0dfbce63a89	929	{
elmot	1:d0dfbce63a89	930	HAL_StatusTypeDef status = HAL_OK;
elmot	1:d0dfbce63a89	931	uint32_t tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	932	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
elmot	1:d0dfbce63a89	933	__IO uint32_t *data_reg = &hqspi->Instance->DR;
elmot	1:d0dfbce63a89	934
elmot	1:d0dfbce63a89	935	/* Process locked */
elmot	1:d0dfbce63a89	936	__HAL_LOCK(hqspi);
elmot	1:d0dfbce63a89	937
elmot	1:d0dfbce63a89	938	if(hqspi->State == HAL_QSPI_STATE_READY)
elmot	1:d0dfbce63a89	939	{
elmot	1:d0dfbce63a89	940	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
elmot	1:d0dfbce63a89	941
elmot	1:d0dfbce63a89	942	if(pData != NULL )
elmot	1:d0dfbce63a89	943	{
elmot	1:d0dfbce63a89	944	/* Update state */
elmot	1:d0dfbce63a89	945	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
elmot	1:d0dfbce63a89	946
elmot	1:d0dfbce63a89	947	/* Configure counters and size of the handle */
elmot	1:d0dfbce63a89	948	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
elmot	1:d0dfbce63a89	949	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
elmot	1:d0dfbce63a89	950	hqspi->pRxBuffPtr = pData;
elmot	1:d0dfbce63a89	951
elmot	1:d0dfbce63a89	952	/* Configure QSPI: CCR register with functional as indirect read */
elmot	1:d0dfbce63a89	953	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
elmot	1:d0dfbce63a89	954
elmot	1:d0dfbce63a89	955	/* Start the transfer by re-writing the address in AR register */
elmot	1:d0dfbce63a89	956	WRITE_REG(hqspi->Instance->AR, addr_reg);
elmot	1:d0dfbce63a89	957
elmot	1:d0dfbce63a89	958	while(hqspi->RxXferCount > 0)
elmot	1:d0dfbce63a89	959	{
elmot	1:d0dfbce63a89	960	/* Wait until FT or TC flag is set to read received data */
elmot	1:d0dfbce63a89	961	status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT \| QSPI_FLAG_TC), SET, tickstart, Timeout);
elmot	1:d0dfbce63a89	962
elmot	1:d0dfbce63a89	963	if (status != HAL_OK)
elmot	1:d0dfbce63a89	964	{
elmot	1:d0dfbce63a89	965	break;
elmot	1:d0dfbce63a89	966	}
elmot	1:d0dfbce63a89	967
elmot	1:d0dfbce63a89	968	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
elmot	1:d0dfbce63a89	969	hqspi->RxXferCount--;
elmot	1:d0dfbce63a89	970	}
elmot	1:d0dfbce63a89	971
elmot	1:d0dfbce63a89	972	if (status == HAL_OK)
elmot	1:d0dfbce63a89	973	{
elmot	1:d0dfbce63a89	974	/* Wait until TC flag is set to go back in idle state */
elmot	1:d0dfbce63a89	975	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
elmot	1:d0dfbce63a89	976
elmot	1:d0dfbce63a89	977	if (status == HAL_OK)
elmot	1:d0dfbce63a89	978	{
elmot	1:d0dfbce63a89	979	/* Clear Transfer Complete bit */
elmot	1:d0dfbce63a89	980	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
elmot	1:d0dfbce63a89	981
elmot	1:d0dfbce63a89	982	#if defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
elmot	1:d0dfbce63a89	983	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
elmot	1:d0dfbce63a89	984	status = HAL_QSPI_Abort(hqspi);
elmot	1:d0dfbce63a89	985	#endif
elmot	1:d0dfbce63a89	986	}
elmot	1:d0dfbce63a89	987	}
elmot	1:d0dfbce63a89	988
elmot	1:d0dfbce63a89	989	/* Update QSPI state */
elmot	1:d0dfbce63a89	990	hqspi->State = HAL_QSPI_STATE_READY;
elmot	1:d0dfbce63a89	991	}
elmot	1:d0dfbce63a89	992	else
elmot	1:d0dfbce63a89	993	{
elmot	1:d0dfbce63a89	994	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
elmot	1:d0dfbce63a89	995	status = HAL_ERROR;
elmot	1:d0dfbce63a89	996	}
elmot	1:d0dfbce63a89	997	}
elmot	1:d0dfbce63a89	998	else
elmot	1:d0dfbce63a89	999	{
elmot	1:d0dfbce63a89	1000	status = HAL_BUSY;
elmot	1:d0dfbce63a89	1001	}
elmot	1:d0dfbce63a89	1002
elmot	1:d0dfbce63a89	1003	/* Process unlocked */
elmot	1:d0dfbce63a89	1004	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1005
elmot	1:d0dfbce63a89	1006	return status;
elmot	1:d0dfbce63a89	1007	}
elmot	1:d0dfbce63a89	1008
elmot	1:d0dfbce63a89	1009	/**
elmot	1:d0dfbce63a89	1010	* @brief Send an amount of data in non-blocking mode with interrupt.
elmot	1:d0dfbce63a89	1011	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1012	* @param pData: pointer to data buffer
elmot	1:d0dfbce63a89	1013	* @note This function is used only in Indirect Write Mode
elmot	1:d0dfbce63a89	1014	* @retval HAL status
elmot	1:d0dfbce63a89	1015	*/
elmot	1:d0dfbce63a89	1016	HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
elmot	1:d0dfbce63a89	1017	{
elmot	1:d0dfbce63a89	1018	HAL_StatusTypeDef status = HAL_OK;
elmot	1:d0dfbce63a89	1019
elmot	1:d0dfbce63a89	1020	/* Process locked */
elmot	1:d0dfbce63a89	1021	__HAL_LOCK(hqspi);
elmot	1:d0dfbce63a89	1022
elmot	1:d0dfbce63a89	1023	if(hqspi->State == HAL_QSPI_STATE_READY)
elmot	1:d0dfbce63a89	1024	{
elmot	1:d0dfbce63a89	1025	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
elmot	1:d0dfbce63a89	1026
elmot	1:d0dfbce63a89	1027	if(pData != NULL )
elmot	1:d0dfbce63a89	1028	{
elmot	1:d0dfbce63a89	1029	/* Update state */
elmot	1:d0dfbce63a89	1030	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
elmot	1:d0dfbce63a89	1031
elmot	1:d0dfbce63a89	1032	/* Configure counters and size of the handle */
elmot	1:d0dfbce63a89	1033	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
elmot	1:d0dfbce63a89	1034	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
elmot	1:d0dfbce63a89	1035	hqspi->pTxBuffPtr = pData;
elmot	1:d0dfbce63a89	1036
elmot	1:d0dfbce63a89	1037	/* Configure QSPI: CCR register with functional as indirect write */
elmot	1:d0dfbce63a89	1038	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
elmot	1:d0dfbce63a89	1039
elmot	1:d0dfbce63a89	1040	/* Clear interrupt */
elmot	1:d0dfbce63a89	1041	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_TC);
elmot	1:d0dfbce63a89	1042
elmot	1:d0dfbce63a89	1043	/* Process unlocked */
elmot	1:d0dfbce63a89	1044	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1045
elmot	1:d0dfbce63a89	1046	/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
elmot	1:d0dfbce63a89	1047	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
elmot	1:d0dfbce63a89	1048	}
elmot	1:d0dfbce63a89	1049	else
elmot	1:d0dfbce63a89	1050	{
elmot	1:d0dfbce63a89	1051	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
elmot	1:d0dfbce63a89	1052	status = HAL_ERROR;
elmot	1:d0dfbce63a89	1053
elmot	1:d0dfbce63a89	1054	/* Process unlocked */
elmot	1:d0dfbce63a89	1055	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1056	}
elmot	1:d0dfbce63a89	1057	}
elmot	1:d0dfbce63a89	1058	else
elmot	1:d0dfbce63a89	1059	{
elmot	1:d0dfbce63a89	1060	status = HAL_BUSY;
elmot	1:d0dfbce63a89	1061
elmot	1:d0dfbce63a89	1062	/* Process unlocked */
elmot	1:d0dfbce63a89	1063	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1064	}
elmot	1:d0dfbce63a89	1065
elmot	1:d0dfbce63a89	1066	return status;
elmot	1:d0dfbce63a89	1067	}
elmot	1:d0dfbce63a89	1068
elmot	1:d0dfbce63a89	1069	/**
elmot	1:d0dfbce63a89	1070	* @brief Receive an amount of data in non-blocking mode with interrupt.
elmot	1:d0dfbce63a89	1071	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1072	* @param pData: pointer to data buffer
elmot	1:d0dfbce63a89	1073	* @note This function is used only in Indirect Read Mode
elmot	1:d0dfbce63a89	1074	* @retval HAL status
elmot	1:d0dfbce63a89	1075	*/
elmot	1:d0dfbce63a89	1076	HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
elmot	1:d0dfbce63a89	1077	{
elmot	1:d0dfbce63a89	1078	HAL_StatusTypeDef status = HAL_OK;
elmot	1:d0dfbce63a89	1079	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
elmot	1:d0dfbce63a89	1080
elmot	1:d0dfbce63a89	1081	/* Process locked */
elmot	1:d0dfbce63a89	1082	__HAL_LOCK(hqspi);
elmot	1:d0dfbce63a89	1083
elmot	1:d0dfbce63a89	1084	if(hqspi->State == HAL_QSPI_STATE_READY)
elmot	1:d0dfbce63a89	1085	{
elmot	1:d0dfbce63a89	1086	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
elmot	1:d0dfbce63a89	1087
elmot	1:d0dfbce63a89	1088	if(pData != NULL )
elmot	1:d0dfbce63a89	1089	{
elmot	1:d0dfbce63a89	1090	/* Update state */
elmot	1:d0dfbce63a89	1091	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
elmot	1:d0dfbce63a89	1092
elmot	1:d0dfbce63a89	1093	/* Configure counters and size of the handle */
elmot	1:d0dfbce63a89	1094	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
elmot	1:d0dfbce63a89	1095	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
elmot	1:d0dfbce63a89	1096	hqspi->pRxBuffPtr = pData;
elmot	1:d0dfbce63a89	1097
elmot	1:d0dfbce63a89	1098	/* Configure QSPI: CCR register with functional as indirect read */
elmot	1:d0dfbce63a89	1099	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
elmot	1:d0dfbce63a89	1100
elmot	1:d0dfbce63a89	1101	/* Start the transfer by re-writing the address in AR register */
elmot	1:d0dfbce63a89	1102	WRITE_REG(hqspi->Instance->AR, addr_reg);
elmot	1:d0dfbce63a89	1103
elmot	1:d0dfbce63a89	1104	/* Clear interrupt */
elmot	1:d0dfbce63a89	1105	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_TC);
elmot	1:d0dfbce63a89	1106
elmot	1:d0dfbce63a89	1107	/* Process unlocked */
elmot	1:d0dfbce63a89	1108	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1109
elmot	1:d0dfbce63a89	1110	/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
elmot	1:d0dfbce63a89	1111	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
elmot	1:d0dfbce63a89	1112	}
elmot	1:d0dfbce63a89	1113	else
elmot	1:d0dfbce63a89	1114	{
elmot	1:d0dfbce63a89	1115	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
elmot	1:d0dfbce63a89	1116	status = HAL_ERROR;
elmot	1:d0dfbce63a89	1117
elmot	1:d0dfbce63a89	1118	/* Process unlocked */
elmot	1:d0dfbce63a89	1119	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1120	}
elmot	1:d0dfbce63a89	1121	}
elmot	1:d0dfbce63a89	1122	else
elmot	1:d0dfbce63a89	1123	{
elmot	1:d0dfbce63a89	1124	status = HAL_BUSY;
elmot	1:d0dfbce63a89	1125
elmot	1:d0dfbce63a89	1126	/* Process unlocked */
elmot	1:d0dfbce63a89	1127	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1128	}
elmot	1:d0dfbce63a89	1129
elmot	1:d0dfbce63a89	1130	return status;
elmot	1:d0dfbce63a89	1131	}
elmot	1:d0dfbce63a89	1132
elmot	1:d0dfbce63a89	1133	/**
elmot	1:d0dfbce63a89	1134	* @brief Send an amount of data in non-blocking mode with DMA.
elmot	1:d0dfbce63a89	1135	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1136	* @param pData: pointer to data buffer
elmot	1:d0dfbce63a89	1137	* @note This function is used only in Indirect Write Mode
elmot	1:d0dfbce63a89	1138	* @note If DMA peripheral access is configured as halfword, the number
elmot	1:d0dfbce63a89	1139	* of data and the fifo threshold should be aligned on halfword
elmot	1:d0dfbce63a89	1140	* @note If DMA peripheral access is configured as word, the number
elmot	1:d0dfbce63a89	1141	* of data and the fifo threshold should be aligned on word
elmot	1:d0dfbce63a89	1142	* @retval HAL status
elmot	1:d0dfbce63a89	1143	*/
elmot	1:d0dfbce63a89	1144	HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
elmot	1:d0dfbce63a89	1145	{
elmot	1:d0dfbce63a89	1146	HAL_StatusTypeDef status = HAL_OK;
elmot	1:d0dfbce63a89	1147	uint32_t *tmp;
elmot	1:d0dfbce63a89	1148	uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
elmot	1:d0dfbce63a89	1149
elmot	1:d0dfbce63a89	1150	/* Process locked */
elmot	1:d0dfbce63a89	1151	__HAL_LOCK(hqspi);
elmot	1:d0dfbce63a89	1152
elmot	1:d0dfbce63a89	1153	if(hqspi->State == HAL_QSPI_STATE_READY)
elmot	1:d0dfbce63a89	1154	{
elmot	1:d0dfbce63a89	1155	/* Clear the error code */
elmot	1:d0dfbce63a89	1156	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
elmot	1:d0dfbce63a89	1157
elmot	1:d0dfbce63a89	1158	if(pData != NULL )
elmot	1:d0dfbce63a89	1159	{
elmot	1:d0dfbce63a89	1160	/* Configure counters of the handle */
elmot	1:d0dfbce63a89	1161	if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
elmot	1:d0dfbce63a89	1162	{
elmot	1:d0dfbce63a89	1163	hqspi->TxXferCount = data_size;
elmot	1:d0dfbce63a89	1164	}
elmot	1:d0dfbce63a89	1165	else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
elmot	1:d0dfbce63a89	1166	{
elmot	1:d0dfbce63a89	1167	if (((data_size % 2) != 0) \|\| ((hqspi->Init.FifoThreshold % 2) != 0))
elmot	1:d0dfbce63a89	1168	{
elmot	1:d0dfbce63a89	1169	/* The number of data or the fifo threshold is not aligned on halfword
elmot	1:d0dfbce63a89	1170	=> no transfer possible with DMA peripheral access configured as halfword */
elmot	1:d0dfbce63a89	1171	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
elmot	1:d0dfbce63a89	1172	status = HAL_ERROR;
elmot	1:d0dfbce63a89	1173
elmot	1:d0dfbce63a89	1174	/* Process unlocked */
elmot	1:d0dfbce63a89	1175	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1176	}
elmot	1:d0dfbce63a89	1177	else
elmot	1:d0dfbce63a89	1178	{
elmot	1:d0dfbce63a89	1179	hqspi->TxXferCount = (data_size >> 1);
elmot	1:d0dfbce63a89	1180	}
elmot	1:d0dfbce63a89	1181	}
elmot	1:d0dfbce63a89	1182	else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
elmot	1:d0dfbce63a89	1183	{
elmot	1:d0dfbce63a89	1184	if (((data_size % 4) != 0) \|\| ((hqspi->Init.FifoThreshold % 4) != 0))
elmot	1:d0dfbce63a89	1185	{
elmot	1:d0dfbce63a89	1186	/* The number of data or the fifo threshold is not aligned on word
elmot	1:d0dfbce63a89	1187	=> no transfer possible with DMA peripheral access configured as word */
elmot	1:d0dfbce63a89	1188	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
elmot	1:d0dfbce63a89	1189	status = HAL_ERROR;
elmot	1:d0dfbce63a89	1190
elmot	1:d0dfbce63a89	1191	/* Process unlocked */
elmot	1:d0dfbce63a89	1192	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1193	}
elmot	1:d0dfbce63a89	1194	else
elmot	1:d0dfbce63a89	1195	{
elmot	1:d0dfbce63a89	1196	hqspi->TxXferCount = (data_size >> 2);
elmot	1:d0dfbce63a89	1197	}
elmot	1:d0dfbce63a89	1198	}
elmot	1:d0dfbce63a89	1199
elmot	1:d0dfbce63a89	1200	if (status == HAL_OK)
elmot	1:d0dfbce63a89	1201	{
elmot	1:d0dfbce63a89	1202	/* Update state */
elmot	1:d0dfbce63a89	1203	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
elmot	1:d0dfbce63a89	1204
elmot	1:d0dfbce63a89	1205	/* Clear interrupt */
elmot	1:d0dfbce63a89	1206	__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE \| QSPI_FLAG_TC));
elmot	1:d0dfbce63a89	1207
elmot	1:d0dfbce63a89	1208	/* Configure size and pointer of the handle */
elmot	1:d0dfbce63a89	1209	hqspi->TxXferSize = hqspi->TxXferCount;
elmot	1:d0dfbce63a89	1210	hqspi->pTxBuffPtr = pData;
elmot	1:d0dfbce63a89	1211
elmot	1:d0dfbce63a89	1212	/* Configure QSPI: CCR register with functional mode as indirect write */
elmot	1:d0dfbce63a89	1213	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
elmot	1:d0dfbce63a89	1214
elmot	1:d0dfbce63a89	1215	/* Set the QSPI DMA transfer complete callback */
elmot	1:d0dfbce63a89	1216	hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
elmot	1:d0dfbce63a89	1217
elmot	1:d0dfbce63a89	1218	/* Set the QSPI DMA Half transfer complete callback */
elmot	1:d0dfbce63a89	1219	hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
elmot	1:d0dfbce63a89	1220
elmot	1:d0dfbce63a89	1221	/* Set the DMA error callback */
elmot	1:d0dfbce63a89	1222	hqspi->hdma->XferErrorCallback = QSPI_DMAError;
elmot	1:d0dfbce63a89	1223
elmot	1:d0dfbce63a89	1224	/* Clear the DMA abort callback */
elmot	1:d0dfbce63a89	1225	hqspi->hdma->XferAbortCallback = NULL;
elmot	1:d0dfbce63a89	1226
elmot	1:d0dfbce63a89	1227	/* Configure the direction of the DMA */
elmot	1:d0dfbce63a89	1228	hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
elmot	1:d0dfbce63a89	1229	MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
elmot	1:d0dfbce63a89	1230
elmot	1:d0dfbce63a89	1231	/* Enable the QSPI transmit DMA Channel */
elmot	1:d0dfbce63a89	1232	tmp = (uint32_t*)&pData;
elmot	1:d0dfbce63a89	1233	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
elmot	1:d0dfbce63a89	1234
elmot	1:d0dfbce63a89	1235	/* Process unlocked */
elmot	1:d0dfbce63a89	1236	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1237
elmot	1:d0dfbce63a89	1238	/* Enable the QSPI transfer error Interrupt */
elmot	1:d0dfbce63a89	1239	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
elmot	1:d0dfbce63a89	1240
elmot	1:d0dfbce63a89	1241	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
elmot	1:d0dfbce63a89	1242	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
elmot	1:d0dfbce63a89	1243	}
elmot	1:d0dfbce63a89	1244	}
elmot	1:d0dfbce63a89	1245	else
elmot	1:d0dfbce63a89	1246	{
elmot	1:d0dfbce63a89	1247	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
elmot	1:d0dfbce63a89	1248	status = HAL_ERROR;
elmot	1:d0dfbce63a89	1249
elmot	1:d0dfbce63a89	1250	/* Process unlocked */
elmot	1:d0dfbce63a89	1251	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1252	}
elmot	1:d0dfbce63a89	1253	}
elmot	1:d0dfbce63a89	1254	else
elmot	1:d0dfbce63a89	1255	{
elmot	1:d0dfbce63a89	1256	status = HAL_BUSY;
elmot	1:d0dfbce63a89	1257
elmot	1:d0dfbce63a89	1258	/* Process unlocked */
elmot	1:d0dfbce63a89	1259	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1260	}
elmot	1:d0dfbce63a89	1261
elmot	1:d0dfbce63a89	1262	return status;
elmot	1:d0dfbce63a89	1263	}
elmot	1:d0dfbce63a89	1264
elmot	1:d0dfbce63a89	1265	/**
elmot	1:d0dfbce63a89	1266	* @brief Receive an amount of data in non-blocking mode with DMA.
elmot	1:d0dfbce63a89	1267	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1268	* @param pData: pointer to data buffer.
elmot	1:d0dfbce63a89	1269	* @note This function is used only in Indirect Read Mode
elmot	1:d0dfbce63a89	1270	* @note If DMA peripheral access is configured as halfword, the number
elmot	1:d0dfbce63a89	1271	* of data and the fifo threshold should be aligned on halfword
elmot	1:d0dfbce63a89	1272	* @note If DMA peripheral access is configured as word, the number
elmot	1:d0dfbce63a89	1273	* of data and the fifo threshold should be aligned on word
elmot	1:d0dfbce63a89	1274	* @retval HAL status
elmot	1:d0dfbce63a89	1275	*/
elmot	1:d0dfbce63a89	1276	HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
elmot	1:d0dfbce63a89	1277	{
elmot	1:d0dfbce63a89	1278	HAL_StatusTypeDef status = HAL_OK;
elmot	1:d0dfbce63a89	1279	uint32_t *tmp;
elmot	1:d0dfbce63a89	1280	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
elmot	1:d0dfbce63a89	1281	uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
elmot	1:d0dfbce63a89	1282
elmot	1:d0dfbce63a89	1283	/* Process locked */
elmot	1:d0dfbce63a89	1284	__HAL_LOCK(hqspi);
elmot	1:d0dfbce63a89	1285
elmot	1:d0dfbce63a89	1286	if(hqspi->State == HAL_QSPI_STATE_READY)
elmot	1:d0dfbce63a89	1287	{
elmot	1:d0dfbce63a89	1288	/* Clear the error code */
elmot	1:d0dfbce63a89	1289	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
elmot	1:d0dfbce63a89	1290
elmot	1:d0dfbce63a89	1291	if(pData != NULL)
elmot	1:d0dfbce63a89	1292	{
elmot	1:d0dfbce63a89	1293	/* Configure counters of the handle */
elmot	1:d0dfbce63a89	1294	if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
elmot	1:d0dfbce63a89	1295	{
elmot	1:d0dfbce63a89	1296	hqspi->RxXferCount = data_size;
elmot	1:d0dfbce63a89	1297	}
elmot	1:d0dfbce63a89	1298	else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
elmot	1:d0dfbce63a89	1299	{
elmot	1:d0dfbce63a89	1300	if (((data_size % 2) != 0) \|\| ((hqspi->Init.FifoThreshold % 2) != 0))
elmot	1:d0dfbce63a89	1301	{
elmot	1:d0dfbce63a89	1302	/* The number of data or the fifo threshold is not aligned on halfword
elmot	1:d0dfbce63a89	1303	=> no transfer possible with DMA peripheral access configured as halfword */
elmot	1:d0dfbce63a89	1304	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
elmot	1:d0dfbce63a89	1305	status = HAL_ERROR;
elmot	1:d0dfbce63a89	1306
elmot	1:d0dfbce63a89	1307	/* Process unlocked */
elmot	1:d0dfbce63a89	1308	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1309	}
elmot	1:d0dfbce63a89	1310	else
elmot	1:d0dfbce63a89	1311	{
elmot	1:d0dfbce63a89	1312	hqspi->RxXferCount = (data_size >> 1);
elmot	1:d0dfbce63a89	1313	}
elmot	1:d0dfbce63a89	1314	}
elmot	1:d0dfbce63a89	1315	else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
elmot	1:d0dfbce63a89	1316	{
elmot	1:d0dfbce63a89	1317	if (((data_size % 4) != 0) \|\| ((hqspi->Init.FifoThreshold % 4) != 0))
elmot	1:d0dfbce63a89	1318	{
elmot	1:d0dfbce63a89	1319	/* The number of data or the fifo threshold is not aligned on word
elmot	1:d0dfbce63a89	1320	=> no transfer possible with DMA peripheral access configured as word */
elmot	1:d0dfbce63a89	1321	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
elmot	1:d0dfbce63a89	1322	status = HAL_ERROR;
elmot	1:d0dfbce63a89	1323
elmot	1:d0dfbce63a89	1324	/* Process unlocked */
elmot	1:d0dfbce63a89	1325	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1326	}
elmot	1:d0dfbce63a89	1327	else
elmot	1:d0dfbce63a89	1328	{
elmot	1:d0dfbce63a89	1329	hqspi->RxXferCount = (data_size >> 2);
elmot	1:d0dfbce63a89	1330	}
elmot	1:d0dfbce63a89	1331	}
elmot	1:d0dfbce63a89	1332
elmot	1:d0dfbce63a89	1333	if (status == HAL_OK)
elmot	1:d0dfbce63a89	1334	{
elmot	1:d0dfbce63a89	1335	/* Update state */
elmot	1:d0dfbce63a89	1336	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
elmot	1:d0dfbce63a89	1337
elmot	1:d0dfbce63a89	1338	/* Clear interrupt */
elmot	1:d0dfbce63a89	1339	__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE \| QSPI_FLAG_TC));
elmot	1:d0dfbce63a89	1340
elmot	1:d0dfbce63a89	1341	/* Configure size and pointer of the handle */
elmot	1:d0dfbce63a89	1342	hqspi->RxXferSize = hqspi->RxXferCount;
elmot	1:d0dfbce63a89	1343	hqspi->pRxBuffPtr = pData;
elmot	1:d0dfbce63a89	1344
elmot	1:d0dfbce63a89	1345	/* Set the QSPI DMA transfer complete callback */
elmot	1:d0dfbce63a89	1346	hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
elmot	1:d0dfbce63a89	1347
elmot	1:d0dfbce63a89	1348	/* Set the QSPI DMA Half transfer complete callback */
elmot	1:d0dfbce63a89	1349	hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
elmot	1:d0dfbce63a89	1350
elmot	1:d0dfbce63a89	1351	/* Set the DMA error callback */
elmot	1:d0dfbce63a89	1352	hqspi->hdma->XferErrorCallback = QSPI_DMAError;
elmot	1:d0dfbce63a89	1353
elmot	1:d0dfbce63a89	1354	/* Clear the DMA abort callback */
elmot	1:d0dfbce63a89	1355	hqspi->hdma->XferAbortCallback = NULL;
elmot	1:d0dfbce63a89	1356
elmot	1:d0dfbce63a89	1357	/* Configure the direction of the DMA */
elmot	1:d0dfbce63a89	1358	hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
elmot	1:d0dfbce63a89	1359	MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
elmot	1:d0dfbce63a89	1360
elmot	1:d0dfbce63a89	1361	/* Enable the DMA Channel */
elmot	1:d0dfbce63a89	1362	tmp = (uint32_t*)&pData;
elmot	1:d0dfbce63a89	1363	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)tmp, hqspi->RxXferSize);
elmot	1:d0dfbce63a89	1364
elmot	1:d0dfbce63a89	1365	/* Configure QSPI: CCR register with functional as indirect read */
elmot	1:d0dfbce63a89	1366	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
elmot	1:d0dfbce63a89	1367
elmot	1:d0dfbce63a89	1368	/* Start the transfer by re-writing the address in AR register */
elmot	1:d0dfbce63a89	1369	WRITE_REG(hqspi->Instance->AR, addr_reg);
elmot	1:d0dfbce63a89	1370
elmot	1:d0dfbce63a89	1371	/* Process unlocked */
elmot	1:d0dfbce63a89	1372	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1373
elmot	1:d0dfbce63a89	1374	/* Enable the QSPI transfer error Interrupt */
elmot	1:d0dfbce63a89	1375	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
elmot	1:d0dfbce63a89	1376
elmot	1:d0dfbce63a89	1377	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
elmot	1:d0dfbce63a89	1378	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
elmot	1:d0dfbce63a89	1379	}
elmot	1:d0dfbce63a89	1380	}
elmot	1:d0dfbce63a89	1381	else
elmot	1:d0dfbce63a89	1382	{
elmot	1:d0dfbce63a89	1383	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
elmot	1:d0dfbce63a89	1384	status = HAL_ERROR;
elmot	1:d0dfbce63a89	1385
elmot	1:d0dfbce63a89	1386	/* Process unlocked */
elmot	1:d0dfbce63a89	1387	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1388	}
elmot	1:d0dfbce63a89	1389	}
elmot	1:d0dfbce63a89	1390	else
elmot	1:d0dfbce63a89	1391	{
elmot	1:d0dfbce63a89	1392	status = HAL_BUSY;
elmot	1:d0dfbce63a89	1393
elmot	1:d0dfbce63a89	1394	/* Process unlocked */
elmot	1:d0dfbce63a89	1395	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1396	}
elmot	1:d0dfbce63a89	1397
elmot	1:d0dfbce63a89	1398	return status;
elmot	1:d0dfbce63a89	1399	}
elmot	1:d0dfbce63a89	1400
elmot	1:d0dfbce63a89	1401	/**
elmot	1:d0dfbce63a89	1402	* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
elmot	1:d0dfbce63a89	1403	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1404	* @param cmd: structure that contains the command configuration information.
elmot	1:d0dfbce63a89	1405	* @param cfg: structure that contains the polling configuration information.
elmot	1:d0dfbce63a89	1406	* @param Timeout : Timeout duration
elmot	1:d0dfbce63a89	1407	* @note This function is used only in Automatic Polling Mode
elmot	1:d0dfbce63a89	1408	* @retval HAL status
elmot	1:d0dfbce63a89	1409	*/
elmot	1:d0dfbce63a89	1410	HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
elmot	1:d0dfbce63a89	1411	{
elmot	1:d0dfbce63a89	1412	HAL_StatusTypeDef status = HAL_ERROR;
elmot	1:d0dfbce63a89	1413	uint32_t tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	1414
elmot	1:d0dfbce63a89	1415	/* Check the parameters */
elmot	1:d0dfbce63a89	1416	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
elmot	1:d0dfbce63a89	1417	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
elmot	1:d0dfbce63a89	1418	{
elmot	1:d0dfbce63a89	1419	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
elmot	1:d0dfbce63a89	1420	}
elmot	1:d0dfbce63a89	1421
elmot	1:d0dfbce63a89	1422	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
elmot	1:d0dfbce63a89	1423	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
elmot	1:d0dfbce63a89	1424	{
elmot	1:d0dfbce63a89	1425	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
elmot	1:d0dfbce63a89	1426	}
elmot	1:d0dfbce63a89	1427
elmot	1:d0dfbce63a89	1428	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
elmot	1:d0dfbce63a89	1429	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
elmot	1:d0dfbce63a89	1430	{
elmot	1:d0dfbce63a89	1431	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
elmot	1:d0dfbce63a89	1432	}
elmot	1:d0dfbce63a89	1433
elmot	1:d0dfbce63a89	1434	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
elmot	1:d0dfbce63a89	1435	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
elmot	1:d0dfbce63a89	1436
elmot	1:d0dfbce63a89	1437	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
elmot	1:d0dfbce63a89	1438	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
elmot	1:d0dfbce63a89	1439	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
elmot	1:d0dfbce63a89	1440
elmot	1:d0dfbce63a89	1441	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
elmot	1:d0dfbce63a89	1442	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
elmot	1:d0dfbce63a89	1443	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
elmot	1:d0dfbce63a89	1444
elmot	1:d0dfbce63a89	1445	/* Process locked */
elmot	1:d0dfbce63a89	1446	__HAL_LOCK(hqspi);
elmot	1:d0dfbce63a89	1447
elmot	1:d0dfbce63a89	1448	if(hqspi->State == HAL_QSPI_STATE_READY)
elmot	1:d0dfbce63a89	1449	{
elmot	1:d0dfbce63a89	1450	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
elmot	1:d0dfbce63a89	1451
elmot	1:d0dfbce63a89	1452	/* Update state */
elmot	1:d0dfbce63a89	1453	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
elmot	1:d0dfbce63a89	1454
elmot	1:d0dfbce63a89	1455	/* Wait till BUSY flag reset */
elmot	1:d0dfbce63a89	1456	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
elmot	1:d0dfbce63a89	1457
elmot	1:d0dfbce63a89	1458	if (status == HAL_OK)
elmot	1:d0dfbce63a89	1459	{
elmot	1:d0dfbce63a89	1460	/* Configure QSPI: PSMAR register with the status match value */
elmot	1:d0dfbce63a89	1461	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
elmot	1:d0dfbce63a89	1462
elmot	1:d0dfbce63a89	1463	/* Configure QSPI: PSMKR register with the status mask value */
elmot	1:d0dfbce63a89	1464	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
elmot	1:d0dfbce63a89	1465
elmot	1:d0dfbce63a89	1466	/* Configure QSPI: PIR register with the interval value */
elmot	1:d0dfbce63a89	1467	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
elmot	1:d0dfbce63a89	1468
elmot	1:d0dfbce63a89	1469	/* Configure QSPI: CR register with Match mode and Automatic stop enabled
elmot	1:d0dfbce63a89	1470	(otherwise there will be an infinite loop in blocking mode) */
elmot	1:d0dfbce63a89	1471	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
elmot	1:d0dfbce63a89	1472	(cfg->MatchMode \| QSPI_AUTOMATIC_STOP_ENABLE));
elmot	1:d0dfbce63a89	1473
elmot	1:d0dfbce63a89	1474	/* Call the configuration function */
elmot	1:d0dfbce63a89	1475	cmd->NbData = cfg->StatusBytesSize;
elmot	1:d0dfbce63a89	1476	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
elmot	1:d0dfbce63a89	1477
elmot	1:d0dfbce63a89	1478	/* Wait until SM flag is set to go back in idle state */
elmot	1:d0dfbce63a89	1479	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
elmot	1:d0dfbce63a89	1480
elmot	1:d0dfbce63a89	1481	if (status == HAL_OK)
elmot	1:d0dfbce63a89	1482	{
elmot	1:d0dfbce63a89	1483	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
elmot	1:d0dfbce63a89	1484
elmot	1:d0dfbce63a89	1485	/* Update state */
elmot	1:d0dfbce63a89	1486	hqspi->State = HAL_QSPI_STATE_READY;
elmot	1:d0dfbce63a89	1487	}
elmot	1:d0dfbce63a89	1488	}
elmot	1:d0dfbce63a89	1489	}
elmot	1:d0dfbce63a89	1490	else
elmot	1:d0dfbce63a89	1491	{
elmot	1:d0dfbce63a89	1492	status = HAL_BUSY;
elmot	1:d0dfbce63a89	1493	}
elmot	1:d0dfbce63a89	1494
elmot	1:d0dfbce63a89	1495	/* Process unlocked */
elmot	1:d0dfbce63a89	1496	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1497
elmot	1:d0dfbce63a89	1498	/* Return function status */
elmot	1:d0dfbce63a89	1499	return status;
elmot	1:d0dfbce63a89	1500	}
elmot	1:d0dfbce63a89	1501
elmot	1:d0dfbce63a89	1502	/**
elmot	1:d0dfbce63a89	1503	* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
elmot	1:d0dfbce63a89	1504	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1505	* @param cmd: structure that contains the command configuration information.
elmot	1:d0dfbce63a89	1506	* @param cfg: structure that contains the polling configuration information.
elmot	1:d0dfbce63a89	1507	* @note This function is used only in Automatic Polling Mode
elmot	1:d0dfbce63a89	1508	* @retval HAL status
elmot	1:d0dfbce63a89	1509	*/
elmot	1:d0dfbce63a89	1510	HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg)
elmot	1:d0dfbce63a89	1511	{
elmot	1:d0dfbce63a89	1512	HAL_StatusTypeDef status = HAL_ERROR;
elmot	1:d0dfbce63a89	1513	uint32_t tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	1514
elmot	1:d0dfbce63a89	1515	/* Check the parameters */
elmot	1:d0dfbce63a89	1516	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
elmot	1:d0dfbce63a89	1517	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
elmot	1:d0dfbce63a89	1518	{
elmot	1:d0dfbce63a89	1519	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
elmot	1:d0dfbce63a89	1520	}
elmot	1:d0dfbce63a89	1521
elmot	1:d0dfbce63a89	1522	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
elmot	1:d0dfbce63a89	1523	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
elmot	1:d0dfbce63a89	1524	{
elmot	1:d0dfbce63a89	1525	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
elmot	1:d0dfbce63a89	1526	}
elmot	1:d0dfbce63a89	1527
elmot	1:d0dfbce63a89	1528	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
elmot	1:d0dfbce63a89	1529	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
elmot	1:d0dfbce63a89	1530	{
elmot	1:d0dfbce63a89	1531	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
elmot	1:d0dfbce63a89	1532	}
elmot	1:d0dfbce63a89	1533
elmot	1:d0dfbce63a89	1534	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
elmot	1:d0dfbce63a89	1535	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
elmot	1:d0dfbce63a89	1536
elmot	1:d0dfbce63a89	1537	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
elmot	1:d0dfbce63a89	1538	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
elmot	1:d0dfbce63a89	1539	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
elmot	1:d0dfbce63a89	1540
elmot	1:d0dfbce63a89	1541	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
elmot	1:d0dfbce63a89	1542	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
elmot	1:d0dfbce63a89	1543	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
elmot	1:d0dfbce63a89	1544	assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
elmot	1:d0dfbce63a89	1545
elmot	1:d0dfbce63a89	1546	/* Process locked */
elmot	1:d0dfbce63a89	1547	__HAL_LOCK(hqspi);
elmot	1:d0dfbce63a89	1548
elmot	1:d0dfbce63a89	1549	if(hqspi->State == HAL_QSPI_STATE_READY)
elmot	1:d0dfbce63a89	1550	{
elmot	1:d0dfbce63a89	1551	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
elmot	1:d0dfbce63a89	1552
elmot	1:d0dfbce63a89	1553	/* Update state */
elmot	1:d0dfbce63a89	1554	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
elmot	1:d0dfbce63a89	1555
elmot	1:d0dfbce63a89	1556	/* Wait till BUSY flag reset */
elmot	1:d0dfbce63a89	1557	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
elmot	1:d0dfbce63a89	1558
elmot	1:d0dfbce63a89	1559	if (status == HAL_OK)
elmot	1:d0dfbce63a89	1560	{
elmot	1:d0dfbce63a89	1561	/* Configure QSPI: PSMAR register with the status match value */
elmot	1:d0dfbce63a89	1562	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
elmot	1:d0dfbce63a89	1563
elmot	1:d0dfbce63a89	1564	/* Configure QSPI: PSMKR register with the status mask value */
elmot	1:d0dfbce63a89	1565	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
elmot	1:d0dfbce63a89	1566
elmot	1:d0dfbce63a89	1567	/* Configure QSPI: PIR register with the interval value */
elmot	1:d0dfbce63a89	1568	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
elmot	1:d0dfbce63a89	1569
elmot	1:d0dfbce63a89	1570	/* Configure QSPI: CR register with Match mode and Automatic stop mode */
elmot	1:d0dfbce63a89	1571	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
elmot	1:d0dfbce63a89	1572	(cfg->MatchMode \| cfg->AutomaticStop));
elmot	1:d0dfbce63a89	1573
elmot	1:d0dfbce63a89	1574	/* Clear interrupt */
elmot	1:d0dfbce63a89	1575	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_SM);
elmot	1:d0dfbce63a89	1576
elmot	1:d0dfbce63a89	1577	/* Call the configuration function */
elmot	1:d0dfbce63a89	1578	cmd->NbData = cfg->StatusBytesSize;
elmot	1:d0dfbce63a89	1579	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
elmot	1:d0dfbce63a89	1580
elmot	1:d0dfbce63a89	1581	/* Process unlocked */
elmot	1:d0dfbce63a89	1582	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1583
elmot	1:d0dfbce63a89	1584	/* Enable the QSPI Transfer Error and status match Interrupt */
elmot	1:d0dfbce63a89	1585	__HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM \| QSPI_IT_TE));
elmot	1:d0dfbce63a89	1586
elmot	1:d0dfbce63a89	1587	}
elmot	1:d0dfbce63a89	1588	else
elmot	1:d0dfbce63a89	1589	{
elmot	1:d0dfbce63a89	1590	/* Process unlocked */
elmot	1:d0dfbce63a89	1591	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1592	}
elmot	1:d0dfbce63a89	1593	}
elmot	1:d0dfbce63a89	1594	else
elmot	1:d0dfbce63a89	1595	{
elmot	1:d0dfbce63a89	1596	status = HAL_BUSY;
elmot	1:d0dfbce63a89	1597
elmot	1:d0dfbce63a89	1598	/* Process unlocked */
elmot	1:d0dfbce63a89	1599	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1600	}
elmot	1:d0dfbce63a89	1601
elmot	1:d0dfbce63a89	1602	/* Return function status */
elmot	1:d0dfbce63a89	1603	return status;
elmot	1:d0dfbce63a89	1604	}
elmot	1:d0dfbce63a89	1605
elmot	1:d0dfbce63a89	1606	/**
elmot	1:d0dfbce63a89	1607	* @brief Configure the Memory Mapped mode.
elmot	1:d0dfbce63a89	1608	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1609	* @param cmd: structure that contains the command configuration information.
elmot	1:d0dfbce63a89	1610	* @param cfg: structure that contains the memory mapped configuration information.
elmot	1:d0dfbce63a89	1611	* @note This function is used only in Memory mapped Mode
elmot	1:d0dfbce63a89	1612	* @retval HAL status
elmot	1:d0dfbce63a89	1613	*/
elmot	1:d0dfbce63a89	1614	HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_MemoryMappedTypeDef *cfg)
elmot	1:d0dfbce63a89	1615	{
elmot	1:d0dfbce63a89	1616	HAL_StatusTypeDef status = HAL_ERROR;
elmot	1:d0dfbce63a89	1617	uint32_t tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	1618
elmot	1:d0dfbce63a89	1619	/* Check the parameters */
elmot	1:d0dfbce63a89	1620	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
elmot	1:d0dfbce63a89	1621	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
elmot	1:d0dfbce63a89	1622	{
elmot	1:d0dfbce63a89	1623	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
elmot	1:d0dfbce63a89	1624	}
elmot	1:d0dfbce63a89	1625
elmot	1:d0dfbce63a89	1626	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
elmot	1:d0dfbce63a89	1627	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
elmot	1:d0dfbce63a89	1628	{
elmot	1:d0dfbce63a89	1629	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
elmot	1:d0dfbce63a89	1630	}
elmot	1:d0dfbce63a89	1631
elmot	1:d0dfbce63a89	1632	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
elmot	1:d0dfbce63a89	1633	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
elmot	1:d0dfbce63a89	1634	{
elmot	1:d0dfbce63a89	1635	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
elmot	1:d0dfbce63a89	1636	}
elmot	1:d0dfbce63a89	1637
elmot	1:d0dfbce63a89	1638	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
elmot	1:d0dfbce63a89	1639	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
elmot	1:d0dfbce63a89	1640
elmot	1:d0dfbce63a89	1641	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
elmot	1:d0dfbce63a89	1642	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
elmot	1:d0dfbce63a89	1643	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
elmot	1:d0dfbce63a89	1644
elmot	1:d0dfbce63a89	1645	assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
elmot	1:d0dfbce63a89	1646
elmot	1:d0dfbce63a89	1647	/* Process locked */
elmot	1:d0dfbce63a89	1648	__HAL_LOCK(hqspi);
elmot	1:d0dfbce63a89	1649
elmot	1:d0dfbce63a89	1650	if(hqspi->State == HAL_QSPI_STATE_READY)
elmot	1:d0dfbce63a89	1651	{
elmot	1:d0dfbce63a89	1652	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
elmot	1:d0dfbce63a89	1653
elmot	1:d0dfbce63a89	1654	/* Update state */
elmot	1:d0dfbce63a89	1655	hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
elmot	1:d0dfbce63a89	1656
elmot	1:d0dfbce63a89	1657	/* Wait till BUSY flag reset */
elmot	1:d0dfbce63a89	1658	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
elmot	1:d0dfbce63a89	1659
elmot	1:d0dfbce63a89	1660	if (status == HAL_OK)
elmot	1:d0dfbce63a89	1661	{
elmot	1:d0dfbce63a89	1662	/* Configure QSPI: CR register with timeout counter enable */
elmot	1:d0dfbce63a89	1663	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
elmot	1:d0dfbce63a89	1664
elmot	1:d0dfbce63a89	1665	if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
elmot	1:d0dfbce63a89	1666	{
elmot	1:d0dfbce63a89	1667	assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
elmot	1:d0dfbce63a89	1668
elmot	1:d0dfbce63a89	1669	/* Configure QSPI: LPTR register with the low-power timeout value */
elmot	1:d0dfbce63a89	1670	WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
elmot	1:d0dfbce63a89	1671
elmot	1:d0dfbce63a89	1672	/* Clear interrupt */
elmot	1:d0dfbce63a89	1673	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
elmot	1:d0dfbce63a89	1674
elmot	1:d0dfbce63a89	1675	/* Enable the QSPI TimeOut Interrupt */
elmot	1:d0dfbce63a89	1676	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
elmot	1:d0dfbce63a89	1677	}
elmot	1:d0dfbce63a89	1678
elmot	1:d0dfbce63a89	1679	/* Call the configuration function */
elmot	1:d0dfbce63a89	1680	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
elmot	1:d0dfbce63a89	1681	}
elmot	1:d0dfbce63a89	1682	}
elmot	1:d0dfbce63a89	1683	else
elmot	1:d0dfbce63a89	1684	{
elmot	1:d0dfbce63a89	1685	status = HAL_BUSY;
elmot	1:d0dfbce63a89	1686	}
elmot	1:d0dfbce63a89	1687
elmot	1:d0dfbce63a89	1688	/* Process unlocked */
elmot	1:d0dfbce63a89	1689	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1690
elmot	1:d0dfbce63a89	1691	/* Return function status */
elmot	1:d0dfbce63a89	1692	return status;
elmot	1:d0dfbce63a89	1693	}
elmot	1:d0dfbce63a89	1694
elmot	1:d0dfbce63a89	1695	/**
elmot	1:d0dfbce63a89	1696	* @brief Transfer Error callback.
elmot	1:d0dfbce63a89	1697	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1698	* @retval None
elmot	1:d0dfbce63a89	1699	*/
elmot	1:d0dfbce63a89	1700	__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	1701	{
elmot	1:d0dfbce63a89	1702	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	1703	UNUSED(hqspi);
elmot	1:d0dfbce63a89	1704
elmot	1:d0dfbce63a89	1705	/* NOTE : This function should not be modified, when the callback is needed,
elmot	1:d0dfbce63a89	1706	the HAL_QSPI_ErrorCallback could be implemented in the user file
elmot	1:d0dfbce63a89	1707	*/
elmot	1:d0dfbce63a89	1708	}
elmot	1:d0dfbce63a89	1709
elmot	1:d0dfbce63a89	1710	/**
elmot	1:d0dfbce63a89	1711	* @brief Abort completed callback.
elmot	1:d0dfbce63a89	1712	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1713	* @retval None
elmot	1:d0dfbce63a89	1714	*/
elmot	1:d0dfbce63a89	1715	__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	1716	{
elmot	1:d0dfbce63a89	1717	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	1718	UNUSED(hqspi);
elmot	1:d0dfbce63a89	1719
elmot	1:d0dfbce63a89	1720	/* NOTE: This function should not be modified, when the callback is needed,
elmot	1:d0dfbce63a89	1721	the HAL_QSPI_AbortCpltCallback could be implemented in the user file
elmot	1:d0dfbce63a89	1722	*/
elmot	1:d0dfbce63a89	1723	}
elmot	1:d0dfbce63a89	1724
elmot	1:d0dfbce63a89	1725	/**
elmot	1:d0dfbce63a89	1726	* @brief Command completed callback.
elmot	1:d0dfbce63a89	1727	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1728	* @retval None
elmot	1:d0dfbce63a89	1729	*/
elmot	1:d0dfbce63a89	1730	__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	1731	{
elmot	1:d0dfbce63a89	1732	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	1733	UNUSED(hqspi);
elmot	1:d0dfbce63a89	1734
elmot	1:d0dfbce63a89	1735	/* NOTE: This function should not be modified, when the callback is needed,
elmot	1:d0dfbce63a89	1736	the HAL_QSPI_CmdCpltCallback could be implemented in the user file
elmot	1:d0dfbce63a89	1737	*/
elmot	1:d0dfbce63a89	1738	}
elmot	1:d0dfbce63a89	1739
elmot	1:d0dfbce63a89	1740	/**
elmot	1:d0dfbce63a89	1741	* @brief Rx Transfer completed callback.
elmot	1:d0dfbce63a89	1742	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1743	* @retval None
elmot	1:d0dfbce63a89	1744	*/
elmot	1:d0dfbce63a89	1745	__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	1746	{
elmot	1:d0dfbce63a89	1747	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	1748	UNUSED(hqspi);
elmot	1:d0dfbce63a89	1749
elmot	1:d0dfbce63a89	1750	/* NOTE: This function should not be modified, when the callback is needed,
elmot	1:d0dfbce63a89	1751	the HAL_QSPI_RxCpltCallback could be implemented in the user file
elmot	1:d0dfbce63a89	1752	*/
elmot	1:d0dfbce63a89	1753	}
elmot	1:d0dfbce63a89	1754
elmot	1:d0dfbce63a89	1755	/**
elmot	1:d0dfbce63a89	1756	* @brief Tx Transfer completed callback.
elmot	1:d0dfbce63a89	1757	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1758	* @retval None
elmot	1:d0dfbce63a89	1759	*/
elmot	1:d0dfbce63a89	1760	__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	1761	{
elmot	1:d0dfbce63a89	1762	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	1763	UNUSED(hqspi);
elmot	1:d0dfbce63a89	1764
elmot	1:d0dfbce63a89	1765	/* NOTE: This function should not be modified, when the callback is needed,
elmot	1:d0dfbce63a89	1766	the HAL_QSPI_TxCpltCallback could be implemented in the user file
elmot	1:d0dfbce63a89	1767	*/
elmot	1:d0dfbce63a89	1768	}
elmot	1:d0dfbce63a89	1769
elmot	1:d0dfbce63a89	1770	/**
elmot	1:d0dfbce63a89	1771	* @brief Rx Half Transfer completed callback.
elmot	1:d0dfbce63a89	1772	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1773	* @retval None
elmot	1:d0dfbce63a89	1774	*/
elmot	1:d0dfbce63a89	1775	__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	1776	{
elmot	1:d0dfbce63a89	1777	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	1778	UNUSED(hqspi);
elmot	1:d0dfbce63a89	1779
elmot	1:d0dfbce63a89	1780	/* NOTE: This function should not be modified, when the callback is needed,
elmot	1:d0dfbce63a89	1781	the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
elmot	1:d0dfbce63a89	1782	*/
elmot	1:d0dfbce63a89	1783	}
elmot	1:d0dfbce63a89	1784
elmot	1:d0dfbce63a89	1785	/**
elmot	1:d0dfbce63a89	1786	* @brief Tx Half Transfer completed callback.
elmot	1:d0dfbce63a89	1787	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1788	* @retval None
elmot	1:d0dfbce63a89	1789	*/
elmot	1:d0dfbce63a89	1790	__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	1791	{
elmot	1:d0dfbce63a89	1792	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	1793	UNUSED(hqspi);
elmot	1:d0dfbce63a89	1794
elmot	1:d0dfbce63a89	1795	/* NOTE: This function should not be modified, when the callback is needed,
elmot	1:d0dfbce63a89	1796	the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
elmot	1:d0dfbce63a89	1797	*/
elmot	1:d0dfbce63a89	1798	}
elmot	1:d0dfbce63a89	1799
elmot	1:d0dfbce63a89	1800	/**
elmot	1:d0dfbce63a89	1801	* @brief FIFO Threshold callback.
elmot	1:d0dfbce63a89	1802	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1803	* @retval None
elmot	1:d0dfbce63a89	1804	*/
elmot	1:d0dfbce63a89	1805	__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	1806	{
elmot	1:d0dfbce63a89	1807	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	1808	UNUSED(hqspi);
elmot	1:d0dfbce63a89	1809
elmot	1:d0dfbce63a89	1810	/* NOTE : This function should not be modified, when the callback is needed,
elmot	1:d0dfbce63a89	1811	the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
elmot	1:d0dfbce63a89	1812	*/
elmot	1:d0dfbce63a89	1813	}
elmot	1:d0dfbce63a89	1814
elmot	1:d0dfbce63a89	1815	/**
elmot	1:d0dfbce63a89	1816	* @brief Status Match callback.
elmot	1:d0dfbce63a89	1817	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1818	* @retval None
elmot	1:d0dfbce63a89	1819	*/
elmot	1:d0dfbce63a89	1820	__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	1821	{
elmot	1:d0dfbce63a89	1822	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	1823	UNUSED(hqspi);
elmot	1:d0dfbce63a89	1824
elmot	1:d0dfbce63a89	1825	/* NOTE : This function should not be modified, when the callback is needed,
elmot	1:d0dfbce63a89	1826	the HAL_QSPI_StatusMatchCallback could be implemented in the user file
elmot	1:d0dfbce63a89	1827	*/
elmot	1:d0dfbce63a89	1828	}
elmot	1:d0dfbce63a89	1829
elmot	1:d0dfbce63a89	1830	/**
elmot	1:d0dfbce63a89	1831	* @brief Timeout callback.
elmot	1:d0dfbce63a89	1832	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1833	* @retval None
elmot	1:d0dfbce63a89	1834	*/
elmot	1:d0dfbce63a89	1835	__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	1836	{
elmot	1:d0dfbce63a89	1837	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	1838	UNUSED(hqspi);
elmot	1:d0dfbce63a89	1839
elmot	1:d0dfbce63a89	1840	/* NOTE : This function should not be modified, when the callback is needed,
elmot	1:d0dfbce63a89	1841	the HAL_QSPI_TimeOutCallback could be implemented in the user file
elmot	1:d0dfbce63a89	1842	*/
elmot	1:d0dfbce63a89	1843	}
elmot	1:d0dfbce63a89	1844
elmot	1:d0dfbce63a89	1845	/**
elmot	1:d0dfbce63a89	1846	* @}
elmot	1:d0dfbce63a89	1847	*/
elmot	1:d0dfbce63a89	1848
elmot	1:d0dfbce63a89	1849	/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
elmot	1:d0dfbce63a89	1850	* @brief QSPI control and State functions
elmot	1:d0dfbce63a89	1851	*
elmot	1:d0dfbce63a89	1852	@verbatim
elmot	1:d0dfbce63a89	1853	===============================================================================
elmot	1:d0dfbce63a89	1854	##### Peripheral Control and State functions #####
elmot	1:d0dfbce63a89	1855	===============================================================================
elmot	1:d0dfbce63a89	1856	[..]
elmot	1:d0dfbce63a89	1857	This subsection provides a set of functions allowing to :
elmot	1:d0dfbce63a89	1858	(+) Check in run-time the state of the driver.
elmot	1:d0dfbce63a89	1859	(+) Check the error code set during last operation.
elmot	1:d0dfbce63a89	1860	(+) Abort any operation.
elmot	1:d0dfbce63a89	1861
elmot	1:d0dfbce63a89	1862
elmot	1:d0dfbce63a89	1863	@endverbatim
elmot	1:d0dfbce63a89	1864	* @{
elmot	1:d0dfbce63a89	1865	*/
elmot	1:d0dfbce63a89	1866
elmot	1:d0dfbce63a89	1867	/**
elmot	1:d0dfbce63a89	1868	* @brief Return the QSPI handle state.
elmot	1:d0dfbce63a89	1869	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1870	* @retval HAL state
elmot	1:d0dfbce63a89	1871	*/
elmot	1:d0dfbce63a89	1872	HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	1873	{
elmot	1:d0dfbce63a89	1874	/* Return QSPI handle state */
elmot	1:d0dfbce63a89	1875	return hqspi->State;
elmot	1:d0dfbce63a89	1876	}
elmot	1:d0dfbce63a89	1877
elmot	1:d0dfbce63a89	1878	/**
elmot	1:d0dfbce63a89	1879	* @brief Return the QSPI error code.
elmot	1:d0dfbce63a89	1880	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1881	* @retval QSPI Error Code
elmot	1:d0dfbce63a89	1882	*/
elmot	1:d0dfbce63a89	1883	uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	1884	{
elmot	1:d0dfbce63a89	1885	return hqspi->ErrorCode;
elmot	1:d0dfbce63a89	1886	}
elmot	1:d0dfbce63a89	1887
elmot	1:d0dfbce63a89	1888	/**
elmot	1:d0dfbce63a89	1889	* @brief Abort the current transmission.
elmot	1:d0dfbce63a89	1890	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1891	* @retval HAL status
elmot	1:d0dfbce63a89	1892	*/
elmot	1:d0dfbce63a89	1893	HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	1894	{
elmot	1:d0dfbce63a89	1895	HAL_StatusTypeDef status = HAL_OK;
elmot	1:d0dfbce63a89	1896	uint32_t tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	1897
elmot	1:d0dfbce63a89	1898	/* Check if the state is in one of the busy states */
elmot	1:d0dfbce63a89	1899	if ((hqspi->State & 0x2) != 0)
elmot	1:d0dfbce63a89	1900	{
elmot	1:d0dfbce63a89	1901	/* Process unlocked */
elmot	1:d0dfbce63a89	1902	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1903
elmot	1:d0dfbce63a89	1904	if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
elmot	1:d0dfbce63a89	1905	{
elmot	1:d0dfbce63a89	1906	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
elmot	1:d0dfbce63a89	1907	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
elmot	1:d0dfbce63a89	1908
elmot	1:d0dfbce63a89	1909	/* Abort DMA channel */
elmot	1:d0dfbce63a89	1910	status = HAL_DMA_Abort(hqspi->hdma);
elmot	1:d0dfbce63a89	1911	if(status != HAL_OK)
elmot	1:d0dfbce63a89	1912	{
elmot	1:d0dfbce63a89	1913	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
elmot	1:d0dfbce63a89	1914	}
elmot	1:d0dfbce63a89	1915	}
elmot	1:d0dfbce63a89	1916
elmot	1:d0dfbce63a89	1917	/* Configure QSPI: CR register with Abort request */
elmot	1:d0dfbce63a89	1918	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
elmot	1:d0dfbce63a89	1919
elmot	1:d0dfbce63a89	1920	/* Wait until TC flag is set to go back in idle state */
elmot	1:d0dfbce63a89	1921	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
elmot	1:d0dfbce63a89	1922
elmot	1:d0dfbce63a89	1923	if(status == HAL_OK)
elmot	1:d0dfbce63a89	1924	{
elmot	1:d0dfbce63a89	1925	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
elmot	1:d0dfbce63a89	1926
elmot	1:d0dfbce63a89	1927	/* Wait until BUSY flag is reset */
elmot	1:d0dfbce63a89	1928	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
elmot	1:d0dfbce63a89	1929	}
elmot	1:d0dfbce63a89	1930
elmot	1:d0dfbce63a89	1931	if (status == HAL_OK)
elmot	1:d0dfbce63a89	1932	{
elmot	1:d0dfbce63a89	1933	/* Update state */
elmot	1:d0dfbce63a89	1934	hqspi->State = HAL_QSPI_STATE_READY;
elmot	1:d0dfbce63a89	1935	}
elmot	1:d0dfbce63a89	1936	}
elmot	1:d0dfbce63a89	1937
elmot	1:d0dfbce63a89	1938	return status;
elmot	1:d0dfbce63a89	1939	}
elmot	1:d0dfbce63a89	1940
elmot	1:d0dfbce63a89	1941	/**
elmot	1:d0dfbce63a89	1942	* @brief Abort the current transmission (non-blocking function)
elmot	1:d0dfbce63a89	1943	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	1944	* @retval HAL status
elmot	1:d0dfbce63a89	1945	*/
elmot	1:d0dfbce63a89	1946	HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	1947	{
elmot	1:d0dfbce63a89	1948	HAL_StatusTypeDef status = HAL_OK;
elmot	1:d0dfbce63a89	1949
elmot	1:d0dfbce63a89	1950	/* Check if the state is in one of the busy states */
elmot	1:d0dfbce63a89	1951	if ((hqspi->State & 0x2) != 0)
elmot	1:d0dfbce63a89	1952	{
elmot	1:d0dfbce63a89	1953	/* Process unlocked */
elmot	1:d0dfbce63a89	1954	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	1955
elmot	1:d0dfbce63a89	1956	/* Update QSPI state */
elmot	1:d0dfbce63a89	1957	hqspi->State = HAL_QSPI_STATE_ABORT;
elmot	1:d0dfbce63a89	1958
elmot	1:d0dfbce63a89	1959	/* Disable all interrupts */
elmot	1:d0dfbce63a89	1960	__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO \| QSPI_IT_SM \| QSPI_IT_FT \| QSPI_IT_TC \| QSPI_IT_TE));
elmot	1:d0dfbce63a89	1961
elmot	1:d0dfbce63a89	1962	if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
elmot	1:d0dfbce63a89	1963	{
elmot	1:d0dfbce63a89	1964	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
elmot	1:d0dfbce63a89	1965	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
elmot	1:d0dfbce63a89	1966
elmot	1:d0dfbce63a89	1967	/* Abort DMA channel */
elmot	1:d0dfbce63a89	1968	hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
elmot	1:d0dfbce63a89	1969	HAL_DMA_Abort_IT(hqspi->hdma);
elmot	1:d0dfbce63a89	1970	}
elmot	1:d0dfbce63a89	1971	else
elmot	1:d0dfbce63a89	1972	{
elmot	1:d0dfbce63a89	1973	/* Clear interrupt */
elmot	1:d0dfbce63a89	1974	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
elmot	1:d0dfbce63a89	1975
elmot	1:d0dfbce63a89	1976	/* Enable the QSPI Transfer Complete Interrupt */
elmot	1:d0dfbce63a89	1977	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
elmot	1:d0dfbce63a89	1978
elmot	1:d0dfbce63a89	1979	/* Configure QSPI: CR register with Abort request */
elmot	1:d0dfbce63a89	1980	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
elmot	1:d0dfbce63a89	1981	}
elmot	1:d0dfbce63a89	1982	}
elmot	1:d0dfbce63a89	1983	return status;
elmot	1:d0dfbce63a89	1984	}
elmot	1:d0dfbce63a89	1985
elmot	1:d0dfbce63a89	1986	/** @brief Set QSPI timeout.
elmot	1:d0dfbce63a89	1987	* @param hqspi: QSPI handle.
elmot	1:d0dfbce63a89	1988	* @param Timeout: Timeout for the QSPI memory access.
elmot	1:d0dfbce63a89	1989	* @retval None
elmot	1:d0dfbce63a89	1990	*/
elmot	1:d0dfbce63a89	1991	void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
elmot	1:d0dfbce63a89	1992	{
elmot	1:d0dfbce63a89	1993	hqspi->Timeout = Timeout;
elmot	1:d0dfbce63a89	1994	}
elmot	1:d0dfbce63a89	1995
elmot	1:d0dfbce63a89	1996	/** @brief Set QSPI Fifo threshold.
elmot	1:d0dfbce63a89	1997	* @param hqspi: QSPI handle.
elmot	1:d0dfbce63a89	1998	* @param Threshold: Threshold of the Fifo (value between 1 and 16).
elmot	1:d0dfbce63a89	1999	* @retval HAL status
elmot	1:d0dfbce63a89	2000	*/
elmot	1:d0dfbce63a89	2001	HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
elmot	1:d0dfbce63a89	2002	{
elmot	1:d0dfbce63a89	2003	HAL_StatusTypeDef status = HAL_OK;
elmot	1:d0dfbce63a89	2004
elmot	1:d0dfbce63a89	2005	/* Process locked */
elmot	1:d0dfbce63a89	2006	__HAL_LOCK(hqspi);
elmot	1:d0dfbce63a89	2007
elmot	1:d0dfbce63a89	2008	if(hqspi->State == HAL_QSPI_STATE_READY)
elmot	1:d0dfbce63a89	2009	{
elmot	1:d0dfbce63a89	2010	/* Synchronize init structure with new FIFO threshold value */
elmot	1:d0dfbce63a89	2011	hqspi->Init.FifoThreshold = Threshold;
elmot	1:d0dfbce63a89	2012
elmot	1:d0dfbce63a89	2013	/* Configure QSPI FIFO Threshold */
elmot	1:d0dfbce63a89	2014	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
elmot	1:d0dfbce63a89	2015	((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
elmot	1:d0dfbce63a89	2016	}
elmot	1:d0dfbce63a89	2017	else
elmot	1:d0dfbce63a89	2018	{
elmot	1:d0dfbce63a89	2019	status = HAL_BUSY;
elmot	1:d0dfbce63a89	2020	}
elmot	1:d0dfbce63a89	2021
elmot	1:d0dfbce63a89	2022	/* Process unlocked */
elmot	1:d0dfbce63a89	2023	__HAL_UNLOCK(hqspi);
elmot	1:d0dfbce63a89	2024
elmot	1:d0dfbce63a89	2025	/* Return function status */
elmot	1:d0dfbce63a89	2026	return status;
elmot	1:d0dfbce63a89	2027	}
elmot	1:d0dfbce63a89	2028
elmot	1:d0dfbce63a89	2029	/** @brief Get QSPI Fifo threshold.
elmot	1:d0dfbce63a89	2030	* @param hqspi: QSPI handle.
elmot	1:d0dfbce63a89	2031	* @retval Fifo threshold (value between 1 and 16)
elmot	1:d0dfbce63a89	2032	*/
elmot	1:d0dfbce63a89	2033	uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
elmot	1:d0dfbce63a89	2034	{
elmot	1:d0dfbce63a89	2035	return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1);
elmot	1:d0dfbce63a89	2036	}
elmot	1:d0dfbce63a89	2037
elmot	1:d0dfbce63a89	2038	/**
elmot	1:d0dfbce63a89	2039	* @}
elmot	1:d0dfbce63a89	2040	*/
elmot	1:d0dfbce63a89	2041
elmot	1:d0dfbce63a89	2042	/**
elmot	1:d0dfbce63a89	2043	* @brief DMA QSPI receive process complete callback.
elmot	1:d0dfbce63a89	2044	* @param hdma: DMA handle
elmot	1:d0dfbce63a89	2045	* @retval None
elmot	1:d0dfbce63a89	2046	*/
elmot	1:d0dfbce63a89	2047	static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
elmot	1:d0dfbce63a89	2048	{
elmot	1:d0dfbce63a89	2049	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elmot	1:d0dfbce63a89	2050	hqspi->RxXferCount = 0;
elmot	1:d0dfbce63a89	2051
elmot	1:d0dfbce63a89	2052	/* Enable the QSPI transfer complete Interrupt */
elmot	1:d0dfbce63a89	2053	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
elmot	1:d0dfbce63a89	2054	}
elmot	1:d0dfbce63a89	2055
elmot	1:d0dfbce63a89	2056	/**
elmot	1:d0dfbce63a89	2057	* @brief DMA QSPI transmit process complete callback.
elmot	1:d0dfbce63a89	2058	* @param hdma: DMA handle
elmot	1:d0dfbce63a89	2059	* @retval None
elmot	1:d0dfbce63a89	2060	*/
elmot	1:d0dfbce63a89	2061	static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
elmot	1:d0dfbce63a89	2062	{
elmot	1:d0dfbce63a89	2063	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elmot	1:d0dfbce63a89	2064	hqspi->TxXferCount = 0;
elmot	1:d0dfbce63a89	2065
elmot	1:d0dfbce63a89	2066	/* Enable the QSPI transfer complete Interrupt */
elmot	1:d0dfbce63a89	2067	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
elmot	1:d0dfbce63a89	2068	}
elmot	1:d0dfbce63a89	2069
elmot	1:d0dfbce63a89	2070	/**
elmot	1:d0dfbce63a89	2071	* @brief DMA QSPI receive process half complete callback.
elmot	1:d0dfbce63a89	2072	* @param hdma : DMA handle
elmot	1:d0dfbce63a89	2073	* @retval None
elmot	1:d0dfbce63a89	2074	*/
elmot	1:d0dfbce63a89	2075	static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
elmot	1:d0dfbce63a89	2076	{
elmot	1:d0dfbce63a89	2077	QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
elmot	1:d0dfbce63a89	2078
elmot	1:d0dfbce63a89	2079	HAL_QSPI_RxHalfCpltCallback(hqspi);
elmot	1:d0dfbce63a89	2080	}
elmot	1:d0dfbce63a89	2081
elmot	1:d0dfbce63a89	2082	/**
elmot	1:d0dfbce63a89	2083	* @brief DMA QSPI transmit process half complete callback.
elmot	1:d0dfbce63a89	2084	* @param hdma : DMA handle
elmot	1:d0dfbce63a89	2085	* @retval None
elmot	1:d0dfbce63a89	2086	*/
elmot	1:d0dfbce63a89	2087	static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
elmot	1:d0dfbce63a89	2088	{
elmot	1:d0dfbce63a89	2089	QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
elmot	1:d0dfbce63a89	2090
elmot	1:d0dfbce63a89	2091	HAL_QSPI_TxHalfCpltCallback(hqspi);
elmot	1:d0dfbce63a89	2092	}
elmot	1:d0dfbce63a89	2093
elmot	1:d0dfbce63a89	2094	/**
elmot	1:d0dfbce63a89	2095	* @brief DMA QSPI communication error callback.
elmot	1:d0dfbce63a89	2096	* @param hdma: DMA handle
elmot	1:d0dfbce63a89	2097	* @retval None
elmot	1:d0dfbce63a89	2098	*/
elmot	1:d0dfbce63a89	2099	static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
elmot	1:d0dfbce63a89	2100	{
elmot	1:d0dfbce63a89	2101	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elmot	1:d0dfbce63a89	2102
elmot	1:d0dfbce63a89	2103	hqspi->RxXferCount = 0;
elmot	1:d0dfbce63a89	2104	hqspi->TxXferCount = 0;
elmot	1:d0dfbce63a89	2105	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
elmot	1:d0dfbce63a89	2106
elmot	1:d0dfbce63a89	2107	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
elmot	1:d0dfbce63a89	2108	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
elmot	1:d0dfbce63a89	2109
elmot	1:d0dfbce63a89	2110	/* Abort the QSPI */
elmot	1:d0dfbce63a89	2111	HAL_QSPI_Abort_IT(hqspi);
elmot	1:d0dfbce63a89	2112	}
elmot	1:d0dfbce63a89	2113
elmot	1:d0dfbce63a89	2114	/**
elmot	1:d0dfbce63a89	2115	* @brief DMA QSPI abort complete callback.
elmot	1:d0dfbce63a89	2116	* @param hdma: DMA handle
elmot	1:d0dfbce63a89	2117	* @retval None
elmot	1:d0dfbce63a89	2118	*/
elmot	1:d0dfbce63a89	2119	static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
elmot	1:d0dfbce63a89	2120	{
elmot	1:d0dfbce63a89	2121	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elmot	1:d0dfbce63a89	2122
elmot	1:d0dfbce63a89	2123	hqspi->RxXferCount = 0;
elmot	1:d0dfbce63a89	2124	hqspi->TxXferCount = 0;
elmot	1:d0dfbce63a89	2125
elmot	1:d0dfbce63a89	2126	if(hqspi->State == HAL_QSPI_STATE_ABORT)
elmot	1:d0dfbce63a89	2127	{
elmot	1:d0dfbce63a89	2128	/* DMA Abort called by QSPI abort */
elmot	1:d0dfbce63a89	2129	/* Clear interrupt */
elmot	1:d0dfbce63a89	2130	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
elmot	1:d0dfbce63a89	2131
elmot	1:d0dfbce63a89	2132	/* Enable the QSPI Transfer Complete Interrupt */
elmot	1:d0dfbce63a89	2133	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
elmot	1:d0dfbce63a89	2134
elmot	1:d0dfbce63a89	2135	/* Configure QSPI: CR register with Abort request */
elmot	1:d0dfbce63a89	2136	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
elmot	1:d0dfbce63a89	2137	}
elmot	1:d0dfbce63a89	2138	else
elmot	1:d0dfbce63a89	2139	{
elmot	1:d0dfbce63a89	2140	/* DMA Abort called due to a transfer error interrupt */
elmot	1:d0dfbce63a89	2141	/* Change state of QSPI */
elmot	1:d0dfbce63a89	2142	hqspi->State = HAL_QSPI_STATE_READY;
elmot	1:d0dfbce63a89	2143
elmot	1:d0dfbce63a89	2144	/* Error callback */
elmot	1:d0dfbce63a89	2145	HAL_QSPI_ErrorCallback(hqspi);
elmot	1:d0dfbce63a89	2146	}
elmot	1:d0dfbce63a89	2147	}
elmot	1:d0dfbce63a89	2148	/**
elmot	1:d0dfbce63a89	2149	* @brief Wait for a flag state until timeout.
elmot	1:d0dfbce63a89	2150	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	2151	* @param Flag: Flag checked
elmot	1:d0dfbce63a89	2152	* @param State: Value of the flag expected
elmot	1:d0dfbce63a89	2153	* @param Timeout: Duration of the timeout
elmot	1:d0dfbce63a89	2154	* @param Tickstart Tick start value
elmot	1:d0dfbce63a89	2155	* @retval HAL status
elmot	1:d0dfbce63a89	2156	*/
elmot	1:d0dfbce63a89	2157	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
elmot	1:d0dfbce63a89	2158	FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
elmot	1:d0dfbce63a89	2159	{
elmot	1:d0dfbce63a89	2160	/* Wait until flag is in expected state */
elmot	1:d0dfbce63a89	2161	while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
elmot	1:d0dfbce63a89	2162	{
elmot	1:d0dfbce63a89	2163	/* Check for the Timeout */
elmot	1:d0dfbce63a89	2164	if (Timeout != HAL_MAX_DELAY)
elmot	1:d0dfbce63a89	2165	{
elmot	1:d0dfbce63a89	2166	if((Timeout == 0) \|\| ((HAL_GetTick() - Tickstart) > Timeout))
elmot	1:d0dfbce63a89	2167	{
elmot	1:d0dfbce63a89	2168	hqspi->State = HAL_QSPI_STATE_ERROR;
elmot	1:d0dfbce63a89	2169	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TIMEOUT;
elmot	1:d0dfbce63a89	2170
elmot	1:d0dfbce63a89	2171	return HAL_ERROR;
elmot	1:d0dfbce63a89	2172	}
elmot	1:d0dfbce63a89	2173	}
elmot	1:d0dfbce63a89	2174	}
elmot	1:d0dfbce63a89	2175	return HAL_OK;
elmot	1:d0dfbce63a89	2176	}
elmot	1:d0dfbce63a89	2177
elmot	1:d0dfbce63a89	2178	/**
elmot	1:d0dfbce63a89	2179	* @brief Configure the communication registers.
elmot	1:d0dfbce63a89	2180	* @param hqspi: QSPI handle
elmot	1:d0dfbce63a89	2181	* @param cmd: structure that contains the command configuration information
elmot	1:d0dfbce63a89	2182	* @param FunctionalMode: functional mode to configured
elmot	1:d0dfbce63a89	2183	* This parameter can be one of the following values:
elmot	1:d0dfbce63a89	2184	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
elmot	1:d0dfbce63a89	2185	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
elmot	1:d0dfbce63a89	2186	* @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
elmot	1:d0dfbce63a89	2187	* @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
elmot	1:d0dfbce63a89	2188	* @retval None
elmot	1:d0dfbce63a89	2189	*/
elmot	1:d0dfbce63a89	2190	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode)
elmot	1:d0dfbce63a89	2191	{
elmot	1:d0dfbce63a89	2192	assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
elmot	1:d0dfbce63a89	2193
elmot	1:d0dfbce63a89	2194	if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
elmot	1:d0dfbce63a89	2195	{
elmot	1:d0dfbce63a89	2196	/* Configure QSPI: DLR register with the number of data to read or write */
elmot	1:d0dfbce63a89	2197	WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
elmot	1:d0dfbce63a89	2198	}
elmot	1:d0dfbce63a89	2199
elmot	1:d0dfbce63a89	2200	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
elmot	1:d0dfbce63a89	2201	{
elmot	1:d0dfbce63a89	2202	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
elmot	1:d0dfbce63a89	2203	{
elmot	1:d0dfbce63a89	2204	/* Configure QSPI: ABR register with alternate bytes value */
elmot	1:d0dfbce63a89	2205	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
elmot	1:d0dfbce63a89	2206
elmot	1:d0dfbce63a89	2207	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
elmot	1:d0dfbce63a89	2208	{
elmot	1:d0dfbce63a89	2209	/---- Command with instruction, address and alternate bytes ----/
elmot	1:d0dfbce63a89	2210	/* Configure QSPI: CCR register with all communications parameters */
elmot	1:d0dfbce63a89	2211	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
elmot	1:d0dfbce63a89	2212	cmd->DataMode \| (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) \|
elmot	1:d0dfbce63a89	2213	cmd->AlternateBytesSize \| cmd->AlternateByteMode \|
elmot	1:d0dfbce63a89	2214	cmd->AddressSize \| cmd->AddressMode \| cmd->InstructionMode \|
elmot	1:d0dfbce63a89	2215	cmd->Instruction \| FunctionalMode));
elmot	1:d0dfbce63a89	2216
elmot	1:d0dfbce63a89	2217	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
elmot	1:d0dfbce63a89	2218	{
elmot	1:d0dfbce63a89	2219	/* Configure QSPI: AR register with address value */
elmot	1:d0dfbce63a89	2220	WRITE_REG(hqspi->Instance->AR, cmd->Address);
elmot	1:d0dfbce63a89	2221	}
elmot	1:d0dfbce63a89	2222	}
elmot	1:d0dfbce63a89	2223	else
elmot	1:d0dfbce63a89	2224	{
elmot	1:d0dfbce63a89	2225	/---- Command with instruction and alternate bytes ----/
elmot	1:d0dfbce63a89	2226	/* Configure QSPI: CCR register with all communications parameters */
elmot	1:d0dfbce63a89	2227	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
elmot	1:d0dfbce63a89	2228	cmd->DataMode \| (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) \|
elmot	1:d0dfbce63a89	2229	cmd->AlternateBytesSize \| cmd->AlternateByteMode \|
elmot	1:d0dfbce63a89	2230	cmd->AddressMode \| cmd->InstructionMode \|
elmot	1:d0dfbce63a89	2231	cmd->Instruction \| FunctionalMode));
elmot	1:d0dfbce63a89	2232	}
elmot	1:d0dfbce63a89	2233	}
elmot	1:d0dfbce63a89	2234	else
elmot	1:d0dfbce63a89	2235	{
elmot	1:d0dfbce63a89	2236	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
elmot	1:d0dfbce63a89	2237	{
elmot	1:d0dfbce63a89	2238	/---- Command with instruction and address ----/
elmot	1:d0dfbce63a89	2239	/* Configure QSPI: CCR register with all communications parameters */
elmot	1:d0dfbce63a89	2240	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
elmot	1:d0dfbce63a89	2241	cmd->DataMode \| (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) \|
elmot	1:d0dfbce63a89	2242	cmd->AlternateByteMode \| cmd->AddressSize \| cmd->AddressMode \|
elmot	1:d0dfbce63a89	2243	cmd->InstructionMode \| cmd->Instruction \| FunctionalMode));
elmot	1:d0dfbce63a89	2244
elmot	1:d0dfbce63a89	2245	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
elmot	1:d0dfbce63a89	2246	{
elmot	1:d0dfbce63a89	2247	/* Configure QSPI: AR register with address value */
elmot	1:d0dfbce63a89	2248	WRITE_REG(hqspi->Instance->AR, cmd->Address);
elmot	1:d0dfbce63a89	2249	}
elmot	1:d0dfbce63a89	2250	}
elmot	1:d0dfbce63a89	2251	else
elmot	1:d0dfbce63a89	2252	{
elmot	1:d0dfbce63a89	2253	/---- Command with only instruction ----/
elmot	1:d0dfbce63a89	2254	/* Configure QSPI: CCR register with all communications parameters */
elmot	1:d0dfbce63a89	2255	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
elmot	1:d0dfbce63a89	2256	cmd->DataMode \| (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) \|
elmot	1:d0dfbce63a89	2257	cmd->AlternateByteMode \| cmd->AddressMode \|
elmot	1:d0dfbce63a89	2258	cmd->InstructionMode \| cmd->Instruction \| FunctionalMode));
elmot	1:d0dfbce63a89	2259	}
elmot	1:d0dfbce63a89	2260	}
elmot	1:d0dfbce63a89	2261	}
elmot	1:d0dfbce63a89	2262	else
elmot	1:d0dfbce63a89	2263	{
elmot	1:d0dfbce63a89	2264	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
elmot	1:d0dfbce63a89	2265	{
elmot	1:d0dfbce63a89	2266	/* Configure QSPI: ABR register with alternate bytes value */
elmot	1:d0dfbce63a89	2267	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
elmot	1:d0dfbce63a89	2268
elmot	1:d0dfbce63a89	2269	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
elmot	1:d0dfbce63a89	2270	{
elmot	1:d0dfbce63a89	2271	/---- Command with address and alternate bytes ----/
elmot	1:d0dfbce63a89	2272	/* Configure QSPI: CCR register with all communications parameters */
elmot	1:d0dfbce63a89	2273	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
elmot	1:d0dfbce63a89	2274	cmd->DataMode \| (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) \|
elmot	1:d0dfbce63a89	2275	cmd->AlternateBytesSize \| cmd->AlternateByteMode \|
elmot	1:d0dfbce63a89	2276	cmd->AddressSize \| cmd->AddressMode \|
elmot	1:d0dfbce63a89	2277	cmd->InstructionMode \| FunctionalMode));
elmot	1:d0dfbce63a89	2278
elmot	1:d0dfbce63a89	2279	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
elmot	1:d0dfbce63a89	2280	{
elmot	1:d0dfbce63a89	2281	/* Configure QSPI: AR register with address value */
elmot	1:d0dfbce63a89	2282	WRITE_REG(hqspi->Instance->AR, cmd->Address);
elmot	1:d0dfbce63a89	2283	}
elmot	1:d0dfbce63a89	2284	}
elmot	1:d0dfbce63a89	2285	else
elmot	1:d0dfbce63a89	2286	{
elmot	1:d0dfbce63a89	2287	/---- Command with only alternate bytes ----/
elmot	1:d0dfbce63a89	2288	/* Configure QSPI: CCR register with all communications parameters */
elmot	1:d0dfbce63a89	2289	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
elmot	1:d0dfbce63a89	2290	cmd->DataMode \| (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) \|
elmot	1:d0dfbce63a89	2291	cmd->AlternateBytesSize \| cmd->AlternateByteMode \|
elmot	1:d0dfbce63a89	2292	cmd->AddressMode \| cmd->InstructionMode \| FunctionalMode));
elmot	1:d0dfbce63a89	2293	}
elmot	1:d0dfbce63a89	2294	}
elmot	1:d0dfbce63a89	2295	else
elmot	1:d0dfbce63a89	2296	{
elmot	1:d0dfbce63a89	2297	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
elmot	1:d0dfbce63a89	2298	{
elmot	1:d0dfbce63a89	2299	/---- Command with only address ----/
elmot	1:d0dfbce63a89	2300	/* Configure QSPI: CCR register with all communications parameters */
elmot	1:d0dfbce63a89	2301	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
elmot	1:d0dfbce63a89	2302	cmd->DataMode \| (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) \|
elmot	1:d0dfbce63a89	2303	cmd->AlternateByteMode \| cmd->AddressSize \|
elmot	1:d0dfbce63a89	2304	cmd->AddressMode \| cmd->InstructionMode \| FunctionalMode));
elmot	1:d0dfbce63a89	2305
elmot	1:d0dfbce63a89	2306	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
elmot	1:d0dfbce63a89	2307	{
elmot	1:d0dfbce63a89	2308	/* Configure QSPI: AR register with address value */
elmot	1:d0dfbce63a89	2309	WRITE_REG(hqspi->Instance->AR, cmd->Address);
elmot	1:d0dfbce63a89	2310	}
elmot	1:d0dfbce63a89	2311	}
elmot	1:d0dfbce63a89	2312	else
elmot	1:d0dfbce63a89	2313	{
elmot	1:d0dfbce63a89	2314	/---- Command with only data phase ----/
elmot	1:d0dfbce63a89	2315	if (cmd->DataMode != QSPI_DATA_NONE)
elmot	1:d0dfbce63a89	2316	{
elmot	1:d0dfbce63a89	2317	/* Configure QSPI: CCR register with all communications parameters */
elmot	1:d0dfbce63a89	2318	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
elmot	1:d0dfbce63a89	2319	cmd->DataMode \| (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) \|
elmot	1:d0dfbce63a89	2320	cmd->AlternateByteMode \| cmd->AddressMode \|
elmot	1:d0dfbce63a89	2321	cmd->InstructionMode \| FunctionalMode));
elmot	1:d0dfbce63a89	2322	}
elmot	1:d0dfbce63a89	2323	}
elmot	1:d0dfbce63a89	2324	}
elmot	1:d0dfbce63a89	2325	}
elmot	1:d0dfbce63a89	2326	}
elmot	1:d0dfbce63a89	2327
elmot	1:d0dfbce63a89	2328	/**
elmot	1:d0dfbce63a89	2329	* @}
elmot	1:d0dfbce63a89	2330	*/
elmot	1:d0dfbce63a89	2331
elmot	1:d0dfbce63a89	2332	#endif /* HAL_QSPI_MODULE_ENABLED */
elmot	1:d0dfbce63a89	2333	/**
elmot	1:d0dfbce63a89	2334	* @}
elmot	1:d0dfbce63a89	2335	*/
elmot	1:d0dfbce63a89	2336
elmot	1:d0dfbce63a89	2337	/**
elmot	1:d0dfbce63a89	2338	* @}
elmot	1:d0dfbce63a89	2339	*/
elmot	1:d0dfbce63a89	2340
elmot	1:d0dfbce63a89	2341	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	25 Feb 2017
Imports:	20
Forks:	1
Commits:	3
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The code in this repository is Apache licensed.

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HAL_L476/stm32l4xx_hal_qspi.c@1:d0dfbce63a89, 2017-02-24 (annotated)

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