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HAL_L476/stm32l4xx_hal_pwr_ex.c@1:d0dfbce63a89, 2017-02-24 (annotated)
- Committer:
- elmot
- Date:
- Fri Feb 24 21:13:56 2017 +0000
- Revision:
- 1:d0dfbce63a89
Ready-to-copy
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| elmot | 1:d0dfbce63a89 | 1 | /** |
| elmot | 1:d0dfbce63a89 | 2 | ****************************************************************************** |
| elmot | 1:d0dfbce63a89 | 3 | * @file stm32l4xx_hal_pwr_ex.c |
| elmot | 1:d0dfbce63a89 | 4 | * @author MCD Application Team |
| elmot | 1:d0dfbce63a89 | 5 | * @version V1.5.1 |
| elmot | 1:d0dfbce63a89 | 6 | * @date 31-May-2016 |
| elmot | 1:d0dfbce63a89 | 7 | * @brief Extended PWR HAL module driver. |
| elmot | 1:d0dfbce63a89 | 8 | * This file provides firmware functions to manage the following |
| elmot | 1:d0dfbce63a89 | 9 | * functionalities of the Power Controller (PWR) peripheral: |
| elmot | 1:d0dfbce63a89 | 10 | * + Extended Initialization and de-initialization functions |
| elmot | 1:d0dfbce63a89 | 11 | * + Extended Peripheral Control functions |
| elmot | 1:d0dfbce63a89 | 12 | * |
| elmot | 1:d0dfbce63a89 | 13 | ****************************************************************************** |
| elmot | 1:d0dfbce63a89 | 14 | * @attention |
| elmot | 1:d0dfbce63a89 | 15 | * |
| elmot | 1:d0dfbce63a89 | 16 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| elmot | 1:d0dfbce63a89 | 17 | * |
| elmot | 1:d0dfbce63a89 | 18 | * Redistribution and use in source and binary forms, with or without modification, |
| elmot | 1:d0dfbce63a89 | 19 | * are permitted provided that the following conditions are met: |
| elmot | 1:d0dfbce63a89 | 20 | * 1. Redistributions of source code must retain the above copyright notice, |
| elmot | 1:d0dfbce63a89 | 21 | * this list of conditions and the following disclaimer. |
| elmot | 1:d0dfbce63a89 | 22 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| elmot | 1:d0dfbce63a89 | 23 | * this list of conditions and the following disclaimer in the documentation |
| elmot | 1:d0dfbce63a89 | 24 | * and/or other materials provided with the distribution. |
| elmot | 1:d0dfbce63a89 | 25 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| elmot | 1:d0dfbce63a89 | 26 | * may be used to endorse or promote products derived from this software |
| elmot | 1:d0dfbce63a89 | 27 | * without specific prior written permission. |
| elmot | 1:d0dfbce63a89 | 28 | * |
| elmot | 1:d0dfbce63a89 | 29 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| elmot | 1:d0dfbce63a89 | 30 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| elmot | 1:d0dfbce63a89 | 31 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| elmot | 1:d0dfbce63a89 | 32 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| elmot | 1:d0dfbce63a89 | 33 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| elmot | 1:d0dfbce63a89 | 34 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| elmot | 1:d0dfbce63a89 | 35 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| elmot | 1:d0dfbce63a89 | 36 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| elmot | 1:d0dfbce63a89 | 37 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| elmot | 1:d0dfbce63a89 | 38 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| elmot | 1:d0dfbce63a89 | 39 | * |
| elmot | 1:d0dfbce63a89 | 40 | ****************************************************************************** |
| elmot | 1:d0dfbce63a89 | 41 | */ |
| elmot | 1:d0dfbce63a89 | 42 | |
| elmot | 1:d0dfbce63a89 | 43 | /* Includes ------------------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 44 | #include "stm32l4xx_hal.h" |
| elmot | 1:d0dfbce63a89 | 45 | |
| elmot | 1:d0dfbce63a89 | 46 | /** @addtogroup STM32L4xx_HAL_Driver |
| elmot | 1:d0dfbce63a89 | 47 | * @{ |
| elmot | 1:d0dfbce63a89 | 48 | */ |
| elmot | 1:d0dfbce63a89 | 49 | |
| elmot | 1:d0dfbce63a89 | 50 | /** @defgroup PWREx PWREx |
| elmot | 1:d0dfbce63a89 | 51 | * @brief PWR Extended HAL module driver |
| elmot | 1:d0dfbce63a89 | 52 | * @{ |
| elmot | 1:d0dfbce63a89 | 53 | */ |
| elmot | 1:d0dfbce63a89 | 54 | |
| elmot | 1:d0dfbce63a89 | 55 | #ifdef HAL_PWR_MODULE_ENABLED |
| elmot | 1:d0dfbce63a89 | 56 | |
| elmot | 1:d0dfbce63a89 | 57 | /* Private typedef -----------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 58 | /* Private define ------------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 59 | |
| elmot | 1:d0dfbce63a89 | 60 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 61 | #define PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_0|PWR_GPIO_BIT_1) |
| elmot | 1:d0dfbce63a89 | 62 | #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) |
| elmot | 1:d0dfbce63a89 | 63 | #define PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_0|PWR_GPIO_BIT_1|PWR_GPIO_BIT_3) |
| elmot | 1:d0dfbce63a89 | 64 | #endif |
| elmot | 1:d0dfbce63a89 | 65 | |
| elmot | 1:d0dfbce63a89 | 66 | /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines |
| elmot | 1:d0dfbce63a89 | 67 | * @{ |
| elmot | 1:d0dfbce63a89 | 68 | */ |
| elmot | 1:d0dfbce63a89 | 69 | |
| elmot | 1:d0dfbce63a89 | 70 | /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask |
| elmot | 1:d0dfbce63a89 | 71 | * @{ |
| elmot | 1:d0dfbce63a89 | 72 | */ |
| elmot | 1:d0dfbce63a89 | 73 | #define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */ |
| elmot | 1:d0dfbce63a89 | 74 | #define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */ |
| elmot | 1:d0dfbce63a89 | 75 | #define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */ |
| elmot | 1:d0dfbce63a89 | 76 | #define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */ |
| elmot | 1:d0dfbce63a89 | 77 | /** |
| elmot | 1:d0dfbce63a89 | 78 | * @} |
| elmot | 1:d0dfbce63a89 | 79 | */ |
| elmot | 1:d0dfbce63a89 | 80 | |
| elmot | 1:d0dfbce63a89 | 81 | /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value |
| elmot | 1:d0dfbce63a89 | 82 | * @{ |
| elmot | 1:d0dfbce63a89 | 83 | */ |
| elmot | 1:d0dfbce63a89 | 84 | #define PWR_FLAG_SETTING_DELAY_US 50 /*!< Time out value for REGLPF and VOSF flags setting */ |
| elmot | 1:d0dfbce63a89 | 85 | /** |
| elmot | 1:d0dfbce63a89 | 86 | * @} |
| elmot | 1:d0dfbce63a89 | 87 | */ |
| elmot | 1:d0dfbce63a89 | 88 | |
| elmot | 1:d0dfbce63a89 | 89 | |
| elmot | 1:d0dfbce63a89 | 90 | |
| elmot | 1:d0dfbce63a89 | 91 | /** |
| elmot | 1:d0dfbce63a89 | 92 | * @} |
| elmot | 1:d0dfbce63a89 | 93 | */ |
| elmot | 1:d0dfbce63a89 | 94 | |
| elmot | 1:d0dfbce63a89 | 95 | |
| elmot | 1:d0dfbce63a89 | 96 | |
| elmot | 1:d0dfbce63a89 | 97 | /* Private macro -------------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 98 | /* Private variables ---------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 99 | /* Private function prototypes -----------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 100 | /* Exported functions --------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 101 | |
| elmot | 1:d0dfbce63a89 | 102 | /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions |
| elmot | 1:d0dfbce63a89 | 103 | * @{ |
| elmot | 1:d0dfbce63a89 | 104 | */ |
| elmot | 1:d0dfbce63a89 | 105 | |
| elmot | 1:d0dfbce63a89 | 106 | /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions |
| elmot | 1:d0dfbce63a89 | 107 | * @brief Extended Peripheral Control functions |
| elmot | 1:d0dfbce63a89 | 108 | * |
| elmot | 1:d0dfbce63a89 | 109 | @verbatim |
| elmot | 1:d0dfbce63a89 | 110 | =============================================================================== |
| elmot | 1:d0dfbce63a89 | 111 | ##### Extended Peripheral Initialization and de-initialization functions ##### |
| elmot | 1:d0dfbce63a89 | 112 | =============================================================================== |
| elmot | 1:d0dfbce63a89 | 113 | [..] |
| elmot | 1:d0dfbce63a89 | 114 | |
| elmot | 1:d0dfbce63a89 | 115 | @endverbatim |
| elmot | 1:d0dfbce63a89 | 116 | * @{ |
| elmot | 1:d0dfbce63a89 | 117 | */ |
| elmot | 1:d0dfbce63a89 | 118 | |
| elmot | 1:d0dfbce63a89 | 119 | |
| elmot | 1:d0dfbce63a89 | 120 | /** |
| elmot | 1:d0dfbce63a89 | 121 | * @brief Return Voltage Scaling Range. |
| elmot | 1:d0dfbce63a89 | 122 | * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2) |
| elmot | 1:d0dfbce63a89 | 123 | */ |
| elmot | 1:d0dfbce63a89 | 124 | uint32_t HAL_PWREx_GetVoltageRange(void) |
| elmot | 1:d0dfbce63a89 | 125 | { |
| elmot | 1:d0dfbce63a89 | 126 | return (PWR->CR1 & PWR_CR1_VOS); |
| elmot | 1:d0dfbce63a89 | 127 | } |
| elmot | 1:d0dfbce63a89 | 128 | |
| elmot | 1:d0dfbce63a89 | 129 | |
| elmot | 1:d0dfbce63a89 | 130 | |
| elmot | 1:d0dfbce63a89 | 131 | /** |
| elmot | 1:d0dfbce63a89 | 132 | * @brief Configure the main internal regulator output voltage. |
| elmot | 1:d0dfbce63a89 | 133 | * @param VoltageScaling: specifies the regulator output voltage to achieve |
| elmot | 1:d0dfbce63a89 | 134 | * a tradeoff between performance and power consumption. |
| elmot | 1:d0dfbce63a89 | 135 | * This parameter can be one of the following values: |
| elmot | 1:d0dfbce63a89 | 136 | * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, |
| elmot | 1:d0dfbce63a89 | 137 | * typical output voltage at 1.2 V, |
| elmot | 1:d0dfbce63a89 | 138 | * system frequency up to 80 MHz. |
| elmot | 1:d0dfbce63a89 | 139 | * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, |
| elmot | 1:d0dfbce63a89 | 140 | * typical output voltage at 1.0 V, |
| elmot | 1:d0dfbce63a89 | 141 | * system frequency up to 26 MHz. |
| elmot | 1:d0dfbce63a89 | 142 | * @note When moving from Range 1 to Range 2, the system frequency must be decreased to |
| elmot | 1:d0dfbce63a89 | 143 | * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API. |
| elmot | 1:d0dfbce63a89 | 144 | * When moving from Range 2 to Range 1, the system frequency can be increased to |
| elmot | 1:d0dfbce63a89 | 145 | * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. |
| elmot | 1:d0dfbce63a89 | 146 | * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be |
| elmot | 1:d0dfbce63a89 | 147 | * cleared before returning the status. If the flag is not cleared within |
| elmot | 1:d0dfbce63a89 | 148 | * 50 microseconds, HAL_TIMEOUT status is reported. |
| elmot | 1:d0dfbce63a89 | 149 | * @retval HAL Status |
| elmot | 1:d0dfbce63a89 | 150 | */ |
| elmot | 1:d0dfbce63a89 | 151 | HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) |
| elmot | 1:d0dfbce63a89 | 152 | { |
| elmot | 1:d0dfbce63a89 | 153 | uint32_t wait_loop_index = 0; |
| elmot | 1:d0dfbce63a89 | 154 | |
| elmot | 1:d0dfbce63a89 | 155 | assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); |
| elmot | 1:d0dfbce63a89 | 156 | |
| elmot | 1:d0dfbce63a89 | 157 | /* If Set Range 1 */ |
| elmot | 1:d0dfbce63a89 | 158 | if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) |
| elmot | 1:d0dfbce63a89 | 159 | { |
| elmot | 1:d0dfbce63a89 | 160 | if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1) |
| elmot | 1:d0dfbce63a89 | 161 | { |
| elmot | 1:d0dfbce63a89 | 162 | /* Set Range 1 */ |
| elmot | 1:d0dfbce63a89 | 163 | MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); |
| elmot | 1:d0dfbce63a89 | 164 | |
| elmot | 1:d0dfbce63a89 | 165 | /* Wait until VOSF is cleared */ |
| elmot | 1:d0dfbce63a89 | 166 | wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); |
| elmot | 1:d0dfbce63a89 | 167 | while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) |
| elmot | 1:d0dfbce63a89 | 168 | { |
| elmot | 1:d0dfbce63a89 | 169 | wait_loop_index--; |
| elmot | 1:d0dfbce63a89 | 170 | } |
| elmot | 1:d0dfbce63a89 | 171 | if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) |
| elmot | 1:d0dfbce63a89 | 172 | { |
| elmot | 1:d0dfbce63a89 | 173 | return HAL_TIMEOUT; |
| elmot | 1:d0dfbce63a89 | 174 | } |
| elmot | 1:d0dfbce63a89 | 175 | } |
| elmot | 1:d0dfbce63a89 | 176 | } |
| elmot | 1:d0dfbce63a89 | 177 | else |
| elmot | 1:d0dfbce63a89 | 178 | { |
| elmot | 1:d0dfbce63a89 | 179 | if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2) |
| elmot | 1:d0dfbce63a89 | 180 | { |
| elmot | 1:d0dfbce63a89 | 181 | /* Set Range 2 */ |
| elmot | 1:d0dfbce63a89 | 182 | MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); |
| elmot | 1:d0dfbce63a89 | 183 | /* No need to wait for VOSF to be cleared for this transition */ |
| elmot | 1:d0dfbce63a89 | 184 | } |
| elmot | 1:d0dfbce63a89 | 185 | } |
| elmot | 1:d0dfbce63a89 | 186 | |
| elmot | 1:d0dfbce63a89 | 187 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 188 | } |
| elmot | 1:d0dfbce63a89 | 189 | |
| elmot | 1:d0dfbce63a89 | 190 | |
| elmot | 1:d0dfbce63a89 | 191 | /** |
| elmot | 1:d0dfbce63a89 | 192 | * @brief Enable battery charging. |
| elmot | 1:d0dfbce63a89 | 193 | * When VDD is present, charge the external battery on VBAT thru an internal resistor. |
| elmot | 1:d0dfbce63a89 | 194 | * @param ResistorSelection: specifies the resistor impedance. |
| elmot | 1:d0dfbce63a89 | 195 | * This parameter can be one of the following values: |
| elmot | 1:d0dfbce63a89 | 196 | * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor |
| elmot | 1:d0dfbce63a89 | 197 | * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor |
| elmot | 1:d0dfbce63a89 | 198 | * @retval None |
| elmot | 1:d0dfbce63a89 | 199 | */ |
| elmot | 1:d0dfbce63a89 | 200 | void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) |
| elmot | 1:d0dfbce63a89 | 201 | { |
| elmot | 1:d0dfbce63a89 | 202 | assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection)); |
| elmot | 1:d0dfbce63a89 | 203 | |
| elmot | 1:d0dfbce63a89 | 204 | /* Specify resistor selection */ |
| elmot | 1:d0dfbce63a89 | 205 | MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection); |
| elmot | 1:d0dfbce63a89 | 206 | |
| elmot | 1:d0dfbce63a89 | 207 | /* Enable battery charging */ |
| elmot | 1:d0dfbce63a89 | 208 | SET_BIT(PWR->CR4, PWR_CR4_VBE); |
| elmot | 1:d0dfbce63a89 | 209 | } |
| elmot | 1:d0dfbce63a89 | 210 | |
| elmot | 1:d0dfbce63a89 | 211 | |
| elmot | 1:d0dfbce63a89 | 212 | /** |
| elmot | 1:d0dfbce63a89 | 213 | * @brief Disable battery charging. |
| elmot | 1:d0dfbce63a89 | 214 | * @retval None |
| elmot | 1:d0dfbce63a89 | 215 | */ |
| elmot | 1:d0dfbce63a89 | 216 | void HAL_PWREx_DisableBatteryCharging(void) |
| elmot | 1:d0dfbce63a89 | 217 | { |
| elmot | 1:d0dfbce63a89 | 218 | CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); |
| elmot | 1:d0dfbce63a89 | 219 | } |
| elmot | 1:d0dfbce63a89 | 220 | |
| elmot | 1:d0dfbce63a89 | 221 | |
| elmot | 1:d0dfbce63a89 | 222 | #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 223 | /** |
| elmot | 1:d0dfbce63a89 | 224 | * @brief Enable VDDUSB supply. |
| elmot | 1:d0dfbce63a89 | 225 | * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. |
| elmot | 1:d0dfbce63a89 | 226 | * @retval None |
| elmot | 1:d0dfbce63a89 | 227 | */ |
| elmot | 1:d0dfbce63a89 | 228 | void HAL_PWREx_EnableVddUSB(void) |
| elmot | 1:d0dfbce63a89 | 229 | { |
| elmot | 1:d0dfbce63a89 | 230 | SET_BIT(PWR->CR2, PWR_CR2_USV); |
| elmot | 1:d0dfbce63a89 | 231 | } |
| elmot | 1:d0dfbce63a89 | 232 | |
| elmot | 1:d0dfbce63a89 | 233 | |
| elmot | 1:d0dfbce63a89 | 234 | /** |
| elmot | 1:d0dfbce63a89 | 235 | * @brief Disable VDDUSB supply. |
| elmot | 1:d0dfbce63a89 | 236 | * @retval None |
| elmot | 1:d0dfbce63a89 | 237 | */ |
| elmot | 1:d0dfbce63a89 | 238 | void HAL_PWREx_DisableVddUSB(void) |
| elmot | 1:d0dfbce63a89 | 239 | { |
| elmot | 1:d0dfbce63a89 | 240 | CLEAR_BIT(PWR->CR2, PWR_CR2_USV); |
| elmot | 1:d0dfbce63a89 | 241 | } |
| elmot | 1:d0dfbce63a89 | 242 | #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ |
| elmot | 1:d0dfbce63a89 | 243 | |
| elmot | 1:d0dfbce63a89 | 244 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 245 | /** |
| elmot | 1:d0dfbce63a89 | 246 | * @brief Enable VDDIO2 supply. |
| elmot | 1:d0dfbce63a89 | 247 | * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present. |
| elmot | 1:d0dfbce63a89 | 248 | * @retval None |
| elmot | 1:d0dfbce63a89 | 249 | */ |
| elmot | 1:d0dfbce63a89 | 250 | void HAL_PWREx_EnableVddIO2(void) |
| elmot | 1:d0dfbce63a89 | 251 | { |
| elmot | 1:d0dfbce63a89 | 252 | SET_BIT(PWR->CR2, PWR_CR2_IOSV); |
| elmot | 1:d0dfbce63a89 | 253 | } |
| elmot | 1:d0dfbce63a89 | 254 | |
| elmot | 1:d0dfbce63a89 | 255 | |
| elmot | 1:d0dfbce63a89 | 256 | /** |
| elmot | 1:d0dfbce63a89 | 257 | * @brief Disable VDDIO2 supply. |
| elmot | 1:d0dfbce63a89 | 258 | * @retval None |
| elmot | 1:d0dfbce63a89 | 259 | */ |
| elmot | 1:d0dfbce63a89 | 260 | void HAL_PWREx_DisableVddIO2(void) |
| elmot | 1:d0dfbce63a89 | 261 | { |
| elmot | 1:d0dfbce63a89 | 262 | CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); |
| elmot | 1:d0dfbce63a89 | 263 | } |
| elmot | 1:d0dfbce63a89 | 264 | #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ |
| elmot | 1:d0dfbce63a89 | 265 | |
| elmot | 1:d0dfbce63a89 | 266 | |
| elmot | 1:d0dfbce63a89 | 267 | /** |
| elmot | 1:d0dfbce63a89 | 268 | * @brief Enable Internal Wake-up Line. |
| elmot | 1:d0dfbce63a89 | 269 | * @retval None |
| elmot | 1:d0dfbce63a89 | 270 | */ |
| elmot | 1:d0dfbce63a89 | 271 | void HAL_PWREx_EnableInternalWakeUpLine(void) |
| elmot | 1:d0dfbce63a89 | 272 | { |
| elmot | 1:d0dfbce63a89 | 273 | SET_BIT(PWR->CR3, PWR_CR3_EIWF); |
| elmot | 1:d0dfbce63a89 | 274 | } |
| elmot | 1:d0dfbce63a89 | 275 | |
| elmot | 1:d0dfbce63a89 | 276 | |
| elmot | 1:d0dfbce63a89 | 277 | /** |
| elmot | 1:d0dfbce63a89 | 278 | * @brief Disable Internal Wake-up Line. |
| elmot | 1:d0dfbce63a89 | 279 | * @retval None |
| elmot | 1:d0dfbce63a89 | 280 | */ |
| elmot | 1:d0dfbce63a89 | 281 | void HAL_PWREx_DisableInternalWakeUpLine(void) |
| elmot | 1:d0dfbce63a89 | 282 | { |
| elmot | 1:d0dfbce63a89 | 283 | CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF); |
| elmot | 1:d0dfbce63a89 | 284 | } |
| elmot | 1:d0dfbce63a89 | 285 | |
| elmot | 1:d0dfbce63a89 | 286 | |
| elmot | 1:d0dfbce63a89 | 287 | |
| elmot | 1:d0dfbce63a89 | 288 | /** |
| elmot | 1:d0dfbce63a89 | 289 | * @brief Enable GPIO pull-up state in Standby and Shutdown modes. |
| elmot | 1:d0dfbce63a89 | 290 | * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in |
| elmot | 1:d0dfbce63a89 | 291 | * pull-up state in Standby and Shutdown modes. |
| elmot | 1:d0dfbce63a89 | 292 | * @note This state is effective in Standby and Shutdown modes only if APC bit |
| elmot | 1:d0dfbce63a89 | 293 | * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. |
| elmot | 1:d0dfbce63a89 | 294 | * @note The configuration is lost when exiting the Shutdown mode due to the |
| elmot | 1:d0dfbce63a89 | 295 | * power-on reset, maintained when exiting the Standby mode. |
| elmot | 1:d0dfbce63a89 | 296 | * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding |
| elmot | 1:d0dfbce63a89 | 297 | * PDy bit of PWR_PDCRx register is cleared unless it is reserved. |
| elmot | 1:d0dfbce63a89 | 298 | * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input |
| elmot | 1:d0dfbce63a89 | 299 | * parameter at the same time are set. |
| elmot | 1:d0dfbce63a89 | 300 | * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H |
| elmot | 1:d0dfbce63a89 | 301 | * to select the GPIO peripheral. |
| elmot | 1:d0dfbce63a89 | 302 | * @param GPIONumber: Specify the I/O pins numbers. |
| elmot | 1:d0dfbce63a89 | 303 | * This parameter can be one of the following values: |
| elmot | 1:d0dfbce63a89 | 304 | * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less |
| elmot | 1:d0dfbce63a89 | 305 | * I/O pins are available) or the logical OR of several of them to set |
| elmot | 1:d0dfbce63a89 | 306 | * several bits for a given port in a single API call. |
| elmot | 1:d0dfbce63a89 | 307 | * @retval HAL Status |
| elmot | 1:d0dfbce63a89 | 308 | */ |
| elmot | 1:d0dfbce63a89 | 309 | HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) |
| elmot | 1:d0dfbce63a89 | 310 | { |
| elmot | 1:d0dfbce63a89 | 311 | assert_param(IS_PWR_GPIO(GPIO)); |
| elmot | 1:d0dfbce63a89 | 312 | assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); |
| elmot | 1:d0dfbce63a89 | 313 | |
| elmot | 1:d0dfbce63a89 | 314 | switch (GPIO) |
| elmot | 1:d0dfbce63a89 | 315 | { |
| elmot | 1:d0dfbce63a89 | 316 | case PWR_GPIO_A: |
| elmot | 1:d0dfbce63a89 | 317 | SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); |
| elmot | 1:d0dfbce63a89 | 318 | CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); |
| elmot | 1:d0dfbce63a89 | 319 | break; |
| elmot | 1:d0dfbce63a89 | 320 | case PWR_GPIO_B: |
| elmot | 1:d0dfbce63a89 | 321 | SET_BIT(PWR->PUCRB, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 322 | CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); |
| elmot | 1:d0dfbce63a89 | 323 | break; |
| elmot | 1:d0dfbce63a89 | 324 | case PWR_GPIO_C: |
| elmot | 1:d0dfbce63a89 | 325 | SET_BIT(PWR->PUCRC, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 326 | CLEAR_BIT(PWR->PDCRC, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 327 | break; |
| elmot | 1:d0dfbce63a89 | 328 | #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 329 | case PWR_GPIO_D: |
| elmot | 1:d0dfbce63a89 | 330 | SET_BIT(PWR->PUCRD, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 331 | CLEAR_BIT(PWR->PDCRD, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 332 | break; |
| elmot | 1:d0dfbce63a89 | 333 | case PWR_GPIO_E: |
| elmot | 1:d0dfbce63a89 | 334 | SET_BIT(PWR->PUCRE, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 335 | CLEAR_BIT(PWR->PDCRE, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 336 | break; |
| elmot | 1:d0dfbce63a89 | 337 | #endif |
| elmot | 1:d0dfbce63a89 | 338 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 339 | case PWR_GPIO_F: |
| elmot | 1:d0dfbce63a89 | 340 | SET_BIT(PWR->PUCRF, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 341 | CLEAR_BIT(PWR->PDCRF, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 342 | break; |
| elmot | 1:d0dfbce63a89 | 343 | case PWR_GPIO_G: |
| elmot | 1:d0dfbce63a89 | 344 | SET_BIT(PWR->PUCRG, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 345 | CLEAR_BIT(PWR->PDCRG, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 346 | break; |
| elmot | 1:d0dfbce63a89 | 347 | #endif |
| elmot | 1:d0dfbce63a89 | 348 | case PWR_GPIO_H: |
| elmot | 1:d0dfbce63a89 | 349 | SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); |
| elmot | 1:d0dfbce63a89 | 350 | CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); |
| elmot | 1:d0dfbce63a89 | 351 | break; |
| elmot | 1:d0dfbce63a89 | 352 | default: |
| elmot | 1:d0dfbce63a89 | 353 | return HAL_ERROR; |
| elmot | 1:d0dfbce63a89 | 354 | } |
| elmot | 1:d0dfbce63a89 | 355 | |
| elmot | 1:d0dfbce63a89 | 356 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 357 | } |
| elmot | 1:d0dfbce63a89 | 358 | |
| elmot | 1:d0dfbce63a89 | 359 | |
| elmot | 1:d0dfbce63a89 | 360 | /** |
| elmot | 1:d0dfbce63a89 | 361 | * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. |
| elmot | 1:d0dfbce63a89 | 362 | * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O |
| elmot | 1:d0dfbce63a89 | 363 | * in pull-up state in Standby and Shutdown modes. |
| elmot | 1:d0dfbce63a89 | 364 | * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input |
| elmot | 1:d0dfbce63a89 | 365 | * parameter at the same time are reset. |
| elmot | 1:d0dfbce63a89 | 366 | * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H |
| elmot | 1:d0dfbce63a89 | 367 | * to select the GPIO peripheral. |
| elmot | 1:d0dfbce63a89 | 368 | * @param GPIONumber: Specify the I/O pins numbers. |
| elmot | 1:d0dfbce63a89 | 369 | * This parameter can be one of the following values: |
| elmot | 1:d0dfbce63a89 | 370 | * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less |
| elmot | 1:d0dfbce63a89 | 371 | * I/O pins are available) or the logical OR of several of them to reset |
| elmot | 1:d0dfbce63a89 | 372 | * several bits for a given port in a single API call. |
| elmot | 1:d0dfbce63a89 | 373 | * @retval HAL Status |
| elmot | 1:d0dfbce63a89 | 374 | */ |
| elmot | 1:d0dfbce63a89 | 375 | HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) |
| elmot | 1:d0dfbce63a89 | 376 | { |
| elmot | 1:d0dfbce63a89 | 377 | assert_param(IS_PWR_GPIO(GPIO)); |
| elmot | 1:d0dfbce63a89 | 378 | assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); |
| elmot | 1:d0dfbce63a89 | 379 | |
| elmot | 1:d0dfbce63a89 | 380 | switch (GPIO) |
| elmot | 1:d0dfbce63a89 | 381 | { |
| elmot | 1:d0dfbce63a89 | 382 | case PWR_GPIO_A: |
| elmot | 1:d0dfbce63a89 | 383 | CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); |
| elmot | 1:d0dfbce63a89 | 384 | break; |
| elmot | 1:d0dfbce63a89 | 385 | case PWR_GPIO_B: |
| elmot | 1:d0dfbce63a89 | 386 | CLEAR_BIT(PWR->PUCRB, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 387 | break; |
| elmot | 1:d0dfbce63a89 | 388 | case PWR_GPIO_C: |
| elmot | 1:d0dfbce63a89 | 389 | CLEAR_BIT(PWR->PUCRC, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 390 | break; |
| elmot | 1:d0dfbce63a89 | 391 | #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 392 | case PWR_GPIO_D: |
| elmot | 1:d0dfbce63a89 | 393 | CLEAR_BIT(PWR->PUCRD, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 394 | break; |
| elmot | 1:d0dfbce63a89 | 395 | case PWR_GPIO_E: |
| elmot | 1:d0dfbce63a89 | 396 | CLEAR_BIT(PWR->PUCRE, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 397 | break; |
| elmot | 1:d0dfbce63a89 | 398 | #endif |
| elmot | 1:d0dfbce63a89 | 399 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 400 | case PWR_GPIO_F: |
| elmot | 1:d0dfbce63a89 | 401 | CLEAR_BIT(PWR->PUCRF, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 402 | break; |
| elmot | 1:d0dfbce63a89 | 403 | case PWR_GPIO_G: |
| elmot | 1:d0dfbce63a89 | 404 | CLEAR_BIT(PWR->PUCRG, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 405 | break; |
| elmot | 1:d0dfbce63a89 | 406 | #endif |
| elmot | 1:d0dfbce63a89 | 407 | case PWR_GPIO_H: |
| elmot | 1:d0dfbce63a89 | 408 | CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); |
| elmot | 1:d0dfbce63a89 | 409 | break; |
| elmot | 1:d0dfbce63a89 | 410 | default: |
| elmot | 1:d0dfbce63a89 | 411 | return HAL_ERROR; |
| elmot | 1:d0dfbce63a89 | 412 | } |
| elmot | 1:d0dfbce63a89 | 413 | |
| elmot | 1:d0dfbce63a89 | 414 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 415 | } |
| elmot | 1:d0dfbce63a89 | 416 | |
| elmot | 1:d0dfbce63a89 | 417 | |
| elmot | 1:d0dfbce63a89 | 418 | |
| elmot | 1:d0dfbce63a89 | 419 | /** |
| elmot | 1:d0dfbce63a89 | 420 | * @brief Enable GPIO pull-down state in Standby and Shutdown modes. |
| elmot | 1:d0dfbce63a89 | 421 | * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in |
| elmot | 1:d0dfbce63a89 | 422 | * pull-down state in Standby and Shutdown modes. |
| elmot | 1:d0dfbce63a89 | 423 | * @note This state is effective in Standby and Shutdown modes only if APC bit |
| elmot | 1:d0dfbce63a89 | 424 | * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. |
| elmot | 1:d0dfbce63a89 | 425 | * @note The configuration is lost when exiting the Shutdown mode due to the |
| elmot | 1:d0dfbce63a89 | 426 | * power-on reset, maintained when exiting the Standby mode. |
| elmot | 1:d0dfbce63a89 | 427 | * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding |
| elmot | 1:d0dfbce63a89 | 428 | * PUy bit of PWR_PUCRx register is cleared unless it is reserved. |
| elmot | 1:d0dfbce63a89 | 429 | * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input |
| elmot | 1:d0dfbce63a89 | 430 | * parameter at the same time are set. |
| elmot | 1:d0dfbce63a89 | 431 | * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H |
| elmot | 1:d0dfbce63a89 | 432 | * to select the GPIO peripheral. |
| elmot | 1:d0dfbce63a89 | 433 | * @param GPIONumber: Specify the I/O pins numbers. |
| elmot | 1:d0dfbce63a89 | 434 | * This parameter can be one of the following values: |
| elmot | 1:d0dfbce63a89 | 435 | * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less |
| elmot | 1:d0dfbce63a89 | 436 | * I/O pins are available) or the logical OR of several of them to set |
| elmot | 1:d0dfbce63a89 | 437 | * several bits for a given port in a single API call. |
| elmot | 1:d0dfbce63a89 | 438 | * @retval HAL Status |
| elmot | 1:d0dfbce63a89 | 439 | */ |
| elmot | 1:d0dfbce63a89 | 440 | HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) |
| elmot | 1:d0dfbce63a89 | 441 | { |
| elmot | 1:d0dfbce63a89 | 442 | assert_param(IS_PWR_GPIO(GPIO)); |
| elmot | 1:d0dfbce63a89 | 443 | assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); |
| elmot | 1:d0dfbce63a89 | 444 | |
| elmot | 1:d0dfbce63a89 | 445 | switch (GPIO) |
| elmot | 1:d0dfbce63a89 | 446 | { |
| elmot | 1:d0dfbce63a89 | 447 | case PWR_GPIO_A: |
| elmot | 1:d0dfbce63a89 | 448 | SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); |
| elmot | 1:d0dfbce63a89 | 449 | CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); |
| elmot | 1:d0dfbce63a89 | 450 | break; |
| elmot | 1:d0dfbce63a89 | 451 | case PWR_GPIO_B: |
| elmot | 1:d0dfbce63a89 | 452 | SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); |
| elmot | 1:d0dfbce63a89 | 453 | CLEAR_BIT(PWR->PUCRB, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 454 | break; |
| elmot | 1:d0dfbce63a89 | 455 | case PWR_GPIO_C: |
| elmot | 1:d0dfbce63a89 | 456 | SET_BIT(PWR->PDCRC, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 457 | CLEAR_BIT(PWR->PUCRC, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 458 | break; |
| elmot | 1:d0dfbce63a89 | 459 | #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 460 | case PWR_GPIO_D: |
| elmot | 1:d0dfbce63a89 | 461 | SET_BIT(PWR->PDCRD, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 462 | CLEAR_BIT(PWR->PUCRD, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 463 | break; |
| elmot | 1:d0dfbce63a89 | 464 | case PWR_GPIO_E: |
| elmot | 1:d0dfbce63a89 | 465 | SET_BIT(PWR->PDCRE, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 466 | CLEAR_BIT(PWR->PUCRE, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 467 | break; |
| elmot | 1:d0dfbce63a89 | 468 | #endif |
| elmot | 1:d0dfbce63a89 | 469 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 470 | case PWR_GPIO_F: |
| elmot | 1:d0dfbce63a89 | 471 | SET_BIT(PWR->PDCRF, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 472 | CLEAR_BIT(PWR->PUCRF, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 473 | break; |
| elmot | 1:d0dfbce63a89 | 474 | case PWR_GPIO_G: |
| elmot | 1:d0dfbce63a89 | 475 | SET_BIT(PWR->PDCRG, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 476 | CLEAR_BIT(PWR->PUCRG, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 477 | break; |
| elmot | 1:d0dfbce63a89 | 478 | #endif |
| elmot | 1:d0dfbce63a89 | 479 | case PWR_GPIO_H: |
| elmot | 1:d0dfbce63a89 | 480 | SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); |
| elmot | 1:d0dfbce63a89 | 481 | CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); |
| elmot | 1:d0dfbce63a89 | 482 | break; |
| elmot | 1:d0dfbce63a89 | 483 | default: |
| elmot | 1:d0dfbce63a89 | 484 | return HAL_ERROR; |
| elmot | 1:d0dfbce63a89 | 485 | } |
| elmot | 1:d0dfbce63a89 | 486 | |
| elmot | 1:d0dfbce63a89 | 487 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 488 | } |
| elmot | 1:d0dfbce63a89 | 489 | |
| elmot | 1:d0dfbce63a89 | 490 | |
| elmot | 1:d0dfbce63a89 | 491 | /** |
| elmot | 1:d0dfbce63a89 | 492 | * @brief Disable GPIO pull-down state in Standby and Shutdown modes. |
| elmot | 1:d0dfbce63a89 | 493 | * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O |
| elmot | 1:d0dfbce63a89 | 494 | * in pull-down state in Standby and Shutdown modes. |
| elmot | 1:d0dfbce63a89 | 495 | * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input |
| elmot | 1:d0dfbce63a89 | 496 | * parameter at the same time are reset. |
| elmot | 1:d0dfbce63a89 | 497 | * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H |
| elmot | 1:d0dfbce63a89 | 498 | * to select the GPIO peripheral. |
| elmot | 1:d0dfbce63a89 | 499 | * @param GPIONumber: Specify the I/O pins numbers. |
| elmot | 1:d0dfbce63a89 | 500 | * This parameter can be one of the following values: |
| elmot | 1:d0dfbce63a89 | 501 | * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less |
| elmot | 1:d0dfbce63a89 | 502 | * I/O pins are available) or the logical OR of several of them to reset |
| elmot | 1:d0dfbce63a89 | 503 | * several bits for a given port in a single API call. |
| elmot | 1:d0dfbce63a89 | 504 | * @retval HAL Status |
| elmot | 1:d0dfbce63a89 | 505 | */ |
| elmot | 1:d0dfbce63a89 | 506 | HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) |
| elmot | 1:d0dfbce63a89 | 507 | { |
| elmot | 1:d0dfbce63a89 | 508 | assert_param(IS_PWR_GPIO(GPIO)); |
| elmot | 1:d0dfbce63a89 | 509 | assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); |
| elmot | 1:d0dfbce63a89 | 510 | |
| elmot | 1:d0dfbce63a89 | 511 | switch (GPIO) |
| elmot | 1:d0dfbce63a89 | 512 | { |
| elmot | 1:d0dfbce63a89 | 513 | case PWR_GPIO_A: |
| elmot | 1:d0dfbce63a89 | 514 | CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); |
| elmot | 1:d0dfbce63a89 | 515 | break; |
| elmot | 1:d0dfbce63a89 | 516 | case PWR_GPIO_B: |
| elmot | 1:d0dfbce63a89 | 517 | CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); |
| elmot | 1:d0dfbce63a89 | 518 | break; |
| elmot | 1:d0dfbce63a89 | 519 | case PWR_GPIO_C: |
| elmot | 1:d0dfbce63a89 | 520 | CLEAR_BIT(PWR->PDCRC, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 521 | break; |
| elmot | 1:d0dfbce63a89 | 522 | #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 523 | case PWR_GPIO_D: |
| elmot | 1:d0dfbce63a89 | 524 | CLEAR_BIT(PWR->PDCRD, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 525 | break; |
| elmot | 1:d0dfbce63a89 | 526 | case PWR_GPIO_E: |
| elmot | 1:d0dfbce63a89 | 527 | CLEAR_BIT(PWR->PDCRE, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 528 | break; |
| elmot | 1:d0dfbce63a89 | 529 | #endif |
| elmot | 1:d0dfbce63a89 | 530 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 531 | case PWR_GPIO_F: |
| elmot | 1:d0dfbce63a89 | 532 | CLEAR_BIT(PWR->PDCRF, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 533 | break; |
| elmot | 1:d0dfbce63a89 | 534 | case PWR_GPIO_G: |
| elmot | 1:d0dfbce63a89 | 535 | CLEAR_BIT(PWR->PDCRG, GPIONumber); |
| elmot | 1:d0dfbce63a89 | 536 | break; |
| elmot | 1:d0dfbce63a89 | 537 | #endif |
| elmot | 1:d0dfbce63a89 | 538 | case PWR_GPIO_H: |
| elmot | 1:d0dfbce63a89 | 539 | CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); |
| elmot | 1:d0dfbce63a89 | 540 | break; |
| elmot | 1:d0dfbce63a89 | 541 | default: |
| elmot | 1:d0dfbce63a89 | 542 | return HAL_ERROR; |
| elmot | 1:d0dfbce63a89 | 543 | } |
| elmot | 1:d0dfbce63a89 | 544 | |
| elmot | 1:d0dfbce63a89 | 545 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 546 | } |
| elmot | 1:d0dfbce63a89 | 547 | |
| elmot | 1:d0dfbce63a89 | 548 | |
| elmot | 1:d0dfbce63a89 | 549 | |
| elmot | 1:d0dfbce63a89 | 550 | /** |
| elmot | 1:d0dfbce63a89 | 551 | * @brief Enable pull-up and pull-down configuration. |
| elmot | 1:d0dfbce63a89 | 552 | * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in |
| elmot | 1:d0dfbce63a89 | 553 | * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. |
| elmot | 1:d0dfbce63a89 | 554 | * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding |
| elmot | 1:d0dfbce63a89 | 555 | * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). |
| elmot | 1:d0dfbce63a89 | 556 | * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there |
| elmot | 1:d0dfbce63a89 | 557 | * is no conflict when setting PUy or PDy bit. |
| elmot | 1:d0dfbce63a89 | 558 | * @retval None |
| elmot | 1:d0dfbce63a89 | 559 | */ |
| elmot | 1:d0dfbce63a89 | 560 | void HAL_PWREx_EnablePullUpPullDownConfig(void) |
| elmot | 1:d0dfbce63a89 | 561 | { |
| elmot | 1:d0dfbce63a89 | 562 | SET_BIT(PWR->CR3, PWR_CR3_APC); |
| elmot | 1:d0dfbce63a89 | 563 | } |
| elmot | 1:d0dfbce63a89 | 564 | |
| elmot | 1:d0dfbce63a89 | 565 | |
| elmot | 1:d0dfbce63a89 | 566 | /** |
| elmot | 1:d0dfbce63a89 | 567 | * @brief Disable pull-up and pull-down configuration. |
| elmot | 1:d0dfbce63a89 | 568 | * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in |
| elmot | 1:d0dfbce63a89 | 569 | * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. |
| elmot | 1:d0dfbce63a89 | 570 | * @retval None |
| elmot | 1:d0dfbce63a89 | 571 | */ |
| elmot | 1:d0dfbce63a89 | 572 | void HAL_PWREx_DisablePullUpPullDownConfig(void) |
| elmot | 1:d0dfbce63a89 | 573 | { |
| elmot | 1:d0dfbce63a89 | 574 | CLEAR_BIT(PWR->CR3, PWR_CR3_APC); |
| elmot | 1:d0dfbce63a89 | 575 | } |
| elmot | 1:d0dfbce63a89 | 576 | |
| elmot | 1:d0dfbce63a89 | 577 | |
| elmot | 1:d0dfbce63a89 | 578 | |
| elmot | 1:d0dfbce63a89 | 579 | /** |
| elmot | 1:d0dfbce63a89 | 580 | * @brief Enable SRAM2 content retention in Standby mode. |
| elmot | 1:d0dfbce63a89 | 581 | * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in |
| elmot | 1:d0dfbce63a89 | 582 | * Standby mode and its content is kept. |
| elmot | 1:d0dfbce63a89 | 583 | * @retval None |
| elmot | 1:d0dfbce63a89 | 584 | */ |
| elmot | 1:d0dfbce63a89 | 585 | void HAL_PWREx_EnableSRAM2ContentRetention(void) |
| elmot | 1:d0dfbce63a89 | 586 | { |
| elmot | 1:d0dfbce63a89 | 587 | SET_BIT(PWR->CR3, PWR_CR3_RRS); |
| elmot | 1:d0dfbce63a89 | 588 | } |
| elmot | 1:d0dfbce63a89 | 589 | |
| elmot | 1:d0dfbce63a89 | 590 | |
| elmot | 1:d0dfbce63a89 | 591 | /** |
| elmot | 1:d0dfbce63a89 | 592 | * @brief Disable SRAM2 content retention in Standby mode. |
| elmot | 1:d0dfbce63a89 | 593 | * @note When RRS bit is reset, SRAM2 is powered off in Standby mode |
| elmot | 1:d0dfbce63a89 | 594 | * and its content is lost. |
| elmot | 1:d0dfbce63a89 | 595 | * @retval None |
| elmot | 1:d0dfbce63a89 | 596 | */ |
| elmot | 1:d0dfbce63a89 | 597 | void HAL_PWREx_DisableSRAM2ContentRetention(void) |
| elmot | 1:d0dfbce63a89 | 598 | { |
| elmot | 1:d0dfbce63a89 | 599 | CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); |
| elmot | 1:d0dfbce63a89 | 600 | } |
| elmot | 1:d0dfbce63a89 | 601 | |
| elmot | 1:d0dfbce63a89 | 602 | |
| elmot | 1:d0dfbce63a89 | 603 | |
| elmot | 1:d0dfbce63a89 | 604 | |
| elmot | 1:d0dfbce63a89 | 605 | #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 606 | /** |
| elmot | 1:d0dfbce63a89 | 607 | * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V. |
| elmot | 1:d0dfbce63a89 | 608 | * @retval None |
| elmot | 1:d0dfbce63a89 | 609 | */ |
| elmot | 1:d0dfbce63a89 | 610 | void HAL_PWREx_EnablePVM1(void) |
| elmot | 1:d0dfbce63a89 | 611 | { |
| elmot | 1:d0dfbce63a89 | 612 | SET_BIT(PWR->CR2, PWR_PVM_1); |
| elmot | 1:d0dfbce63a89 | 613 | } |
| elmot | 1:d0dfbce63a89 | 614 | |
| elmot | 1:d0dfbce63a89 | 615 | /** |
| elmot | 1:d0dfbce63a89 | 616 | * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V. |
| elmot | 1:d0dfbce63a89 | 617 | * @retval None |
| elmot | 1:d0dfbce63a89 | 618 | */ |
| elmot | 1:d0dfbce63a89 | 619 | void HAL_PWREx_DisablePVM1(void) |
| elmot | 1:d0dfbce63a89 | 620 | { |
| elmot | 1:d0dfbce63a89 | 621 | CLEAR_BIT(PWR->CR2, PWR_PVM_1); |
| elmot | 1:d0dfbce63a89 | 622 | } |
| elmot | 1:d0dfbce63a89 | 623 | #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ |
| elmot | 1:d0dfbce63a89 | 624 | |
| elmot | 1:d0dfbce63a89 | 625 | |
| elmot | 1:d0dfbce63a89 | 626 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 627 | /** |
| elmot | 1:d0dfbce63a89 | 628 | * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V. |
| elmot | 1:d0dfbce63a89 | 629 | * @retval None |
| elmot | 1:d0dfbce63a89 | 630 | */ |
| elmot | 1:d0dfbce63a89 | 631 | void HAL_PWREx_EnablePVM2(void) |
| elmot | 1:d0dfbce63a89 | 632 | { |
| elmot | 1:d0dfbce63a89 | 633 | SET_BIT(PWR->CR2, PWR_PVM_2); |
| elmot | 1:d0dfbce63a89 | 634 | } |
| elmot | 1:d0dfbce63a89 | 635 | |
| elmot | 1:d0dfbce63a89 | 636 | /** |
| elmot | 1:d0dfbce63a89 | 637 | * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V. |
| elmot | 1:d0dfbce63a89 | 638 | * @retval None |
| elmot | 1:d0dfbce63a89 | 639 | */ |
| elmot | 1:d0dfbce63a89 | 640 | void HAL_PWREx_DisablePVM2(void) |
| elmot | 1:d0dfbce63a89 | 641 | { |
| elmot | 1:d0dfbce63a89 | 642 | CLEAR_BIT(PWR->CR2, PWR_PVM_2); |
| elmot | 1:d0dfbce63a89 | 643 | } |
| elmot | 1:d0dfbce63a89 | 644 | #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ |
| elmot | 1:d0dfbce63a89 | 645 | |
| elmot | 1:d0dfbce63a89 | 646 | |
| elmot | 1:d0dfbce63a89 | 647 | /** |
| elmot | 1:d0dfbce63a89 | 648 | * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V. |
| elmot | 1:d0dfbce63a89 | 649 | * @retval None |
| elmot | 1:d0dfbce63a89 | 650 | */ |
| elmot | 1:d0dfbce63a89 | 651 | void HAL_PWREx_EnablePVM3(void) |
| elmot | 1:d0dfbce63a89 | 652 | { |
| elmot | 1:d0dfbce63a89 | 653 | SET_BIT(PWR->CR2, PWR_PVM_3); |
| elmot | 1:d0dfbce63a89 | 654 | } |
| elmot | 1:d0dfbce63a89 | 655 | |
| elmot | 1:d0dfbce63a89 | 656 | /** |
| elmot | 1:d0dfbce63a89 | 657 | * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V. |
| elmot | 1:d0dfbce63a89 | 658 | * @retval None |
| elmot | 1:d0dfbce63a89 | 659 | */ |
| elmot | 1:d0dfbce63a89 | 660 | void HAL_PWREx_DisablePVM3(void) |
| elmot | 1:d0dfbce63a89 | 661 | { |
| elmot | 1:d0dfbce63a89 | 662 | CLEAR_BIT(PWR->CR2, PWR_PVM_3); |
| elmot | 1:d0dfbce63a89 | 663 | } |
| elmot | 1:d0dfbce63a89 | 664 | |
| elmot | 1:d0dfbce63a89 | 665 | |
| elmot | 1:d0dfbce63a89 | 666 | /** |
| elmot | 1:d0dfbce63a89 | 667 | * @brief Enable the Power Voltage Monitoring 4: VDDA versus 2.2V. |
| elmot | 1:d0dfbce63a89 | 668 | * @retval None |
| elmot | 1:d0dfbce63a89 | 669 | */ |
| elmot | 1:d0dfbce63a89 | 670 | void HAL_PWREx_EnablePVM4(void) |
| elmot | 1:d0dfbce63a89 | 671 | { |
| elmot | 1:d0dfbce63a89 | 672 | SET_BIT(PWR->CR2, PWR_PVM_4); |
| elmot | 1:d0dfbce63a89 | 673 | } |
| elmot | 1:d0dfbce63a89 | 674 | |
| elmot | 1:d0dfbce63a89 | 675 | /** |
| elmot | 1:d0dfbce63a89 | 676 | * @brief Disable the Power Voltage Monitoring 4: VDDA versus 2.2V. |
| elmot | 1:d0dfbce63a89 | 677 | * @retval None |
| elmot | 1:d0dfbce63a89 | 678 | */ |
| elmot | 1:d0dfbce63a89 | 679 | void HAL_PWREx_DisablePVM4(void) |
| elmot | 1:d0dfbce63a89 | 680 | { |
| elmot | 1:d0dfbce63a89 | 681 | CLEAR_BIT(PWR->CR2, PWR_PVM_4); |
| elmot | 1:d0dfbce63a89 | 682 | } |
| elmot | 1:d0dfbce63a89 | 683 | |
| elmot | 1:d0dfbce63a89 | 684 | |
| elmot | 1:d0dfbce63a89 | 685 | |
| elmot | 1:d0dfbce63a89 | 686 | |
| elmot | 1:d0dfbce63a89 | 687 | /** |
| elmot | 1:d0dfbce63a89 | 688 | * @brief Configure the Peripheral Voltage Monitoring (PVM). |
| elmot | 1:d0dfbce63a89 | 689 | * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the |
| elmot | 1:d0dfbce63a89 | 690 | * PVM configuration information. |
| elmot | 1:d0dfbce63a89 | 691 | * @note The API configures a single PVM according to the information contained |
| elmot | 1:d0dfbce63a89 | 692 | * in the input structure. To configure several PVMs, the API must be singly |
| elmot | 1:d0dfbce63a89 | 693 | * called for each PVM used. |
| elmot | 1:d0dfbce63a89 | 694 | * @note Refer to the electrical characteristics of your device datasheet for |
| elmot | 1:d0dfbce63a89 | 695 | * more details about the voltage thresholds corresponding to each |
| elmot | 1:d0dfbce63a89 | 696 | * detection level and to each monitored supply. |
| elmot | 1:d0dfbce63a89 | 697 | * @retval HAL status |
| elmot | 1:d0dfbce63a89 | 698 | */ |
| elmot | 1:d0dfbce63a89 | 699 | HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) |
| elmot | 1:d0dfbce63a89 | 700 | { |
| elmot | 1:d0dfbce63a89 | 701 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 702 | assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); |
| elmot | 1:d0dfbce63a89 | 703 | assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); |
| elmot | 1:d0dfbce63a89 | 704 | |
| elmot | 1:d0dfbce63a89 | 705 | |
| elmot | 1:d0dfbce63a89 | 706 | /* Configure EXTI 35 to 38 interrupts if so required: |
| elmot | 1:d0dfbce63a89 | 707 | scan thru PVMType to detect which PVMx is set and |
| elmot | 1:d0dfbce63a89 | 708 | configure the corresponding EXTI line accordingly. */ |
| elmot | 1:d0dfbce63a89 | 709 | switch (sConfigPVM->PVMType) |
| elmot | 1:d0dfbce63a89 | 710 | { |
| elmot | 1:d0dfbce63a89 | 711 | #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 712 | case PWR_PVM_1: |
| elmot | 1:d0dfbce63a89 | 713 | /* Clear any previous config. Keep it clear if no event or IT mode is selected */ |
| elmot | 1:d0dfbce63a89 | 714 | __HAL_PWR_PVM1_EXTI_DISABLE_EVENT(); |
| elmot | 1:d0dfbce63a89 | 715 | __HAL_PWR_PVM1_EXTI_DISABLE_IT(); |
| elmot | 1:d0dfbce63a89 | 716 | __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); |
| elmot | 1:d0dfbce63a89 | 717 | __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); |
| elmot | 1:d0dfbce63a89 | 718 | |
| elmot | 1:d0dfbce63a89 | 719 | /* Configure interrupt mode */ |
| elmot | 1:d0dfbce63a89 | 720 | if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) |
| elmot | 1:d0dfbce63a89 | 721 | { |
| elmot | 1:d0dfbce63a89 | 722 | __HAL_PWR_PVM1_EXTI_ENABLE_IT(); |
| elmot | 1:d0dfbce63a89 | 723 | } |
| elmot | 1:d0dfbce63a89 | 724 | |
| elmot | 1:d0dfbce63a89 | 725 | /* Configure event mode */ |
| elmot | 1:d0dfbce63a89 | 726 | if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) |
| elmot | 1:d0dfbce63a89 | 727 | { |
| elmot | 1:d0dfbce63a89 | 728 | __HAL_PWR_PVM1_EXTI_ENABLE_EVENT(); |
| elmot | 1:d0dfbce63a89 | 729 | } |
| elmot | 1:d0dfbce63a89 | 730 | |
| elmot | 1:d0dfbce63a89 | 731 | /* Configure the edge */ |
| elmot | 1:d0dfbce63a89 | 732 | if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) |
| elmot | 1:d0dfbce63a89 | 733 | { |
| elmot | 1:d0dfbce63a89 | 734 | __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); |
| elmot | 1:d0dfbce63a89 | 735 | } |
| elmot | 1:d0dfbce63a89 | 736 | |
| elmot | 1:d0dfbce63a89 | 737 | if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) |
| elmot | 1:d0dfbce63a89 | 738 | { |
| elmot | 1:d0dfbce63a89 | 739 | __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); |
| elmot | 1:d0dfbce63a89 | 740 | } |
| elmot | 1:d0dfbce63a89 | 741 | break; |
| elmot | 1:d0dfbce63a89 | 742 | #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ |
| elmot | 1:d0dfbce63a89 | 743 | |
| elmot | 1:d0dfbce63a89 | 744 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 745 | case PWR_PVM_2: |
| elmot | 1:d0dfbce63a89 | 746 | /* Clear any previous config. Keep it clear if no event or IT mode is selected */ |
| elmot | 1:d0dfbce63a89 | 747 | __HAL_PWR_PVM2_EXTI_DISABLE_EVENT(); |
| elmot | 1:d0dfbce63a89 | 748 | __HAL_PWR_PVM2_EXTI_DISABLE_IT(); |
| elmot | 1:d0dfbce63a89 | 749 | __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); |
| elmot | 1:d0dfbce63a89 | 750 | __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); |
| elmot | 1:d0dfbce63a89 | 751 | |
| elmot | 1:d0dfbce63a89 | 752 | /* Configure interrupt mode */ |
| elmot | 1:d0dfbce63a89 | 753 | if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) |
| elmot | 1:d0dfbce63a89 | 754 | { |
| elmot | 1:d0dfbce63a89 | 755 | __HAL_PWR_PVM2_EXTI_ENABLE_IT(); |
| elmot | 1:d0dfbce63a89 | 756 | } |
| elmot | 1:d0dfbce63a89 | 757 | |
| elmot | 1:d0dfbce63a89 | 758 | /* Configure event mode */ |
| elmot | 1:d0dfbce63a89 | 759 | if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) |
| elmot | 1:d0dfbce63a89 | 760 | { |
| elmot | 1:d0dfbce63a89 | 761 | __HAL_PWR_PVM2_EXTI_ENABLE_EVENT(); |
| elmot | 1:d0dfbce63a89 | 762 | } |
| elmot | 1:d0dfbce63a89 | 763 | |
| elmot | 1:d0dfbce63a89 | 764 | /* Configure the edge */ |
| elmot | 1:d0dfbce63a89 | 765 | if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) |
| elmot | 1:d0dfbce63a89 | 766 | { |
| elmot | 1:d0dfbce63a89 | 767 | __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); |
| elmot | 1:d0dfbce63a89 | 768 | } |
| elmot | 1:d0dfbce63a89 | 769 | |
| elmot | 1:d0dfbce63a89 | 770 | if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) |
| elmot | 1:d0dfbce63a89 | 771 | { |
| elmot | 1:d0dfbce63a89 | 772 | __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); |
| elmot | 1:d0dfbce63a89 | 773 | } |
| elmot | 1:d0dfbce63a89 | 774 | break; |
| elmot | 1:d0dfbce63a89 | 775 | #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ |
| elmot | 1:d0dfbce63a89 | 776 | |
| elmot | 1:d0dfbce63a89 | 777 | case PWR_PVM_3: |
| elmot | 1:d0dfbce63a89 | 778 | /* Clear any previous config. Keep it clear if no event or IT mode is selected */ |
| elmot | 1:d0dfbce63a89 | 779 | __HAL_PWR_PVM3_EXTI_DISABLE_EVENT(); |
| elmot | 1:d0dfbce63a89 | 780 | __HAL_PWR_PVM3_EXTI_DISABLE_IT(); |
| elmot | 1:d0dfbce63a89 | 781 | __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); |
| elmot | 1:d0dfbce63a89 | 782 | __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); |
| elmot | 1:d0dfbce63a89 | 783 | |
| elmot | 1:d0dfbce63a89 | 784 | /* Configure interrupt mode */ |
| elmot | 1:d0dfbce63a89 | 785 | if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) |
| elmot | 1:d0dfbce63a89 | 786 | { |
| elmot | 1:d0dfbce63a89 | 787 | __HAL_PWR_PVM3_EXTI_ENABLE_IT(); |
| elmot | 1:d0dfbce63a89 | 788 | } |
| elmot | 1:d0dfbce63a89 | 789 | |
| elmot | 1:d0dfbce63a89 | 790 | /* Configure event mode */ |
| elmot | 1:d0dfbce63a89 | 791 | if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) |
| elmot | 1:d0dfbce63a89 | 792 | { |
| elmot | 1:d0dfbce63a89 | 793 | __HAL_PWR_PVM3_EXTI_ENABLE_EVENT(); |
| elmot | 1:d0dfbce63a89 | 794 | } |
| elmot | 1:d0dfbce63a89 | 795 | |
| elmot | 1:d0dfbce63a89 | 796 | /* Configure the edge */ |
| elmot | 1:d0dfbce63a89 | 797 | if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) |
| elmot | 1:d0dfbce63a89 | 798 | { |
| elmot | 1:d0dfbce63a89 | 799 | __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); |
| elmot | 1:d0dfbce63a89 | 800 | } |
| elmot | 1:d0dfbce63a89 | 801 | |
| elmot | 1:d0dfbce63a89 | 802 | if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) |
| elmot | 1:d0dfbce63a89 | 803 | { |
| elmot | 1:d0dfbce63a89 | 804 | __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); |
| elmot | 1:d0dfbce63a89 | 805 | } |
| elmot | 1:d0dfbce63a89 | 806 | break; |
| elmot | 1:d0dfbce63a89 | 807 | |
| elmot | 1:d0dfbce63a89 | 808 | case PWR_PVM_4: |
| elmot | 1:d0dfbce63a89 | 809 | /* Clear any previous config. Keep it clear if no event or IT mode is selected */ |
| elmot | 1:d0dfbce63a89 | 810 | __HAL_PWR_PVM4_EXTI_DISABLE_EVENT(); |
| elmot | 1:d0dfbce63a89 | 811 | __HAL_PWR_PVM4_EXTI_DISABLE_IT(); |
| elmot | 1:d0dfbce63a89 | 812 | __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); |
| elmot | 1:d0dfbce63a89 | 813 | __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); |
| elmot | 1:d0dfbce63a89 | 814 | |
| elmot | 1:d0dfbce63a89 | 815 | /* Configure interrupt mode */ |
| elmot | 1:d0dfbce63a89 | 816 | if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) |
| elmot | 1:d0dfbce63a89 | 817 | { |
| elmot | 1:d0dfbce63a89 | 818 | __HAL_PWR_PVM4_EXTI_ENABLE_IT(); |
| elmot | 1:d0dfbce63a89 | 819 | } |
| elmot | 1:d0dfbce63a89 | 820 | |
| elmot | 1:d0dfbce63a89 | 821 | /* Configure event mode */ |
| elmot | 1:d0dfbce63a89 | 822 | if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) |
| elmot | 1:d0dfbce63a89 | 823 | { |
| elmot | 1:d0dfbce63a89 | 824 | __HAL_PWR_PVM4_EXTI_ENABLE_EVENT(); |
| elmot | 1:d0dfbce63a89 | 825 | } |
| elmot | 1:d0dfbce63a89 | 826 | |
| elmot | 1:d0dfbce63a89 | 827 | /* Configure the edge */ |
| elmot | 1:d0dfbce63a89 | 828 | if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) |
| elmot | 1:d0dfbce63a89 | 829 | { |
| elmot | 1:d0dfbce63a89 | 830 | __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); |
| elmot | 1:d0dfbce63a89 | 831 | } |
| elmot | 1:d0dfbce63a89 | 832 | |
| elmot | 1:d0dfbce63a89 | 833 | if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) |
| elmot | 1:d0dfbce63a89 | 834 | { |
| elmot | 1:d0dfbce63a89 | 835 | __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); |
| elmot | 1:d0dfbce63a89 | 836 | } |
| elmot | 1:d0dfbce63a89 | 837 | break; |
| elmot | 1:d0dfbce63a89 | 838 | |
| elmot | 1:d0dfbce63a89 | 839 | default: |
| elmot | 1:d0dfbce63a89 | 840 | return HAL_ERROR; |
| elmot | 1:d0dfbce63a89 | 841 | |
| elmot | 1:d0dfbce63a89 | 842 | } |
| elmot | 1:d0dfbce63a89 | 843 | |
| elmot | 1:d0dfbce63a89 | 844 | |
| elmot | 1:d0dfbce63a89 | 845 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 846 | } |
| elmot | 1:d0dfbce63a89 | 847 | |
| elmot | 1:d0dfbce63a89 | 848 | |
| elmot | 1:d0dfbce63a89 | 849 | |
| elmot | 1:d0dfbce63a89 | 850 | /** |
| elmot | 1:d0dfbce63a89 | 851 | * @brief Enter Low-power Run mode |
| elmot | 1:d0dfbce63a89 | 852 | * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. |
| elmot | 1:d0dfbce63a89 | 853 | * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the |
| elmot | 1:d0dfbce63a89 | 854 | * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register. |
| elmot | 1:d0dfbce63a89 | 855 | * Additionally, the clock frequency must be reduced below 2 MHz. |
| elmot | 1:d0dfbce63a89 | 856 | * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must |
| elmot | 1:d0dfbce63a89 | 857 | * be done before calling HAL_PWREx_EnableLowPowerRunMode() API. |
| elmot | 1:d0dfbce63a89 | 858 | * @retval None |
| elmot | 1:d0dfbce63a89 | 859 | */ |
| elmot | 1:d0dfbce63a89 | 860 | void HAL_PWREx_EnableLowPowerRunMode(void) |
| elmot | 1:d0dfbce63a89 | 861 | { |
| elmot | 1:d0dfbce63a89 | 862 | /* Set Regulator parameter */ |
| elmot | 1:d0dfbce63a89 | 863 | SET_BIT(PWR->CR1, PWR_CR1_LPR); |
| elmot | 1:d0dfbce63a89 | 864 | } |
| elmot | 1:d0dfbce63a89 | 865 | |
| elmot | 1:d0dfbce63a89 | 866 | |
| elmot | 1:d0dfbce63a89 | 867 | /** |
| elmot | 1:d0dfbce63a89 | 868 | * @brief Exit Low-power Run mode. |
| elmot | 1:d0dfbce63a89 | 869 | * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that |
| elmot | 1:d0dfbce63a89 | 870 | * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode |
| elmot | 1:d0dfbce63a89 | 871 | * returns HAL_TIMEOUT status). The system clock frequency can then be |
| elmot | 1:d0dfbce63a89 | 872 | * increased above 2 MHz. |
| elmot | 1:d0dfbce63a89 | 873 | * @retval HAL Status |
| elmot | 1:d0dfbce63a89 | 874 | */ |
| elmot | 1:d0dfbce63a89 | 875 | HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) |
| elmot | 1:d0dfbce63a89 | 876 | { |
| elmot | 1:d0dfbce63a89 | 877 | uint32_t wait_loop_index = 0; |
| elmot | 1:d0dfbce63a89 | 878 | |
| elmot | 1:d0dfbce63a89 | 879 | /* Clear LPR bit */ |
| elmot | 1:d0dfbce63a89 | 880 | CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); |
| elmot | 1:d0dfbce63a89 | 881 | |
| elmot | 1:d0dfbce63a89 | 882 | /* Wait until REGLPF is reset */ |
| elmot | 1:d0dfbce63a89 | 883 | wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); |
| elmot | 1:d0dfbce63a89 | 884 | while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))) |
| elmot | 1:d0dfbce63a89 | 885 | { |
| elmot | 1:d0dfbce63a89 | 886 | wait_loop_index--; |
| elmot | 1:d0dfbce63a89 | 887 | } |
| elmot | 1:d0dfbce63a89 | 888 | if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) |
| elmot | 1:d0dfbce63a89 | 889 | { |
| elmot | 1:d0dfbce63a89 | 890 | return HAL_TIMEOUT; |
| elmot | 1:d0dfbce63a89 | 891 | } |
| elmot | 1:d0dfbce63a89 | 892 | |
| elmot | 1:d0dfbce63a89 | 893 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 894 | } |
| elmot | 1:d0dfbce63a89 | 895 | |
| elmot | 1:d0dfbce63a89 | 896 | |
| elmot | 1:d0dfbce63a89 | 897 | /** |
| elmot | 1:d0dfbce63a89 | 898 | * @brief Enter Stop 0 mode. |
| elmot | 1:d0dfbce63a89 | 899 | * @note In Stop 0 mode, main and low voltage regulators are ON. |
| elmot | 1:d0dfbce63a89 | 900 | * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode. |
| elmot | 1:d0dfbce63a89 | 901 | * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, |
| elmot | 1:d0dfbce63a89 | 902 | * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability |
| elmot | 1:d0dfbce63a89 | 903 | * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI |
| elmot | 1:d0dfbce63a89 | 904 | * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated |
| elmot | 1:d0dfbce63a89 | 905 | * only to the peripheral requesting it. |
| elmot | 1:d0dfbce63a89 | 906 | * SRAM1, SRAM2 and register contents are preserved. |
| elmot | 1:d0dfbce63a89 | 907 | * The BOR is available. |
| elmot | 1:d0dfbce63a89 | 908 | * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event, |
| elmot | 1:d0dfbce63a89 | 909 | * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register |
| elmot | 1:d0dfbce63a89 | 910 | * is set; the MSI oscillator is selected if STOPWUCK is cleared. |
| elmot | 1:d0dfbce63a89 | 911 | * @note By keeping the internal regulator ON during Stop 0 mode, the consumption |
| elmot | 1:d0dfbce63a89 | 912 | * is higher although the startup time is reduced. |
| elmot | 1:d0dfbce63a89 | 913 | * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. |
| elmot | 1:d0dfbce63a89 | 914 | * This parameter can be one of the following values: |
| elmot | 1:d0dfbce63a89 | 915 | * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction |
| elmot | 1:d0dfbce63a89 | 916 | * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction |
| elmot | 1:d0dfbce63a89 | 917 | * @retval None |
| elmot | 1:d0dfbce63a89 | 918 | */ |
| elmot | 1:d0dfbce63a89 | 919 | void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) |
| elmot | 1:d0dfbce63a89 | 920 | { |
| elmot | 1:d0dfbce63a89 | 921 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 922 | assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); |
| elmot | 1:d0dfbce63a89 | 923 | |
| elmot | 1:d0dfbce63a89 | 924 | /* Stop 0 mode with Main Regulator */ |
| elmot | 1:d0dfbce63a89 | 925 | MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0); |
| elmot | 1:d0dfbce63a89 | 926 | |
| elmot | 1:d0dfbce63a89 | 927 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
| elmot | 1:d0dfbce63a89 | 928 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
| elmot | 1:d0dfbce63a89 | 929 | |
| elmot | 1:d0dfbce63a89 | 930 | /* Select Stop mode entry --------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 931 | if(STOPEntry == PWR_STOPENTRY_WFI) |
| elmot | 1:d0dfbce63a89 | 932 | { |
| elmot | 1:d0dfbce63a89 | 933 | /* Request Wait For Interrupt */ |
| elmot | 1:d0dfbce63a89 | 934 | __WFI(); |
| elmot | 1:d0dfbce63a89 | 935 | } |
| elmot | 1:d0dfbce63a89 | 936 | else |
| elmot | 1:d0dfbce63a89 | 937 | { |
| elmot | 1:d0dfbce63a89 | 938 | /* Request Wait For Event */ |
| elmot | 1:d0dfbce63a89 | 939 | __SEV(); |
| elmot | 1:d0dfbce63a89 | 940 | __WFE(); |
| elmot | 1:d0dfbce63a89 | 941 | __WFE(); |
| elmot | 1:d0dfbce63a89 | 942 | } |
| elmot | 1:d0dfbce63a89 | 943 | |
| elmot | 1:d0dfbce63a89 | 944 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ |
| elmot | 1:d0dfbce63a89 | 945 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
| elmot | 1:d0dfbce63a89 | 946 | } |
| elmot | 1:d0dfbce63a89 | 947 | |
| elmot | 1:d0dfbce63a89 | 948 | |
| elmot | 1:d0dfbce63a89 | 949 | /** |
| elmot | 1:d0dfbce63a89 | 950 | * @brief Enter Stop 1 mode. |
| elmot | 1:d0dfbce63a89 | 951 | * @note In Stop 1 mode, only low power voltage regulator is ON. |
| elmot | 1:d0dfbce63a89 | 952 | * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode. |
| elmot | 1:d0dfbce63a89 | 953 | * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, |
| elmot | 1:d0dfbce63a89 | 954 | * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability |
| elmot | 1:d0dfbce63a89 | 955 | * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI |
| elmot | 1:d0dfbce63a89 | 956 | * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated |
| elmot | 1:d0dfbce63a89 | 957 | * only to the peripheral requesting it. |
| elmot | 1:d0dfbce63a89 | 958 | * SRAM1, SRAM2 and register contents are preserved. |
| elmot | 1:d0dfbce63a89 | 959 | * The BOR is available. |
| elmot | 1:d0dfbce63a89 | 960 | * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event, |
| elmot | 1:d0dfbce63a89 | 961 | * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register |
| elmot | 1:d0dfbce63a89 | 962 | * is set; the MSI oscillator is selected if STOPWUCK is cleared. |
| elmot | 1:d0dfbce63a89 | 963 | * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode. |
| elmot | 1:d0dfbce63a89 | 964 | * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. |
| elmot | 1:d0dfbce63a89 | 965 | * This parameter can be one of the following values: |
| elmot | 1:d0dfbce63a89 | 966 | * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction |
| elmot | 1:d0dfbce63a89 | 967 | * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction |
| elmot | 1:d0dfbce63a89 | 968 | * @retval None |
| elmot | 1:d0dfbce63a89 | 969 | */ |
| elmot | 1:d0dfbce63a89 | 970 | void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) |
| elmot | 1:d0dfbce63a89 | 971 | { |
| elmot | 1:d0dfbce63a89 | 972 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 973 | assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); |
| elmot | 1:d0dfbce63a89 | 974 | |
| elmot | 1:d0dfbce63a89 | 975 | /* Stop 1 mode with Low-Power Regulator */ |
| elmot | 1:d0dfbce63a89 | 976 | MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1); |
| elmot | 1:d0dfbce63a89 | 977 | |
| elmot | 1:d0dfbce63a89 | 978 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
| elmot | 1:d0dfbce63a89 | 979 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
| elmot | 1:d0dfbce63a89 | 980 | |
| elmot | 1:d0dfbce63a89 | 981 | /* Select Stop mode entry --------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 982 | if(STOPEntry == PWR_STOPENTRY_WFI) |
| elmot | 1:d0dfbce63a89 | 983 | { |
| elmot | 1:d0dfbce63a89 | 984 | /* Request Wait For Interrupt */ |
| elmot | 1:d0dfbce63a89 | 985 | __WFI(); |
| elmot | 1:d0dfbce63a89 | 986 | } |
| elmot | 1:d0dfbce63a89 | 987 | else |
| elmot | 1:d0dfbce63a89 | 988 | { |
| elmot | 1:d0dfbce63a89 | 989 | /* Request Wait For Event */ |
| elmot | 1:d0dfbce63a89 | 990 | __SEV(); |
| elmot | 1:d0dfbce63a89 | 991 | __WFE(); |
| elmot | 1:d0dfbce63a89 | 992 | __WFE(); |
| elmot | 1:d0dfbce63a89 | 993 | } |
| elmot | 1:d0dfbce63a89 | 994 | |
| elmot | 1:d0dfbce63a89 | 995 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ |
| elmot | 1:d0dfbce63a89 | 996 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
| elmot | 1:d0dfbce63a89 | 997 | } |
| elmot | 1:d0dfbce63a89 | 998 | |
| elmot | 1:d0dfbce63a89 | 999 | |
| elmot | 1:d0dfbce63a89 | 1000 | /** |
| elmot | 1:d0dfbce63a89 | 1001 | * @brief Enter Stop 2 mode. |
| elmot | 1:d0dfbce63a89 | 1002 | * @note In Stop 2 mode, only low power voltage regulator is ON. |
| elmot | 1:d0dfbce63a89 | 1003 | * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode. |
| elmot | 1:d0dfbce63a89 | 1004 | * @note All clocks in the VCORE domain are stopped, the PLL, the MSI, |
| elmot | 1:d0dfbce63a89 | 1005 | * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability |
| elmot | 1:d0dfbce63a89 | 1006 | * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after |
| elmot | 1:d0dfbce63a89 | 1007 | * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only |
| elmot | 1:d0dfbce63a89 | 1008 | * to the peripheral requesting it. |
| elmot | 1:d0dfbce63a89 | 1009 | * SRAM1, SRAM2 and register contents are preserved. |
| elmot | 1:d0dfbce63a89 | 1010 | * The BOR is available. |
| elmot | 1:d0dfbce63a89 | 1011 | * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode. |
| elmot | 1:d0dfbce63a89 | 1012 | * Otherwise, Stop 1 mode is entered. |
| elmot | 1:d0dfbce63a89 | 1013 | * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event, |
| elmot | 1:d0dfbce63a89 | 1014 | * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register |
| elmot | 1:d0dfbce63a89 | 1015 | * is set; the MSI oscillator is selected if STOPWUCK is cleared. |
| elmot | 1:d0dfbce63a89 | 1016 | * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. |
| elmot | 1:d0dfbce63a89 | 1017 | * This parameter can be one of the following values: |
| elmot | 1:d0dfbce63a89 | 1018 | * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction |
| elmot | 1:d0dfbce63a89 | 1019 | * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction |
| elmot | 1:d0dfbce63a89 | 1020 | * @retval None |
| elmot | 1:d0dfbce63a89 | 1021 | */ |
| elmot | 1:d0dfbce63a89 | 1022 | void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) |
| elmot | 1:d0dfbce63a89 | 1023 | { |
| elmot | 1:d0dfbce63a89 | 1024 | /* Check the parameter */ |
| elmot | 1:d0dfbce63a89 | 1025 | assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); |
| elmot | 1:d0dfbce63a89 | 1026 | |
| elmot | 1:d0dfbce63a89 | 1027 | /* Set Stop mode 2 */ |
| elmot | 1:d0dfbce63a89 | 1028 | MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2); |
| elmot | 1:d0dfbce63a89 | 1029 | |
| elmot | 1:d0dfbce63a89 | 1030 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
| elmot | 1:d0dfbce63a89 | 1031 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
| elmot | 1:d0dfbce63a89 | 1032 | |
| elmot | 1:d0dfbce63a89 | 1033 | /* Select Stop mode entry --------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 1034 | if(STOPEntry == PWR_STOPENTRY_WFI) |
| elmot | 1:d0dfbce63a89 | 1035 | { |
| elmot | 1:d0dfbce63a89 | 1036 | /* Request Wait For Interrupt */ |
| elmot | 1:d0dfbce63a89 | 1037 | __WFI(); |
| elmot | 1:d0dfbce63a89 | 1038 | } |
| elmot | 1:d0dfbce63a89 | 1039 | else |
| elmot | 1:d0dfbce63a89 | 1040 | { |
| elmot | 1:d0dfbce63a89 | 1041 | /* Request Wait For Event */ |
| elmot | 1:d0dfbce63a89 | 1042 | __SEV(); |
| elmot | 1:d0dfbce63a89 | 1043 | __WFE(); |
| elmot | 1:d0dfbce63a89 | 1044 | __WFE(); |
| elmot | 1:d0dfbce63a89 | 1045 | } |
| elmot | 1:d0dfbce63a89 | 1046 | |
| elmot | 1:d0dfbce63a89 | 1047 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ |
| elmot | 1:d0dfbce63a89 | 1048 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
| elmot | 1:d0dfbce63a89 | 1049 | } |
| elmot | 1:d0dfbce63a89 | 1050 | |
| elmot | 1:d0dfbce63a89 | 1051 | |
| elmot | 1:d0dfbce63a89 | 1052 | |
| elmot | 1:d0dfbce63a89 | 1053 | |
| elmot | 1:d0dfbce63a89 | 1054 | |
| elmot | 1:d0dfbce63a89 | 1055 | /** |
| elmot | 1:d0dfbce63a89 | 1056 | * @brief Enter Shutdown mode. |
| elmot | 1:d0dfbce63a89 | 1057 | * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched |
| elmot | 1:d0dfbce63a89 | 1058 | * off. The voltage regulator is disabled and Vcore domain is powered off. |
| elmot | 1:d0dfbce63a89 | 1059 | * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain. |
| elmot | 1:d0dfbce63a89 | 1060 | * The BOR is not available. |
| elmot | 1:d0dfbce63a89 | 1061 | * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. |
| elmot | 1:d0dfbce63a89 | 1062 | * @retval None |
| elmot | 1:d0dfbce63a89 | 1063 | */ |
| elmot | 1:d0dfbce63a89 | 1064 | void HAL_PWREx_EnterSHUTDOWNMode(void) |
| elmot | 1:d0dfbce63a89 | 1065 | { |
| elmot | 1:d0dfbce63a89 | 1066 | |
| elmot | 1:d0dfbce63a89 | 1067 | /* Set Shutdown mode */ |
| elmot | 1:d0dfbce63a89 | 1068 | MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN); |
| elmot | 1:d0dfbce63a89 | 1069 | |
| elmot | 1:d0dfbce63a89 | 1070 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
| elmot | 1:d0dfbce63a89 | 1071 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
| elmot | 1:d0dfbce63a89 | 1072 | |
| elmot | 1:d0dfbce63a89 | 1073 | /* This option is used to ensure that store operations are completed */ |
| elmot | 1:d0dfbce63a89 | 1074 | #if defined ( __CC_ARM) |
| elmot | 1:d0dfbce63a89 | 1075 | __force_stores(); |
| elmot | 1:d0dfbce63a89 | 1076 | #endif |
| elmot | 1:d0dfbce63a89 | 1077 | /* Request Wait For Interrupt */ |
| elmot | 1:d0dfbce63a89 | 1078 | __WFI(); |
| elmot | 1:d0dfbce63a89 | 1079 | } |
| elmot | 1:d0dfbce63a89 | 1080 | |
| elmot | 1:d0dfbce63a89 | 1081 | |
| elmot | 1:d0dfbce63a89 | 1082 | |
| elmot | 1:d0dfbce63a89 | 1083 | |
| elmot | 1:d0dfbce63a89 | 1084 | /** |
| elmot | 1:d0dfbce63a89 | 1085 | * @brief This function handles the PWR PVD/PVMx interrupt request. |
| elmot | 1:d0dfbce63a89 | 1086 | * @note This API should be called under the PVD_PVM_IRQHandler(). |
| elmot | 1:d0dfbce63a89 | 1087 | * @retval None |
| elmot | 1:d0dfbce63a89 | 1088 | */ |
| elmot | 1:d0dfbce63a89 | 1089 | void HAL_PWREx_PVD_PVM_IRQHandler(void) |
| elmot | 1:d0dfbce63a89 | 1090 | { |
| elmot | 1:d0dfbce63a89 | 1091 | /* Check PWR exti flag */ |
| elmot | 1:d0dfbce63a89 | 1092 | if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) |
| elmot | 1:d0dfbce63a89 | 1093 | { |
| elmot | 1:d0dfbce63a89 | 1094 | /* PWR PVD interrupt user callback */ |
| elmot | 1:d0dfbce63a89 | 1095 | HAL_PWR_PVDCallback(); |
| elmot | 1:d0dfbce63a89 | 1096 | |
| elmot | 1:d0dfbce63a89 | 1097 | /* Clear PVD exti pending bit */ |
| elmot | 1:d0dfbce63a89 | 1098 | __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); |
| elmot | 1:d0dfbce63a89 | 1099 | } |
| elmot | 1:d0dfbce63a89 | 1100 | /* Next, successively check PVMx exti flags */ |
| elmot | 1:d0dfbce63a89 | 1101 | #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 1102 | if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET) |
| elmot | 1:d0dfbce63a89 | 1103 | { |
| elmot | 1:d0dfbce63a89 | 1104 | /* PWR PVM1 interrupt user callback */ |
| elmot | 1:d0dfbce63a89 | 1105 | HAL_PWREx_PVM1Callback(); |
| elmot | 1:d0dfbce63a89 | 1106 | |
| elmot | 1:d0dfbce63a89 | 1107 | /* Clear PVM1 exti pending bit */ |
| elmot | 1:d0dfbce63a89 | 1108 | __HAL_PWR_PVM1_EXTI_CLEAR_FLAG(); |
| elmot | 1:d0dfbce63a89 | 1109 | } |
| elmot | 1:d0dfbce63a89 | 1110 | #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ |
| elmot | 1:d0dfbce63a89 | 1111 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 1112 | if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET) |
| elmot | 1:d0dfbce63a89 | 1113 | { |
| elmot | 1:d0dfbce63a89 | 1114 | /* PWR PVM2 interrupt user callback */ |
| elmot | 1:d0dfbce63a89 | 1115 | HAL_PWREx_PVM2Callback(); |
| elmot | 1:d0dfbce63a89 | 1116 | |
| elmot | 1:d0dfbce63a89 | 1117 | /* Clear PVM2 exti pending bit */ |
| elmot | 1:d0dfbce63a89 | 1118 | __HAL_PWR_PVM2_EXTI_CLEAR_FLAG(); |
| elmot | 1:d0dfbce63a89 | 1119 | } |
| elmot | 1:d0dfbce63a89 | 1120 | #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ |
| elmot | 1:d0dfbce63a89 | 1121 | if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET) |
| elmot | 1:d0dfbce63a89 | 1122 | { |
| elmot | 1:d0dfbce63a89 | 1123 | /* PWR PVM3 interrupt user callback */ |
| elmot | 1:d0dfbce63a89 | 1124 | HAL_PWREx_PVM3Callback(); |
| elmot | 1:d0dfbce63a89 | 1125 | |
| elmot | 1:d0dfbce63a89 | 1126 | /* Clear PVM3 exti pending bit */ |
| elmot | 1:d0dfbce63a89 | 1127 | __HAL_PWR_PVM3_EXTI_CLEAR_FLAG(); |
| elmot | 1:d0dfbce63a89 | 1128 | } |
| elmot | 1:d0dfbce63a89 | 1129 | if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET) |
| elmot | 1:d0dfbce63a89 | 1130 | { |
| elmot | 1:d0dfbce63a89 | 1131 | /* PWR PVM4 interrupt user callback */ |
| elmot | 1:d0dfbce63a89 | 1132 | HAL_PWREx_PVM4Callback(); |
| elmot | 1:d0dfbce63a89 | 1133 | |
| elmot | 1:d0dfbce63a89 | 1134 | /* Clear PVM4 exti pending bit */ |
| elmot | 1:d0dfbce63a89 | 1135 | __HAL_PWR_PVM4_EXTI_CLEAR_FLAG(); |
| elmot | 1:d0dfbce63a89 | 1136 | } |
| elmot | 1:d0dfbce63a89 | 1137 | } |
| elmot | 1:d0dfbce63a89 | 1138 | |
| elmot | 1:d0dfbce63a89 | 1139 | |
| elmot | 1:d0dfbce63a89 | 1140 | #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 1141 | /** |
| elmot | 1:d0dfbce63a89 | 1142 | * @brief PWR PVM1 interrupt callback |
| elmot | 1:d0dfbce63a89 | 1143 | * @retval None |
| elmot | 1:d0dfbce63a89 | 1144 | */ |
| elmot | 1:d0dfbce63a89 | 1145 | __weak void HAL_PWREx_PVM1Callback(void) |
| elmot | 1:d0dfbce63a89 | 1146 | { |
| elmot | 1:d0dfbce63a89 | 1147 | /* NOTE : This function should not be modified; when the callback is needed, |
| elmot | 1:d0dfbce63a89 | 1148 | HAL_PWREx_PVM1Callback() API can be implemented in the user file |
| elmot | 1:d0dfbce63a89 | 1149 | */ |
| elmot | 1:d0dfbce63a89 | 1150 | } |
| elmot | 1:d0dfbce63a89 | 1151 | #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ |
| elmot | 1:d0dfbce63a89 | 1152 | |
| elmot | 1:d0dfbce63a89 | 1153 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 1154 | /** |
| elmot | 1:d0dfbce63a89 | 1155 | * @brief PWR PVM2 interrupt callback |
| elmot | 1:d0dfbce63a89 | 1156 | * @retval None |
| elmot | 1:d0dfbce63a89 | 1157 | */ |
| elmot | 1:d0dfbce63a89 | 1158 | __weak void HAL_PWREx_PVM2Callback(void) |
| elmot | 1:d0dfbce63a89 | 1159 | { |
| elmot | 1:d0dfbce63a89 | 1160 | /* NOTE : This function should not be modified; when the callback is needed, |
| elmot | 1:d0dfbce63a89 | 1161 | HAL_PWREx_PVM2Callback() API can be implemented in the user file |
| elmot | 1:d0dfbce63a89 | 1162 | */ |
| elmot | 1:d0dfbce63a89 | 1163 | } |
| elmot | 1:d0dfbce63a89 | 1164 | #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ |
| elmot | 1:d0dfbce63a89 | 1165 | |
| elmot | 1:d0dfbce63a89 | 1166 | /** |
| elmot | 1:d0dfbce63a89 | 1167 | * @brief PWR PVM3 interrupt callback |
| elmot | 1:d0dfbce63a89 | 1168 | * @retval None |
| elmot | 1:d0dfbce63a89 | 1169 | */ |
| elmot | 1:d0dfbce63a89 | 1170 | __weak void HAL_PWREx_PVM3Callback(void) |
| elmot | 1:d0dfbce63a89 | 1171 | { |
| elmot | 1:d0dfbce63a89 | 1172 | /* NOTE : This function should not be modified; when the callback is needed, |
| elmot | 1:d0dfbce63a89 | 1173 | HAL_PWREx_PVM3Callback() API can be implemented in the user file |
| elmot | 1:d0dfbce63a89 | 1174 | */ |
| elmot | 1:d0dfbce63a89 | 1175 | } |
| elmot | 1:d0dfbce63a89 | 1176 | |
| elmot | 1:d0dfbce63a89 | 1177 | /** |
| elmot | 1:d0dfbce63a89 | 1178 | * @brief PWR PVM4 interrupt callback |
| elmot | 1:d0dfbce63a89 | 1179 | * @retval None |
| elmot | 1:d0dfbce63a89 | 1180 | */ |
| elmot | 1:d0dfbce63a89 | 1181 | __weak void HAL_PWREx_PVM4Callback(void) |
| elmot | 1:d0dfbce63a89 | 1182 | { |
| elmot | 1:d0dfbce63a89 | 1183 | /* NOTE : This function should not be modified; when the callback is needed, |
| elmot | 1:d0dfbce63a89 | 1184 | HAL_PWREx_PVM4Callback() API can be implemented in the user file |
| elmot | 1:d0dfbce63a89 | 1185 | */ |
| elmot | 1:d0dfbce63a89 | 1186 | } |
| elmot | 1:d0dfbce63a89 | 1187 | |
| elmot | 1:d0dfbce63a89 | 1188 | |
| elmot | 1:d0dfbce63a89 | 1189 | /** |
| elmot | 1:d0dfbce63a89 | 1190 | * @} |
| elmot | 1:d0dfbce63a89 | 1191 | */ |
| elmot | 1:d0dfbce63a89 | 1192 | |
| elmot | 1:d0dfbce63a89 | 1193 | /** |
| elmot | 1:d0dfbce63a89 | 1194 | * @} |
| elmot | 1:d0dfbce63a89 | 1195 | */ |
| elmot | 1:d0dfbce63a89 | 1196 | |
| elmot | 1:d0dfbce63a89 | 1197 | #endif /* HAL_PWR_MODULE_ENABLED */ |
| elmot | 1:d0dfbce63a89 | 1198 | /** |
| elmot | 1:d0dfbce63a89 | 1199 | * @} |
| elmot | 1:d0dfbce63a89 | 1200 | */ |
| elmot | 1:d0dfbce63a89 | 1201 | |
| elmot | 1:d0dfbce63a89 | 1202 | /** |
| elmot | 1:d0dfbce63a89 | 1203 | * @} |
| elmot | 1:d0dfbce63a89 | 1204 | */ |
| elmot | 1:d0dfbce63a89 | 1205 | |
| elmot | 1:d0dfbce63a89 | 1206 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |