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HAL_L476/stm32l4xx_hal_pwr.c@1:d0dfbce63a89, 2017-02-24 (annotated)

Committer:
elmot
Date:
Fri Feb 24 21:13:56 2017 +0000
Revision:
1:d0dfbce63a89
Ready-to-copy

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elmot 1:d0dfbce63a89 1 /**
elmot 1:d0dfbce63a89 2 ******************************************************************************
elmot 1:d0dfbce63a89 3 * @file stm32l4xx_hal_pwr.c
elmot 1:d0dfbce63a89 4 * @author MCD Application Team
elmot 1:d0dfbce63a89 5 * @version V1.5.1
elmot 1:d0dfbce63a89 6 * @date 31-May-2016
elmot 1:d0dfbce63a89 7 * @brief PWR HAL module driver.
elmot 1:d0dfbce63a89 8 * This file provides firmware functions to manage the following
elmot 1:d0dfbce63a89 9 * functionalities of the Power Controller (PWR) peripheral:
elmot 1:d0dfbce63a89 10 * + Initialization/de-initialization functions
elmot 1:d0dfbce63a89 11 * + Peripheral Control functions
elmot 1:d0dfbce63a89 12 *
elmot 1:d0dfbce63a89 13 ******************************************************************************
elmot 1:d0dfbce63a89 14 * @attention
elmot 1:d0dfbce63a89 15 *
elmot 1:d0dfbce63a89 16 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
elmot 1:d0dfbce63a89 17 *
elmot 1:d0dfbce63a89 18 * Redistribution and use in source and binary forms, with or without modification,
elmot 1:d0dfbce63a89 19 * are permitted provided that the following conditions are met:
elmot 1:d0dfbce63a89 20 * 1. Redistributions of source code must retain the above copyright notice,
elmot 1:d0dfbce63a89 21 * this list of conditions and the following disclaimer.
elmot 1:d0dfbce63a89 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
elmot 1:d0dfbce63a89 23 * this list of conditions and the following disclaimer in the documentation
elmot 1:d0dfbce63a89 24 * and/or other materials provided with the distribution.
elmot 1:d0dfbce63a89 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
elmot 1:d0dfbce63a89 26 * may be used to endorse or promote products derived from this software
elmot 1:d0dfbce63a89 27 * without specific prior written permission.
elmot 1:d0dfbce63a89 28 *
elmot 1:d0dfbce63a89 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elmot 1:d0dfbce63a89 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elmot 1:d0dfbce63a89 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elmot 1:d0dfbce63a89 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
elmot 1:d0dfbce63a89 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
elmot 1:d0dfbce63a89 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
elmot 1:d0dfbce63a89 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
elmot 1:d0dfbce63a89 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
elmot 1:d0dfbce63a89 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
elmot 1:d0dfbce63a89 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elmot 1:d0dfbce63a89 39 *
elmot 1:d0dfbce63a89 40 ******************************************************************************
elmot 1:d0dfbce63a89 41 */
elmot 1:d0dfbce63a89 42
elmot 1:d0dfbce63a89 43 /* Includes ------------------------------------------------------------------*/
elmot 1:d0dfbce63a89 44 #include "stm32l4xx_hal.h"
elmot 1:d0dfbce63a89 45
elmot 1:d0dfbce63a89 46 /** @addtogroup STM32L4xx_HAL_Driver
elmot 1:d0dfbce63a89 47 * @{
elmot 1:d0dfbce63a89 48 */
elmot 1:d0dfbce63a89 49
elmot 1:d0dfbce63a89 50 /** @defgroup PWR PWR
elmot 1:d0dfbce63a89 51 * @brief PWR HAL module driver
elmot 1:d0dfbce63a89 52 * @{
elmot 1:d0dfbce63a89 53 */
elmot 1:d0dfbce63a89 54
elmot 1:d0dfbce63a89 55 #ifdef HAL_PWR_MODULE_ENABLED
elmot 1:d0dfbce63a89 56
elmot 1:d0dfbce63a89 57 /* Private typedef -----------------------------------------------------------*/
elmot 1:d0dfbce63a89 58 /* Private define ------------------------------------------------------------*/
elmot 1:d0dfbce63a89 59
elmot 1:d0dfbce63a89 60 /** @defgroup PWR_Private_Defines PWR Private Defines
elmot 1:d0dfbce63a89 61 * @{
elmot 1:d0dfbce63a89 62 */
elmot 1:d0dfbce63a89 63
elmot 1:d0dfbce63a89 64 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
elmot 1:d0dfbce63a89 65 * @{
elmot 1:d0dfbce63a89 66 */
elmot 1:d0dfbce63a89 67 #define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */
elmot 1:d0dfbce63a89 68 #define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */
elmot 1:d0dfbce63a89 69 #define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */
elmot 1:d0dfbce63a89 70 #define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */
elmot 1:d0dfbce63a89 71 /**
elmot 1:d0dfbce63a89 72 * @}
elmot 1:d0dfbce63a89 73 */
elmot 1:d0dfbce63a89 74
elmot 1:d0dfbce63a89 75 /**
elmot 1:d0dfbce63a89 76 * @}
elmot 1:d0dfbce63a89 77 */
elmot 1:d0dfbce63a89 78
elmot 1:d0dfbce63a89 79 /* Private macro -------------------------------------------------------------*/
elmot 1:d0dfbce63a89 80 /* Private variables ---------------------------------------------------------*/
elmot 1:d0dfbce63a89 81 /* Private function prototypes -----------------------------------------------*/
elmot 1:d0dfbce63a89 82 /* Exported functions --------------------------------------------------------*/
elmot 1:d0dfbce63a89 83
elmot 1:d0dfbce63a89 84 /** @defgroup PWR_Exported_Functions PWR Exported Functions
elmot 1:d0dfbce63a89 85 * @{
elmot 1:d0dfbce63a89 86 */
elmot 1:d0dfbce63a89 87
elmot 1:d0dfbce63a89 88 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
elmot 1:d0dfbce63a89 89 * @brief Initialization and de-initialization functions
elmot 1:d0dfbce63a89 90 *
elmot 1:d0dfbce63a89 91 @verbatim
elmot 1:d0dfbce63a89 92 ===============================================================================
elmot 1:d0dfbce63a89 93 ##### Initialization and de-initialization functions #####
elmot 1:d0dfbce63a89 94 ===============================================================================
elmot 1:d0dfbce63a89 95 [..]
elmot 1:d0dfbce63a89 96
elmot 1:d0dfbce63a89 97 @endverbatim
elmot 1:d0dfbce63a89 98 * @{
elmot 1:d0dfbce63a89 99 */
elmot 1:d0dfbce63a89 100
elmot 1:d0dfbce63a89 101 /**
elmot 1:d0dfbce63a89 102 * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
elmot 1:d0dfbce63a89 103 * @retval None
elmot 1:d0dfbce63a89 104 */
elmot 1:d0dfbce63a89 105 void HAL_PWR_DeInit(void)
elmot 1:d0dfbce63a89 106 {
elmot 1:d0dfbce63a89 107 __HAL_RCC_PWR_FORCE_RESET();
elmot 1:d0dfbce63a89 108 __HAL_RCC_PWR_RELEASE_RESET();
elmot 1:d0dfbce63a89 109 }
elmot 1:d0dfbce63a89 110
elmot 1:d0dfbce63a89 111 /**
elmot 1:d0dfbce63a89 112 * @brief Enable access to the backup domain
elmot 1:d0dfbce63a89 113 * (RTC registers, RTC backup data registers).
elmot 1:d0dfbce63a89 114 * @note After reset, the backup domain is protected against
elmot 1:d0dfbce63a89 115 * possible unwanted write accesses.
elmot 1:d0dfbce63a89 116 * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
elmot 1:d0dfbce63a89 117 * In order to set or modify the RTC clock, the backup domain access must be
elmot 1:d0dfbce63a89 118 * disabled.
elmot 1:d0dfbce63a89 119 * @note LSEON bit that switches on and off the LSE crystal belongs as well to the
elmot 1:d0dfbce63a89 120 * back-up domain.
elmot 1:d0dfbce63a89 121 * @retval None
elmot 1:d0dfbce63a89 122 */
elmot 1:d0dfbce63a89 123 void HAL_PWR_EnableBkUpAccess(void)
elmot 1:d0dfbce63a89 124 {
elmot 1:d0dfbce63a89 125 SET_BIT(PWR->CR1, PWR_CR1_DBP);
elmot 1:d0dfbce63a89 126 }
elmot 1:d0dfbce63a89 127
elmot 1:d0dfbce63a89 128 /**
elmot 1:d0dfbce63a89 129 * @brief Disable access to the backup domain
elmot 1:d0dfbce63a89 130 * (RTC registers, RTC backup data registers).
elmot 1:d0dfbce63a89 131 * @retval None
elmot 1:d0dfbce63a89 132 */
elmot 1:d0dfbce63a89 133 void HAL_PWR_DisableBkUpAccess(void)
elmot 1:d0dfbce63a89 134 {
elmot 1:d0dfbce63a89 135 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
elmot 1:d0dfbce63a89 136 }
elmot 1:d0dfbce63a89 137
elmot 1:d0dfbce63a89 138
elmot 1:d0dfbce63a89 139
elmot 1:d0dfbce63a89 140
elmot 1:d0dfbce63a89 141 /**
elmot 1:d0dfbce63a89 142 * @}
elmot 1:d0dfbce63a89 143 */
elmot 1:d0dfbce63a89 144
elmot 1:d0dfbce63a89 145
elmot 1:d0dfbce63a89 146
elmot 1:d0dfbce63a89 147 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
elmot 1:d0dfbce63a89 148 * @brief Low Power modes configuration functions
elmot 1:d0dfbce63a89 149 *
elmot 1:d0dfbce63a89 150 @verbatim
elmot 1:d0dfbce63a89 151
elmot 1:d0dfbce63a89 152 ===============================================================================
elmot 1:d0dfbce63a89 153 ##### Peripheral Control functions #####
elmot 1:d0dfbce63a89 154 ===============================================================================
elmot 1:d0dfbce63a89 155
elmot 1:d0dfbce63a89 156 [..]
elmot 1:d0dfbce63a89 157 *** PVD configuration ***
elmot 1:d0dfbce63a89 158 =========================
elmot 1:d0dfbce63a89 159 [..]
elmot 1:d0dfbce63a89 160 (+) The PVD is used to monitor the VDD power supply by comparing it to a
elmot 1:d0dfbce63a89 161 threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
elmot 1:d0dfbce63a89 162
elmot 1:d0dfbce63a89 163 (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
elmot 1:d0dfbce63a89 164 than the PVD threshold. This event is internally connected to the EXTI
elmot 1:d0dfbce63a89 165 line16 and can generate an interrupt if enabled. This is done through
elmot 1:d0dfbce63a89 166 __HAL_PVD_EXTI_ENABLE_IT() macro.
elmot 1:d0dfbce63a89 167 (+) The PVD is stopped in Standby mode.
elmot 1:d0dfbce63a89 168
elmot 1:d0dfbce63a89 169
elmot 1:d0dfbce63a89 170 *** WakeUp pin configuration ***
elmot 1:d0dfbce63a89 171 ================================
elmot 1:d0dfbce63a89 172 [..]
elmot 1:d0dfbce63a89 173 (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
elmot 1:d0dfbce63a89 174 The polarity of these pins can be set to configure event detection on high
elmot 1:d0dfbce63a89 175 level (rising edge) or low level (falling edge).
elmot 1:d0dfbce63a89 176
elmot 1:d0dfbce63a89 177
elmot 1:d0dfbce63a89 178
elmot 1:d0dfbce63a89 179 *** Low Power modes configuration ***
elmot 1:d0dfbce63a89 180 =====================================
elmot 1:d0dfbce63a89 181 [..]
elmot 1:d0dfbce63a89 182 The devices feature 8 low-power modes:
elmot 1:d0dfbce63a89 183 (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
elmot 1:d0dfbce63a89 184 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
elmot 1:d0dfbce63a89 185 (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
elmot 1:d0dfbce63a89 186 (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
elmot 1:d0dfbce63a89 187 (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
elmot 1:d0dfbce63a89 188 (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
elmot 1:d0dfbce63a89 189 (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
elmot 1:d0dfbce63a89 190 (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
elmot 1:d0dfbce63a89 191 (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
elmot 1:d0dfbce63a89 192
elmot 1:d0dfbce63a89 193
elmot 1:d0dfbce63a89 194 *** Low-power run mode ***
elmot 1:d0dfbce63a89 195 ==========================
elmot 1:d0dfbce63a89 196 [..]
elmot 1:d0dfbce63a89 197 (+) Entry: (from main run mode)
elmot 1:d0dfbce63a89 198 (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
elmot 1:d0dfbce63a89 199
elmot 1:d0dfbce63a89 200 (+) Exit:
elmot 1:d0dfbce63a89 201 (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
elmot 1:d0dfbce63a89 202 then can the system clock frequency be increased above 2 MHz.
elmot 1:d0dfbce63a89 203
elmot 1:d0dfbce63a89 204
elmot 1:d0dfbce63a89 205 *** Sleep mode / Low-power sleep mode ***
elmot 1:d0dfbce63a89 206 =========================================
elmot 1:d0dfbce63a89 207 [..]
elmot 1:d0dfbce63a89 208 (+) Entry:
elmot 1:d0dfbce63a89 209 The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
elmot 1:d0dfbce63a89 210 in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
elmot 1:d0dfbce63a89 211 (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
elmot 1:d0dfbce63a89 212 (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
elmot 1:d0dfbce63a89 213 In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
elmot 1:d0dfbce63a89 214 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
elmot 1:d0dfbce63a89 215 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
elmot 1:d0dfbce63a89 216
elmot 1:d0dfbce63a89 217 (+) WFI Exit:
elmot 1:d0dfbce63a89 218 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
elmot 1:d0dfbce63a89 219 controller (NVIC) or any wake-up event.
elmot 1:d0dfbce63a89 220
elmot 1:d0dfbce63a89 221 (+) WFE Exit:
elmot 1:d0dfbce63a89 222 (++) Any wake-up event such as an EXTI line configured in event mode.
elmot 1:d0dfbce63a89 223
elmot 1:d0dfbce63a89 224 [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
elmot 1:d0dfbce63a89 225 the MCU is in Low-power Run mode.
elmot 1:d0dfbce63a89 226
elmot 1:d0dfbce63a89 227 *** Stop 0, Stop 1 and Stop 2 modes ***
elmot 1:d0dfbce63a89 228 ===============================
elmot 1:d0dfbce63a89 229 [..]
elmot 1:d0dfbce63a89 230 (+) Entry:
elmot 1:d0dfbce63a89 231 The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
elmot 1:d0dfbce63a89 232 (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
elmot 1:d0dfbce63a89 233 (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
elmot 1:d0dfbce63a89 234 (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
elmot 1:d0dfbce63a89 235 (++) PWR_MAINREGULATOR_ON
elmot 1:d0dfbce63a89 236 (++) PWR_LOWPOWERREGULATOR_ON
elmot 1:d0dfbce63a89 237 (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
elmot 1:d0dfbce63a89 238 (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
elmot 1:d0dfbce63a89 239 (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
elmot 1:d0dfbce63a89 240
elmot 1:d0dfbce63a89 241 (+) WFI Exit:
elmot 1:d0dfbce63a89 242 (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
elmot 1:d0dfbce63a89 243 (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
elmot 1:d0dfbce63a89 244 when programmed in wakeup mode.
elmot 1:d0dfbce63a89 245 (+) WFE Exit:
elmot 1:d0dfbce63a89 246 (++) Any EXTI Line (Internal or External) configured in Event mode.
elmot 1:d0dfbce63a89 247
elmot 1:d0dfbce63a89 248 [..]
elmot 1:d0dfbce63a89 249 When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
elmot 1:d0dfbce63a89 250 depending on the LPR bit setting.
elmot 1:d0dfbce63a89 251 When exiting Stop 2 mode, the MCU is in Run mode.
elmot 1:d0dfbce63a89 252
elmot 1:d0dfbce63a89 253 *** Standby mode ***
elmot 1:d0dfbce63a89 254 ====================
elmot 1:d0dfbce63a89 255 [..]
elmot 1:d0dfbce63a89 256 The Standby mode offers two options:
elmot 1:d0dfbce63a89 257 (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
elmot 1:d0dfbce63a89 258 SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
elmot 1:d0dfbce63a89 259 and Standby circuitry.
elmot 1:d0dfbce63a89 260 (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
elmot 1:d0dfbce63a89 261 SRAM and register contents are lost except for the RTC registers, RTC backup registers
elmot 1:d0dfbce63a89 262 and Standby circuitry.
elmot 1:d0dfbce63a89 263
elmot 1:d0dfbce63a89 264 (++) Entry:
elmot 1:d0dfbce63a89 265 (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
elmot 1:d0dfbce63a89 266 SRAM1 and register contents are lost except for registers in the Backup domain and
elmot 1:d0dfbce63a89 267 Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
elmot 1:d0dfbce63a89 268 To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
elmot 1:d0dfbce63a89 269 to set RRS bit.
elmot 1:d0dfbce63a89 270
elmot 1:d0dfbce63a89 271 (++) Exit:
elmot 1:d0dfbce63a89 272 (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
elmot 1:d0dfbce63a89 273 external reset in NRST pin, IWDG reset.
elmot 1:d0dfbce63a89 274
elmot 1:d0dfbce63a89 275 [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
elmot 1:d0dfbce63a89 276
elmot 1:d0dfbce63a89 277
elmot 1:d0dfbce63a89 278 *** Shutdown mode ***
elmot 1:d0dfbce63a89 279 ======================
elmot 1:d0dfbce63a89 280 [..]
elmot 1:d0dfbce63a89 281 In Shutdown mode,
elmot 1:d0dfbce63a89 282 voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
elmot 1:d0dfbce63a89 283 SRAM and registers contents are lost except for backup domain registers.
elmot 1:d0dfbce63a89 284
elmot 1:d0dfbce63a89 285 (+) Entry:
elmot 1:d0dfbce63a89 286 The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
elmot 1:d0dfbce63a89 287
elmot 1:d0dfbce63a89 288 (+) Exit:
elmot 1:d0dfbce63a89 289 (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
elmot 1:d0dfbce63a89 290 external reset in NRST pin.
elmot 1:d0dfbce63a89 291
elmot 1:d0dfbce63a89 292 [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
elmot 1:d0dfbce63a89 293
elmot 1:d0dfbce63a89 294
elmot 1:d0dfbce63a89 295 *** Auto-wakeup (AWU) from low-power mode ***
elmot 1:d0dfbce63a89 296 =============================================
elmot 1:d0dfbce63a89 297 [..]
elmot 1:d0dfbce63a89 298 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
elmot 1:d0dfbce63a89 299 Wakeup event, a tamper event or a time-stamp event, without depending on
elmot 1:d0dfbce63a89 300 an external interrupt (Auto-wakeup mode).
elmot 1:d0dfbce63a89 301
elmot 1:d0dfbce63a89 302 (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
elmot 1:d0dfbce63a89 303
elmot 1:d0dfbce63a89 304
elmot 1:d0dfbce63a89 305 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
elmot 1:d0dfbce63a89 306 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
elmot 1:d0dfbce63a89 307
elmot 1:d0dfbce63a89 308 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
elmot 1:d0dfbce63a89 309 is necessary to configure the RTC to detect the tamper or time stamp event using the
elmot 1:d0dfbce63a89 310 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
elmot 1:d0dfbce63a89 311
elmot 1:d0dfbce63a89 312 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
elmot 1:d0dfbce63a89 313 configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
elmot 1:d0dfbce63a89 314
elmot 1:d0dfbce63a89 315 @endverbatim
elmot 1:d0dfbce63a89 316 * @{
elmot 1:d0dfbce63a89 317 */
elmot 1:d0dfbce63a89 318
elmot 1:d0dfbce63a89 319
elmot 1:d0dfbce63a89 320
elmot 1:d0dfbce63a89 321 /**
elmot 1:d0dfbce63a89 322 * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
elmot 1:d0dfbce63a89 323 * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
elmot 1:d0dfbce63a89 324 * configuration information.
elmot 1:d0dfbce63a89 325 * @note Refer to the electrical characteristics of your device datasheet for
elmot 1:d0dfbce63a89 326 * more details about the voltage thresholds corresponding to each
elmot 1:d0dfbce63a89 327 * detection level.
elmot 1:d0dfbce63a89 328 * @retval None
elmot 1:d0dfbce63a89 329 */
elmot 1:d0dfbce63a89 330 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
elmot 1:d0dfbce63a89 331 {
elmot 1:d0dfbce63a89 332 /* Check the parameters */
elmot 1:d0dfbce63a89 333 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
elmot 1:d0dfbce63a89 334 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
elmot 1:d0dfbce63a89 335
elmot 1:d0dfbce63a89 336 /* Set PLS bits according to PVDLevel value */
elmot 1:d0dfbce63a89 337 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
elmot 1:d0dfbce63a89 338
elmot 1:d0dfbce63a89 339 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
elmot 1:d0dfbce63a89 340 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
elmot 1:d0dfbce63a89 341 __HAL_PWR_PVD_EXTI_DISABLE_IT();
elmot 1:d0dfbce63a89 342 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
elmot 1:d0dfbce63a89 343 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
elmot 1:d0dfbce63a89 344
elmot 1:d0dfbce63a89 345 /* Configure interrupt mode */
elmot 1:d0dfbce63a89 346 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
elmot 1:d0dfbce63a89 347 {
elmot 1:d0dfbce63a89 348 __HAL_PWR_PVD_EXTI_ENABLE_IT();
elmot 1:d0dfbce63a89 349 }
elmot 1:d0dfbce63a89 350
elmot 1:d0dfbce63a89 351 /* Configure event mode */
elmot 1:d0dfbce63a89 352 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
elmot 1:d0dfbce63a89 353 {
elmot 1:d0dfbce63a89 354 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
elmot 1:d0dfbce63a89 355 }
elmot 1:d0dfbce63a89 356
elmot 1:d0dfbce63a89 357 /* Configure the edge */
elmot 1:d0dfbce63a89 358 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
elmot 1:d0dfbce63a89 359 {
elmot 1:d0dfbce63a89 360 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
elmot 1:d0dfbce63a89 361 }
elmot 1:d0dfbce63a89 362
elmot 1:d0dfbce63a89 363 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
elmot 1:d0dfbce63a89 364 {
elmot 1:d0dfbce63a89 365 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
elmot 1:d0dfbce63a89 366 }
elmot 1:d0dfbce63a89 367
elmot 1:d0dfbce63a89 368 return HAL_OK;
elmot 1:d0dfbce63a89 369 }
elmot 1:d0dfbce63a89 370
elmot 1:d0dfbce63a89 371
elmot 1:d0dfbce63a89 372 /**
elmot 1:d0dfbce63a89 373 * @brief Enable the Power Voltage Detector (PVD).
elmot 1:d0dfbce63a89 374 * @retval None
elmot 1:d0dfbce63a89 375 */
elmot 1:d0dfbce63a89 376 void HAL_PWR_EnablePVD(void)
elmot 1:d0dfbce63a89 377 {
elmot 1:d0dfbce63a89 378 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
elmot 1:d0dfbce63a89 379 }
elmot 1:d0dfbce63a89 380
elmot 1:d0dfbce63a89 381 /**
elmot 1:d0dfbce63a89 382 * @brief Disable the Power Voltage Detector (PVD).
elmot 1:d0dfbce63a89 383 * @retval None
elmot 1:d0dfbce63a89 384 */
elmot 1:d0dfbce63a89 385 void HAL_PWR_DisablePVD(void)
elmot 1:d0dfbce63a89 386 {
elmot 1:d0dfbce63a89 387 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
elmot 1:d0dfbce63a89 388 }
elmot 1:d0dfbce63a89 389
elmot 1:d0dfbce63a89 390
elmot 1:d0dfbce63a89 391
elmot 1:d0dfbce63a89 392
elmot 1:d0dfbce63a89 393 /**
elmot 1:d0dfbce63a89 394 * @brief Enable the WakeUp PINx functionality.
elmot 1:d0dfbce63a89 395 * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
elmot 1:d0dfbce63a89 396 * This parameter can be one of the following legacy values which set the default polarity
elmot 1:d0dfbce63a89 397 * i.e. detection on high level (rising edge):
elmot 1:d0dfbce63a89 398 * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
elmot 1:d0dfbce63a89 399 *
elmot 1:d0dfbce63a89 400 * or one of the following value where the user can explicitly specify the enabled pin and
elmot 1:d0dfbce63a89 401 * the chosen polarity:
elmot 1:d0dfbce63a89 402 * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
elmot 1:d0dfbce63a89 403 * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
elmot 1:d0dfbce63a89 404 * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
elmot 1:d0dfbce63a89 405 * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
elmot 1:d0dfbce63a89 406 * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
elmot 1:d0dfbce63a89 407 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
elmot 1:d0dfbce63a89 408 * @retval None
elmot 1:d0dfbce63a89 409 */
elmot 1:d0dfbce63a89 410 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
elmot 1:d0dfbce63a89 411 {
elmot 1:d0dfbce63a89 412 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
elmot 1:d0dfbce63a89 413
elmot 1:d0dfbce63a89 414 /* Specifies the Wake-Up pin polarity for the event detection
elmot 1:d0dfbce63a89 415 (rising or falling edge) */
elmot 1:d0dfbce63a89 416 MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
elmot 1:d0dfbce63a89 417
elmot 1:d0dfbce63a89 418 /* Enable wake-up pin */
elmot 1:d0dfbce63a89 419 SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
elmot 1:d0dfbce63a89 420
elmot 1:d0dfbce63a89 421
elmot 1:d0dfbce63a89 422 }
elmot 1:d0dfbce63a89 423
elmot 1:d0dfbce63a89 424 /**
elmot 1:d0dfbce63a89 425 * @brief Disable the WakeUp PINx functionality.
elmot 1:d0dfbce63a89 426 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
elmot 1:d0dfbce63a89 427 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 428 * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
elmot 1:d0dfbce63a89 429 * @retval None
elmot 1:d0dfbce63a89 430 */
elmot 1:d0dfbce63a89 431 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
elmot 1:d0dfbce63a89 432 {
elmot 1:d0dfbce63a89 433 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
elmot 1:d0dfbce63a89 434
elmot 1:d0dfbce63a89 435 CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
elmot 1:d0dfbce63a89 436 }
elmot 1:d0dfbce63a89 437
elmot 1:d0dfbce63a89 438
elmot 1:d0dfbce63a89 439 /**
elmot 1:d0dfbce63a89 440 * @brief Enter Sleep or Low-power Sleep mode.
elmot 1:d0dfbce63a89 441 * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
elmot 1:d0dfbce63a89 442 * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
elmot 1:d0dfbce63a89 443 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 444 * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
elmot 1:d0dfbce63a89 445 * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
elmot 1:d0dfbce63a89 446 * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
elmot 1:d0dfbce63a89 447 * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
elmot 1:d0dfbce63a89 448 * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
elmot 1:d0dfbce63a89 449 * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
elmot 1:d0dfbce63a89 450 * Additionally, the clock frequency must be reduced below 2 MHz.
elmot 1:d0dfbce63a89 451 * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
elmot 1:d0dfbce63a89 452 * be done before calling HAL_PWR_EnterSLEEPMode() API.
elmot 1:d0dfbce63a89 453 * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
elmot 1:d0dfbce63a89 454 * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
elmot 1:d0dfbce63a89 455 * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
elmot 1:d0dfbce63a89 456 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 457 * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
elmot 1:d0dfbce63a89 458 * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
elmot 1:d0dfbce63a89 459 * @note When WFI entry is used, tick interrupt have to be disabled if not desired as
elmot 1:d0dfbce63a89 460 * the interrupt wake up source.
elmot 1:d0dfbce63a89 461 * @retval None
elmot 1:d0dfbce63a89 462 */
elmot 1:d0dfbce63a89 463 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
elmot 1:d0dfbce63a89 464 {
elmot 1:d0dfbce63a89 465 /* Check the parameters */
elmot 1:d0dfbce63a89 466 assert_param(IS_PWR_REGULATOR(Regulator));
elmot 1:d0dfbce63a89 467 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
elmot 1:d0dfbce63a89 468
elmot 1:d0dfbce63a89 469 /* Set Regulator parameter */
elmot 1:d0dfbce63a89 470 if (Regulator == PWR_MAINREGULATOR_ON)
elmot 1:d0dfbce63a89 471 {
elmot 1:d0dfbce63a89 472 /* If in low-power run mode at this point, exit it */
elmot 1:d0dfbce63a89 473 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
elmot 1:d0dfbce63a89 474 {
elmot 1:d0dfbce63a89 475 HAL_PWREx_DisableLowPowerRunMode();
elmot 1:d0dfbce63a89 476 }
elmot 1:d0dfbce63a89 477 /* Regulator now in main mode. */
elmot 1:d0dfbce63a89 478 }
elmot 1:d0dfbce63a89 479 else
elmot 1:d0dfbce63a89 480 {
elmot 1:d0dfbce63a89 481 /* If in run mode, first move to low-power run mode.
elmot 1:d0dfbce63a89 482 The system clock frequency must be below 2 MHz at this point. */
elmot 1:d0dfbce63a89 483 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
elmot 1:d0dfbce63a89 484 {
elmot 1:d0dfbce63a89 485 HAL_PWREx_EnableLowPowerRunMode();
elmot 1:d0dfbce63a89 486 }
elmot 1:d0dfbce63a89 487 }
elmot 1:d0dfbce63a89 488
elmot 1:d0dfbce63a89 489 /* Clear SLEEPDEEP bit of Cortex System Control Register */
elmot 1:d0dfbce63a89 490 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
elmot 1:d0dfbce63a89 491
elmot 1:d0dfbce63a89 492 /* Select SLEEP mode entry -------------------------------------------------*/
elmot 1:d0dfbce63a89 493 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
elmot 1:d0dfbce63a89 494 {
elmot 1:d0dfbce63a89 495 /* Request Wait For Interrupt */
elmot 1:d0dfbce63a89 496 __WFI();
elmot 1:d0dfbce63a89 497 }
elmot 1:d0dfbce63a89 498 else
elmot 1:d0dfbce63a89 499 {
elmot 1:d0dfbce63a89 500 /* Request Wait For Event */
elmot 1:d0dfbce63a89 501 __SEV();
elmot 1:d0dfbce63a89 502 __WFE();
elmot 1:d0dfbce63a89 503 __WFE();
elmot 1:d0dfbce63a89 504 }
elmot 1:d0dfbce63a89 505
elmot 1:d0dfbce63a89 506 }
elmot 1:d0dfbce63a89 507
elmot 1:d0dfbce63a89 508
elmot 1:d0dfbce63a89 509 /**
elmot 1:d0dfbce63a89 510 * @brief Enter Stop mode
elmot 1:d0dfbce63a89 511 * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
elmot 1:d0dfbce63a89 512 * on devices where only "Stop mode" is mentioned with main or low power regulator ON.
elmot 1:d0dfbce63a89 513 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
elmot 1:d0dfbce63a89 514 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
elmot 1:d0dfbce63a89 515 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
elmot 1:d0dfbce63a89 516 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
elmot 1:d0dfbce63a89 517 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
elmot 1:d0dfbce63a89 518 * only to the peripheral requesting it.
elmot 1:d0dfbce63a89 519 * SRAM1, SRAM2 and register contents are preserved.
elmot 1:d0dfbce63a89 520 * The BOR is available.
elmot 1:d0dfbce63a89 521 * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
elmot 1:d0dfbce63a89 522 * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
elmot 1:d0dfbce63a89 523 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
elmot 1:d0dfbce63a89 524 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
elmot 1:d0dfbce63a89 525 * @note When the voltage regulator operates in low power mode (Stop 1), an additional
elmot 1:d0dfbce63a89 526 * startup delay is incurred when waking up.
elmot 1:d0dfbce63a89 527 * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
elmot 1:d0dfbce63a89 528 * is higher although the startup time is reduced.
elmot 1:d0dfbce63a89 529 * @param Regulator: Specifies the regulator state in Stop mode.
elmot 1:d0dfbce63a89 530 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 531 * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
elmot 1:d0dfbce63a89 532 * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
elmot 1:d0dfbce63a89 533 * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
elmot 1:d0dfbce63a89 534 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 535 * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
elmot 1:d0dfbce63a89 536 * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
elmot 1:d0dfbce63a89 537 * @retval None
elmot 1:d0dfbce63a89 538 */
elmot 1:d0dfbce63a89 539 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
elmot 1:d0dfbce63a89 540 {
elmot 1:d0dfbce63a89 541 /* Check the parameters */
elmot 1:d0dfbce63a89 542 assert_param(IS_PWR_REGULATOR(Regulator));
elmot 1:d0dfbce63a89 543
elmot 1:d0dfbce63a89 544 if(Regulator == PWR_LOWPOWERREGULATOR_ON)
elmot 1:d0dfbce63a89 545 {
elmot 1:d0dfbce63a89 546 HAL_PWREx_EnterSTOP1Mode(STOPEntry);
elmot 1:d0dfbce63a89 547 }
elmot 1:d0dfbce63a89 548 else
elmot 1:d0dfbce63a89 549 {
elmot 1:d0dfbce63a89 550 HAL_PWREx_EnterSTOP0Mode(STOPEntry);
elmot 1:d0dfbce63a89 551 }
elmot 1:d0dfbce63a89 552 }
elmot 1:d0dfbce63a89 553
elmot 1:d0dfbce63a89 554 /**
elmot 1:d0dfbce63a89 555 * @brief Enter Standby mode.
elmot 1:d0dfbce63a89 556 * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
elmot 1:d0dfbce63a89 557 * off. The voltage regulator is disabled, except when SRAM2 content is preserved
elmot 1:d0dfbce63a89 558 * in which case the regulator is in low-power mode.
elmot 1:d0dfbce63a89 559 * SRAM1 and register contents are lost except for registers in the Backup domain and
elmot 1:d0dfbce63a89 560 * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
elmot 1:d0dfbce63a89 561 * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
elmot 1:d0dfbce63a89 562 * to set RRS bit.
elmot 1:d0dfbce63a89 563 * The BOR is available.
elmot 1:d0dfbce63a89 564 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
elmot 1:d0dfbce63a89 565 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
elmot 1:d0dfbce63a89 566 * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
elmot 1:d0dfbce63a89 567 * same.
elmot 1:d0dfbce63a89 568 * These states are effective in Standby mode only if APC bit is set through
elmot 1:d0dfbce63a89 569 * HAL_PWREx_EnablePullUpPullDownConfig() API.
elmot 1:d0dfbce63a89 570 * @retval None
elmot 1:d0dfbce63a89 571 */
elmot 1:d0dfbce63a89 572 void HAL_PWR_EnterSTANDBYMode(void)
elmot 1:d0dfbce63a89 573 {
elmot 1:d0dfbce63a89 574 /* Set Stand-by mode */
elmot 1:d0dfbce63a89 575 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
elmot 1:d0dfbce63a89 576
elmot 1:d0dfbce63a89 577 /* Set SLEEPDEEP bit of Cortex System Control Register */
elmot 1:d0dfbce63a89 578 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
elmot 1:d0dfbce63a89 579
elmot 1:d0dfbce63a89 580 /* This option is used to ensure that store operations are completed */
elmot 1:d0dfbce63a89 581 #if defined ( __CC_ARM)
elmot 1:d0dfbce63a89 582 __force_stores();
elmot 1:d0dfbce63a89 583 #endif
elmot 1:d0dfbce63a89 584 /* Request Wait For Interrupt */
elmot 1:d0dfbce63a89 585 __WFI();
elmot 1:d0dfbce63a89 586 }
elmot 1:d0dfbce63a89 587
elmot 1:d0dfbce63a89 588
elmot 1:d0dfbce63a89 589
elmot 1:d0dfbce63a89 590 /**
elmot 1:d0dfbce63a89 591 * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
elmot 1:d0dfbce63a89 592 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
elmot 1:d0dfbce63a89 593 * re-enters SLEEP mode when an interruption handling is over.
elmot 1:d0dfbce63a89 594 * Setting this bit is useful when the processor is expected to run only on
elmot 1:d0dfbce63a89 595 * interruptions handling.
elmot 1:d0dfbce63a89 596 * @retval None
elmot 1:d0dfbce63a89 597 */
elmot 1:d0dfbce63a89 598 void HAL_PWR_EnableSleepOnExit(void)
elmot 1:d0dfbce63a89 599 {
elmot 1:d0dfbce63a89 600 /* Set SLEEPONEXIT bit of Cortex System Control Register */
elmot 1:d0dfbce63a89 601 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
elmot 1:d0dfbce63a89 602 }
elmot 1:d0dfbce63a89 603
elmot 1:d0dfbce63a89 604
elmot 1:d0dfbce63a89 605 /**
elmot 1:d0dfbce63a89 606 * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
elmot 1:d0dfbce63a89 607 * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
elmot 1:d0dfbce63a89 608 * re-enters SLEEP mode when an interruption handling is over.
elmot 1:d0dfbce63a89 609 * @retval None
elmot 1:d0dfbce63a89 610 */
elmot 1:d0dfbce63a89 611 void HAL_PWR_DisableSleepOnExit(void)
elmot 1:d0dfbce63a89 612 {
elmot 1:d0dfbce63a89 613 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
elmot 1:d0dfbce63a89 614 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
elmot 1:d0dfbce63a89 615 }
elmot 1:d0dfbce63a89 616
elmot 1:d0dfbce63a89 617
elmot 1:d0dfbce63a89 618
elmot 1:d0dfbce63a89 619 /**
elmot 1:d0dfbce63a89 620 * @brief Enable CORTEX M4 SEVONPEND bit.
elmot 1:d0dfbce63a89 621 * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
elmot 1:d0dfbce63a89 622 * WFE to wake up when an interrupt moves from inactive to pended.
elmot 1:d0dfbce63a89 623 * @retval None
elmot 1:d0dfbce63a89 624 */
elmot 1:d0dfbce63a89 625 void HAL_PWR_EnableSEVOnPend(void)
elmot 1:d0dfbce63a89 626 {
elmot 1:d0dfbce63a89 627 /* Set SEVONPEND bit of Cortex System Control Register */
elmot 1:d0dfbce63a89 628 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
elmot 1:d0dfbce63a89 629 }
elmot 1:d0dfbce63a89 630
elmot 1:d0dfbce63a89 631
elmot 1:d0dfbce63a89 632 /**
elmot 1:d0dfbce63a89 633 * @brief Disable CORTEX M4 SEVONPEND bit.
elmot 1:d0dfbce63a89 634 * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
elmot 1:d0dfbce63a89 635 * WFE to wake up when an interrupt moves from inactive to pended.
elmot 1:d0dfbce63a89 636 * @retval None
elmot 1:d0dfbce63a89 637 */
elmot 1:d0dfbce63a89 638 void HAL_PWR_DisableSEVOnPend(void)
elmot 1:d0dfbce63a89 639 {
elmot 1:d0dfbce63a89 640 /* Clear SEVONPEND bit of Cortex System Control Register */
elmot 1:d0dfbce63a89 641 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
elmot 1:d0dfbce63a89 642 }
elmot 1:d0dfbce63a89 643
elmot 1:d0dfbce63a89 644
elmot 1:d0dfbce63a89 645
elmot 1:d0dfbce63a89 646
elmot 1:d0dfbce63a89 647
elmot 1:d0dfbce63a89 648 /**
elmot 1:d0dfbce63a89 649 * @brief PWR PVD interrupt callback
elmot 1:d0dfbce63a89 650 * @retval None
elmot 1:d0dfbce63a89 651 */
elmot 1:d0dfbce63a89 652 __weak void HAL_PWR_PVDCallback(void)
elmot 1:d0dfbce63a89 653 {
elmot 1:d0dfbce63a89 654 /* NOTE : This function should not be modified; when the callback is needed,
elmot 1:d0dfbce63a89 655 the HAL_PWR_PVDCallback can be implemented in the user file
elmot 1:d0dfbce63a89 656 */
elmot 1:d0dfbce63a89 657 }
elmot 1:d0dfbce63a89 658
elmot 1:d0dfbce63a89 659 /**
elmot 1:d0dfbce63a89 660 * @}
elmot 1:d0dfbce63a89 661 */
elmot 1:d0dfbce63a89 662
elmot 1:d0dfbce63a89 663 /**
elmot 1:d0dfbce63a89 664 * @}
elmot 1:d0dfbce63a89 665 */
elmot 1:d0dfbce63a89 666
elmot 1:d0dfbce63a89 667 #endif /* HAL_PWR_MODULE_ENABLED */
elmot 1:d0dfbce63a89 668 /**
elmot 1:d0dfbce63a89 669 * @}
elmot 1:d0dfbce63a89 670 */
elmot 1:d0dfbce63a89 671
elmot 1:d0dfbce63a89 672 /**
elmot 1:d0dfbce63a89 673 * @}
elmot 1:d0dfbce63a89 674 */
elmot 1:d0dfbce63a89 675
elmot 1:d0dfbce63a89 676 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/