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HAL_L476/stm32l4xx_hal_dma.h@1:d0dfbce63a89, 2017-02-24 (annotated)
- Committer:
- elmot
- Date:
- Fri Feb 24 21:13:56 2017 +0000
- Revision:
- 1:d0dfbce63a89
Ready-to-copy
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| elmot | 1:d0dfbce63a89 | 1 | /** |
| elmot | 1:d0dfbce63a89 | 2 | ****************************************************************************** |
| elmot | 1:d0dfbce63a89 | 3 | * @file stm32l4xx_hal_dma.h |
| elmot | 1:d0dfbce63a89 | 4 | * @author MCD Application Team |
| elmot | 1:d0dfbce63a89 | 5 | * @version V1.5.1 |
| elmot | 1:d0dfbce63a89 | 6 | * @date 31-May-2016 |
| elmot | 1:d0dfbce63a89 | 7 | * @brief Header file of DMA HAL module. |
| elmot | 1:d0dfbce63a89 | 8 | ****************************************************************************** |
| elmot | 1:d0dfbce63a89 | 9 | * @attention |
| elmot | 1:d0dfbce63a89 | 10 | * |
| elmot | 1:d0dfbce63a89 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| elmot | 1:d0dfbce63a89 | 12 | * |
| elmot | 1:d0dfbce63a89 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| elmot | 1:d0dfbce63a89 | 14 | * are permitted provided that the following conditions are met: |
| elmot | 1:d0dfbce63a89 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| elmot | 1:d0dfbce63a89 | 16 | * this list of conditions and the following disclaimer. |
| elmot | 1:d0dfbce63a89 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| elmot | 1:d0dfbce63a89 | 18 | * this list of conditions and the following disclaimer in the documentation |
| elmot | 1:d0dfbce63a89 | 19 | * and/or other materials provided with the distribution. |
| elmot | 1:d0dfbce63a89 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| elmot | 1:d0dfbce63a89 | 21 | * may be used to endorse or promote products derived from this software |
| elmot | 1:d0dfbce63a89 | 22 | * without specific prior written permission. |
| elmot | 1:d0dfbce63a89 | 23 | * |
| elmot | 1:d0dfbce63a89 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| elmot | 1:d0dfbce63a89 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| elmot | 1:d0dfbce63a89 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| elmot | 1:d0dfbce63a89 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| elmot | 1:d0dfbce63a89 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| elmot | 1:d0dfbce63a89 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| elmot | 1:d0dfbce63a89 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| elmot | 1:d0dfbce63a89 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| elmot | 1:d0dfbce63a89 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| elmot | 1:d0dfbce63a89 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| elmot | 1:d0dfbce63a89 | 34 | * |
| elmot | 1:d0dfbce63a89 | 35 | ****************************************************************************** |
| elmot | 1:d0dfbce63a89 | 36 | */ |
| elmot | 1:d0dfbce63a89 | 37 | |
| elmot | 1:d0dfbce63a89 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 39 | #ifndef __STM32L4xx_HAL_DMA_H |
| elmot | 1:d0dfbce63a89 | 40 | #define __STM32L4xx_HAL_DMA_H |
| elmot | 1:d0dfbce63a89 | 41 | |
| elmot | 1:d0dfbce63a89 | 42 | #ifdef __cplusplus |
| elmot | 1:d0dfbce63a89 | 43 | extern "C" { |
| elmot | 1:d0dfbce63a89 | 44 | #endif |
| elmot | 1:d0dfbce63a89 | 45 | |
| elmot | 1:d0dfbce63a89 | 46 | /* Includes ------------------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 47 | #include "stm32l4xx_hal_def.h" |
| elmot | 1:d0dfbce63a89 | 48 | |
| elmot | 1:d0dfbce63a89 | 49 | /** @addtogroup STM32L4xx_HAL_Driver |
| elmot | 1:d0dfbce63a89 | 50 | * @{ |
| elmot | 1:d0dfbce63a89 | 51 | */ |
| elmot | 1:d0dfbce63a89 | 52 | |
| elmot | 1:d0dfbce63a89 | 53 | /** @addtogroup DMA |
| elmot | 1:d0dfbce63a89 | 54 | * @{ |
| elmot | 1:d0dfbce63a89 | 55 | */ |
| elmot | 1:d0dfbce63a89 | 56 | |
| elmot | 1:d0dfbce63a89 | 57 | /* Exported types ------------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 58 | |
| elmot | 1:d0dfbce63a89 | 59 | /** @defgroup DMA_Exported_Types DMA Exported Types |
| elmot | 1:d0dfbce63a89 | 60 | * @{ |
| elmot | 1:d0dfbce63a89 | 61 | */ |
| elmot | 1:d0dfbce63a89 | 62 | |
| elmot | 1:d0dfbce63a89 | 63 | /** |
| elmot | 1:d0dfbce63a89 | 64 | * @brief DMA Configuration Structure definition |
| elmot | 1:d0dfbce63a89 | 65 | */ |
| elmot | 1:d0dfbce63a89 | 66 | typedef struct |
| elmot | 1:d0dfbce63a89 | 67 | { |
| elmot | 1:d0dfbce63a89 | 68 | uint32_t Request; /*!< Specifies the request selected for the specified channel. |
| elmot | 1:d0dfbce63a89 | 69 | This parameter can be a value of @ref DMA_request */ |
| elmot | 1:d0dfbce63a89 | 70 | |
| elmot | 1:d0dfbce63a89 | 71 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
| elmot | 1:d0dfbce63a89 | 72 | from memory to memory or from peripheral to memory. |
| elmot | 1:d0dfbce63a89 | 73 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
| elmot | 1:d0dfbce63a89 | 74 | |
| elmot | 1:d0dfbce63a89 | 75 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
| elmot | 1:d0dfbce63a89 | 76 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
| elmot | 1:d0dfbce63a89 | 77 | |
| elmot | 1:d0dfbce63a89 | 78 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
| elmot | 1:d0dfbce63a89 | 79 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
| elmot | 1:d0dfbce63a89 | 80 | |
| elmot | 1:d0dfbce63a89 | 81 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
| elmot | 1:d0dfbce63a89 | 82 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
| elmot | 1:d0dfbce63a89 | 83 | |
| elmot | 1:d0dfbce63a89 | 84 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
| elmot | 1:d0dfbce63a89 | 85 | This parameter can be a value of @ref DMA_Memory_data_size */ |
| elmot | 1:d0dfbce63a89 | 86 | |
| elmot | 1:d0dfbce63a89 | 87 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. |
| elmot | 1:d0dfbce63a89 | 88 | This parameter can be a value of @ref DMA_mode |
| elmot | 1:d0dfbce63a89 | 89 | @note The circular buffer mode cannot be used if the memory-to-memory |
| elmot | 1:d0dfbce63a89 | 90 | data transfer is configured on the selected Channel */ |
| elmot | 1:d0dfbce63a89 | 91 | |
| elmot | 1:d0dfbce63a89 | 92 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. |
| elmot | 1:d0dfbce63a89 | 93 | This parameter can be a value of @ref DMA_Priority_level */ |
| elmot | 1:d0dfbce63a89 | 94 | } DMA_InitTypeDef; |
| elmot | 1:d0dfbce63a89 | 95 | |
| elmot | 1:d0dfbce63a89 | 96 | /** |
| elmot | 1:d0dfbce63a89 | 97 | * @brief HAL DMA State structures definition |
| elmot | 1:d0dfbce63a89 | 98 | */ |
| elmot | 1:d0dfbce63a89 | 99 | typedef enum |
| elmot | 1:d0dfbce63a89 | 100 | { |
| elmot | 1:d0dfbce63a89 | 101 | HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ |
| elmot | 1:d0dfbce63a89 | 102 | HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ |
| elmot | 1:d0dfbce63a89 | 103 | HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ |
| elmot | 1:d0dfbce63a89 | 104 | HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ |
| elmot | 1:d0dfbce63a89 | 105 | }HAL_DMA_StateTypeDef; |
| elmot | 1:d0dfbce63a89 | 106 | |
| elmot | 1:d0dfbce63a89 | 107 | /** |
| elmot | 1:d0dfbce63a89 | 108 | * @brief HAL DMA Error Code structure definition |
| elmot | 1:d0dfbce63a89 | 109 | */ |
| elmot | 1:d0dfbce63a89 | 110 | typedef enum |
| elmot | 1:d0dfbce63a89 | 111 | { |
| elmot | 1:d0dfbce63a89 | 112 | HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ |
| elmot | 1:d0dfbce63a89 | 113 | HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */ |
| elmot | 1:d0dfbce63a89 | 114 | }HAL_DMA_LevelCompleteTypeDef; |
| elmot | 1:d0dfbce63a89 | 115 | |
| elmot | 1:d0dfbce63a89 | 116 | |
| elmot | 1:d0dfbce63a89 | 117 | /** |
| elmot | 1:d0dfbce63a89 | 118 | * @brief HAL DMA Callback ID structure definition |
| elmot | 1:d0dfbce63a89 | 119 | */ |
| elmot | 1:d0dfbce63a89 | 120 | typedef enum |
| elmot | 1:d0dfbce63a89 | 121 | { |
| elmot | 1:d0dfbce63a89 | 122 | HAL_DMA_XFER_CPLT_CB_ID = 0x00, /*!< Full transfer */ |
| elmot | 1:d0dfbce63a89 | 123 | HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /*!< Half transfer */ |
| elmot | 1:d0dfbce63a89 | 124 | HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */ |
| elmot | 1:d0dfbce63a89 | 125 | HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */ |
| elmot | 1:d0dfbce63a89 | 126 | HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */ |
| elmot | 1:d0dfbce63a89 | 127 | |
| elmot | 1:d0dfbce63a89 | 128 | }HAL_DMA_CallbackIDTypeDef; |
| elmot | 1:d0dfbce63a89 | 129 | |
| elmot | 1:d0dfbce63a89 | 130 | /** |
| elmot | 1:d0dfbce63a89 | 131 | * @brief DMA handle Structure definition |
| elmot | 1:d0dfbce63a89 | 132 | */ |
| elmot | 1:d0dfbce63a89 | 133 | typedef struct __DMA_HandleTypeDef |
| elmot | 1:d0dfbce63a89 | 134 | { |
| elmot | 1:d0dfbce63a89 | 135 | DMA_Channel_TypeDef *Instance; /*!< Register base address */ |
| elmot | 1:d0dfbce63a89 | 136 | |
| elmot | 1:d0dfbce63a89 | 137 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
| elmot | 1:d0dfbce63a89 | 138 | |
| elmot | 1:d0dfbce63a89 | 139 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
| elmot | 1:d0dfbce63a89 | 140 | |
| elmot | 1:d0dfbce63a89 | 141 | __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
| elmot | 1:d0dfbce63a89 | 142 | |
| elmot | 1:d0dfbce63a89 | 143 | void *Parent; /*!< Parent object state */ |
| elmot | 1:d0dfbce63a89 | 144 | |
| elmot | 1:d0dfbce63a89 | 145 | void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
| elmot | 1:d0dfbce63a89 | 146 | |
| elmot | 1:d0dfbce63a89 | 147 | void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
| elmot | 1:d0dfbce63a89 | 148 | |
| elmot | 1:d0dfbce63a89 | 149 | void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
| elmot | 1:d0dfbce63a89 | 150 | |
| elmot | 1:d0dfbce63a89 | 151 | void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ |
| elmot | 1:d0dfbce63a89 | 152 | |
| elmot | 1:d0dfbce63a89 | 153 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
| elmot | 1:d0dfbce63a89 | 154 | |
| elmot | 1:d0dfbce63a89 | 155 | DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ |
| elmot | 1:d0dfbce63a89 | 156 | |
| elmot | 1:d0dfbce63a89 | 157 | uint32_t ChannelIndex; /*!< DMA Channel Index */ |
| elmot | 1:d0dfbce63a89 | 158 | }DMA_HandleTypeDef; |
| elmot | 1:d0dfbce63a89 | 159 | /** |
| elmot | 1:d0dfbce63a89 | 160 | * @} |
| elmot | 1:d0dfbce63a89 | 161 | */ |
| elmot | 1:d0dfbce63a89 | 162 | |
| elmot | 1:d0dfbce63a89 | 163 | /* Exported constants --------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 164 | |
| elmot | 1:d0dfbce63a89 | 165 | /** @defgroup DMA_Exported_Constants DMA Exported Constants |
| elmot | 1:d0dfbce63a89 | 166 | * @{ |
| elmot | 1:d0dfbce63a89 | 167 | */ |
| elmot | 1:d0dfbce63a89 | 168 | |
| elmot | 1:d0dfbce63a89 | 169 | /** @defgroup DMA_Error_Code DMA Error Code |
| elmot | 1:d0dfbce63a89 | 170 | * @{ |
| elmot | 1:d0dfbce63a89 | 171 | */ |
| elmot | 1:d0dfbce63a89 | 172 | #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ |
| elmot | 1:d0dfbce63a89 | 173 | #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ |
| elmot | 1:d0dfbce63a89 | 174 | #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoing transfer */ |
| elmot | 1:d0dfbce63a89 | 175 | #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ |
| elmot | 1:d0dfbce63a89 | 176 | #define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100) /*!< Not supported mode */ |
| elmot | 1:d0dfbce63a89 | 177 | /** |
| elmot | 1:d0dfbce63a89 | 178 | * @} |
| elmot | 1:d0dfbce63a89 | 179 | */ |
| elmot | 1:d0dfbce63a89 | 180 | |
| elmot | 1:d0dfbce63a89 | 181 | /** @defgroup DMA_request DMA request |
| elmot | 1:d0dfbce63a89 | 182 | * @{ |
| elmot | 1:d0dfbce63a89 | 183 | */ |
| elmot | 1:d0dfbce63a89 | 184 | #define DMA_REQUEST_0 ((uint32_t)0x00000000) |
| elmot | 1:d0dfbce63a89 | 185 | #define DMA_REQUEST_1 ((uint32_t)0x00000001) |
| elmot | 1:d0dfbce63a89 | 186 | #define DMA_REQUEST_2 ((uint32_t)0x00000002) |
| elmot | 1:d0dfbce63a89 | 187 | #define DMA_REQUEST_3 ((uint32_t)0x00000003) |
| elmot | 1:d0dfbce63a89 | 188 | #define DMA_REQUEST_4 ((uint32_t)0x00000004) |
| elmot | 1:d0dfbce63a89 | 189 | #define DMA_REQUEST_5 ((uint32_t)0x00000005) |
| elmot | 1:d0dfbce63a89 | 190 | #define DMA_REQUEST_6 ((uint32_t)0x00000006) |
| elmot | 1:d0dfbce63a89 | 191 | #define DMA_REQUEST_7 ((uint32_t)0x00000007) |
| elmot | 1:d0dfbce63a89 | 192 | |
| elmot | 1:d0dfbce63a89 | 193 | /** |
| elmot | 1:d0dfbce63a89 | 194 | * @} |
| elmot | 1:d0dfbce63a89 | 195 | */ |
| elmot | 1:d0dfbce63a89 | 196 | |
| elmot | 1:d0dfbce63a89 | 197 | /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction |
| elmot | 1:d0dfbce63a89 | 198 | * @{ |
| elmot | 1:d0dfbce63a89 | 199 | */ |
| elmot | 1:d0dfbce63a89 | 200 | #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ |
| elmot | 1:d0dfbce63a89 | 201 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ |
| elmot | 1:d0dfbce63a89 | 202 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ |
| elmot | 1:d0dfbce63a89 | 203 | |
| elmot | 1:d0dfbce63a89 | 204 | /** |
| elmot | 1:d0dfbce63a89 | 205 | * @} |
| elmot | 1:d0dfbce63a89 | 206 | */ |
| elmot | 1:d0dfbce63a89 | 207 | |
| elmot | 1:d0dfbce63a89 | 208 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode |
| elmot | 1:d0dfbce63a89 | 209 | * @{ |
| elmot | 1:d0dfbce63a89 | 210 | */ |
| elmot | 1:d0dfbce63a89 | 211 | #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ |
| elmot | 1:d0dfbce63a89 | 212 | #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ |
| elmot | 1:d0dfbce63a89 | 213 | /** |
| elmot | 1:d0dfbce63a89 | 214 | * @} |
| elmot | 1:d0dfbce63a89 | 215 | */ |
| elmot | 1:d0dfbce63a89 | 216 | |
| elmot | 1:d0dfbce63a89 | 217 | /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode |
| elmot | 1:d0dfbce63a89 | 218 | * @{ |
| elmot | 1:d0dfbce63a89 | 219 | */ |
| elmot | 1:d0dfbce63a89 | 220 | #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ |
| elmot | 1:d0dfbce63a89 | 221 | #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ |
| elmot | 1:d0dfbce63a89 | 222 | /** |
| elmot | 1:d0dfbce63a89 | 223 | * @} |
| elmot | 1:d0dfbce63a89 | 224 | */ |
| elmot | 1:d0dfbce63a89 | 225 | |
| elmot | 1:d0dfbce63a89 | 226 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size |
| elmot | 1:d0dfbce63a89 | 227 | * @{ |
| elmot | 1:d0dfbce63a89 | 228 | */ |
| elmot | 1:d0dfbce63a89 | 229 | #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ |
| elmot | 1:d0dfbce63a89 | 230 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ |
| elmot | 1:d0dfbce63a89 | 231 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ |
| elmot | 1:d0dfbce63a89 | 232 | /** |
| elmot | 1:d0dfbce63a89 | 233 | * @} |
| elmot | 1:d0dfbce63a89 | 234 | */ |
| elmot | 1:d0dfbce63a89 | 235 | |
| elmot | 1:d0dfbce63a89 | 236 | /** @defgroup DMA_Memory_data_size DMA Memory data size |
| elmot | 1:d0dfbce63a89 | 237 | * @{ |
| elmot | 1:d0dfbce63a89 | 238 | */ |
| elmot | 1:d0dfbce63a89 | 239 | #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ |
| elmot | 1:d0dfbce63a89 | 240 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ |
| elmot | 1:d0dfbce63a89 | 241 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ |
| elmot | 1:d0dfbce63a89 | 242 | /** |
| elmot | 1:d0dfbce63a89 | 243 | * @} |
| elmot | 1:d0dfbce63a89 | 244 | */ |
| elmot | 1:d0dfbce63a89 | 245 | |
| elmot | 1:d0dfbce63a89 | 246 | /** @defgroup DMA_mode DMA mode |
| elmot | 1:d0dfbce63a89 | 247 | * @{ |
| elmot | 1:d0dfbce63a89 | 248 | */ |
| elmot | 1:d0dfbce63a89 | 249 | #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ |
| elmot | 1:d0dfbce63a89 | 250 | #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ |
| elmot | 1:d0dfbce63a89 | 251 | /** |
| elmot | 1:d0dfbce63a89 | 252 | * @} |
| elmot | 1:d0dfbce63a89 | 253 | */ |
| elmot | 1:d0dfbce63a89 | 254 | |
| elmot | 1:d0dfbce63a89 | 255 | /** @defgroup DMA_Priority_level DMA Priority level |
| elmot | 1:d0dfbce63a89 | 256 | * @{ |
| elmot | 1:d0dfbce63a89 | 257 | */ |
| elmot | 1:d0dfbce63a89 | 258 | #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ |
| elmot | 1:d0dfbce63a89 | 259 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ |
| elmot | 1:d0dfbce63a89 | 260 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ |
| elmot | 1:d0dfbce63a89 | 261 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ |
| elmot | 1:d0dfbce63a89 | 262 | /** |
| elmot | 1:d0dfbce63a89 | 263 | * @} |
| elmot | 1:d0dfbce63a89 | 264 | */ |
| elmot | 1:d0dfbce63a89 | 265 | |
| elmot | 1:d0dfbce63a89 | 266 | |
| elmot | 1:d0dfbce63a89 | 267 | /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions |
| elmot | 1:d0dfbce63a89 | 268 | * @{ |
| elmot | 1:d0dfbce63a89 | 269 | */ |
| elmot | 1:d0dfbce63a89 | 270 | #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) |
| elmot | 1:d0dfbce63a89 | 271 | #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) |
| elmot | 1:d0dfbce63a89 | 272 | #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) |
| elmot | 1:d0dfbce63a89 | 273 | /** |
| elmot | 1:d0dfbce63a89 | 274 | * @} |
| elmot | 1:d0dfbce63a89 | 275 | */ |
| elmot | 1:d0dfbce63a89 | 276 | |
| elmot | 1:d0dfbce63a89 | 277 | /** @defgroup DMA_flag_definitions DMA flag definitions |
| elmot | 1:d0dfbce63a89 | 278 | * @{ |
| elmot | 1:d0dfbce63a89 | 279 | */ |
| elmot | 1:d0dfbce63a89 | 280 | #define DMA_FLAG_GL1 ((uint32_t)0x00000001) |
| elmot | 1:d0dfbce63a89 | 281 | #define DMA_FLAG_TC1 ((uint32_t)0x00000002) |
| elmot | 1:d0dfbce63a89 | 282 | #define DMA_FLAG_HT1 ((uint32_t)0x00000004) |
| elmot | 1:d0dfbce63a89 | 283 | #define DMA_FLAG_TE1 ((uint32_t)0x00000008) |
| elmot | 1:d0dfbce63a89 | 284 | #define DMA_FLAG_GL2 ((uint32_t)0x00000010) |
| elmot | 1:d0dfbce63a89 | 285 | #define DMA_FLAG_TC2 ((uint32_t)0x00000020) |
| elmot | 1:d0dfbce63a89 | 286 | #define DMA_FLAG_HT2 ((uint32_t)0x00000040) |
| elmot | 1:d0dfbce63a89 | 287 | #define DMA_FLAG_TE2 ((uint32_t)0x00000080) |
| elmot | 1:d0dfbce63a89 | 288 | #define DMA_FLAG_GL3 ((uint32_t)0x00000100) |
| elmot | 1:d0dfbce63a89 | 289 | #define DMA_FLAG_TC3 ((uint32_t)0x00000200) |
| elmot | 1:d0dfbce63a89 | 290 | #define DMA_FLAG_HT3 ((uint32_t)0x00000400) |
| elmot | 1:d0dfbce63a89 | 291 | #define DMA_FLAG_TE3 ((uint32_t)0x00000800) |
| elmot | 1:d0dfbce63a89 | 292 | #define DMA_FLAG_GL4 ((uint32_t)0x00001000) |
| elmot | 1:d0dfbce63a89 | 293 | #define DMA_FLAG_TC4 ((uint32_t)0x00002000) |
| elmot | 1:d0dfbce63a89 | 294 | #define DMA_FLAG_HT4 ((uint32_t)0x00004000) |
| elmot | 1:d0dfbce63a89 | 295 | #define DMA_FLAG_TE4 ((uint32_t)0x00008000) |
| elmot | 1:d0dfbce63a89 | 296 | #define DMA_FLAG_GL5 ((uint32_t)0x00010000) |
| elmot | 1:d0dfbce63a89 | 297 | #define DMA_FLAG_TC5 ((uint32_t)0x00020000) |
| elmot | 1:d0dfbce63a89 | 298 | #define DMA_FLAG_HT5 ((uint32_t)0x00040000) |
| elmot | 1:d0dfbce63a89 | 299 | #define DMA_FLAG_TE5 ((uint32_t)0x00080000) |
| elmot | 1:d0dfbce63a89 | 300 | #define DMA_FLAG_GL6 ((uint32_t)0x00100000) |
| elmot | 1:d0dfbce63a89 | 301 | #define DMA_FLAG_TC6 ((uint32_t)0x00200000) |
| elmot | 1:d0dfbce63a89 | 302 | #define DMA_FLAG_HT6 ((uint32_t)0x00400000) |
| elmot | 1:d0dfbce63a89 | 303 | #define DMA_FLAG_TE6 ((uint32_t)0x00800000) |
| elmot | 1:d0dfbce63a89 | 304 | #define DMA_FLAG_GL7 ((uint32_t)0x01000000) |
| elmot | 1:d0dfbce63a89 | 305 | #define DMA_FLAG_TC7 ((uint32_t)0x02000000) |
| elmot | 1:d0dfbce63a89 | 306 | #define DMA_FLAG_HT7 ((uint32_t)0x04000000) |
| elmot | 1:d0dfbce63a89 | 307 | #define DMA_FLAG_TE7 ((uint32_t)0x08000000) |
| elmot | 1:d0dfbce63a89 | 308 | /** |
| elmot | 1:d0dfbce63a89 | 309 | * @} |
| elmot | 1:d0dfbce63a89 | 310 | */ |
| elmot | 1:d0dfbce63a89 | 311 | |
| elmot | 1:d0dfbce63a89 | 312 | /** |
| elmot | 1:d0dfbce63a89 | 313 | * @} |
| elmot | 1:d0dfbce63a89 | 314 | */ |
| elmot | 1:d0dfbce63a89 | 315 | |
| elmot | 1:d0dfbce63a89 | 316 | /* Exported macros -----------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 317 | /** @defgroup DMA_Exported_Macros DMA Exported Macros |
| elmot | 1:d0dfbce63a89 | 318 | * @{ |
| elmot | 1:d0dfbce63a89 | 319 | */ |
| elmot | 1:d0dfbce63a89 | 320 | |
| elmot | 1:d0dfbce63a89 | 321 | /** @brief Reset DMA handle state. |
| elmot | 1:d0dfbce63a89 | 322 | * @param __HANDLE__: DMA handle |
| elmot | 1:d0dfbce63a89 | 323 | * @retval None |
| elmot | 1:d0dfbce63a89 | 324 | */ |
| elmot | 1:d0dfbce63a89 | 325 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
| elmot | 1:d0dfbce63a89 | 326 | |
| elmot | 1:d0dfbce63a89 | 327 | /** |
| elmot | 1:d0dfbce63a89 | 328 | * @brief Enable the specified DMA Channel. |
| elmot | 1:d0dfbce63a89 | 329 | * @param __HANDLE__: DMA handle |
| elmot | 1:d0dfbce63a89 | 330 | * @retval None |
| elmot | 1:d0dfbce63a89 | 331 | */ |
| elmot | 1:d0dfbce63a89 | 332 | #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) |
| elmot | 1:d0dfbce63a89 | 333 | |
| elmot | 1:d0dfbce63a89 | 334 | /** |
| elmot | 1:d0dfbce63a89 | 335 | * @brief Disable the specified DMA Channel. |
| elmot | 1:d0dfbce63a89 | 336 | * @param __HANDLE__: DMA handle |
| elmot | 1:d0dfbce63a89 | 337 | * @retval None |
| elmot | 1:d0dfbce63a89 | 338 | */ |
| elmot | 1:d0dfbce63a89 | 339 | #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) |
| elmot | 1:d0dfbce63a89 | 340 | |
| elmot | 1:d0dfbce63a89 | 341 | |
| elmot | 1:d0dfbce63a89 | 342 | /* Interrupt & Flag management */ |
| elmot | 1:d0dfbce63a89 | 343 | |
| elmot | 1:d0dfbce63a89 | 344 | /** |
| elmot | 1:d0dfbce63a89 | 345 | * @brief Return the current DMA Channel transfer complete flag. |
| elmot | 1:d0dfbce63a89 | 346 | * @param __HANDLE__: DMA handle |
| elmot | 1:d0dfbce63a89 | 347 | * @retval The specified transfer complete flag index. |
| elmot | 1:d0dfbce63a89 | 348 | */ |
| elmot | 1:d0dfbce63a89 | 349 | |
| elmot | 1:d0dfbce63a89 | 350 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| elmot | 1:d0dfbce63a89 | 351 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
| elmot | 1:d0dfbce63a89 | 352 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ |
| elmot | 1:d0dfbce63a89 | 353 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
| elmot | 1:d0dfbce63a89 | 354 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ |
| elmot | 1:d0dfbce63a89 | 355 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
| elmot | 1:d0dfbce63a89 | 356 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ |
| elmot | 1:d0dfbce63a89 | 357 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
| elmot | 1:d0dfbce63a89 | 358 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ |
| elmot | 1:d0dfbce63a89 | 359 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ |
| elmot | 1:d0dfbce63a89 | 360 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ |
| elmot | 1:d0dfbce63a89 | 361 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ |
| elmot | 1:d0dfbce63a89 | 362 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ |
| elmot | 1:d0dfbce63a89 | 363 | DMA_FLAG_TC7) |
| elmot | 1:d0dfbce63a89 | 364 | |
| elmot | 1:d0dfbce63a89 | 365 | /** |
| elmot | 1:d0dfbce63a89 | 366 | * @brief Return the current DMA Channel half transfer complete flag. |
| elmot | 1:d0dfbce63a89 | 367 | * @param __HANDLE__: DMA handle |
| elmot | 1:d0dfbce63a89 | 368 | * @retval The specified half transfer complete flag index. |
| elmot | 1:d0dfbce63a89 | 369 | */ |
| elmot | 1:d0dfbce63a89 | 370 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| elmot | 1:d0dfbce63a89 | 371 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
| elmot | 1:d0dfbce63a89 | 372 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ |
| elmot | 1:d0dfbce63a89 | 373 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
| elmot | 1:d0dfbce63a89 | 374 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ |
| elmot | 1:d0dfbce63a89 | 375 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
| elmot | 1:d0dfbce63a89 | 376 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ |
| elmot | 1:d0dfbce63a89 | 377 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
| elmot | 1:d0dfbce63a89 | 378 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ |
| elmot | 1:d0dfbce63a89 | 379 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ |
| elmot | 1:d0dfbce63a89 | 380 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ |
| elmot | 1:d0dfbce63a89 | 381 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ |
| elmot | 1:d0dfbce63a89 | 382 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ |
| elmot | 1:d0dfbce63a89 | 383 | DMA_FLAG_HT7) |
| elmot | 1:d0dfbce63a89 | 384 | |
| elmot | 1:d0dfbce63a89 | 385 | /** |
| elmot | 1:d0dfbce63a89 | 386 | * @brief Return the current DMA Channel transfer error flag. |
| elmot | 1:d0dfbce63a89 | 387 | * @param __HANDLE__: DMA handle |
| elmot | 1:d0dfbce63a89 | 388 | * @retval The specified transfer error flag index. |
| elmot | 1:d0dfbce63a89 | 389 | */ |
| elmot | 1:d0dfbce63a89 | 390 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| elmot | 1:d0dfbce63a89 | 391 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
| elmot | 1:d0dfbce63a89 | 392 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ |
| elmot | 1:d0dfbce63a89 | 393 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
| elmot | 1:d0dfbce63a89 | 394 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ |
| elmot | 1:d0dfbce63a89 | 395 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
| elmot | 1:d0dfbce63a89 | 396 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ |
| elmot | 1:d0dfbce63a89 | 397 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
| elmot | 1:d0dfbce63a89 | 398 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ |
| elmot | 1:d0dfbce63a89 | 399 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ |
| elmot | 1:d0dfbce63a89 | 400 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ |
| elmot | 1:d0dfbce63a89 | 401 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ |
| elmot | 1:d0dfbce63a89 | 402 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ |
| elmot | 1:d0dfbce63a89 | 403 | DMA_FLAG_TE7) |
| elmot | 1:d0dfbce63a89 | 404 | |
| elmot | 1:d0dfbce63a89 | 405 | /** |
| elmot | 1:d0dfbce63a89 | 406 | * @brief Return the current DMA Channel Global interrupt flag. |
| elmot | 1:d0dfbce63a89 | 407 | * @param __HANDLE__: DMA handle |
| elmot | 1:d0dfbce63a89 | 408 | * @retval The specified transfer error flag index. |
| elmot | 1:d0dfbce63a89 | 409 | */ |
| elmot | 1:d0dfbce63a89 | 410 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
| elmot | 1:d0dfbce63a89 | 411 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ |
| elmot | 1:d0dfbce63a89 | 412 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ |
| elmot | 1:d0dfbce63a89 | 413 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ |
| elmot | 1:d0dfbce63a89 | 414 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ |
| elmot | 1:d0dfbce63a89 | 415 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ |
| elmot | 1:d0dfbce63a89 | 416 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ |
| elmot | 1:d0dfbce63a89 | 417 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ |
| elmot | 1:d0dfbce63a89 | 418 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ |
| elmot | 1:d0dfbce63a89 | 419 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ |
| elmot | 1:d0dfbce63a89 | 420 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ |
| elmot | 1:d0dfbce63a89 | 421 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ |
| elmot | 1:d0dfbce63a89 | 422 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ |
| elmot | 1:d0dfbce63a89 | 423 | DMA_ISR_GIF7) |
| elmot | 1:d0dfbce63a89 | 424 | |
| elmot | 1:d0dfbce63a89 | 425 | /** |
| elmot | 1:d0dfbce63a89 | 426 | * @brief Get the DMA Channel pending flags. |
| elmot | 1:d0dfbce63a89 | 427 | * @param __HANDLE__: DMA handle |
| elmot | 1:d0dfbce63a89 | 428 | * @param __FLAG__: Get the specified flag. |
| elmot | 1:d0dfbce63a89 | 429 | * This parameter can be any combination of the following values: |
| elmot | 1:d0dfbce63a89 | 430 | * @arg DMA_FLAG_TCx: Transfer complete flag |
| elmot | 1:d0dfbce63a89 | 431 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
| elmot | 1:d0dfbce63a89 | 432 | * @arg DMA_FLAG_TEx: Transfer error flag |
| elmot | 1:d0dfbce63a89 | 433 | * @arg DMA_FLAG_GLx: Global interrupt flag |
| elmot | 1:d0dfbce63a89 | 434 | * Where x can be from 1 to 7 to select the DMA Channel x flag. |
| elmot | 1:d0dfbce63a89 | 435 | * @retval The state of FLAG (SET or RESET). |
| elmot | 1:d0dfbce63a89 | 436 | */ |
| elmot | 1:d0dfbce63a89 | 437 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ |
| elmot | 1:d0dfbce63a89 | 438 | (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) |
| elmot | 1:d0dfbce63a89 | 439 | |
| elmot | 1:d0dfbce63a89 | 440 | /** |
| elmot | 1:d0dfbce63a89 | 441 | * @brief Clear the DMA Channel pending flags. |
| elmot | 1:d0dfbce63a89 | 442 | * @param __HANDLE__: DMA handle |
| elmot | 1:d0dfbce63a89 | 443 | * @param __FLAG__: specifies the flag to clear. |
| elmot | 1:d0dfbce63a89 | 444 | * This parameter can be any combination of the following values: |
| elmot | 1:d0dfbce63a89 | 445 | * @arg DMA_FLAG_TCx: Transfer complete flag |
| elmot | 1:d0dfbce63a89 | 446 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
| elmot | 1:d0dfbce63a89 | 447 | * @arg DMA_FLAG_TEx: Transfer error flag |
| elmot | 1:d0dfbce63a89 | 448 | * @arg DMA_FLAG_GLx: Global interrupt flag |
| elmot | 1:d0dfbce63a89 | 449 | * Where x can be from 1 to 7 to select the DMA Channel x flag. |
| elmot | 1:d0dfbce63a89 | 450 | * @retval None |
| elmot | 1:d0dfbce63a89 | 451 | */ |
| elmot | 1:d0dfbce63a89 | 452 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ |
| elmot | 1:d0dfbce63a89 | 453 | (DMA2->IFCR |= (__FLAG__)) : (DMA1->IFCR |= (__FLAG__))) |
| elmot | 1:d0dfbce63a89 | 454 | |
| elmot | 1:d0dfbce63a89 | 455 | /** |
| elmot | 1:d0dfbce63a89 | 456 | * @brief Enable the specified DMA Channel interrupts. |
| elmot | 1:d0dfbce63a89 | 457 | * @param __HANDLE__: DMA handle |
| elmot | 1:d0dfbce63a89 | 458 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| elmot | 1:d0dfbce63a89 | 459 | * This parameter can be any combination of the following values: |
| elmot | 1:d0dfbce63a89 | 460 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| elmot | 1:d0dfbce63a89 | 461 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| elmot | 1:d0dfbce63a89 | 462 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| elmot | 1:d0dfbce63a89 | 463 | * @retval None |
| elmot | 1:d0dfbce63a89 | 464 | */ |
| elmot | 1:d0dfbce63a89 | 465 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) |
| elmot | 1:d0dfbce63a89 | 466 | |
| elmot | 1:d0dfbce63a89 | 467 | /** |
| elmot | 1:d0dfbce63a89 | 468 | * @brief Disable the specified DMA Channel interrupts. |
| elmot | 1:d0dfbce63a89 | 469 | * @param __HANDLE__: DMA handle |
| elmot | 1:d0dfbce63a89 | 470 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| elmot | 1:d0dfbce63a89 | 471 | * This parameter can be any combination of the following values: |
| elmot | 1:d0dfbce63a89 | 472 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| elmot | 1:d0dfbce63a89 | 473 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| elmot | 1:d0dfbce63a89 | 474 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| elmot | 1:d0dfbce63a89 | 475 | * @retval None |
| elmot | 1:d0dfbce63a89 | 476 | */ |
| elmot | 1:d0dfbce63a89 | 477 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) |
| elmot | 1:d0dfbce63a89 | 478 | |
| elmot | 1:d0dfbce63a89 | 479 | /** |
| elmot | 1:d0dfbce63a89 | 480 | * @brief Check whether the specified DMA Channel interrupt is enabled or not. |
| elmot | 1:d0dfbce63a89 | 481 | * @param __HANDLE__: DMA handle |
| elmot | 1:d0dfbce63a89 | 482 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
| elmot | 1:d0dfbce63a89 | 483 | * This parameter can be one of the following values: |
| elmot | 1:d0dfbce63a89 | 484 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| elmot | 1:d0dfbce63a89 | 485 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| elmot | 1:d0dfbce63a89 | 486 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| elmot | 1:d0dfbce63a89 | 487 | * @retval The state of DMA_IT (SET or RESET). |
| elmot | 1:d0dfbce63a89 | 488 | */ |
| elmot | 1:d0dfbce63a89 | 489 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) |
| elmot | 1:d0dfbce63a89 | 490 | |
| elmot | 1:d0dfbce63a89 | 491 | /** |
| elmot | 1:d0dfbce63a89 | 492 | * @brief Return the number of remaining data units in the current DMA Channel transfer. |
| elmot | 1:d0dfbce63a89 | 493 | * @param __HANDLE__: DMA handle |
| elmot | 1:d0dfbce63a89 | 494 | * @retval The number of remaining data units in the current DMA Channel transfer. |
| elmot | 1:d0dfbce63a89 | 495 | */ |
| elmot | 1:d0dfbce63a89 | 496 | #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) |
| elmot | 1:d0dfbce63a89 | 497 | |
| elmot | 1:d0dfbce63a89 | 498 | /** |
| elmot | 1:d0dfbce63a89 | 499 | * @} |
| elmot | 1:d0dfbce63a89 | 500 | */ |
| elmot | 1:d0dfbce63a89 | 501 | |
| elmot | 1:d0dfbce63a89 | 502 | /* Exported functions --------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 503 | |
| elmot | 1:d0dfbce63a89 | 504 | /** @addtogroup DMA_Exported_Functions |
| elmot | 1:d0dfbce63a89 | 505 | * @{ |
| elmot | 1:d0dfbce63a89 | 506 | */ |
| elmot | 1:d0dfbce63a89 | 507 | |
| elmot | 1:d0dfbce63a89 | 508 | /** @addtogroup DMA_Exported_Functions_Group1 |
| elmot | 1:d0dfbce63a89 | 509 | * @{ |
| elmot | 1:d0dfbce63a89 | 510 | */ |
| elmot | 1:d0dfbce63a89 | 511 | /* Initialization and de-initialization functions *****************************/ |
| elmot | 1:d0dfbce63a89 | 512 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
| elmot | 1:d0dfbce63a89 | 513 | HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); |
| elmot | 1:d0dfbce63a89 | 514 | /** |
| elmot | 1:d0dfbce63a89 | 515 | * @} |
| elmot | 1:d0dfbce63a89 | 516 | */ |
| elmot | 1:d0dfbce63a89 | 517 | |
| elmot | 1:d0dfbce63a89 | 518 | /** @addtogroup DMA_Exported_Functions_Group2 |
| elmot | 1:d0dfbce63a89 | 519 | * @{ |
| elmot | 1:d0dfbce63a89 | 520 | */ |
| elmot | 1:d0dfbce63a89 | 521 | /* IO operation functions *****************************************************/ |
| elmot | 1:d0dfbce63a89 | 522 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| elmot | 1:d0dfbce63a89 | 523 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| elmot | 1:d0dfbce63a89 | 524 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
| elmot | 1:d0dfbce63a89 | 525 | HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); |
| elmot | 1:d0dfbce63a89 | 526 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
| elmot | 1:d0dfbce63a89 | 527 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
| elmot | 1:d0dfbce63a89 | 528 | HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); |
| elmot | 1:d0dfbce63a89 | 529 | HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); |
| elmot | 1:d0dfbce63a89 | 530 | |
| elmot | 1:d0dfbce63a89 | 531 | /** |
| elmot | 1:d0dfbce63a89 | 532 | * @} |
| elmot | 1:d0dfbce63a89 | 533 | */ |
| elmot | 1:d0dfbce63a89 | 534 | |
| elmot | 1:d0dfbce63a89 | 535 | /** @addtogroup DMA_Exported_Functions_Group3 |
| elmot | 1:d0dfbce63a89 | 536 | * @{ |
| elmot | 1:d0dfbce63a89 | 537 | */ |
| elmot | 1:d0dfbce63a89 | 538 | /* Peripheral State and Error functions ***************************************/ |
| elmot | 1:d0dfbce63a89 | 539 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
| elmot | 1:d0dfbce63a89 | 540 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
| elmot | 1:d0dfbce63a89 | 541 | /** |
| elmot | 1:d0dfbce63a89 | 542 | * @} |
| elmot | 1:d0dfbce63a89 | 543 | */ |
| elmot | 1:d0dfbce63a89 | 544 | |
| elmot | 1:d0dfbce63a89 | 545 | /** |
| elmot | 1:d0dfbce63a89 | 546 | * @} |
| elmot | 1:d0dfbce63a89 | 547 | */ |
| elmot | 1:d0dfbce63a89 | 548 | |
| elmot | 1:d0dfbce63a89 | 549 | /* Private macros ------------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 550 | /** @defgroup DMA_Private_Macros DMA Private Macros |
| elmot | 1:d0dfbce63a89 | 551 | * @{ |
| elmot | 1:d0dfbce63a89 | 552 | */ |
| elmot | 1:d0dfbce63a89 | 553 | |
| elmot | 1:d0dfbce63a89 | 554 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
| elmot | 1:d0dfbce63a89 | 555 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
| elmot | 1:d0dfbce63a89 | 556 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
| elmot | 1:d0dfbce63a89 | 557 | |
| elmot | 1:d0dfbce63a89 | 558 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
| elmot | 1:d0dfbce63a89 | 559 | |
| elmot | 1:d0dfbce63a89 | 560 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
| elmot | 1:d0dfbce63a89 | 561 | ((STATE) == DMA_PINC_DISABLE)) |
| elmot | 1:d0dfbce63a89 | 562 | |
| elmot | 1:d0dfbce63a89 | 563 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
| elmot | 1:d0dfbce63a89 | 564 | ((STATE) == DMA_MINC_DISABLE)) |
| elmot | 1:d0dfbce63a89 | 565 | |
| elmot | 1:d0dfbce63a89 | 566 | #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ |
| elmot | 1:d0dfbce63a89 | 567 | ((REQUEST) == DMA_REQUEST_1) || \ |
| elmot | 1:d0dfbce63a89 | 568 | ((REQUEST) == DMA_REQUEST_2) || \ |
| elmot | 1:d0dfbce63a89 | 569 | ((REQUEST) == DMA_REQUEST_3) || \ |
| elmot | 1:d0dfbce63a89 | 570 | ((REQUEST) == DMA_REQUEST_4) || \ |
| elmot | 1:d0dfbce63a89 | 571 | ((REQUEST) == DMA_REQUEST_5) || \ |
| elmot | 1:d0dfbce63a89 | 572 | ((REQUEST) == DMA_REQUEST_6) || \ |
| elmot | 1:d0dfbce63a89 | 573 | ((REQUEST) == DMA_REQUEST_7)) |
| elmot | 1:d0dfbce63a89 | 574 | |
| elmot | 1:d0dfbce63a89 | 575 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
| elmot | 1:d0dfbce63a89 | 576 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
| elmot | 1:d0dfbce63a89 | 577 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
| elmot | 1:d0dfbce63a89 | 578 | |
| elmot | 1:d0dfbce63a89 | 579 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
| elmot | 1:d0dfbce63a89 | 580 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
| elmot | 1:d0dfbce63a89 | 581 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
| elmot | 1:d0dfbce63a89 | 582 | |
| elmot | 1:d0dfbce63a89 | 583 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
| elmot | 1:d0dfbce63a89 | 584 | ((MODE) == DMA_CIRCULAR)) |
| elmot | 1:d0dfbce63a89 | 585 | |
| elmot | 1:d0dfbce63a89 | 586 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
| elmot | 1:d0dfbce63a89 | 587 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
| elmot | 1:d0dfbce63a89 | 588 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
| elmot | 1:d0dfbce63a89 | 589 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
| elmot | 1:d0dfbce63a89 | 590 | |
| elmot | 1:d0dfbce63a89 | 591 | /** |
| elmot | 1:d0dfbce63a89 | 592 | * @} |
| elmot | 1:d0dfbce63a89 | 593 | */ |
| elmot | 1:d0dfbce63a89 | 594 | |
| elmot | 1:d0dfbce63a89 | 595 | /* Private functions ---------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 596 | |
| elmot | 1:d0dfbce63a89 | 597 | /** |
| elmot | 1:d0dfbce63a89 | 598 | * @} |
| elmot | 1:d0dfbce63a89 | 599 | */ |
| elmot | 1:d0dfbce63a89 | 600 | |
| elmot | 1:d0dfbce63a89 | 601 | /** |
| elmot | 1:d0dfbce63a89 | 602 | * @} |
| elmot | 1:d0dfbce63a89 | 603 | */ |
| elmot | 1:d0dfbce63a89 | 604 | |
| elmot | 1:d0dfbce63a89 | 605 | #ifdef __cplusplus |
| elmot | 1:d0dfbce63a89 | 606 | } |
| elmot | 1:d0dfbce63a89 | 607 | #endif |
| elmot | 1:d0dfbce63a89 | 608 | |
| elmot | 1:d0dfbce63a89 | 609 | #endif /* __STM32L4xx_HAL_DMA_H */ |
| elmot | 1:d0dfbce63a89 | 610 | |
| elmot | 1:d0dfbce63a89 | 611 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |