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stm32l4xx_ll_tim.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_tim.h 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief Header file of TIM LL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_LL_TIM_H 00040 #define __STM32L4xx_LL_TIM_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx.h" 00048 00049 /** @addtogroup STM32L4xx_LL_Driver 00050 * @{ 00051 */ 00052 00053 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7) 00054 00055 /** @defgroup TIM_LL TIM 00056 * @{ 00057 */ 00058 00059 /* Private types -------------------------------------------------------------*/ 00060 /* Private variables ---------------------------------------------------------*/ 00061 /** @defgroup TIM_LL_Private_Variables TIM Private Variables 00062 * @{ 00063 */ 00064 static const uint8_t OFFSET_TAB_CCMRx[] = 00065 { 00066 0x00U, /* 0: TIMx_CH1 */ 00067 0x00U, /* 1: TIMx_CH1N */ 00068 0x00U, /* 2: TIMx_CH2 */ 00069 0x00U, /* 3: TIMx_CH2N */ 00070 0x04U, /* 4: TIMx_CH3 */ 00071 0x04U, /* 5: TIMx_CH3N */ 00072 0x04U, /* 6: TIMx_CH4 */ 00073 0x3CU, /* 7: TIMx_CH5 */ 00074 0x3CU /* 8: TIMx_CH6 */ 00075 }; 00076 00077 static const uint8_t SHIFT_TAB_OCxx[] = 00078 { 00079 0U, /* 0: OC1M, OC1FE, OC1PE */ 00080 0U, /* 1: - NA */ 00081 8U, /* 2: OC2M, OC2FE, OC2PE */ 00082 0U, /* 3: - NA */ 00083 0U, /* 4: OC3M, OC3FE, OC3PE */ 00084 0U, /* 5: - NA */ 00085 8U, /* 6: OC4M, OC4FE, OC4PE */ 00086 0U, /* 7: OC5M, OC5FE, OC5PE */ 00087 8U /* 8: OC6M, OC6FE, OC6PE */ 00088 }; 00089 00090 static const uint8_t SHIFT_TAB_ICxx[] = 00091 { 00092 0U, /* 0: CC1S, IC1PSC, IC1F */ 00093 0U, /* 1: - NA */ 00094 8U, /* 2: CC2S, IC2PSC, IC2F */ 00095 0U, /* 3: - NA */ 00096 0U, /* 4: CC3S, IC3PSC, IC3F */ 00097 0U, /* 5: - NA */ 00098 8U, /* 6: CC4S, IC4PSC, IC4F */ 00099 0U, /* 7: - NA */ 00100 0U /* 8: - NA */ 00101 }; 00102 00103 static const uint8_t SHIFT_TAB_CCxP[] = 00104 { 00105 0U, /* 0: CC1P */ 00106 2U, /* 1: CC1NP */ 00107 4U, /* 2: CC2P */ 00108 6U, /* 3: CC2NP */ 00109 8U, /* 4: CC3P */ 00110 10U, /* 5: CC3NP */ 00111 12U, /* 6: CC4P */ 00112 16U, /* 7: CC5P */ 00113 20U /* 8: CC6P */ 00114 }; 00115 00116 static const uint8_t SHIFT_TAB_OISx[] = 00117 { 00118 0U, /* 0: OIS1 */ 00119 1U, /* 1: OIS1N */ 00120 2U, /* 2: OIS2 */ 00121 3U, /* 3: OIS2N */ 00122 4U, /* 4: OIS3 */ 00123 5U, /* 5: OIS3N */ 00124 6U, /* 6: OIS4 */ 00125 8U, /* 7: OIS5 */ 00126 10U /* 8: OIS6 */ 00127 }; 00128 /** 00129 * @} 00130 */ 00131 00132 00133 /* Private constants ---------------------------------------------------------*/ 00134 /** @defgroup TIM_LL_Private_Constants TIM Private Constants 00135 * @{ 00136 */ 00137 /** @defgroup TIM_LL_POSITION_VAL Bit Position Value 00138 * @brief Position of the bit in the register. 00139 * @{ 00140 */ 00141 #define TIM_POSITION_ICPSC POSITION_VAL(TIM_CCMR1_IC1PSC) 00142 /** 00143 * @} 00144 */ 00145 00146 /* Generic bit definitions for TIMx_OR2 register */ 00147 #define TIMx_OR2_BKINE TIM1_OR2_BKINE /*!< BRK BKIN input enable */ 00148 #define TIMx_OR2_BKCOMP1E TIM1_OR2_BKCMP1E /*!< BRK COMP1 enable */ 00149 #define TIMx_OR2_BKCOMP2E TIM1_OR2_BKCMP2E /*!< BRK COMP2 enable */ 00150 #if defined(DFSDM1_Channel0) 00151 #define TIMx_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E /*!< BRK DFSDM1_BREAK[0] enable */ 00152 #endif /* DFSDM1_Channel0 */ 00153 #define TIMx_OR2_BKINP TIM1_OR2_BKINP /*!< BRK BKIN input polarity */ 00154 #define TIMx_OR2_BKCOMP1P TIM1_OR2_BKCMP1P /*!< BRK COMP1 input polarity */ 00155 #define TIMx_OR2_BKCOMP2P TIM1_OR2_BKCMP2P /*!< BRK COMP2 input polarity */ 00156 #define TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL /*!< TIMx ETR source selection */ 00157 00158 /* Generic bit definitions for TIMx_OR3 register */ 00159 #define TIMx_OR3_BK2INE TIM1_OR3_BK2INE /*!< BRK2 BKIN2 input enable */ 00160 #define TIMx_OR3_BK2COMP1E TIM1_OR3_BK2CMP1E /*!< BRK2 COMP1 enable */ 00161 #define TIMx_OR3_BK2COMP2E TIM1_OR3_BK2CMP2E /*!< BRK2 COMP2 enable */ 00162 #if defined(DFSDM1_Channel0) 00163 #define TIMx_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E /*!< BRK2 DFSDM1_BREAK[1] enable */ 00164 #endif /* DFSDM1_Channel0 */ 00165 #define TIMx_OR3_BK2INP TIM1_OR3_BK2INP /*!< BRK2 BKIN2 input polarity */ 00166 #define TIMx_OR3_BK2COMP1P TIM1_OR3_BK2CMP1P /*!< BRK2 COMP1 input polarity */ 00167 #define TIMx_OR3_BK2COMP2P TIM1_OR3_BK2CMP2P /*!< BRK2 COMP2 input polarity */ 00168 00169 /* Remap mask definitions */ 00170 #define TIMx_OR1_RMP_SHIFT ((uint32_t)16U) 00171 #define TIMx_OR1_RMP_MASK ((uint32_t)0x0000FFFFU) 00172 #if defined(ADC3) 00173 #define TIM1_OR1_RMP_MASK ((uint32_t)((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)) 00174 #else 00175 #define TIM1_OR1_RMP_MASK ((uint32_t)((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)) 00176 #endif /* ADC3 */ 00177 #define TIM2_OR1_RMP_MASK ((uint32_t)((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT)) 00178 #define TIM3_OR1_RMP_MASK ((uint32_t)(TIM3_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT) 00179 #define TIM8_OR1_RMP_MASK ((uint32_t)((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)) 00180 #define TIM15_OR1_RMP_MASK ((uint32_t)((TIM15_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)) 00181 #define TIM16_OR1_RMP_MASK ((uint32_t)((TIM16_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)) 00182 #define TIM17_OR1_RMP_MASK ((uint32_t)((TIM17_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)) 00183 00184 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ 00185 #define DT_DELAY_1 ((uint8_t)0x7FU) 00186 #define DT_DELAY_2 ((uint8_t)0x3FU) 00187 #define DT_DELAY_3 ((uint8_t)0x1FU) 00188 #define DT_DELAY_4 ((uint8_t)0x1FU) 00189 00190 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ 00191 #define DT_RANGE_1 ((uint8_t)0x00U) 00192 #define DT_RANGE_2 ((uint8_t)0x80U) 00193 #define DT_RANGE_3 ((uint8_t)0xC0U) 00194 #define DT_RANGE_4 ((uint8_t)0xE0U) 00195 00196 /** Legacy definitions for compatibility purpose 00197 @cond 0 00198 */ 00199 #if defined(DFSDM1_Channel0) 00200 #define TIMx_OR2_BKDFBK0E TIMx_OR2_BKDF1BK0E 00201 #define TIMx_OR3_BK2DFBK1E TIMx_OR3_BK2DF1BK1E 00202 #endif /* DFSDM1_Channel0 */ 00203 /** 00204 @endcond 00205 */ 00206 00207 /** 00208 * @} 00209 */ 00210 00211 00212 /* Private macros ------------------------------------------------------------*/ 00213 /** @defgroup TIM_LL_Private_Macros TIM Private Macros 00214 * @{ 00215 */ 00216 /** @brief Convert channel id into channel index. 00217 * @param __CHANNEL__ This parameter can be one of the following values: 00218 * @arg @ref LL_TIM_CHANNEL_CH1 00219 * @arg @ref LL_TIM_CHANNEL_CH1N 00220 * @arg @ref LL_TIM_CHANNEL_CH2 00221 * @arg @ref LL_TIM_CHANNEL_CH2N 00222 * @arg @ref LL_TIM_CHANNEL_CH3 00223 * @arg @ref LL_TIM_CHANNEL_CH3N 00224 * @arg @ref LL_TIM_CHANNEL_CH4 00225 * @arg @ref LL_TIM_CHANNEL_CH5 00226 * @arg @ref LL_TIM_CHANNEL_CH6 00227 * @retval none 00228 */ 00229 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ 00230 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ 00231 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ 00232 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ 00233 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ 00234 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ 00235 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ 00236 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ 00237 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) 00238 00239 /** @brief Calculate the deadtime sampling period(in ps). 00240 * @param __TIMCLK__ timer input clock frequency (in Hz). 00241 * @param __CKD__ This parameter can be one of the following values: 00242 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 00243 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 00244 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 00245 * @retval none 00246 */ 00247 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ 00248 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ 00249 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ 00250 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) 00251 /** 00252 * @} 00253 */ 00254 00255 00256 /* Exported types ------------------------------------------------------------*/ 00257 #if defined(USE_FULL_LL_DRIVER) 00258 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure 00259 * @{ 00260 */ 00261 00262 /** 00263 * @brief TIM Time Base configuration structure definition. 00264 */ 00265 typedef struct 00266 { 00267 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 00268 This parameter can be a number between 0x0000 and 0xFFFF. 00269 00270 This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ 00271 00272 uint32_t CounterMode; /*!< Specifies the counter mode. 00273 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. 00274 00275 This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ 00276 00277 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active 00278 Auto-Reload Register at the next update event. 00279 This parameter must be a number between 0x0000 and 0xFFFF. 00280 Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. 00281 00282 This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ 00283 00284 uint32_t ClockDivision; /*!< Specifies the clock division. 00285 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. 00286 00287 This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ 00288 00289 uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 00290 reaches zero, an update event is generated and counting restarts 00291 from the RCR value (N). 00292 This means in PWM mode that (N+1) corresponds to: 00293 - the number of PWM periods in edge-aligned mode 00294 - the number of half PWM period in center-aligned mode 00295 This parameter must be a number between 0x00 and 0xFF. 00296 00297 This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ 00298 } LL_TIM_InitTypeDef; 00299 00300 /** 00301 * @brief TIM Output Compare configuration structure definition. 00302 */ 00303 typedef struct 00304 { 00305 uint32_t OCMode; /*!< Specifies the output mode. 00306 This parameter can be a value of @ref TIM_LL_EC_OCMODE. 00307 00308 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ 00309 00310 uint32_t OCState; /*!< Specifies the TIM Output Compare state. 00311 This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 00312 00313 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 00314 00315 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. 00316 This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 00317 00318 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 00319 00320 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. 00321 This parameter can be a number between 0x0000 and 0xFFFF. 00322 00323 This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ 00324 00325 uint32_t OCPolarity; /*!< Specifies the output polarity. 00326 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 00327 00328 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ 00329 00330 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 00331 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 00332 00333 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ 00334 00335 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00336 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 00337 00338 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ 00339 00340 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00341 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 00342 00343 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ 00344 } LL_TIM_OC_InitTypeDef; 00345 00346 /** 00347 * @brief TIM Input Capture configuration structure definition. 00348 */ 00349 00350 typedef struct 00351 { 00352 00353 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 00354 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00355 00356 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ 00357 00358 uint32_t ICActiveInput; /*!< Specifies the input. 00359 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 00360 00361 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ 00362 00363 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 00364 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00365 00366 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ 00367 00368 uint32_t ICFilter; /*!< Specifies the input capture filter. 00369 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00370 00371 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ 00372 } LL_TIM_IC_InitTypeDef; 00373 00374 00375 /** 00376 * @brief TIM Encoder interface configuration structure definition. 00377 */ 00378 typedef struct 00379 { 00380 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). 00381 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. 00382 00383 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ 00384 00385 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 00386 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00387 00388 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ 00389 00390 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source 00391 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 00392 00393 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ 00394 00395 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 00396 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00397 00398 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ 00399 00400 uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 00401 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00402 00403 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ 00404 00405 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. 00406 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00407 00408 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ 00409 00410 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source 00411 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 00412 00413 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ 00414 00415 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. 00416 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00417 00418 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ 00419 00420 uint32_t IC2Filter; /*!< Specifies the TI2 input filter. 00421 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00422 00423 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ 00424 00425 } LL_TIM_ENCODER_InitTypeDef; 00426 00427 /** 00428 * @brief TIM Hall sensor interface configuration structure definition. 00429 */ 00430 typedef struct 00431 { 00432 00433 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 00434 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00435 00436 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ 00437 00438 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 00439 Prescaler must be set to get a maximum counter period longer than the 00440 time interval between 2 consecutive changes on the Hall inputs. 00441 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00442 00443 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ 00444 00445 uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 00446 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00447 00448 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ 00449 00450 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. 00451 A positive pulse (TRGO event) is generated with a programmable delay every time 00452 a change occurs on the Hall inputs. 00453 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. 00454 00455 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ 00456 } LL_TIM_HALLSENSOR_InitTypeDef; 00457 00458 /** 00459 * @} 00460 */ 00461 #endif /* USE_FULL_LL_DRIVER */ 00462 00463 /* Exported constants --------------------------------------------------------*/ 00464 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants 00465 * @{ 00466 */ 00467 00468 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines 00469 * @brief Flags defines which can be used with LL_TIM_ReadReg function. 00470 * @{ 00471 */ 00472 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ 00473 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ 00474 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ 00475 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ 00476 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ 00477 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ 00478 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ 00479 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ 00480 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ 00481 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ 00482 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ 00483 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ 00484 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ 00485 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ 00486 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ 00487 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ 00488 /** 00489 * @} 00490 */ 00491 00492 /** @defgroup TIM_LL_EC_IT IT Defines 00493 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. 00494 * @{ 00495 */ 00496 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ 00497 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ 00498 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ 00499 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ 00500 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ 00501 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ 00502 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ 00503 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ 00504 /** 00505 * @} 00506 */ 00507 00508 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source 00509 * @{ 00510 */ 00511 #define LL_TIM_UPDATESOURCE_REGULAR ((uint32_t)0x00000000U) /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ 00512 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ 00513 /** 00514 * @} 00515 */ 00516 00517 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode 00518 * @{ 00519 */ 00520 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ 00521 #define LL_TIM_ONEPULSEMODE_REPETITIVE ((uint32_t)0x00000000U) /*!< Counter stops counting at the next update event */ 00522 /** 00523 * @} 00524 */ 00525 00526 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode 00527 * @{ 00528 */ 00529 #define LL_TIM_COUNTERMODE_UP ((uint32_t)0x00000000U) /*!<Counter used as upcounter */ 00530 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ 00531 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ 00532 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ 00533 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ 00534 /** 00535 * @} 00536 */ 00537 00538 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division 00539 * @{ 00540 */ 00541 #define LL_TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000U) /*!< tDTS=tCK_INT */ 00542 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ 00543 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ 00544 /** 00545 * @} 00546 */ 00547 00548 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction 00549 * @{ 00550 */ 00551 #define LL_TIM_COUNTERDIRECTION_UP ((uint32_t)0x00000000U) /*!< Timer counter counts up */ 00552 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ 00553 /** 00554 * @} 00555 */ 00556 00557 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source 00558 * @{ 00559 */ 00560 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY ((uint32_t)0x00000000U) /*!< Capture/compare control bits are updated by setting the COMG bit only */ 00561 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ 00562 /** 00563 * @} 00564 */ 00565 00566 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request 00567 * @{ 00568 */ 00569 #define LL_TIM_CCDMAREQUEST_CC ((uint32_t)0x00000000U) /*!< CCx DMA request sent when CCx event occurs */ 00570 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ 00571 /** 00572 * @} 00573 */ 00574 00575 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level 00576 * @{ 00577 */ 00578 #define LL_TIM_LOCKLEVEL_OFF ((uint32_t)0x00000000U) /*!< LOCK OFF - No bit is write protected */ 00579 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 00580 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 00581 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 00582 /** 00583 * @} 00584 */ 00585 00586 /** @defgroup TIM_LL_EC_CHANNEL Channel 00587 * @{ 00588 */ 00589 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ 00590 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ 00591 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ 00592 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ 00593 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ 00594 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ 00595 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ 00596 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ 00597 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ 00598 /** 00599 * @} 00600 */ 00601 00602 #if defined(USE_FULL_LL_DRIVER) 00603 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State 00604 * @{ 00605 */ 00606 #define LL_TIM_OCSTATE_DISABLE ((uint32_t)0x00000000U) /*!< OCx is not active */ 00607 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ 00608 /** 00609 * @} 00610 */ 00611 #endif /* USE_FULL_LL_DRIVER */ 00612 00613 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode 00614 * @{ 00615 */ 00616 #define LL_TIM_OCMODE_FROZEN ((uint32_t)0x00000000U) /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */ 00617 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/ 00618 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/ 00619 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/ 00620 #define LL_TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) /*!<OCyREF is forced low*/ 00621 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/ 00622 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/ 00623 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/ 00624 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/ 00625 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/ 00626 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/ 00627 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/ 00628 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/ 00629 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/ 00630 /** 00631 * @} 00632 */ 00633 00634 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity 00635 * @{ 00636 */ 00637 #define LL_TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U) /*!< OCxactive high*/ 00638 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ 00639 /** 00640 * @} 00641 */ 00642 00643 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State 00644 * @{ 00645 */ 00646 #define LL_TIM_OCIDLESTATE_LOW ((uint32_t)0x00000000U) /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/ 00647 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/ 00648 /** 00649 * @} 00650 */ 00651 00652 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5 00653 * @{ 00654 */ 00655 #define LL_TIM_GROUPCH5_NONE (uint32_t)0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 00656 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ 00657 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ 00658 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ 00659 /** 00660 * @} 00661 */ 00662 00663 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection 00664 * @{ 00665 */ 00666 #define LL_TIM_ACTIVEINPUT_DIRECTTI (uint32_t)(TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */ 00667 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (uint32_t)(TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */ 00668 #define LL_TIM_ACTIVEINPUT_TRC (uint32_t)(TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */ 00669 /** 00670 * @} 00671 */ 00672 00673 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler 00674 * @{ 00675 */ 00676 #define LL_TIM_ICPSC_DIV1 ((uint32_t)0x00000000U) /*!< No prescaler, capture is done each time an edge is detected on the capture input */ 00677 #define LL_TIM_ICPSC_DIV2 (uint32_t)(TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ 00678 #define LL_TIM_ICPSC_DIV4 (uint32_t)(TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ 00679 #define LL_TIM_ICPSC_DIV8 (uint32_t)(TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ 00680 /** 00681 * @} 00682 */ 00683 00684 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter 00685 * @{ 00686 */ 00687 #define LL_TIM_IC_FILTER_FDIV1 ((uint32_t)0x00000000U) /*!< No filter, sampling is done at fDTS */ 00688 #define LL_TIM_IC_FILTER_FDIV1_N2 (uint32_t)(TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */ 00689 #define LL_TIM_IC_FILTER_FDIV1_N4 (uint32_t)(TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */ 00690 #define LL_TIM_IC_FILTER_FDIV1_N8 (uint32_t)((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */ 00691 #define LL_TIM_IC_FILTER_FDIV2_N6 (uint32_t)(TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */ 00692 #define LL_TIM_IC_FILTER_FDIV2_N8 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */ 00693 #define LL_TIM_IC_FILTER_FDIV4_N6 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */ 00694 #define LL_TIM_IC_FILTER_FDIV4_N8 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */ 00695 #define LL_TIM_IC_FILTER_FDIV8_N6 (uint32_t)(TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */ 00696 #define LL_TIM_IC_FILTER_FDIV8_N8 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */ 00697 #define LL_TIM_IC_FILTER_FDIV16_N5 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */ 00698 #define LL_TIM_IC_FILTER_FDIV16_N6 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */ 00699 #define LL_TIM_IC_FILTER_FDIV16_N8 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */ 00700 #define LL_TIM_IC_FILTER_FDIV32_N5 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */ 00701 #define LL_TIM_IC_FILTER_FDIV32_N6 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */ 00702 #define LL_TIM_IC_FILTER_FDIV32_N8 (uint32_t)(TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */ 00703 /** 00704 * @} 00705 */ 00706 00707 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity 00708 * @{ 00709 */ 00710 #define LL_TIM_IC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */ 00711 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */ 00712 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */ 00713 /** 00714 * @} 00715 */ 00716 00717 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source 00718 * @{ 00719 */ 00720 #define LL_TIM_CLOCKSOURCE_INTERNAL ((uint32_t)0x00000000U) /*!< The timer is clocked by the internal clock provided from the RCC */ 00721 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0 ) /*!< Counter counts at each rising or falling edge on a selected inpu t*/ 00722 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ 00723 /** 00724 * @} 00725 */ 00726 00727 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode 00728 * @{ 00729 */ 00730 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ 00731 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ 00732 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */ 00733 /** 00734 * @} 00735 */ 00736 00737 /** @defgroup TIM_LL_EC_TRGO Trigger Output 00738 * @{ 00739 */ 00740 #define LL_TIM_TRGO_RESET ((uint32_t)0x00000000U) /*!< UG bit from the TIMx_EGR register is used as trigger output */ 00741 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */ 00742 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */ 00743 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */ 00744 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */ 00745 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */ 00746 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */ 00747 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */ 00748 /** 00749 * @} 00750 */ 00751 00752 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2 00753 * @{ 00754 */ 00755 #define LL_TIM_TRGO2_RESET ((uint32_t)0x00000000U) /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */ 00756 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */ 00757 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */ 00758 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */ 00759 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */ 00760 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */ 00761 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */ 00762 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */ 00763 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */ 00764 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */ 00765 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */ 00766 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */ 00767 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */ 00768 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */ 00769 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */ 00770 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */ 00771 /** 00772 * @} 00773 */ 00774 00775 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode 00776 * @{ 00777 */ 00778 #define LL_TIM_SLAVEMODE_DISABLED ((uint32_t)0x00000000U) /*!< Slave mode disabled */ 00779 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */ 00780 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ 00781 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ 00782 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */ 00783 /** 00784 * @} 00785 */ 00786 00787 /** @defgroup TIM_LL_EC_TS Trigger Selection 00788 * @{ 00789 */ 00790 #define LL_TIM_TS_ITR0 ((uint32_t)0x00000000U) /*!< Internal Trigger 0 (ITR0) is used as trigger input */ 00791 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ 00792 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ 00793 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ 00794 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ 00795 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ 00796 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ 00797 #define LL_TIM_TS_ETRF TIM_SMCR_TS /*!< Filtered external Trigger (ETRF) is used as trigger input */ 00798 /** 00799 * @} 00800 */ 00801 00802 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity 00803 * @{ 00804 */ 00805 #define LL_TIM_ETR_POLARITY_NONINVERTED ((uint32_t)0x00000000U) /*!< ETR is non-inverted, active at high level or rising edge */ 00806 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */ 00807 /** 00808 * @} 00809 */ 00810 00811 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler 00812 * @{ 00813 */ 00814 #define LL_TIM_ETR_PRESCALER_DIV1 ((uint32_t)0x00000000U) /*!< ETR prescaler OFF */ 00815 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */ 00816 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */ 00817 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */ 00818 /** 00819 * @} 00820 */ 00821 00822 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter 00823 * @{ 00824 */ 00825 #define LL_TIM_ETR_FILTER_FDIV1 ((uint32_t)0x00000000U) /*!< No filter, sampling is done at fDTS */ 00826 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */ 00827 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */ 00828 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */ 00829 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */ 00830 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ 00831 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 ) /*!< fSAMPLING=fDTS/4, N=6 */ 00832 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ 00833 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ 00834 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ 00835 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 ) /*!< fSAMPLING=fDTS/16, N=6 */ 00836 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ 00837 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 ) /*!< fSAMPLING=fDTS/16, N=5 */ 00838 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ 00839 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ 00840 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ 00841 /** 00842 * @} 00843 */ 00844 00845 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source 00846 * @{ 00847 */ 00848 #define LL_TIM_ETRSOURCE_LEGACY ((uint32_t)(0x00000000U)) /*!< ETR legacy mode */ 00849 #define LL_TIM_ETRSOURCE_COMP1 TIM1_OR2_ETRSEL_0 /*!< COMP1 output connected to ETR input */ 00850 #define LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1 /*!< COMP2 output connected to ETR input */ 00851 /** 00852 * @} 00853 */ 00854 00855 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity 00856 * @{ 00857 */ 00858 #define LL_TIM_BREAK_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Break input BRK is active low */ 00859 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 00860 /** 00861 * @} 00862 */ 00863 00864 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter 00865 * @{ 00866 */ 00867 #define LL_TIM_BREAK_FILTER_FDIV1 ((uint32_t)0x00000000U) /*!< No filter, BRK acts asynchronously */ 00868 #define LL_TIM_BREAK_FILTER_FDIV1_N2 ((uint32_t)0x00010000U) /*!< fSAMPLING=fCK_INT, N=2 */ 00869 #define LL_TIM_BREAK_FILTER_FDIV1_N4 ((uint32_t)0x00020000U) /*!< fSAMPLING=fCK_INT, N=4 */ 00870 #define LL_TIM_BREAK_FILTER_FDIV1_N8 ((uint32_t)0x00030000U) /*!< fSAMPLING=fCK_INT, N=8 */ 00871 #define LL_TIM_BREAK_FILTER_FDIV2_N6 ((uint32_t)0x00040000U) /*!< fSAMPLING=fDTS/2, N=6 */ 00872 #define LL_TIM_BREAK_FILTER_FDIV2_N8 ((uint32_t)0x00050000U) /*!< fSAMPLING=fDTS/2, N=8 */ 00873 #define LL_TIM_BREAK_FILTER_FDIV4_N6 ((uint32_t)0x00060000U) /*!< fSAMPLING=fDTS/4, N=6 */ 00874 #define LL_TIM_BREAK_FILTER_FDIV4_N8 ((uint32_t)0x00070000U) /*!< fSAMPLING=fDTS/4, N=8 */ 00875 #define LL_TIM_BREAK_FILTER_FDIV8_N6 ((uint32_t)0x00080000U) /*!< fSAMPLING=fDTS/8, N=6 */ 00876 #define LL_TIM_BREAK_FILTER_FDIV8_N8 ((uint32_t)0x00090000U) /*!< fSAMPLING=fDTS/8, N=8 */ 00877 #define LL_TIM_BREAK_FILTER_FDIV16_N5 ((uint32_t)0x000A0000U) /*!< fSAMPLING=fDTS/16, N=5 */ 00878 #define LL_TIM_BREAK_FILTER_FDIV16_N6 ((uint32_t)0x000B0000U) /*!< fSAMPLING=fDTS/16, N=6 */ 00879 #define LL_TIM_BREAK_FILTER_FDIV16_N8 ((uint32_t)0x000C0000U) /*!< fSAMPLING=fDTS/16, N=8 */ 00880 #define LL_TIM_BREAK_FILTER_FDIV32_N5 ((uint32_t)0x000D0000U) /*!< fSAMPLING=fDTS/32, N=5 */ 00881 #define LL_TIM_BREAK_FILTER_FDIV32_N6 ((uint32_t)0x000E0000U) /*!< fSAMPLING=fDTS/32, N=6 */ 00882 #define LL_TIM_BREAK_FILTER_FDIV32_N8 ((uint32_t)0x000F0000U) /*!< fSAMPLING=fDTS/32, N=8 */ 00883 /** 00884 * @} 00885 */ 00886 00887 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY 00888 * @{ 00889 */ 00890 #define LL_TIM_BREAK2_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Break input BRK2 is active low */ 00891 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 00892 /** 00893 * @} 00894 */ 00895 00896 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER 00897 * @{ 00898 */ 00899 #define LL_TIM_BREAK2_FILTER_FDIV1 ((uint32_t)0x00000000U) /*!< No filter, BRK acts asynchronously */ 00900 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 ((uint32_t)0x00100000U) /*!< fSAMPLING=fCK_INT, N=2 */ 00901 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 ((uint32_t)0x00200000U) /*!< fSAMPLING=fCK_INT, N=4 */ 00902 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 ((uint32_t)0x00300000U) /*!< fSAMPLING=fCK_INT, N=8 */ 00903 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 ((uint32_t)0x00400000U) /*!< fSAMPLING=fDTS/2, N=6 */ 00904 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 ((uint32_t)0x00500000U) /*!< fSAMPLING=fDTS/2, N=8 */ 00905 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 ((uint32_t)0x00600000U) /*!< fSAMPLING=fDTS/4, N=6 */ 00906 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 ((uint32_t)0x00700000U) /*!< fSAMPLING=fDTS/4, N=8 */ 00907 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 ((uint32_t)0x00800000U) /*!< fSAMPLING=fDTS/8, N=6 */ 00908 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 ((uint32_t)0x00900000U) /*!< fSAMPLING=fDTS/8, N=8 */ 00909 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 ((uint32_t)0x00A00000U) /*!< fSAMPLING=fDTS/16, N=5 */ 00910 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 ((uint32_t)0x00B00000U) /*!< fSAMPLING=fDTS/16, N=6 */ 00911 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 ((uint32_t)0x00C00000U) /*!< fSAMPLING=fDTS/16, N=8 */ 00912 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 ((uint32_t)0x00D00000U) /*!< fSAMPLING=fDTS/32, N=5 */ 00913 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 ((uint32_t)0x00E00000U) /*!< fSAMPLING=fDTS/32, N=6 */ 00914 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 ((uint32_t)0x00F00000U) /*!< fSAMPLING=fDTS/32, N=8 */ 00915 /** 00916 * @} 00917 */ 00918 00919 /** @defgroup TIM_LL_EC_OSSI OSSI 00920 * @{ 00921 */ 00922 #define LL_TIM_OSSI_DISABLE ((uint32_t)0x00000000U) /*!< When inactive, OCx/OCxN outputs are disabled */ 00923 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */ 00924 /** 00925 * @} 00926 */ 00927 00928 /** @defgroup TIM_LL_EC_OSSR OSSR 00929 * @{ 00930 */ 00931 #define LL_TIM_OSSR_DISABLE ((uint32_t)0x00000000U) /*!< When inactive, OCx/OCxN outputs are disabled */ 00932 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */ 00933 /** 00934 * @} 00935 */ 00936 00937 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT 00938 * @{ 00939 */ 00940 #define LL_TIM_BREAK_INPUT_BKIN ((uint32_t)0x00000000U) /*!< TIMx_BKIN input */ 00941 #define LL_TIM_BREAK_INPUT_BKIN2 ((uint32_t)0x00000004U) /*!< TIMx_BKIN2 input */ 00942 /** 00943 * @} 00944 */ 00945 00946 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE 00947 * @{ 00948 */ 00949 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /*!< BKIN input from AF controller */ 00950 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /*!< internal signal: COMP1 output */ 00951 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /*!< internal signal: COMP2 output */ 00952 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E /*!< internal signal: DFSDM1 break output */ 00953 /** 00954 * @} 00955 */ 00956 00957 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY 00958 * @{ 00959 */ 00960 #define LL_TIM_BKIN_POLARITY_LOW ((uint32_t)0x00000000U) /*!< BRK BKIN input is active low */ 00961 #define LL_TIM_BKIN_POLARITY_HIGH TIM1_OR2_BKINP /*!< BRK BKIN input is active high */ 00962 /** 00963 * @} 00964 */ 00965 00966 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address 00967 * @{ 00968 */ 00969 #define LL_TIM_DMABURST_BASEADDR_CR1 ((uint32_t)0x00000000U) /*!< TIMx_CR1 register is the DMA base address for DMA burst */ /*!< TIMx_CR1 register is the DMA base address for DMA burst */ 00970 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */ 00971 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */ 00972 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */ 00973 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */ 00974 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */ 00975 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */ 00976 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */ 00977 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */ 00978 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */ 00979 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */ 00980 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */ 00981 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */ 00982 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */ 00983 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */ 00984 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ 00985 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ 00986 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */ 00987 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */ 00988 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */ 00989 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */ 00990 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_OR1 register is the DMA base address for DMA burst */ 00991 #define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_OR2 register is the DMA base address for DMA burst */ 00992 #define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_OR3 register is the DMA base address for DMA burst */ 00993 /** 00994 * @} 00995 */ 00996 00997 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length 00998 * @{ 00999 */ 01000 #define LL_TIM_DMABURST_LENGTH_1TRANSFER ((uint32_t)0x00000000U) /*!< Transfer is done to 1 register starting from the DMA burst base address */ 01001 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */ 01002 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */ 01003 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */ 01004 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */ 01005 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */ 01006 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */ 01007 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */ 01008 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */ 01009 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */ 01010 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */ 01011 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */ 01012 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */ 01013 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */ 01014 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */ 01015 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */ 01016 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */ 01017 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */ 01018 /** 01019 * @} 01020 */ 01021 01022 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap 01023 * @{ 01024 */ 01025 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC ((uint32_t)0x00000000U | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */ 01026 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */ 01027 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */ 01028 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */ 01029 /** 01030 * @} 01031 */ 01032 01033 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP TIM1 External Trigger ADC3 Remap 01034 * @{ 01035 */ 01036 #define LL_TIM_TIM1_ETR_ADC3_RMP_NC ((uint32_t)0x00000000U | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is not connected to ADC3 analog watchdog x*/ 01037 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 1 */ 01038 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 2 */ 01039 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 3 */ 01040 /** 01041 * @} 01042 */ 01043 01044 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap 01045 * @{ 01046 */ 01047 #define LL_TIM_TIM1_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM1_OR1_RMP_MASK) /*!< TIM1 input capture 1 is connected to GPIO */ 01048 #define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1 input capture 1 is connected to COMP1 output */ 01049 /** 01050 * @} 01051 */ 01052 01053 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8 01054 * @{ 01055 */ 01056 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO ((uint32_t)0x00000000U | TIM2_OR1_RMP_MASK) /*!< TIM2_ITR1 is connected to TIM8_TRGO */ 01057 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */ 01058 #define LL_TIM_TIM2_ETR_RMP_GPIO ((uint32_t)0x00000000U | TIM2_OR1_RMP_MASK) /*!< TIM2_ETR is connected to GPIO */ 01059 #define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ETR is connected to LSE */ 01060 /** 01061 * @} 01062 */ 01063 01064 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap 01065 * @{ 01066 */ 01067 #define LL_TIM_TIM2_TI4_RMP_GPIO ((uint32_t)0x00000000U | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to GPIO */ 01068 #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */ 01069 #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */ 01070 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */ 01071 /** 01072 * @} 01073 */ 01074 01075 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap 01076 * @{ 01077 */ 01078 #define LL_TIM_TIM3_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to GPIO */ 01079 #define LL_TIM_TIM3_TI1_RMP_COMP1 (TIM3_OR1_TI1_RMP_0 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP1_OUT */ 01080 #define LL_TIM_TIM3_TI1_RMP_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP2_OUT */ 01081 #define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM3_OR1_TI1_RMP | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT */ 01082 /** 01083 * @} 01084 */ 01085 01086 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap 01087 * @{ 01088 */ 01089 #define LL_TIM_TIM8_ETR_ADC2_RMP_NC ((uint32_t)0x00000000U | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */ 01090 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog */ 01091 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */ 01092 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */ 01093 /** 01094 * @} 01095 */ 01096 01097 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap 01098 * @{ 01099 */ 01100 #define LL_TIM_TIM8_ETR_ADC3_RMP_NC ((uint32_t)0x00000000U | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */ 01101 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */ 01102 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */ 01103 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */ 01104 /** 01105 * @} 01106 */ 01107 01108 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 External Input Ch1 Remap 01109 * @{ 01110 */ 01111 #define LL_TIM_TIM8_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM8_OR1_RMP_MASK) /*!< TIM8 input capture 1 is connected to GPIO */ 01112 #define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8 input capture 1 is connected to COMP2 output */ 01113 /** 01114 * @} 01115 */ 01116 01117 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap 01118 * @{ 01119 */ 01120 #define LL_TIM_TIM15_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM15_OR1_RMP_MASK) /*!< TIM15 input capture 1 is connected to GPIO */ 01121 #define LL_TIM_TIM15_TI1_RMP_LSE (TIM15_OR1_TI1_RMP | TIM15_OR1_RMP_MASK) /*!< TIM15 input capture 1 is connected to LSE */ 01122 /** 01123 * @} 01124 */ 01125 01126 /** @defgroup TIM_LL_EC_TIM15_ENCODERMODE TIM15 ENCODERMODE 01127 * @{ 01128 */ 01129 #define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION ((uint32_t)0x00000000U | TIM15_OR1_RMP_MASK) /*!< No redirection*/ 01130 #define LL_TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0 | TIM15_OR1_RMP_MASK) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ 01131 #define LL_TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_RMP_MASK) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y*/ 01132 #define LL_TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE | TIM15_OR1_RMP_MASK) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ 01133 /** 01134 * @} 01135 */ 01136 01137 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap 01138 * @{ 01139 */ 01140 #define LL_TIM_TIM16_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to GPIO */ 01141 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSI */ 01142 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSE */ 01143 #define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */ 01144 #if defined TIM16_OR1_TI1_RMP_2 01145 #define LL_TIM_TIM16_TI1_RMP_MSI (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to MSI */ 01146 #define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to HSE/32 */ 01147 #define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to MCO */ 01148 #endif 01149 /** 01150 * @} 01151 */ 01152 01153 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap 01154 * @{ 01155 */ 01156 #define LL_TIM_TIM17_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to GPIO */ 01157 #define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MSI */ 01158 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to HSE/32 */ 01159 #define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MCO */ 01160 /** 01161 * @} 01162 */ 01163 01164 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection 01165 * @{ 01166 */ 01167 #define LL_TIM_OCREF_CLR_INT_NC ((uint32_t)0x00000000U ) /*!< OCREF_CLR_INT is not connected */ 01168 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */ 01169 /** 01170 * @} 01171 */ 01172 01173 /** Legacy definitions for compatibility purpose 01174 @cond 0 01175 */ 01176 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK 01177 /** 01178 @endcond 01179 */ 01180 01181 /** 01182 * @} 01183 */ 01184 01185 /* Exported macro ------------------------------------------------------------*/ 01186 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros 01187 * @{ 01188 */ 01189 01190 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros 01191 * @{ 01192 */ 01193 /** 01194 * @brief Write a value in TIM register. 01195 * @param __INSTANCE__ TIM Instance 01196 * @param __REG__ Register to be written 01197 * @param __VALUE__ Value to be written in the register 01198 * @retval None 01199 */ 01200 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 01201 01202 /** 01203 * @brief Read a value in TIM register. 01204 * @param __INSTANCE__ TIM Instance 01205 * @param __REG__ Register to be read 01206 * @retval Register value 01207 */ 01208 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 01209 /** 01210 * @} 01211 */ 01212 01213 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros 01214 * @{ 01215 */ 01216 /** 01217 * @brief HELPER macro retrieving the UIFCPY flag from the counter value. 01218 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); 01219 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied 01220 * to TIMx_CNT register bit 31) 01221 * @param __CNT__ Counter value 01222 * @retval UIF status bit 01223 */ 01224 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ 01225 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> POSITION_VAL(TIM_CNT_UIFCPY)) 01226 01227 /** 01228 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. 01229 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); 01230 * @param __TIMCLK__ timer input clock frequency (in Hz) 01231 * @param __CKD__ This parameter can be one of the following values: 01232 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 01233 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 01234 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 01235 * @param __DT__ deadtime duration (in ns) 01236 * @retval DTG[0:7] 01237 */ 01238 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ 01239 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ 01240 (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\ 01241 (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\ 01242 (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\ 01243 0U) 01244 01245 /** 01246 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. 01247 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); 01248 * @param __TIMCLK__ timer input clock frequency (in Hz) 01249 * @param __CNTCLK__ counter clock frequency (in Hz) 01250 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) 01251 */ 01252 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ 01253 ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U 01254 01255 /** 01256 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. 01257 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); 01258 * @param __TIMCLK__ timer input clock frequency (in Hz) 01259 * @param __PSC__ prescaler 01260 * @param __FREQ__ output signal frequency (in Hz) 01261 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 01262 */ 01263 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ 01264 (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U 01265 01266 /** 01267 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. 01268 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); 01269 * @param __TIMCLK__ timer input clock frequency (in Hz) 01270 * @param __PSC__ prescaler 01271 * @param __DELAY__ timer output compare active/inactive delay (in us) 01272 * @retval Compare value (between Min_Data=0 and Max_Data=65535) 01273 */ 01274 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ 01275 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ 01276 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) 01277 01278 /** 01279 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). 01280 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); 01281 * @param __TIMCLK__ timer input clock frequency (in Hz) 01282 * @param __PSC__ prescaler 01283 * @param __DELAY__ timer output compare active/inactive delay (in us) 01284 * @param __PULSE__ pulse duration (in us) 01285 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 01286 */ 01287 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ 01288 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ 01289 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) 01290 01291 /** 01292 * @brief HELPER macro retrieving the ratio of the input capture prescaler 01293 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); 01294 * @param __ICPSC__ This parameter can be one of the following values: 01295 * @arg @ref LL_TIM_ICPSC_DIV1 01296 * @arg @ref LL_TIM_ICPSC_DIV2 01297 * @arg @ref LL_TIM_ICPSC_DIV4 01298 * @arg @ref LL_TIM_ICPSC_DIV8 01299 * @retval Input capture prescaler ratio (1, 2, 4 or 8) 01300 */ 01301 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ 01302 ((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_POSITION_ICPSC))) 01303 01304 01305 /** 01306 * @} 01307 */ 01308 01309 01310 /** 01311 * @} 01312 */ 01313 01314 /* Exported functions --------------------------------------------------------*/ 01315 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions 01316 * @{ 01317 */ 01318 01319 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration 01320 * @{ 01321 */ 01322 /** 01323 * @brief Enable timer counter. 01324 * @rmtoll CR1 CEN LL_TIM_EnableCounter 01325 * @param TIMx Timer instance 01326 * @retval None 01327 */ 01328 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef * TIMx) 01329 { 01330 SET_BIT(TIMx->CR1, TIM_CR1_CEN); 01331 } 01332 01333 /** 01334 * @brief Disable timer counter. 01335 * @rmtoll CR1 CEN LL_TIM_DisableCounter 01336 * @param TIMx Timer instance 01337 * @retval None 01338 */ 01339 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef * TIMx) 01340 { 01341 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); 01342 } 01343 01344 /** 01345 * @brief Indicates whether the timer counter is enabled. 01346 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter 01347 * @param TIMx Timer instance 01348 * @retval State of bit (1 or 0). 01349 */ 01350 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef * TIMx) 01351 { 01352 return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)); 01353 } 01354 01355 /** 01356 * @brief Enable update event generation. 01357 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent 01358 * @param TIMx Timer instance 01359 * @retval None 01360 */ 01361 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx) 01362 { 01363 SET_BIT(TIMx->CR1, TIM_CR1_UDIS); 01364 } 01365 01366 /** 01367 * @brief Disable update event generation. 01368 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent 01369 * @param TIMx Timer instance 01370 * @retval None 01371 */ 01372 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx) 01373 { 01374 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); 01375 } 01376 01377 /** 01378 * @brief Indicates whether update event generation is enabled. 01379 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent 01380 * @param TIMx Timer instance 01381 * @retval State of bit (1 or 0). 01382 */ 01383 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef * TIMx) 01384 { 01385 return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS)); 01386 } 01387 01388 /** 01389 * @brief Set update event source 01390 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events 01391 * generate an update interrupt or DMA request if enabled: 01392 * - Counter overflow/underflow 01393 * - Setting the UG bit 01394 * - Update generation through the slave mode controller 01395 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter 01396 * overflow/underflow generates an update interrupt or DMA request if enabled. 01397 * @rmtoll CR1 URS LL_TIM_SetUpdateSource 01398 * @param TIMx Timer instance 01399 * @param UpdateSource This parameter can be one of the following values: 01400 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 01401 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 01402 * @retval None 01403 */ 01404 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx, uint32_t UpdateSource) 01405 { 01406 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); 01407 } 01408 01409 /** 01410 * @brief Get actual event update source 01411 * @rmtoll CR1 URS LL_TIM_GetUpdateSource 01412 * @param TIMx Timer instance 01413 * @retval Returned value can be one of the following values: 01414 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 01415 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 01416 */ 01417 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef * TIMx) 01418 { 01419 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); 01420 } 01421 01422 /** 01423 * @brief Set one pulse mode (one shot v.s. repetitive). 01424 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode 01425 * @param TIMx Timer instance 01426 * @param OnePulseMode This parameter can be one of the following values: 01427 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 01428 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 01429 * @retval None 01430 */ 01431 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx, uint32_t OnePulseMode) 01432 { 01433 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); 01434 } 01435 01436 /** 01437 * @brief Get actual one pulse mode. 01438 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode 01439 * @param TIMx Timer instance 01440 * @retval Returned value can be one of the following values: 01441 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 01442 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 01443 */ 01444 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef * TIMx) 01445 { 01446 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); 01447 } 01448 01449 /** 01450 * @brief Set the timer counter counting mode. 01451 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 01452 * check whether or not the counter mode selection feature is supported 01453 * by a timer instance. 01454 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n 01455 * CR1 CMS LL_TIM_SetCounterMode 01456 * @param TIMx Timer instance 01457 * @param CounterMode This parameter can be one of the following values: 01458 * @arg @ref LL_TIM_COUNTERMODE_UP 01459 * @arg @ref LL_TIM_COUNTERMODE_DOWN 01460 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 01461 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 01462 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 01463 * @retval None 01464 */ 01465 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef * TIMx, uint32_t CounterMode) 01466 { 01467 MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode); 01468 } 01469 01470 /** 01471 * @brief Get actual counter mode. 01472 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 01473 * check whether or not the counter mode selection feature is supported 01474 * by a timer instance. 01475 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n 01476 * CR1 CMS LL_TIM_GetCounterMode 01477 * @param TIMx Timer instance 01478 * @retval Returned value can be one of the following values: 01479 * @arg @ref LL_TIM_COUNTERMODE_UP 01480 * @arg @ref LL_TIM_COUNTERMODE_DOWN 01481 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 01482 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 01483 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 01484 */ 01485 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef * TIMx) 01486 { 01487 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); 01488 } 01489 01490 /** 01491 * @brief Enable auto-reload (ARR) preload. 01492 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload 01493 * @param TIMx Timer instance 01494 * @retval None 01495 */ 01496 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx) 01497 { 01498 SET_BIT(TIMx->CR1, TIM_CR1_ARPE); 01499 } 01500 01501 /** 01502 * @brief Disable auto-reload (ARR) preload. 01503 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload 01504 * @param TIMx Timer instance 01505 * @retval None 01506 */ 01507 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx) 01508 { 01509 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); 01510 } 01511 01512 /** 01513 * @brief Indicates whether auto-reload (ARR) preload is enabled. 01514 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload 01515 * @param TIMx Timer instance 01516 * @retval State of bit (1 or 0). 01517 */ 01518 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef * TIMx) 01519 { 01520 return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)); 01521 } 01522 01523 /** 01524 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. 01525 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 01526 * whether or not the clock division feature is supported by the timer 01527 * instance. 01528 * @rmtoll CR1 CKD LL_TIM_SetClockDivision 01529 * @param TIMx Timer instance 01530 * @param ClockDivision This parameter can be one of the following values: 01531 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 01532 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 01533 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 01534 * @retval None 01535 */ 01536 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef * TIMx, uint32_t ClockDivision) 01537 { 01538 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); 01539 } 01540 01541 /** 01542 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. 01543 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 01544 * whether or not the clock division feature is supported by the timer 01545 * instance. 01546 * @rmtoll CR1 CKD LL_TIM_GetClockDivision 01547 * @param TIMx Timer instance 01548 * @retval Returned value can be one of the following values: 01549 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 01550 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 01551 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 01552 */ 01553 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef * TIMx) 01554 { 01555 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); 01556 } 01557 01558 /** 01559 * @brief Set the counter value. 01560 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01561 * whether or not a timer instance supports a 32 bits counter. 01562 * @rmtoll CNT CNT LL_TIM_SetCounter 01563 * @param TIMx Timer instance 01564 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 01565 * @retval None 01566 */ 01567 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef * TIMx, uint32_t Counter) 01568 { 01569 WRITE_REG(TIMx->CNT, Counter); 01570 } 01571 01572 /** 01573 * @brief Get the counter value. 01574 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01575 * whether or not a timer instance supports a 32 bits counter. 01576 * @rmtoll CNT CNT LL_TIM_GetCounter 01577 * @param TIMx Timer instance 01578 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 01579 */ 01580 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef * TIMx) 01581 { 01582 return (uint32_t)(READ_REG(TIMx->CNT)); 01583 } 01584 01585 /** 01586 * @brief Get the current direction of the counter 01587 * @rmtoll CR1 DIR LL_TIM_GetDirection 01588 * @param TIMx Timer instance 01589 * @retval Returned value can be one of the following values: 01590 * @arg @ref LL_TIM_COUNTERDIRECTION_UP 01591 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN 01592 */ 01593 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef * TIMx) 01594 { 01595 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 01596 } 01597 01598 /** 01599 * @brief Set the prescaler value. 01600 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). 01601 * @note The prescaler can be changed on the fly as this control register is buffered. The new 01602 * prescaler ratio is taken into account at the next update event. 01603 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter 01604 * @rmtoll PSC PSC LL_TIM_SetPrescaler 01605 * @param TIMx Timer instance 01606 * @param Prescaler between Min_Data=0 and Max_Data=65535 01607 * @retval None 01608 */ 01609 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef * TIMx, uint32_t Prescaler) 01610 { 01611 WRITE_REG(TIMx->PSC, Prescaler); 01612 } 01613 01614 /** 01615 * @brief Get the prescaler value. 01616 * @rmtoll PSC PSC LL_TIM_GetPrescaler 01617 * @param TIMx Timer instance 01618 * @retval Prescaler value between Min_Data=0 and Max_Data=65535 01619 */ 01620 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef * TIMx) 01621 { 01622 return (uint32_t)(READ_REG(TIMx->PSC)); 01623 } 01624 01625 /** 01626 * @brief Set the auto-reload value. 01627 * @note The counter is blocked while the auto-reload value is null. 01628 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01629 * whether or not a timer instance supports a 32 bits counter. 01630 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter 01631 * @rmtoll ARR ARR LL_TIM_SetAutoReload 01632 * @param TIMx Timer instance 01633 * @param AutoReload between Min_Data=0 and Max_Data=65535 01634 * @retval None 01635 */ 01636 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef * TIMx, uint32_t AutoReload) 01637 { 01638 WRITE_REG(TIMx->ARR, AutoReload); 01639 } 01640 01641 /** 01642 * @brief Get the auto-reload value. 01643 * @rmtoll ARR ARR LL_TIM_GetAutoReload 01644 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01645 * whether or not a timer instance supports a 32 bits counter. 01646 * @param TIMx Timer instance 01647 * @retval Auto-reload value 01648 */ 01649 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef * TIMx) 01650 { 01651 return (uint32_t)(READ_REG(TIMx->ARR)); 01652 } 01653 01654 /** 01655 * @brief Set the repetition counter value. 01656 * @note For advanced timer instances RepetitionCounter can be up to 65535. 01657 * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 01658 * whether or not a timer instance supports a repetition counter. 01659 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter 01660 * @param TIMx Timer instance 01661 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 01662 * @retval None 01663 */ 01664 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx, uint32_t RepetitionCounter) 01665 { 01666 WRITE_REG(TIMx->RCR, RepetitionCounter); 01667 } 01668 01669 /** 01670 * @brief Get the repetition counter value. 01671 * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 01672 * whether or not a timer instance supports a repetition counter. 01673 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter 01674 * @param TIMx Timer instance 01675 * @retval Repetition counter value 01676 */ 01677 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef * TIMx) 01678 { 01679 return (uint32_t)(READ_REG(TIMx->RCR)); 01680 } 01681 01682 /** 01683 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). 01684 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. 01685 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap 01686 * @param TIMx Timer instance 01687 * @retval None 01688 */ 01689 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx) 01690 { 01691 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 01692 } 01693 01694 /** 01695 * @brief Disable update interrupt flag (UIF) remapping. 01696 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap 01697 * @param TIMx Timer instance 01698 * @retval None 01699 */ 01700 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx) 01701 { 01702 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 01703 } 01704 01705 /** 01706 * @} 01707 */ 01708 01709 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration 01710 * @{ 01711 */ 01712 /** 01713 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 01714 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, 01715 * they are updated only when a commutation event (COM) occurs. 01716 * @note Only on channels that have a complementary output. 01717 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 01718 * whether or not a timer instance is able to generate a commutation event. 01719 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload 01720 * @param TIMx Timer instance 01721 * @retval None 01722 */ 01723 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx) 01724 { 01725 SET_BIT(TIMx->CR2, TIM_CR2_CCPC); 01726 } 01727 01728 /** 01729 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 01730 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 01731 * whether or not a timer instance is able to generate a commutation event. 01732 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload 01733 * @param TIMx Timer instance 01734 * @retval None 01735 */ 01736 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx) 01737 { 01738 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); 01739 } 01740 01741 /** 01742 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). 01743 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 01744 * whether or not a timer instance is able to generate a commutation event. 01745 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate 01746 * @param TIMx Timer instance 01747 * @param CCUpdateSource This parameter can be one of the following values: 01748 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY 01749 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI 01750 * @retval None 01751 */ 01752 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx, uint32_t CCUpdateSource) 01753 { 01754 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); 01755 } 01756 01757 /** 01758 * @brief Set the trigger of the capture/compare DMA request. 01759 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger 01760 * @param TIMx Timer instance 01761 * @param DMAReqTrigger This parameter can be one of the following values: 01762 * @arg @ref LL_TIM_CCDMAREQUEST_CC 01763 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 01764 * @retval None 01765 */ 01766 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx, uint32_t DMAReqTrigger) 01767 { 01768 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); 01769 } 01770 01771 /** 01772 * @brief Get actual trigger of the capture/compare DMA request. 01773 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger 01774 * @param TIMx Timer instance 01775 * @retval Returned value can be one of the following values: 01776 * @arg @ref LL_TIM_CCDMAREQUEST_CC 01777 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 01778 */ 01779 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef * TIMx) 01780 { 01781 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); 01782 } 01783 01784 /** 01785 * @brief Set the lock level to freeze the 01786 * configuration of several capture/compare parameters. 01787 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 01788 * the lock mechanism is supported by a timer instance. 01789 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel 01790 * @param TIMx Timer instance 01791 * @param LockLevel This parameter can be one of the following values: 01792 * @arg @ref LL_TIM_LOCKLEVEL_OFF 01793 * @arg @ref LL_TIM_LOCKLEVEL_1 01794 * @arg @ref LL_TIM_LOCKLEVEL_2 01795 * @arg @ref LL_TIM_LOCKLEVEL_3 01796 * @retval None 01797 */ 01798 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx, uint32_t LockLevel) 01799 { 01800 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); 01801 } 01802 01803 /** 01804 * @brief Enable capture/compare channels. 01805 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n 01806 * CCER CC1NE LL_TIM_CC_EnableChannel\n 01807 * CCER CC2E LL_TIM_CC_EnableChannel\n 01808 * CCER CC2NE LL_TIM_CC_EnableChannel\n 01809 * CCER CC3E LL_TIM_CC_EnableChannel\n 01810 * CCER CC3NE LL_TIM_CC_EnableChannel\n 01811 * CCER CC4E LL_TIM_CC_EnableChannel\n 01812 * CCER CC5E LL_TIM_CC_EnableChannel\n 01813 * CCER CC6E LL_TIM_CC_EnableChannel 01814 * @param TIMx Timer instance 01815 * @param Channels This parameter can be a combination of the following values: 01816 * @arg @ref LL_TIM_CHANNEL_CH1 01817 * @arg @ref LL_TIM_CHANNEL_CH1N 01818 * @arg @ref LL_TIM_CHANNEL_CH2 01819 * @arg @ref LL_TIM_CHANNEL_CH2N 01820 * @arg @ref LL_TIM_CHANNEL_CH3 01821 * @arg @ref LL_TIM_CHANNEL_CH3N 01822 * @arg @ref LL_TIM_CHANNEL_CH4 01823 * @arg @ref LL_TIM_CHANNEL_CH5 01824 * @arg @ref LL_TIM_CHANNEL_CH6 01825 * @retval None 01826 */ 01827 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx, uint32_t Channels) 01828 { 01829 SET_BIT(TIMx->CCER, Channels); 01830 } 01831 01832 /** 01833 * @brief Disable capture/compare channels. 01834 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n 01835 * CCER CC1NE LL_TIM_CC_DisableChannel\n 01836 * CCER CC2E LL_TIM_CC_DisableChannel\n 01837 * CCER CC2NE LL_TIM_CC_DisableChannel\n 01838 * CCER CC3E LL_TIM_CC_DisableChannel\n 01839 * CCER CC3NE LL_TIM_CC_DisableChannel\n 01840 * CCER CC4E LL_TIM_CC_DisableChannel\n 01841 * CCER CC5E LL_TIM_CC_DisableChannel\n 01842 * CCER CC6E LL_TIM_CC_DisableChannel 01843 * @param TIMx Timer instance 01844 * @param Channels This parameter can be a combination of the following values: 01845 * @arg @ref LL_TIM_CHANNEL_CH1 01846 * @arg @ref LL_TIM_CHANNEL_CH1N 01847 * @arg @ref LL_TIM_CHANNEL_CH2 01848 * @arg @ref LL_TIM_CHANNEL_CH2N 01849 * @arg @ref LL_TIM_CHANNEL_CH3 01850 * @arg @ref LL_TIM_CHANNEL_CH3N 01851 * @arg @ref LL_TIM_CHANNEL_CH4 01852 * @arg @ref LL_TIM_CHANNEL_CH5 01853 * @arg @ref LL_TIM_CHANNEL_CH6 01854 * @retval None 01855 */ 01856 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx, uint32_t Channels) 01857 { 01858 CLEAR_BIT(TIMx->CCER, Channels); 01859 } 01860 01861 /** 01862 * @brief Indicate whether channel(s) is(are) enabled. 01863 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n 01864 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n 01865 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n 01866 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n 01867 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n 01868 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n 01869 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n 01870 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n 01871 * CCER CC6E LL_TIM_CC_IsEnabledChannel 01872 * @param TIMx Timer instance 01873 * @param Channels This parameter can be a combination of the following values: 01874 * @arg @ref LL_TIM_CHANNEL_CH1 01875 * @arg @ref LL_TIM_CHANNEL_CH1N 01876 * @arg @ref LL_TIM_CHANNEL_CH2 01877 * @arg @ref LL_TIM_CHANNEL_CH2N 01878 * @arg @ref LL_TIM_CHANNEL_CH3 01879 * @arg @ref LL_TIM_CHANNEL_CH3N 01880 * @arg @ref LL_TIM_CHANNEL_CH4 01881 * @arg @ref LL_TIM_CHANNEL_CH5 01882 * @arg @ref LL_TIM_CHANNEL_CH6 01883 * @retval State of bit (1 or 0). 01884 */ 01885 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx, uint32_t Channels) 01886 { 01887 return (READ_BIT(TIMx->CCER, Channels) == (Channels)); 01888 } 01889 01890 /** 01891 * @} 01892 */ 01893 01894 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration 01895 * @{ 01896 */ 01897 /** 01898 * @brief Configure an output channel. 01899 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n 01900 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n 01901 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n 01902 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n 01903 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n 01904 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n 01905 * CCER CC1P LL_TIM_OC_ConfigOutput\n 01906 * CCER CC2P LL_TIM_OC_ConfigOutput\n 01907 * CCER CC3P LL_TIM_OC_ConfigOutput\n 01908 * CCER CC4P LL_TIM_OC_ConfigOutput\n 01909 * CCER CC5P LL_TIM_OC_ConfigOutput\n 01910 * CCER CC6P LL_TIM_OC_ConfigOutput\n 01911 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n 01912 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n 01913 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n 01914 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n 01915 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n 01916 * CR2 OIS6 LL_TIM_OC_ConfigOutput 01917 * @param TIMx Timer instance 01918 * @param Channel This parameter can be one of the following values: 01919 * @arg @ref LL_TIM_CHANNEL_CH1 01920 * @arg @ref LL_TIM_CHANNEL_CH2 01921 * @arg @ref LL_TIM_CHANNEL_CH3 01922 * @arg @ref LL_TIM_CHANNEL_CH4 01923 * @arg @ref LL_TIM_CHANNEL_CH5 01924 * @arg @ref LL_TIM_CHANNEL_CH6 01925 * @param Configuration This parameter must be a combination of all the following values: 01926 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW 01927 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH 01928 * @retval None 01929 */ 01930 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Configuration) 01931 { 01932 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01933 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 01934 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); 01935 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); 01936 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); 01937 } 01938 01939 /** 01940 * @brief Define the behavior of the output reference signal OCxREF from which 01941 * OCx and OCxN (when relevant) are derived. 01942 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n 01943 * CCMR1 OC2M LL_TIM_OC_SetMode\n 01944 * CCMR2 OC3M LL_TIM_OC_SetMode\n 01945 * CCMR2 OC4M LL_TIM_OC_SetMode\n 01946 * CCMR3 OC5M LL_TIM_OC_SetMode\n 01947 * CCMR3 OC6M LL_TIM_OC_SetMode 01948 * @param TIMx Timer instance 01949 * @param Channel This parameter can be one of the following values: 01950 * @arg @ref LL_TIM_CHANNEL_CH1 01951 * @arg @ref LL_TIM_CHANNEL_CH2 01952 * @arg @ref LL_TIM_CHANNEL_CH3 01953 * @arg @ref LL_TIM_CHANNEL_CH4 01954 * @arg @ref LL_TIM_CHANNEL_CH5 01955 * @arg @ref LL_TIM_CHANNEL_CH6 01956 * @param Mode This parameter can be one of the following values: 01957 * @arg @ref LL_TIM_OCMODE_FROZEN 01958 * @arg @ref LL_TIM_OCMODE_ACTIVE 01959 * @arg @ref LL_TIM_OCMODE_INACTIVE 01960 * @arg @ref LL_TIM_OCMODE_TOGGLE 01961 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 01962 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 01963 * @arg @ref LL_TIM_OCMODE_PWM1 01964 * @arg @ref LL_TIM_OCMODE_PWM2 01965 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 01966 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 01967 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 01968 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 01969 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 01970 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 01971 * @retval None 01972 */ 01973 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Mode) 01974 { 01975 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01976 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 01977 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); 01978 } 01979 01980 /** 01981 * @brief Get the output compare mode of an output channel. 01982 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n 01983 * CCMR1 OC2M LL_TIM_OC_GetMode\n 01984 * CCMR2 OC3M LL_TIM_OC_GetMode\n 01985 * CCMR2 OC4M LL_TIM_OC_GetMode\n 01986 * CCMR3 OC5M LL_TIM_OC_GetMode\n 01987 * CCMR3 OC6M LL_TIM_OC_GetMode 01988 * @param TIMx Timer instance 01989 * @param Channel This parameter can be one of the following values: 01990 * @arg @ref LL_TIM_CHANNEL_CH1 01991 * @arg @ref LL_TIM_CHANNEL_CH2 01992 * @arg @ref LL_TIM_CHANNEL_CH3 01993 * @arg @ref LL_TIM_CHANNEL_CH4 01994 * @arg @ref LL_TIM_CHANNEL_CH5 01995 * @arg @ref LL_TIM_CHANNEL_CH6 01996 * @retval Returned value can be one of the following values: 01997 * @arg @ref LL_TIM_OCMODE_FROZEN 01998 * @arg @ref LL_TIM_OCMODE_ACTIVE 01999 * @arg @ref LL_TIM_OCMODE_INACTIVE 02000 * @arg @ref LL_TIM_OCMODE_TOGGLE 02001 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 02002 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 02003 * @arg @ref LL_TIM_OCMODE_PWM1 02004 * @arg @ref LL_TIM_OCMODE_PWM2 02005 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 02006 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 02007 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 02008 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 02009 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 02010 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 02011 */ 02012 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef * TIMx, uint32_t Channel) 02013 { 02014 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02015 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02016 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); 02017 } 02018 02019 /** 02020 * @brief Set the polarity of an output channel. 02021 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n 02022 * CCER CC1NP LL_TIM_OC_SetPolarity\n 02023 * CCER CC2P LL_TIM_OC_SetPolarity\n 02024 * CCER CC2NP LL_TIM_OC_SetPolarity\n 02025 * CCER CC3P LL_TIM_OC_SetPolarity\n 02026 * CCER CC3NP LL_TIM_OC_SetPolarity\n 02027 * CCER CC4P LL_TIM_OC_SetPolarity\n 02028 * CCER CC5P LL_TIM_OC_SetPolarity\n 02029 * CCER CC6P LL_TIM_OC_SetPolarity 02030 * @param TIMx Timer instance 02031 * @param Channel This parameter can be one of the following values: 02032 * @arg @ref LL_TIM_CHANNEL_CH1 02033 * @arg @ref LL_TIM_CHANNEL_CH1N 02034 * @arg @ref LL_TIM_CHANNEL_CH2 02035 * @arg @ref LL_TIM_CHANNEL_CH2N 02036 * @arg @ref LL_TIM_CHANNEL_CH3 02037 * @arg @ref LL_TIM_CHANNEL_CH3N 02038 * @arg @ref LL_TIM_CHANNEL_CH4 02039 * @arg @ref LL_TIM_CHANNEL_CH5 02040 * @arg @ref LL_TIM_CHANNEL_CH6 02041 * @param Polarity This parameter can be one of the following values: 02042 * @arg @ref LL_TIM_OCPOLARITY_HIGH 02043 * @arg @ref LL_TIM_OCPOLARITY_LOW 02044 * @retval None 02045 */ 02046 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Polarity) 02047 { 02048 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02049 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); 02050 } 02051 02052 /** 02053 * @brief Get the polarity of an output channel. 02054 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n 02055 * CCER CC1NP LL_TIM_OC_GetPolarity\n 02056 * CCER CC2P LL_TIM_OC_GetPolarity\n 02057 * CCER CC2NP LL_TIM_OC_GetPolarity\n 02058 * CCER CC3P LL_TIM_OC_GetPolarity\n 02059 * CCER CC3NP LL_TIM_OC_GetPolarity\n 02060 * CCER CC4P LL_TIM_OC_GetPolarity\n 02061 * CCER CC5P LL_TIM_OC_GetPolarity\n 02062 * CCER CC6P LL_TIM_OC_GetPolarity 02063 * @param TIMx Timer instance 02064 * @param Channel This parameter can be one of the following values: 02065 * @arg @ref LL_TIM_CHANNEL_CH1 02066 * @arg @ref LL_TIM_CHANNEL_CH1N 02067 * @arg @ref LL_TIM_CHANNEL_CH2 02068 * @arg @ref LL_TIM_CHANNEL_CH2N 02069 * @arg @ref LL_TIM_CHANNEL_CH3 02070 * @arg @ref LL_TIM_CHANNEL_CH3N 02071 * @arg @ref LL_TIM_CHANNEL_CH4 02072 * @arg @ref LL_TIM_CHANNEL_CH5 02073 * @arg @ref LL_TIM_CHANNEL_CH6 02074 * @retval Returned value can be one of the following values: 02075 * @arg @ref LL_TIM_OCPOLARITY_HIGH 02076 * @arg @ref LL_TIM_OCPOLARITY_LOW 02077 */ 02078 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef * TIMx, uint32_t Channel) 02079 { 02080 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02081 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); 02082 } 02083 02084 /** 02085 * @brief Set the IDLE state of an output channel 02086 * @note This function is significant only for the timer instances 02087 * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) 02088 * can be used to check whether or not a timer instance provides 02089 * a break input. 02090 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n 02091 * CR2 OIS2N LL_TIM_OC_SetIdleState\n 02092 * CR2 OIS2 LL_TIM_OC_SetIdleState\n 02093 * CR2 OIS2N LL_TIM_OC_SetIdleState\n 02094 * CR2 OIS3 LL_TIM_OC_SetIdleState\n 02095 * CR2 OIS3N LL_TIM_OC_SetIdleState\n 02096 * CR2 OIS4 LL_TIM_OC_SetIdleState\n 02097 * CR2 OIS5 LL_TIM_OC_SetIdleState\n 02098 * CR2 OIS6 LL_TIM_OC_SetIdleState 02099 * @param TIMx Timer instance 02100 * @param Channel This parameter can be one of the following values: 02101 * @arg @ref LL_TIM_CHANNEL_CH1 02102 * @arg @ref LL_TIM_CHANNEL_CH1N 02103 * @arg @ref LL_TIM_CHANNEL_CH2 02104 * @arg @ref LL_TIM_CHANNEL_CH2N 02105 * @arg @ref LL_TIM_CHANNEL_CH3 02106 * @arg @ref LL_TIM_CHANNEL_CH3N 02107 * @arg @ref LL_TIM_CHANNEL_CH4 02108 * @arg @ref LL_TIM_CHANNEL_CH5 02109 * @arg @ref LL_TIM_CHANNEL_CH6 02110 * @param IdleState This parameter can be one of the following values: 02111 * @arg @ref LL_TIM_OCIDLESTATE_LOW 02112 * @arg @ref LL_TIM_OCIDLESTATE_HIGH 02113 * @retval None 02114 */ 02115 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t IdleState) 02116 { 02117 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02118 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); 02119 } 02120 02121 /** 02122 * @brief Get the IDLE state of an output channel 02123 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n 02124 * CR2 OIS2N LL_TIM_OC_GetIdleState\n 02125 * CR2 OIS2 LL_TIM_OC_GetIdleState\n 02126 * CR2 OIS2N LL_TIM_OC_GetIdleState\n 02127 * CR2 OIS3 LL_TIM_OC_GetIdleState\n 02128 * CR2 OIS3N LL_TIM_OC_GetIdleState\n 02129 * CR2 OIS4 LL_TIM_OC_GetIdleState\n 02130 * CR2 OIS5 LL_TIM_OC_GetIdleState\n 02131 * CR2 OIS6 LL_TIM_OC_GetIdleState 02132 * @param TIMx Timer instance 02133 * @param Channel This parameter can be one of the following values: 02134 * @arg @ref LL_TIM_CHANNEL_CH1 02135 * @arg @ref LL_TIM_CHANNEL_CH1N 02136 * @arg @ref LL_TIM_CHANNEL_CH2 02137 * @arg @ref LL_TIM_CHANNEL_CH2N 02138 * @arg @ref LL_TIM_CHANNEL_CH3 02139 * @arg @ref LL_TIM_CHANNEL_CH3N 02140 * @arg @ref LL_TIM_CHANNEL_CH4 02141 * @arg @ref LL_TIM_CHANNEL_CH5 02142 * @arg @ref LL_TIM_CHANNEL_CH6 02143 * @retval Returned value can be one of the following values: 02144 * @arg @ref LL_TIM_OCIDLESTATE_LOW 02145 * @arg @ref LL_TIM_OCIDLESTATE_HIGH 02146 */ 02147 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef * TIMx, uint32_t Channel) 02148 { 02149 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02150 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); 02151 } 02152 02153 /** 02154 * @brief Enable fast mode for the output channel. 02155 * @note Acts only if the channel is configured in PWM1 or PWM2 mode. 02156 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n 02157 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n 02158 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n 02159 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n 02160 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n 02161 * CCMR3 OC6FE LL_TIM_OC_EnableFast 02162 * @param TIMx Timer instance 02163 * @param Channel This parameter can be one of the following values: 02164 * @arg @ref LL_TIM_CHANNEL_CH1 02165 * @arg @ref LL_TIM_CHANNEL_CH2 02166 * @arg @ref LL_TIM_CHANNEL_CH3 02167 * @arg @ref LL_TIM_CHANNEL_CH4 02168 * @arg @ref LL_TIM_CHANNEL_CH5 02169 * @arg @ref LL_TIM_CHANNEL_CH6 02170 * @retval None 02171 */ 02172 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx, uint32_t Channel) 02173 { 02174 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02175 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02176 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 02177 02178 } 02179 02180 /** 02181 * @brief Disable fast mode for the output channel. 02182 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n 02183 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n 02184 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n 02185 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n 02186 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n 02187 * CCMR3 OC6FE LL_TIM_OC_DisableFast 02188 * @param TIMx Timer instance 02189 * @param Channel This parameter can be one of the following values: 02190 * @arg @ref LL_TIM_CHANNEL_CH1 02191 * @arg @ref LL_TIM_CHANNEL_CH2 02192 * @arg @ref LL_TIM_CHANNEL_CH3 02193 * @arg @ref LL_TIM_CHANNEL_CH4 02194 * @arg @ref LL_TIM_CHANNEL_CH5 02195 * @arg @ref LL_TIM_CHANNEL_CH6 02196 * @retval None 02197 */ 02198 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx, uint32_t Channel) 02199 { 02200 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02201 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02202 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 02203 02204 } 02205 02206 /** 02207 * @brief Indicates whether fast mode is enabled for the output channel. 02208 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n 02209 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n 02210 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n 02211 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n 02212 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n 02213 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast 02214 * @param TIMx Timer instance 02215 * @param Channel This parameter can be one of the following values: 02216 * @arg @ref LL_TIM_CHANNEL_CH1 02217 * @arg @ref LL_TIM_CHANNEL_CH2 02218 * @arg @ref LL_TIM_CHANNEL_CH3 02219 * @arg @ref LL_TIM_CHANNEL_CH4 02220 * @arg @ref LL_TIM_CHANNEL_CH5 02221 * @arg @ref LL_TIM_CHANNEL_CH6 02222 * @retval State of bit (1 or 0). 02223 */ 02224 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx, uint32_t Channel) 02225 { 02226 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02227 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02228 register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; 02229 return (READ_BIT(*pReg, bitfield) == bitfield); 02230 } 02231 02232 /** 02233 * @brief Enable compare register (TIMx_CCRx) preload for the output channel. 02234 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n 02235 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n 02236 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n 02237 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n 02238 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n 02239 * CCMR3 OC6PE LL_TIM_OC_EnablePreload 02240 * @param TIMx Timer instance 02241 * @param Channel This parameter can be one of the following values: 02242 * @arg @ref LL_TIM_CHANNEL_CH1 02243 * @arg @ref LL_TIM_CHANNEL_CH2 02244 * @arg @ref LL_TIM_CHANNEL_CH3 02245 * @arg @ref LL_TIM_CHANNEL_CH4 02246 * @arg @ref LL_TIM_CHANNEL_CH5 02247 * @arg @ref LL_TIM_CHANNEL_CH6 02248 * @retval None 02249 */ 02250 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx, uint32_t Channel) 02251 { 02252 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02253 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02254 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 02255 } 02256 02257 /** 02258 * @brief Disable compare register (TIMx_CCRx) preload for the output channel. 02259 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n 02260 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n 02261 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n 02262 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n 02263 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n 02264 * CCMR3 OC6PE LL_TIM_OC_DisablePreload 02265 * @param TIMx Timer instance 02266 * @param Channel This parameter can be one of the following values: 02267 * @arg @ref LL_TIM_CHANNEL_CH1 02268 * @arg @ref LL_TIM_CHANNEL_CH2 02269 * @arg @ref LL_TIM_CHANNEL_CH3 02270 * @arg @ref LL_TIM_CHANNEL_CH4 02271 * @arg @ref LL_TIM_CHANNEL_CH5 02272 * @arg @ref LL_TIM_CHANNEL_CH6 02273 * @retval None 02274 */ 02275 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx, uint32_t Channel) 02276 { 02277 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02278 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02279 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 02280 } 02281 02282 /** 02283 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. 02284 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n 02285 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n 02286 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n 02287 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n 02288 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n 02289 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload 02290 * @param TIMx Timer instance 02291 * @param Channel This parameter can be one of the following values: 02292 * @arg @ref LL_TIM_CHANNEL_CH1 02293 * @arg @ref LL_TIM_CHANNEL_CH2 02294 * @arg @ref LL_TIM_CHANNEL_CH3 02295 * @arg @ref LL_TIM_CHANNEL_CH4 02296 * @arg @ref LL_TIM_CHANNEL_CH5 02297 * @arg @ref LL_TIM_CHANNEL_CH6 02298 * @retval State of bit (1 or 0). 02299 */ 02300 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx, uint32_t Channel) 02301 { 02302 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02303 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02304 register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; 02305 return (READ_BIT(*pReg, bitfield) == bitfield); 02306 } 02307 02308 /** 02309 * @brief Enable clearing the output channel on an external event. 02310 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. 02311 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 02312 * or not a timer instance can clear the OCxREF signal on an external event. 02313 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n 02314 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n 02315 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n 02316 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n 02317 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n 02318 * CCMR3 OC6CE LL_TIM_OC_EnableClear 02319 * @param TIMx Timer instance 02320 * @param Channel This parameter can be one of the following values: 02321 * @arg @ref LL_TIM_CHANNEL_CH1 02322 * @arg @ref LL_TIM_CHANNEL_CH2 02323 * @arg @ref LL_TIM_CHANNEL_CH3 02324 * @arg @ref LL_TIM_CHANNEL_CH4 02325 * @arg @ref LL_TIM_CHANNEL_CH5 02326 * @arg @ref LL_TIM_CHANNEL_CH6 02327 * @retval None 02328 */ 02329 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx, uint32_t Channel) 02330 { 02331 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02332 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02333 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 02334 } 02335 02336 /** 02337 * @brief Disable clearing the output channel on an external event. 02338 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 02339 * or not a timer instance can clear the OCxREF signal on an external event. 02340 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n 02341 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n 02342 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n 02343 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n 02344 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n 02345 * CCMR3 OC6CE LL_TIM_OC_DisableClear 02346 * @param TIMx Timer instance 02347 * @param Channel This parameter can be one of the following values: 02348 * @arg @ref LL_TIM_CHANNEL_CH1 02349 * @arg @ref LL_TIM_CHANNEL_CH2 02350 * @arg @ref LL_TIM_CHANNEL_CH3 02351 * @arg @ref LL_TIM_CHANNEL_CH4 02352 * @arg @ref LL_TIM_CHANNEL_CH5 02353 * @arg @ref LL_TIM_CHANNEL_CH6 02354 * @retval None 02355 */ 02356 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx, uint32_t Channel) 02357 { 02358 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02359 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02360 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 02361 } 02362 02363 /** 02364 * @brief Indicates clearing the output channel on an external event is enabled for the output channel. 02365 * @note This function enables clearing the output channel on an external event. 02366 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. 02367 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 02368 * or not a timer instance can clear the OCxREF signal on an external event. 02369 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n 02370 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n 02371 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n 02372 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n 02373 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n 02374 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear 02375 * @param TIMx Timer instance 02376 * @param Channel This parameter can be one of the following values: 02377 * @arg @ref LL_TIM_CHANNEL_CH1 02378 * @arg @ref LL_TIM_CHANNEL_CH2 02379 * @arg @ref LL_TIM_CHANNEL_CH3 02380 * @arg @ref LL_TIM_CHANNEL_CH4 02381 * @arg @ref LL_TIM_CHANNEL_CH5 02382 * @arg @ref LL_TIM_CHANNEL_CH6 02383 * @retval State of bit (1 or 0). 02384 */ 02385 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx, uint32_t Channel) 02386 { 02387 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02388 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02389 register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; 02390 return (READ_BIT(*pReg, bitfield) == bitfield); 02391 } 02392 02393 /** 02394 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals). 02395 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 02396 * dead-time insertion feature is supported by a timer instance. 02397 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter 02398 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime 02399 * @param TIMx Timer instance 02400 * @param DeadTime between Min_Data=0 and Max_Data=255 02401 * @retval None 02402 */ 02403 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx, uint32_t DeadTime) 02404 { 02405 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); 02406 } 02407 02408 /** 02409 * @brief Set compare value for output channel 1 (TIMx_CCR1). 02410 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02411 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02412 * whether or not a timer instance supports a 32 bits counter. 02413 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 02414 * output channel 1 is supported by a timer instance. 02415 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 02416 * @param TIMx Timer instance 02417 * @param CompareValue between Min_Data=0 and Max_Data=65535 02418 * @retval None 02419 */ 02420 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx, uint32_t CompareValue) 02421 { 02422 WRITE_REG(TIMx->CCR1, CompareValue); 02423 } 02424 02425 /** 02426 * @brief Set compare value for output channel 2 (TIMx_CCR2). 02427 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02428 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02429 * whether or not a timer instance supports a 32 bits counter. 02430 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 02431 * output channel 2 is supported by a timer instance. 02432 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 02433 * @param TIMx Timer instance 02434 * @param CompareValue between Min_Data=0 and Max_Data=65535 02435 * @retval None 02436 */ 02437 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx, uint32_t CompareValue) 02438 { 02439 WRITE_REG(TIMx->CCR2, CompareValue); 02440 } 02441 02442 /** 02443 * @brief Set compare value for output channel 3 (TIMx_CCR3). 02444 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02445 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02446 * whether or not a timer instance supports a 32 bits counter. 02447 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 02448 * output channel is supported by a timer instance. 02449 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 02450 * @param TIMx Timer instance 02451 * @param CompareValue between Min_Data=0 and Max_Data=65535 02452 * @retval None 02453 */ 02454 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx, uint32_t CompareValue) 02455 { 02456 WRITE_REG(TIMx->CCR3, CompareValue); 02457 } 02458 02459 /** 02460 * @brief Set compare value for output channel 4 (TIMx_CCR4). 02461 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02462 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02463 * whether or not a timer instance supports a 32 bits counter. 02464 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 02465 * output channel 4 is supported by a timer instance. 02466 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 02467 * @param TIMx Timer instance 02468 * @param CompareValue between Min_Data=0 and Max_Data=65535 02469 * @retval None 02470 */ 02471 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx, uint32_t CompareValue) 02472 { 02473 WRITE_REG(TIMx->CCR4, CompareValue); 02474 } 02475 02476 /** 02477 * @brief Set compare value for output channel 5 (TIMx_CCR5). 02478 * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 02479 * output channel 5 is supported by a timer instance. 02480 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 02481 * @param TIMx Timer instance 02482 * @param CompareValue between Min_Data=0 and Max_Data=65535 02483 * @retval None 02484 */ 02485 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx, uint32_t CompareValue) 02486 { 02487 WRITE_REG(TIMx->CCR5, CompareValue); 02488 } 02489 02490 /** 02491 * @brief Set compare value for output channel 6 (TIMx_CCR6). 02492 * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 02493 * output channel 6 is supported by a timer instance. 02494 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 02495 * @param TIMx Timer instance 02496 * @param CompareValue between Min_Data=0 and Max_Data=65535 02497 * @retval None 02498 */ 02499 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx, uint32_t CompareValue) 02500 { 02501 WRITE_REG(TIMx->CCR6, CompareValue); 02502 } 02503 02504 /** 02505 * @brief Get compare value (TIMx_CCR1) set for output channel 1. 02506 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02507 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02508 * whether or not a timer instance supports a 32 bits counter. 02509 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 02510 * output channel 1 is supported by a timer instance. 02511 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 02512 * @param TIMx Timer instance 02513 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02514 */ 02515 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef * TIMx) 02516 { 02517 return (uint32_t)(READ_REG(TIMx->CCR1)); 02518 } 02519 02520 /** 02521 * @brief Get compare value (TIMx_CCR2) set for output channel 2. 02522 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02523 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02524 * whether or not a timer instance supports a 32 bits counter. 02525 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 02526 * output channel 2 is supported by a timer instance. 02527 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 02528 * @param TIMx Timer instance 02529 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02530 */ 02531 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef * TIMx) 02532 { 02533 return (uint32_t)(READ_REG(TIMx->CCR2)); 02534 } 02535 02536 /** 02537 * @brief Get compare value (TIMx_CCR3) set for output channel 3. 02538 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02539 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02540 * whether or not a timer instance supports a 32 bits counter. 02541 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 02542 * output channel 3 is supported by a timer instance. 02543 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 02544 * @param TIMx Timer instance 02545 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02546 */ 02547 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef * TIMx) 02548 { 02549 return (uint32_t)(READ_REG(TIMx->CCR3)); 02550 } 02551 02552 /** 02553 * @brief Get compare value (TIMx_CCR4) set for output channel 4. 02554 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02555 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02556 * whether or not a timer instance supports a 32 bits counter. 02557 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 02558 * output channel 4 is supported by a timer instance. 02559 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 02560 * @param TIMx Timer instance 02561 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02562 */ 02563 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef * TIMx) 02564 { 02565 return (uint32_t)(READ_REG(TIMx->CCR4)); 02566 } 02567 02568 /** 02569 * @brief Get compare value (TIMx_CCR5) set for output channel 5. 02570 * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 02571 * output channel 5 is supported by a timer instance. 02572 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 02573 * @param TIMx Timer instance 02574 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02575 */ 02576 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef * TIMx) 02577 { 02578 return (uint32_t)(READ_REG(TIMx->CCR5)); 02579 } 02580 02581 /** 02582 * @brief Get compare value (TIMx_CCR6) set for output channel 6. 02583 * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 02584 * output channel 6 is supported by a timer instance. 02585 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 02586 * @param TIMx Timer instance 02587 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02588 */ 02589 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef * TIMx) 02590 { 02591 return (uint32_t)(READ_REG(TIMx->CCR6)); 02592 } 02593 02594 /** 02595 * @brief Select on which reference signal the OC5REF is combined to. 02596 * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check 02597 * whether or not a timer instance supports the combined 3-phase PWM mode. 02598 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n 02599 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n 02600 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels 02601 * @param TIMx Timer instance 02602 * @param GroupCH5 This parameter can be one of the following values: 02603 * @arg @ref LL_TIM_GROUPCH5_NONE 02604 * @arg @ref LL_TIM_GROUPCH5_OC1REFC 02605 * @arg @ref LL_TIM_GROUPCH5_OC2REFC 02606 * @arg @ref LL_TIM_GROUPCH5_OC3REFC 02607 * @retval None 02608 */ 02609 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx, uint32_t GroupCH5) 02610 { 02611 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5); 02612 } 02613 02614 /** 02615 * @} 02616 */ 02617 02618 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration 02619 * @{ 02620 */ 02621 /** 02622 * @brief Configure input channel. 02623 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n 02624 * CCMR1 IC1PSC LL_TIM_IC_Config\n 02625 * CCMR1 IC1F LL_TIM_IC_Config\n 02626 * CCMR1 CC2S LL_TIM_IC_Config\n 02627 * CCMR1 IC2PSC LL_TIM_IC_Config\n 02628 * CCMR1 IC2F LL_TIM_IC_Config\n 02629 * CCMR2 CC3S LL_TIM_IC_Config\n 02630 * CCMR2 IC3PSC LL_TIM_IC_Config\n 02631 * CCMR2 IC3F LL_TIM_IC_Config\n 02632 * CCMR2 CC4S LL_TIM_IC_Config\n 02633 * CCMR2 IC4PSC LL_TIM_IC_Config\n 02634 * CCMR2 IC4F LL_TIM_IC_Config\n 02635 * CCER CC1P LL_TIM_IC_Config\n 02636 * CCER CC1NP LL_TIM_IC_Config\n 02637 * CCER CC2P LL_TIM_IC_Config\n 02638 * CCER CC2NP LL_TIM_IC_Config\n 02639 * CCER CC3P LL_TIM_IC_Config\n 02640 * CCER CC3NP LL_TIM_IC_Config\n 02641 * CCER CC4P LL_TIM_IC_Config\n 02642 * CCER CC4NP LL_TIM_IC_Config 02643 * @param TIMx Timer instance 02644 * @param Channel This parameter can be one of the following values: 02645 * @arg @ref LL_TIM_CHANNEL_CH1 02646 * @arg @ref LL_TIM_CHANNEL_CH2 02647 * @arg @ref LL_TIM_CHANNEL_CH3 02648 * @arg @ref LL_TIM_CHANNEL_CH4 02649 * @param Configuration This parameter must be a combination of all the following values: 02650 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC 02651 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 02652 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 02653 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE 02654 * @retval None 02655 */ 02656 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Configuration) 02657 { 02658 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02659 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02660 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); 02661 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); 02662 } 02663 02664 /** 02665 * @brief Set the active input. 02666 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n 02667 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n 02668 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n 02669 * CCMR2 CC4S LL_TIM_IC_SetActiveInput 02670 * @param TIMx Timer instance 02671 * @param Channel This parameter can be one of the following values: 02672 * @arg @ref LL_TIM_CHANNEL_CH1 02673 * @arg @ref LL_TIM_CHANNEL_CH2 02674 * @arg @ref LL_TIM_CHANNEL_CH3 02675 * @arg @ref LL_TIM_CHANNEL_CH4 02676 * @param ICActiveInput This parameter can be one of the following values: 02677 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 02678 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 02679 * @arg @ref LL_TIM_ACTIVEINPUT_TRC 02680 * @retval None 02681 */ 02682 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICActiveInput) 02683 { 02684 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02685 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02686 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); 02687 } 02688 02689 /** 02690 * @brief Get the current active input. 02691 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n 02692 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n 02693 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n 02694 * CCMR2 CC4S LL_TIM_IC_GetActiveInput 02695 * @param TIMx Timer instance 02696 * @param Channel This parameter can be one of the following values: 02697 * @arg @ref LL_TIM_CHANNEL_CH1 02698 * @arg @ref LL_TIM_CHANNEL_CH2 02699 * @arg @ref LL_TIM_CHANNEL_CH3 02700 * @arg @ref LL_TIM_CHANNEL_CH4 02701 * @retval Returned value can be one of the following values: 02702 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 02703 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 02704 * @arg @ref LL_TIM_ACTIVEINPUT_TRC 02705 */ 02706 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef * TIMx, uint32_t Channel) 02707 { 02708 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02709 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02710 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 02711 } 02712 02713 /** 02714 * @brief Set the prescaler of input channel. 02715 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n 02716 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n 02717 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n 02718 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler 02719 * @param TIMx Timer instance 02720 * @param Channel This parameter can be one of the following values: 02721 * @arg @ref LL_TIM_CHANNEL_CH1 02722 * @arg @ref LL_TIM_CHANNEL_CH2 02723 * @arg @ref LL_TIM_CHANNEL_CH3 02724 * @arg @ref LL_TIM_CHANNEL_CH4 02725 * @param ICPrescaler This parameter can be one of the following values: 02726 * @arg @ref LL_TIM_ICPSC_DIV1 02727 * @arg @ref LL_TIM_ICPSC_DIV2 02728 * @arg @ref LL_TIM_ICPSC_DIV4 02729 * @arg @ref LL_TIM_ICPSC_DIV8 02730 * @retval None 02731 */ 02732 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICPrescaler) 02733 { 02734 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02735 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02736 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); 02737 } 02738 02739 /** 02740 * @brief Get the current prescaler value acting on an input channel. 02741 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n 02742 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n 02743 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n 02744 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler 02745 * @param TIMx Timer instance 02746 * @param Channel This parameter can be one of the following values: 02747 * @arg @ref LL_TIM_CHANNEL_CH1 02748 * @arg @ref LL_TIM_CHANNEL_CH2 02749 * @arg @ref LL_TIM_CHANNEL_CH3 02750 * @arg @ref LL_TIM_CHANNEL_CH4 02751 * @retval Returned value can be one of the following values: 02752 * @arg @ref LL_TIM_ICPSC_DIV1 02753 * @arg @ref LL_TIM_ICPSC_DIV2 02754 * @arg @ref LL_TIM_ICPSC_DIV4 02755 * @arg @ref LL_TIM_ICPSC_DIV8 02756 */ 02757 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef * TIMx, uint32_t Channel) 02758 { 02759 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02760 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02761 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 02762 } 02763 02764 /** 02765 * @brief Set the input filter duration. 02766 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n 02767 * CCMR1 IC2F LL_TIM_IC_SetFilter\n 02768 * CCMR2 IC3F LL_TIM_IC_SetFilter\n 02769 * CCMR2 IC4F LL_TIM_IC_SetFilter 02770 * @param TIMx Timer instance 02771 * @param Channel This parameter can be one of the following values: 02772 * @arg @ref LL_TIM_CHANNEL_CH1 02773 * @arg @ref LL_TIM_CHANNEL_CH2 02774 * @arg @ref LL_TIM_CHANNEL_CH3 02775 * @arg @ref LL_TIM_CHANNEL_CH4 02776 * @param ICFilter This parameter can be one of the following values: 02777 * @arg @ref LL_TIM_IC_FILTER_FDIV1 02778 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 02779 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 02780 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 02781 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 02782 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 02783 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 02784 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 02785 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 02786 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 02787 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 02788 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 02789 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 02790 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 02791 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 02792 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 02793 * @retval None 02794 */ 02795 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICFilter) 02796 { 02797 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02798 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02799 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); 02800 } 02801 02802 /** 02803 * @brief Get the input filter duration. 02804 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n 02805 * CCMR1 IC2F LL_TIM_IC_GetFilter\n 02806 * CCMR2 IC3F LL_TIM_IC_GetFilter\n 02807 * CCMR2 IC4F LL_TIM_IC_GetFilter 02808 * @param TIMx Timer instance 02809 * @param Channel This parameter can be one of the following values: 02810 * @arg @ref LL_TIM_CHANNEL_CH1 02811 * @arg @ref LL_TIM_CHANNEL_CH2 02812 * @arg @ref LL_TIM_CHANNEL_CH3 02813 * @arg @ref LL_TIM_CHANNEL_CH4 02814 * @retval Returned value can be one of the following values: 02815 * @arg @ref LL_TIM_IC_FILTER_FDIV1 02816 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 02817 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 02818 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 02819 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 02820 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 02821 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 02822 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 02823 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 02824 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 02825 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 02826 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 02827 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 02828 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 02829 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 02830 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 02831 */ 02832 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef * TIMx, uint32_t Channel) 02833 { 02834 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02835 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel])); 02836 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U ); 02837 } 02838 02839 /** 02840 * @brief Set the input channel polarity. 02841 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n 02842 * CCER CC1NP LL_TIM_IC_SetPolarity\n 02843 * CCER CC2P LL_TIM_IC_SetPolarity\n 02844 * CCER CC2NP LL_TIM_IC_SetPolarity\n 02845 * CCER CC3P LL_TIM_IC_SetPolarity\n 02846 * CCER CC3NP LL_TIM_IC_SetPolarity\n 02847 * CCER CC4P LL_TIM_IC_SetPolarity\n 02848 * CCER CC4NP LL_TIM_IC_SetPolarity 02849 * @param TIMx Timer instance 02850 * @param Channel This parameter can be one of the following values: 02851 * @arg @ref LL_TIM_CHANNEL_CH1 02852 * @arg @ref LL_TIM_CHANNEL_CH2 02853 * @arg @ref LL_TIM_CHANNEL_CH3 02854 * @arg @ref LL_TIM_CHANNEL_CH4 02855 * @param ICPolarity This parameter can be one of the following values: 02856 * @arg @ref LL_TIM_IC_POLARITY_RISING 02857 * @arg @ref LL_TIM_IC_POLARITY_FALLING 02858 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 02859 * @retval None 02860 */ 02861 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICPolarity) 02862 { 02863 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02864 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), ICPolarity << SHIFT_TAB_CCxP[iChannel]); 02865 } 02866 02867 /** 02868 * @brief Get the current input channel polarity. 02869 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n 02870 * CCER CC1NP LL_TIM_IC_GetPolarity\n 02871 * CCER CC2P LL_TIM_IC_GetPolarity\n 02872 * CCER CC2NP LL_TIM_IC_GetPolarity\n 02873 * CCER CC3P LL_TIM_IC_GetPolarity\n 02874 * CCER CC3NP LL_TIM_IC_GetPolarity\n 02875 * CCER CC4P LL_TIM_IC_GetPolarity\n 02876 * CCER CC4NP LL_TIM_IC_GetPolarity 02877 * @param TIMx Timer instance 02878 * @param Channel This parameter can be one of the following values: 02879 * @arg @ref LL_TIM_CHANNEL_CH1 02880 * @arg @ref LL_TIM_CHANNEL_CH2 02881 * @arg @ref LL_TIM_CHANNEL_CH3 02882 * @arg @ref LL_TIM_CHANNEL_CH4 02883 * @retval Returned value can be one of the following values: 02884 * @arg @ref LL_TIM_IC_POLARITY_RISING 02885 * @arg @ref LL_TIM_IC_POLARITY_FALLING 02886 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 02887 */ 02888 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef * TIMx, uint32_t Channel) 02889 { 02890 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02891 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); 02892 } 02893 02894 /** 02895 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). 02896 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 02897 * a timer instance provides an XOR input. 02898 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination 02899 * @param TIMx Timer instance 02900 * @retval None 02901 */ 02902 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx) 02903 { 02904 SET_BIT(TIMx->CR2, TIM_CR2_TI1S); 02905 } 02906 02907 /** 02908 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. 02909 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 02910 * a timer instance provides an XOR input. 02911 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination 02912 * @param TIMx Timer instance 02913 * @retval None 02914 */ 02915 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx) 02916 { 02917 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); 02918 } 02919 02920 /** 02921 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. 02922 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 02923 * a timer instance provides an XOR input. 02924 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination 02925 * @param TIMx Timer instance 02926 * @retval State of bit (1 or 0). 02927 */ 02928 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx) 02929 { 02930 return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)); 02931 } 02932 02933 /** 02934 * @brief Get captured value for input channel 1. 02935 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 02936 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02937 * whether or not a timer instance supports a 32 bits counter. 02938 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 02939 * input channel 1 is supported by a timer instance. 02940 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 02941 * @param TIMx Timer instance 02942 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 02943 */ 02944 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef * TIMx) 02945 { 02946 return (uint32_t)(READ_REG(TIMx->CCR1)); 02947 } 02948 02949 /** 02950 * @brief Get captured value for input channel 2. 02951 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 02952 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02953 * whether or not a timer instance supports a 32 bits counter. 02954 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 02955 * input channel 2 is supported by a timer instance. 02956 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 02957 * @param TIMx Timer instance 02958 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 02959 */ 02960 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef * TIMx) 02961 { 02962 return (uint32_t)(READ_REG(TIMx->CCR2)); 02963 } 02964 02965 /** 02966 * @brief Get captured value for input channel 3. 02967 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 02968 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02969 * whether or not a timer instance supports a 32 bits counter. 02970 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 02971 * input channel 3 is supported by a timer instance. 02972 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 02973 * @param TIMx Timer instance 02974 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 02975 */ 02976 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef * TIMx) 02977 { 02978 return (uint32_t)(READ_REG(TIMx->CCR3)); 02979 } 02980 02981 /** 02982 * @brief Get captured value for input channel 4. 02983 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 02984 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02985 * whether or not a timer instance supports a 32 bits counter. 02986 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 02987 * input channel 4 is supported by a timer instance. 02988 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 02989 * @param TIMx Timer instance 02990 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 02991 */ 02992 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef * TIMx) 02993 { 02994 return (uint32_t)(READ_REG(TIMx->CCR4)); 02995 } 02996 02997 /** 02998 * @} 02999 */ 03000 03001 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection 03002 * @{ 03003 */ 03004 /** 03005 * @brief Enable external clock mode 2. 03006 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. 03007 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 03008 * whether or not a timer instance supports external clock mode2. 03009 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock 03010 * @param TIMx Timer instance 03011 * @retval None 03012 */ 03013 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx) 03014 { 03015 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); 03016 } 03017 03018 /** 03019 * @brief Disable external clock mode 2. 03020 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 03021 * whether or not a timer instance supports external clock mode2. 03022 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock 03023 * @param TIMx Timer instance 03024 * @retval None 03025 */ 03026 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx) 03027 { 03028 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); 03029 } 03030 03031 /** 03032 * @brief Indicate whether external clock mode 2 is enabled. 03033 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 03034 * whether or not a timer instance supports external clock mode2. 03035 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock 03036 * @param TIMx Timer instance 03037 * @retval State of bit (1 or 0). 03038 */ 03039 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef * TIMx) 03040 { 03041 return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)); 03042 } 03043 03044 /** 03045 * @brief Set the clock source of the counter clock. 03046 * @note when selected clock source is external clock mode 1, the timer input 03047 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() 03048 * function. This timer input must be configured by calling 03049 * the @ref LL_TIM_IC_Config() function. 03050 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check 03051 * whether or not a timer instance supports external clock mode1. 03052 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 03053 * whether or not a timer instance supports external clock mode2. 03054 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n 03055 * SMCR ECE LL_TIM_SetClockSource 03056 * @param TIMx Timer instance 03057 * @param ClockSource This parameter can be one of the following values: 03058 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL 03059 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 03060 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 03061 * @retval None 03062 */ 03063 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef * TIMx, uint32_t ClockSource) 03064 { 03065 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); 03066 } 03067 03068 /** 03069 * @brief Set the encoder interface mode. 03070 * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check 03071 * whether or not a timer instance supports the encoder mode. 03072 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode 03073 * @param TIMx Timer instance 03074 * @param EncoderMode This parameter can be one of the following values: 03075 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 03076 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 03077 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 03078 * @retval None 03079 */ 03080 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx, uint32_t EncoderMode) 03081 { 03082 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); 03083 } 03084 03085 /** 03086 * @} 03087 */ 03088 03089 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration 03090 * @{ 03091 */ 03092 /** 03093 * @brief Set the trigger output (TRGO) used for timer synchronization . 03094 * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check 03095 * whether or not a timer instance can operate as a master timer. 03096 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput 03097 * @param TIMx Timer instance 03098 * @param TimerSynchronization This parameter can be one of the following values: 03099 * @arg @ref LL_TIM_TRGO_RESET 03100 * @arg @ref LL_TIM_TRGO_ENABLE 03101 * @arg @ref LL_TIM_TRGO_UPDATE 03102 * @arg @ref LL_TIM_TRGO_CC1IF 03103 * @arg @ref LL_TIM_TRGO_OC1REF 03104 * @arg @ref LL_TIM_TRGO_OC2REF 03105 * @arg @ref LL_TIM_TRGO_OC3REF 03106 * @arg @ref LL_TIM_TRGO_OC4REF 03107 * @retval None 03108 */ 03109 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx, uint32_t TimerSynchronization) 03110 { 03111 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); 03112 } 03113 03114 /** 03115 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . 03116 * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check 03117 * whether or not a timer instance can be used for ADC synchronization. 03118 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 03119 * @param TIMx Timer Instance 03120 * @param ADCSynchronization This parameter can be one of the following values: 03121 * @arg @ref LL_TIM_TRGO2_RESET 03122 * @arg @ref LL_TIM_TRGO2_ENABLE 03123 * @arg @ref LL_TIM_TRGO2_UPDATE 03124 * @arg @ref LL_TIM_TRGO2_CC1F 03125 * @arg @ref LL_TIM_TRGO2_OC1 03126 * @arg @ref LL_TIM_TRGO2_OC2 03127 * @arg @ref LL_TIM_TRGO2_OC3 03128 * @arg @ref LL_TIM_TRGO2_OC4 03129 * @arg @ref LL_TIM_TRGO2_OC5 03130 * @arg @ref LL_TIM_TRGO2_OC6 03131 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING 03132 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING 03133 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING 03134 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING 03135 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING 03136 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING 03137 * @retval None 03138 */ 03139 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx, uint32_t ADCSynchronization) 03140 { 03141 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); 03142 } 03143 03144 /** 03145 * @brief Set the synchronization mode of a slave timer. 03146 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03147 * a timer instance can operate as a slave timer. 03148 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode 03149 * @param TIMx Timer instance 03150 * @param SlaveMode This parameter can be one of the following values: 03151 * @arg @ref LL_TIM_SLAVEMODE_DISABLED 03152 * @arg @ref LL_TIM_SLAVEMODE_RESET 03153 * @arg @ref LL_TIM_SLAVEMODE_GATED 03154 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER 03155 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER 03156 * @retval None 03157 */ 03158 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx, uint32_t SlaveMode) 03159 { 03160 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); 03161 } 03162 03163 /** 03164 * @brief Set the selects the trigger input to be used to synchronize the counter. 03165 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03166 * a timer instance can operate as a slave timer. 03167 * @rmtoll SMCR TS LL_TIM_SetTriggerInput 03168 * @param TIMx Timer instance 03169 * @param TriggerInput This parameter can be one of the following values: 03170 * @arg @ref LL_TIM_TS_ITR0 03171 * @arg @ref LL_TIM_TS_ITR1 03172 * @arg @ref LL_TIM_TS_ITR2 03173 * @arg @ref LL_TIM_TS_ITR3 03174 * @arg @ref LL_TIM_TS_TI1F_ED 03175 * @arg @ref LL_TIM_TS_TI1FP1 03176 * @arg @ref LL_TIM_TS_TI2FP2 03177 * @arg @ref LL_TIM_TS_ETRF 03178 * @retval None 03179 */ 03180 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx, uint32_t TriggerInput) 03181 { 03182 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); 03183 } 03184 03185 /** 03186 * @brief Enable the Master/Slave mode. 03187 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03188 * a timer instance can operate as a slave timer. 03189 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode 03190 * @param TIMx Timer instance 03191 * @retval None 03192 */ 03193 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx) 03194 { 03195 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); 03196 } 03197 03198 /** 03199 * @brief Disable the Master/Slave mode. 03200 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03201 * a timer instance can operate as a slave timer. 03202 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode 03203 * @param TIMx Timer instance 03204 * @retval None 03205 */ 03206 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx) 03207 { 03208 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); 03209 } 03210 03211 /** 03212 * @brief Indicates whether the Master/Slave mode is enabled. 03213 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03214 * a timer instance can operate as a slave timer. 03215 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode 03216 * @param TIMx Timer instance 03217 * @retval State of bit (1 or 0). 03218 */ 03219 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef * TIMx) 03220 { 03221 return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)); 03222 } 03223 03224 /** 03225 * @brief Configure the external trigger (ETR) input. 03226 * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not 03227 * a timer instance provides an external trigger input. 03228 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n 03229 * SMCR ETPS LL_TIM_ConfigETR\n 03230 * SMCR ETF LL_TIM_ConfigETR 03231 * @param TIMx Timer instance 03232 * @param ETRPolarity This parameter can be one of the following values: 03233 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED 03234 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED 03235 * @param ETRPrescaler This parameter can be one of the following values: 03236 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 03237 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 03238 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 03239 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 03240 * @param ETRFilter This parameter can be one of the following values: 03241 * @arg @ref LL_TIM_ETR_FILTER_FDIV1 03242 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 03243 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 03244 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 03245 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 03246 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 03247 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 03248 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 03249 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 03250 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 03251 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 03252 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 03253 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 03254 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 03255 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 03256 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 03257 * @retval None 03258 */ 03259 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef * TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter) 03260 { 03261 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); 03262 } 03263 03264 /** 03265 * @brief Select the external trigger (ETR) input source. 03266 * @note Macro @ref IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or 03267 * not a timer instance supports ETR source selection. 03268 * @rmtoll OR2 ETRSEL LL_TIM_SetETRSource 03269 * @param TIMx Timer instance 03270 * @param ETRSource This parameter can be one of the following values: 03271 * @arg @ref LL_TIM_ETRSOURCE_LEGACY 03272 * @arg @ref LL_TIM_ETRSOURCE_COMP1 03273 * @arg @ref LL_TIM_ETRSOURCE_COMP2 03274 * @retval None 03275 */ 03276 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef * TIMx, uint32_t ETRSource) 03277 { 03278 03279 MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource); 03280 } 03281 03282 /** 03283 * @} 03284 */ 03285 03286 /** @defgroup TIM_LL_EF_Break_Function Break function configuration 03287 * @{ 03288 */ 03289 /** 03290 * @brief Enable the break function. 03291 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03292 * a timer instance provides a break input. 03293 * @rmtoll BDTR BKE LL_TIM_EnableBRK 03294 * @param TIMx Timer instance 03295 * @retval None 03296 */ 03297 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef * TIMx) 03298 { 03299 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); 03300 } 03301 03302 /** 03303 * @brief Disable the break function. 03304 * @rmtoll BDTR BKE LL_TIM_DisableBRK 03305 * @param TIMx Timer instance 03306 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03307 * a timer instance provides a break input. 03308 * @retval None 03309 */ 03310 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef * TIMx) 03311 { 03312 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); 03313 } 03314 03315 /** 03316 * @brief Configure the break input. 03317 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03318 * a timer instance provides a break input. 03319 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n 03320 * BDTR BKF LL_TIM_ConfigBRK 03321 * @param TIMx Timer instance 03322 * @param BreakPolarity This parameter can be one of the following values: 03323 * @arg @ref LL_TIM_BREAK_POLARITY_LOW 03324 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH 03325 * @param BreakFilter This parameter can be one of the following values: 03326 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 03327 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 03328 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 03329 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 03330 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 03331 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 03332 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 03333 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 03334 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 03335 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 03336 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 03337 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 03338 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 03339 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 03340 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 03341 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 03342 * @retval None 03343 */ 03344 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef * TIMx, uint32_t BreakPolarity, uint32_t BreakFilter) 03345 { 03346 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); 03347 } 03348 03349 /** 03350 * @brief Enable the break 2 function. 03351 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 03352 * a timer instance provides a second break input. 03353 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 03354 * @param TIMx Timer instance 03355 * @retval None 03356 */ 03357 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef * TIMx) 03358 { 03359 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 03360 } 03361 03362 /** 03363 * @brief Disable the break 2 function. 03364 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 03365 * a timer instance provides a second break input. 03366 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 03367 * @param TIMx Timer instance 03368 * @retval None 03369 */ 03370 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef * TIMx) 03371 { 03372 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 03373 } 03374 03375 /** 03376 * @brief Configure the break 2 input. 03377 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 03378 * a timer instance provides a second break input. 03379 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n 03380 * BDTR BK2F LL_TIM_ConfigBRK2 03381 * @param TIMx Timer instance 03382 * @param Break2Polarity This parameter can be one of the following values: 03383 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW 03384 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH 03385 * @param Break2Filter This parameter can be one of the following values: 03386 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 03387 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 03388 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 03389 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 03390 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 03391 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 03392 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 03393 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 03394 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 03395 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 03396 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 03397 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 03398 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 03399 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 03400 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 03401 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 03402 * @retval None 03403 */ 03404 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx, uint32_t Break2Polarity, uint32_t Break2Filter) 03405 { 03406 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); 03407 } 03408 03409 /** 03410 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. 03411 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03412 * a timer instance provides a break input. 03413 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n 03414 * BDTR OSSR LL_TIM_SetOffStates 03415 * @param TIMx Timer instance 03416 * @param OffStateIdle This parameter can be one of the following values: 03417 * @arg @ref LL_TIM_OSSI_DISABLE 03418 * @arg @ref LL_TIM_OSSI_ENABLE 03419 * @param OffStateRun This parameter can be one of the following values: 03420 * @arg @ref LL_TIM_OSSR_DISABLE 03421 * @arg @ref LL_TIM_OSSR_ENABLE 03422 * @retval None 03423 */ 03424 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef * TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) 03425 { 03426 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); 03427 } 03428 03429 /** 03430 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). 03431 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03432 * a timer instance provides a break input. 03433 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput 03434 * @param TIMx Timer instance 03435 * @retval None 03436 */ 03437 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx) 03438 { 03439 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); 03440 } 03441 03442 /** 03443 * @brief Disable automatic output (MOE can be set only by software). 03444 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03445 * a timer instance provides a break input. 03446 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput 03447 * @param TIMx Timer instance 03448 * @retval None 03449 */ 03450 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx) 03451 { 03452 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); 03453 } 03454 03455 /** 03456 * @brief Indicate whether automatic output is enabled. 03457 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03458 * a timer instance provides a break input. 03459 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput 03460 * @param TIMx Timer instance 03461 * @retval State of bit (1 or 0). 03462 */ 03463 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef * TIMx) 03464 { 03465 return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)); 03466 } 03467 03468 /** 03469 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). 03470 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 03471 * software and is reset in case of break or break2 event 03472 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03473 * a timer instance provides a break input. 03474 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs 03475 * @param TIMx Timer instance 03476 * @retval None 03477 */ 03478 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx) 03479 { 03480 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); 03481 } 03482 03483 /** 03484 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). 03485 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 03486 * software and is reset in case of break or break2 event. 03487 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03488 * a timer instance provides a break input. 03489 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs 03490 * @param TIMx Timer instance 03491 * @retval None 03492 */ 03493 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx) 03494 { 03495 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); 03496 } 03497 03498 /** 03499 * @brief Indicates whether outputs are enabled. 03500 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03501 * a timer instance provides a break input. 03502 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs 03503 * @param TIMx Timer instance 03504 * @retval State of bit (1 or 0). 03505 */ 03506 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef * TIMx) 03507 { 03508 return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)); 03509 } 03510 03511 /** 03512 * @brief Enable the signals connected to the designated timer break input. 03513 * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 03514 * or not a timer instance allows for break input selection. 03515 * @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n 03516 * OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n 03517 * OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n 03518 * OR2 BKDFBK0E LL_TIM_EnableBreakInputSource\n 03519 * OR3 BKINE LL_TIM_EnableBreakInputSource\n 03520 * OR3 BKCMP1E LL_TIM_EnableBreakInputSource\n 03521 * OR3 BKCMP2E LL_TIM_EnableBreakInputSource\n 03522 * OR3 BKDFBK0E LL_TIM_EnableBreakInputSource 03523 * @param TIMx Timer instance 03524 * @param BreakInput This parameter can be one of the following values: 03525 * @arg @ref LL_TIM_BREAK_INPUT_BKIN 03526 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 03527 * @param Source This parameter can be one of the following values: 03528 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 03529 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 03530 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 03531 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 03532 * @retval None 03533 */ 03534 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx, uint32_t BreakInput, uint32_t Source) 03535 { 03536 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2)+ BreakInput)); 03537 SET_BIT(*pReg , Source); 03538 } 03539 03540 /** 03541 * @brief Disable the signals connected to the designated timer break input. 03542 * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 03543 * or not a timer instance allows for break input selection. 03544 * @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n 03545 * OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n 03546 * OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n 03547 * OR2 BKDFBK0E LL_TIM_DisableBreakInputSource\n 03548 * OR3 BKINE LL_TIM_DisableBreakInputSource\n 03549 * OR3 BKCMP1E LL_TIM_DisableBreakInputSource\n 03550 * OR3 BKCMP2E LL_TIM_DisableBreakInputSource\n 03551 * OR3 BKDFBK0E LL_TIM_DisableBreakInputSource 03552 * @param TIMx Timer instance 03553 * @param BreakInput This parameter can be one of the following values: 03554 * @arg @ref LL_TIM_BREAK_INPUT_BKIN 03555 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 03556 * @param Source This parameter can be one of the following values: 03557 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 03558 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 03559 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 03560 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 03561 * @retval None 03562 */ 03563 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx, uint32_t BreakInput, uint32_t Source) 03564 { 03565 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2)+ BreakInput)); 03566 CLEAR_BIT(*pReg, Source); 03567 } 03568 03569 /** 03570 * @brief Set the polarity of the break signal for the timer break input. 03571 * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 03572 * or not a timer instance allows for break input selection. 03573 * @rmtoll OR2 BKINE LL_TIM_SetBreakInputSourcePolarity\n 03574 * OR2 BKCMP1E LL_TIM_SetBreakInputSourcePolarity\n 03575 * OR2 BKCMP2E LL_TIM_SetBreakInputSourcePolarity\n 03576 * OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n 03577 * OR3 BKINE LL_TIM_SetBreakInputSourcePolarity\n 03578 * OR3 BKCMP1E LL_TIM_SetBreakInputSourcePolarity\n 03579 * OR3 BKCMP2E LL_TIM_SetBreakInputSourcePolarity\n 03580 * OR3 BKINP LL_TIM_SetBreakInputSourcePolarity 03581 * @param TIMx Timer instance 03582 * @param BreakInput This parameter can be one of the following values: 03583 * @arg @ref LL_TIM_BREAK_INPUT_BKIN 03584 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 03585 * @param Source This parameter can be one of the following values: 03586 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 03587 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 03588 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 03589 * @param Polarity This parameter can be one of the following values: 03590 * @arg @ref LL_TIM_BKIN_POLARITY_LOW 03591 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH 03592 * @retval None 03593 */ 03594 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity) 03595 { 03596 register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2)+ BreakInput)); 03597 MODIFY_REG(*pReg, (TIMx_OR2_BKINP << (POSITION_VAL(Source))) , (Polarity << (POSITION_VAL(Source)))); 03598 } 03599 03600 /** 03601 * @} 03602 */ 03603 03604 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration 03605 * @{ 03606 */ 03607 /** 03608 * @brief Configures the timer DMA burst feature. 03609 * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or 03610 * not a timer instance supports the DMA burst mode. 03611 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n 03612 * DCR DBA LL_TIM_ConfigDMABurst 03613 * @param TIMx Timer instance 03614 * @param DMABurstBaseAddress This parameter can be one of the following values: 03615 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 03616 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 03617 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR 03618 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER 03619 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR 03620 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR 03621 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 03622 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 03623 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER 03624 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT 03625 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC 03626 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR 03627 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR 03628 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 03629 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 03630 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 03631 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 03632 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR 03633 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 03634 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 03635 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 03636 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1 03637 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2 03638 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3 03639 * @param DMABurstLength This parameter can be one of the following values: 03640 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER 03641 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS 03642 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS 03643 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS 03644 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS 03645 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS 03646 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS 03647 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS 03648 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS 03649 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS 03650 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS 03651 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS 03652 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS 03653 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS 03654 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS 03655 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS 03656 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS 03657 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS 03658 * @retval None 03659 */ 03660 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) 03661 { 03662 MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength); 03663 } 03664 03665 /** 03666 * @} 03667 */ 03668 03669 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping 03670 * @{ 03671 */ 03672 /** 03673 * @brief Remap TIM inputs (input channel, internal/external triggers). 03674 * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not 03675 * a some timer inputs can be remapped. 03676 * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n 03677 * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n 03678 * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n 03679 * TIM8_OR1 ETR_ADC2_RMP LL_TIM_SetRemap\n 03680 * TIM8_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n 03681 * TIM8_OR1 TI1_RMP LL_TIM_SetRemap\n 03682 * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n 03683 * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n 03684 * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n 03685 * TIM3_OR1 TI1_RMP LL_TIM_SetRemap\n 03686 * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n 03687 * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n 03688 * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n 03689 * TIM17_OR1 TI1_RMP LL_TIM_SetRemap 03690 * @param TIMx Timer instance 03691 * @param Remap Remap param depends on the TIMx. Description available only 03692 * in CHM version of the User Manual (not in .pdf). 03693 * Otherwise see Reference Manual description of OR registers. 03694 * 03695 * Below description summarizes "Timer Instance" and "Remap" param combinations: 03696 * 03697 * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where 03698 * 03699 * . . ADC1_RMP can be one of the following values 03700 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC 03701 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 03702 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 03703 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 03704 * 03705 * . . ADC3_RMP can be one of the following values 03706 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC 03707 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 03708 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 03709 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 03710 * 03711 * . . TI1_RMP can be one of the following values 03712 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO 03713 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 03714 * 03715 * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where 03716 * 03717 * ITR1_RMP can be one of the following values 03718 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO 03719 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF 03720 * 03721 * . . ETR1_RMP can be one of the following values 03722 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO 03723 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE 03724 * 03725 * . . TI4_RMP can be one of the following values 03726 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO 03727 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 03728 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 03729 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 03730 * 03731 * TIM3: one of the following values 03732 * 03733 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO 03734 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1 03735 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2 03736 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 03737 * 03738 * TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where 03739 * 03740 * . . ADC1_RMP can be one of the following values 03741 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC 03742 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 03743 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 03744 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 03745 * 03746 * . . ADC3_RMP can be one of the following values 03747 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC 03748 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 03749 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 03750 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 03751 * 03752 * . . TI1_RMP can be one of the following values 03753 * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO 03754 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2 03755 * 03756 * TIM15: any combination of TI1_RMP, ENCODER_MODE where 03757 * 03758 * . . TI1_RMP can be one of the following values 03759 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO 03760 * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE 03761 * 03762 * . . ENCODER_MODE can be one of the following values 03763 * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION 03764 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2 03765 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3 03766 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4 03767 * 03768 * TIM16: one of the following values 03769 * 03770 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO 03771 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI 03772 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE 03773 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC 03774 * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI (*) 03775 * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32 (*) 03776 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO (*) 03777 * 03778 * TIM17: one of the following values 03779 * 03780 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO 03781 * @arg @ref LL_TIM_TIM17_TI1_RMP_MSI 03782 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32 03783 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO 03784 * 03785 * (*) Value not defined in all devices. \n 03786 * @retval None 03787 */ 03788 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef * TIMx, uint32_t Remap) 03789 { 03790 MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK)); 03791 } 03792 03793 /** 03794 * @} 03795 */ 03796 03797 #if defined(TIM_SMCR_OCCS) 03798 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management 03799 * @{ 03800 */ 03801 /** 03802 * @brief Set the OCREF clear source 03803 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT 03804 * @note This function can only be used in Output compare and PWM modes. 03805 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource 03806 * @param TIMx Timer instance 03807 * @param OCRefClearInputSource This parameter can be one of the following values: 03808 * @arg @ref LL_TIM_OCREF_CLR_INT_NC 03809 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR 03810 * @retval None 03811 */ 03812 03813 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx, uint32_t OCRefClearInputSource) 03814 { 03815 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); 03816 } 03817 /** 03818 * @} 03819 */ 03820 03821 #endif /* TIM_SMCR_OCCS */ 03822 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management 03823 * @{ 03824 */ 03825 /** 03826 * @brief Clear the update interrupt flag (UIF). 03827 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE 03828 * @param TIMx Timer instance 03829 * @retval None 03830 */ 03831 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx) 03832 { 03833 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); 03834 } 03835 03836 /** 03837 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). 03838 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE 03839 * @param TIMx Timer instance 03840 * @retval State of bit (1 or 0). 03841 */ 03842 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef * TIMx) 03843 { 03844 return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); 03845 } 03846 03847 /** 03848 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). 03849 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 03850 * @param TIMx Timer instance 03851 * @retval None 03852 */ 03853 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx) 03854 { 03855 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); 03856 } 03857 03858 /** 03859 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). 03860 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 03861 * @param TIMx Timer instance 03862 * @retval State of bit (1 or 0). 03863 */ 03864 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef * TIMx) 03865 { 03866 return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)); 03867 } 03868 03869 /** 03870 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). 03871 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 03872 * @param TIMx Timer instance 03873 * @retval None 03874 */ 03875 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx) 03876 { 03877 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); 03878 } 03879 03880 /** 03881 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). 03882 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 03883 * @param TIMx Timer instance 03884 * @retval State of bit (1 or 0). 03885 */ 03886 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef * TIMx) 03887 { 03888 return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)); 03889 } 03890 03891 /** 03892 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). 03893 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 03894 * @param TIMx Timer instance 03895 * @retval None 03896 */ 03897 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx) 03898 { 03899 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); 03900 } 03901 03902 /** 03903 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). 03904 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 03905 * @param TIMx Timer instance 03906 * @retval State of bit (1 or 0). 03907 */ 03908 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef * TIMx) 03909 { 03910 return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)); 03911 } 03912 03913 /** 03914 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). 03915 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 03916 * @param TIMx Timer instance 03917 * @retval None 03918 */ 03919 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx) 03920 { 03921 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); 03922 } 03923 03924 /** 03925 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). 03926 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 03927 * @param TIMx Timer instance 03928 * @retval State of bit (1 or 0). 03929 */ 03930 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef * TIMx) 03931 { 03932 return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)); 03933 } 03934 03935 /** 03936 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). 03937 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 03938 * @param TIMx Timer instance 03939 * @retval None 03940 */ 03941 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx) 03942 { 03943 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); 03944 } 03945 03946 /** 03947 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). 03948 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 03949 * @param TIMx Timer instance 03950 * @retval State of bit (1 or 0). 03951 */ 03952 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef * TIMx) 03953 { 03954 return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)); 03955 } 03956 03957 /** 03958 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). 03959 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 03960 * @param TIMx Timer instance 03961 * @retval None 03962 */ 03963 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx) 03964 { 03965 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); 03966 } 03967 03968 /** 03969 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). 03970 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 03971 * @param TIMx Timer instance 03972 * @retval State of bit (1 or 0). 03973 */ 03974 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef * TIMx) 03975 { 03976 return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)); 03977 } 03978 03979 /** 03980 * @brief Clear the commutation interrupt flag (COMIF). 03981 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM 03982 * @param TIMx Timer instance 03983 * @retval None 03984 */ 03985 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx) 03986 { 03987 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); 03988 } 03989 03990 /** 03991 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). 03992 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM 03993 * @param TIMx Timer instance 03994 * @retval State of bit (1 or 0). 03995 */ 03996 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef * TIMx) 03997 { 03998 return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)); 03999 } 04000 04001 /** 04002 * @brief Clear the trigger interrupt flag (TIF). 04003 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG 04004 * @param TIMx Timer instance 04005 * @retval None 04006 */ 04007 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx) 04008 { 04009 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); 04010 } 04011 04012 /** 04013 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). 04014 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG 04015 * @param TIMx Timer instance 04016 * @retval State of bit (1 or 0). 04017 */ 04018 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef * TIMx) 04019 { 04020 return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)); 04021 } 04022 04023 /** 04024 * @brief Clear the break interrupt flag (BIF). 04025 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK 04026 * @param TIMx Timer instance 04027 * @retval None 04028 */ 04029 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx) 04030 { 04031 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); 04032 } 04033 04034 /** 04035 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). 04036 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK 04037 * @param TIMx Timer instance 04038 * @retval State of bit (1 or 0). 04039 */ 04040 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef * TIMx) 04041 { 04042 return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)); 04043 } 04044 04045 /** 04046 * @brief Clear the break 2 interrupt flag (B2IF). 04047 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 04048 * @param TIMx Timer instance 04049 * @retval None 04050 */ 04051 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx) 04052 { 04053 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); 04054 } 04055 04056 /** 04057 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). 04058 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 04059 * @param TIMx Timer instance 04060 * @retval State of bit (1 or 0). 04061 */ 04062 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef * TIMx) 04063 { 04064 return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)); 04065 } 04066 04067 /** 04068 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). 04069 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR 04070 * @param TIMx Timer instance 04071 * @retval None 04072 */ 04073 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx) 04074 { 04075 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); 04076 } 04077 04078 /** 04079 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). 04080 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR 04081 * @param TIMx Timer instance 04082 * @retval State of bit (1 or 0). 04083 */ 04084 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef * TIMx) 04085 { 04086 return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)); 04087 } 04088 04089 /** 04090 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). 04091 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR 04092 * @param TIMx Timer instance 04093 * @retval None 04094 */ 04095 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx) 04096 { 04097 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); 04098 } 04099 04100 /** 04101 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). 04102 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR 04103 * @param TIMx Timer instance 04104 * @retval State of bit (1 or 0). 04105 */ 04106 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef * TIMx) 04107 { 04108 return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)); 04109 } 04110 04111 /** 04112 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). 04113 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR 04114 * @param TIMx Timer instance 04115 * @retval None 04116 */ 04117 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx) 04118 { 04119 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); 04120 } 04121 04122 /** 04123 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). 04124 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR 04125 * @param TIMx Timer instance 04126 * @retval State of bit (1 or 0). 04127 */ 04128 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef * TIMx) 04129 { 04130 return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)); 04131 } 04132 04133 /** 04134 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). 04135 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR 04136 * @param TIMx Timer instance 04137 * @retval None 04138 */ 04139 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx) 04140 { 04141 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); 04142 } 04143 04144 /** 04145 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). 04146 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR 04147 * @param TIMx Timer instance 04148 * @retval State of bit (1 or 0). 04149 */ 04150 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef * TIMx) 04151 { 04152 return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)); 04153 } 04154 04155 /** 04156 * @brief Clear the system break interrupt flag (SBIF). 04157 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK 04158 * @param TIMx Timer instance 04159 * @retval None 04160 */ 04161 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx) 04162 { 04163 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); 04164 } 04165 04166 /** 04167 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). 04168 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK 04169 * @param TIMx Timer instance 04170 * @retval State of bit (1 or 0). 04171 */ 04172 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef * TIMx) 04173 { 04174 return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)); 04175 } 04176 04177 /** 04178 * @} 04179 */ 04180 04181 /** @defgroup TIM_LL_EF_IT_Management IT-Management 04182 * @{ 04183 */ 04184 /** 04185 * @brief Enable update interrupt (UIE). 04186 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE 04187 * @param TIMx Timer instance 04188 * @retval None 04189 */ 04190 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx) 04191 { 04192 SET_BIT(TIMx->DIER, TIM_DIER_UIE); 04193 } 04194 04195 /** 04196 * @brief Disable update interrupt (UIE). 04197 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE 04198 * @param TIMx Timer instance 04199 * @retval None 04200 */ 04201 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx) 04202 { 04203 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); 04204 } 04205 04206 /** 04207 * @brief Indicates whether the update interrupt (UIE) is enabled. 04208 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE 04209 * @param TIMx Timer instance 04210 * @retval State of bit (1 or 0). 04211 */ 04212 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef * TIMx) 04213 { 04214 return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)); 04215 } 04216 04217 /** 04218 * @brief Enable capture/compare 1 interrupt (CC1IE). 04219 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 04220 * @param TIMx Timer instance 04221 * @retval None 04222 */ 04223 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx) 04224 { 04225 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); 04226 } 04227 04228 /** 04229 * @brief Disable capture/compare 1 interrupt (CC1IE). 04230 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 04231 * @param TIMx Timer instance 04232 * @retval None 04233 */ 04234 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx) 04235 { 04236 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); 04237 } 04238 04239 /** 04240 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. 04241 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 04242 * @param TIMx Timer instance 04243 * @retval State of bit (1 or 0). 04244 */ 04245 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef * TIMx) 04246 { 04247 return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)); 04248 } 04249 04250 /** 04251 * @brief Enable capture/compare 2 interrupt (CC2IE). 04252 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 04253 * @param TIMx Timer instance 04254 * @retval None 04255 */ 04256 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx) 04257 { 04258 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); 04259 } 04260 04261 /** 04262 * @brief Disable capture/compare 2 interrupt (CC2IE). 04263 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 04264 * @param TIMx Timer instance 04265 * @retval None 04266 */ 04267 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx) 04268 { 04269 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); 04270 } 04271 04272 /** 04273 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. 04274 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 04275 * @param TIMx Timer instance 04276 * @retval State of bit (1 or 0). 04277 */ 04278 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef * TIMx) 04279 { 04280 return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)); 04281 } 04282 04283 /** 04284 * @brief Enable capture/compare 3 interrupt (CC3IE). 04285 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 04286 * @param TIMx Timer instance 04287 * @retval None 04288 */ 04289 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx) 04290 { 04291 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); 04292 } 04293 04294 /** 04295 * @brief Disable capture/compare 3 interrupt (CC3IE). 04296 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 04297 * @param TIMx Timer instance 04298 * @retval None 04299 */ 04300 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx) 04301 { 04302 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); 04303 } 04304 04305 /** 04306 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. 04307 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 04308 * @param TIMx Timer instance 04309 * @retval State of bit (1 or 0). 04310 */ 04311 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef * TIMx) 04312 { 04313 return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)); 04314 } 04315 04316 /** 04317 * @brief Enable capture/compare 4 interrupt (CC4IE). 04318 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 04319 * @param TIMx Timer instance 04320 * @retval None 04321 */ 04322 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx) 04323 { 04324 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); 04325 } 04326 04327 /** 04328 * @brief Disable capture/compare 4 interrupt (CC4IE). 04329 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 04330 * @param TIMx Timer instance 04331 * @retval None 04332 */ 04333 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx) 04334 { 04335 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); 04336 } 04337 04338 /** 04339 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. 04340 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 04341 * @param TIMx Timer instance 04342 * @retval State of bit (1 or 0). 04343 */ 04344 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef * TIMx) 04345 { 04346 return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)); 04347 } 04348 04349 /** 04350 * @brief Enable commutation interrupt (COMIE). 04351 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM 04352 * @param TIMx Timer instance 04353 * @retval None 04354 */ 04355 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx) 04356 { 04357 SET_BIT(TIMx->DIER, TIM_DIER_COMIE); 04358 } 04359 04360 /** 04361 * @brief Disable commutation interrupt (COMIE). 04362 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM 04363 * @param TIMx Timer instance 04364 * @retval None 04365 */ 04366 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx) 04367 { 04368 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); 04369 } 04370 04371 /** 04372 * @brief Indicates whether the commutation interrupt (COMIE) is enabled. 04373 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM 04374 * @param TIMx Timer instance 04375 * @retval State of bit (1 or 0). 04376 */ 04377 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef * TIMx) 04378 { 04379 return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)); 04380 } 04381 04382 /** 04383 * @brief Enable trigger interrupt (TIE). 04384 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG 04385 * @param TIMx Timer instance 04386 * @retval None 04387 */ 04388 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx) 04389 { 04390 SET_BIT(TIMx->DIER, TIM_DIER_TIE); 04391 } 04392 04393 /** 04394 * @brief Disable trigger interrupt (TIE). 04395 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG 04396 * @param TIMx Timer instance 04397 * @retval None 04398 */ 04399 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx) 04400 { 04401 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); 04402 } 04403 04404 /** 04405 * @brief Indicates whether the trigger interrupt (TIE) is enabled. 04406 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG 04407 * @param TIMx Timer instance 04408 * @retval State of bit (1 or 0). 04409 */ 04410 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef * TIMx) 04411 { 04412 return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)); 04413 } 04414 04415 /** 04416 * @brief Enable break interrupt (BIE). 04417 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK 04418 * @param TIMx Timer instance 04419 * @retval None 04420 */ 04421 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx) 04422 { 04423 SET_BIT(TIMx->DIER, TIM_DIER_BIE); 04424 } 04425 04426 /** 04427 * @brief Disable break interrupt (BIE). 04428 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK 04429 * @param TIMx Timer instance 04430 * @retval None 04431 */ 04432 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx) 04433 { 04434 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); 04435 } 04436 04437 /** 04438 * @brief Indicates whether the break interrupt (BIE) is enabled. 04439 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK 04440 * @param TIMx Timer instance 04441 * @retval State of bit (1 or 0). 04442 */ 04443 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef * TIMx) 04444 { 04445 return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)); 04446 } 04447 04448 /** 04449 * @} 04450 */ 04451 04452 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management 04453 * @{ 04454 */ 04455 /** 04456 * @brief Enable update DMA request (UDE). 04457 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE 04458 * @param TIMx Timer instance 04459 * @retval None 04460 */ 04461 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx) 04462 { 04463 SET_BIT(TIMx->DIER, TIM_DIER_UDE); 04464 } 04465 04466 /** 04467 * @brief Disable update DMA request (UDE). 04468 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE 04469 * @param TIMx Timer instance 04470 * @retval None 04471 */ 04472 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx) 04473 { 04474 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); 04475 } 04476 04477 /** 04478 * @brief Indicates whether the update DMA request (UDE) is enabled. 04479 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE 04480 * @param TIMx Timer instance 04481 * @retval State of bit (1 or 0). 04482 */ 04483 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef * TIMx) 04484 { 04485 return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)); 04486 } 04487 04488 /** 04489 * @brief Enable capture/compare 1 DMA request (CC1DE). 04490 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 04491 * @param TIMx Timer instance 04492 * @retval None 04493 */ 04494 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx) 04495 { 04496 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); 04497 } 04498 04499 /** 04500 * @brief Disable capture/compare 1 DMA request (CC1DE). 04501 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 04502 * @param TIMx Timer instance 04503 * @retval None 04504 */ 04505 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx) 04506 { 04507 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); 04508 } 04509 04510 /** 04511 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. 04512 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 04513 * @param TIMx Timer instance 04514 * @retval State of bit (1 or 0). 04515 */ 04516 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef * TIMx) 04517 { 04518 return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)); 04519 } 04520 04521 /** 04522 * @brief Enable capture/compare 2 DMA request (CC2DE). 04523 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 04524 * @param TIMx Timer instance 04525 * @retval None 04526 */ 04527 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx) 04528 { 04529 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); 04530 } 04531 04532 /** 04533 * @brief Disable capture/compare 2 DMA request (CC2DE). 04534 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 04535 * @param TIMx Timer instance 04536 * @retval None 04537 */ 04538 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx) 04539 { 04540 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); 04541 } 04542 04543 /** 04544 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. 04545 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 04546 * @param TIMx Timer instance 04547 * @retval State of bit (1 or 0). 04548 */ 04549 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef * TIMx) 04550 { 04551 return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)); 04552 } 04553 04554 /** 04555 * @brief Enable capture/compare 3 DMA request (CC3DE). 04556 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 04557 * @param TIMx Timer instance 04558 * @retval None 04559 */ 04560 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx) 04561 { 04562 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); 04563 } 04564 04565 /** 04566 * @brief Disable capture/compare 3 DMA request (CC3DE). 04567 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 04568 * @param TIMx Timer instance 04569 * @retval None 04570 */ 04571 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx) 04572 { 04573 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); 04574 } 04575 04576 /** 04577 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. 04578 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 04579 * @param TIMx Timer instance 04580 * @retval State of bit (1 or 0). 04581 */ 04582 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef * TIMx) 04583 { 04584 return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)); 04585 } 04586 04587 /** 04588 * @brief Enable capture/compare 4 DMA request (CC4DE). 04589 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 04590 * @param TIMx Timer instance 04591 * @retval None 04592 */ 04593 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx) 04594 { 04595 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); 04596 } 04597 04598 /** 04599 * @brief Disable capture/compare 4 DMA request (CC4DE). 04600 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 04601 * @param TIMx Timer instance 04602 * @retval None 04603 */ 04604 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx) 04605 { 04606 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); 04607 } 04608 04609 /** 04610 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. 04611 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 04612 * @param TIMx Timer instance 04613 * @retval State of bit (1 or 0). 04614 */ 04615 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef * TIMx) 04616 { 04617 return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)); 04618 } 04619 04620 /** 04621 * @brief Enable commutation DMA request (COMDE). 04622 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM 04623 * @param TIMx Timer instance 04624 * @retval None 04625 */ 04626 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx) 04627 { 04628 SET_BIT(TIMx->DIER, TIM_DIER_COMDE); 04629 } 04630 04631 /** 04632 * @brief Disable commutation DMA request (COMDE). 04633 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM 04634 * @param TIMx Timer instance 04635 * @retval None 04636 */ 04637 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx) 04638 { 04639 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); 04640 } 04641 04642 /** 04643 * @brief Indicates whether the commutation DMA request (COMDE) is enabled. 04644 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM 04645 * @param TIMx Timer instance 04646 * @retval State of bit (1 or 0). 04647 */ 04648 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef * TIMx) 04649 { 04650 return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)); 04651 } 04652 04653 /** 04654 * @brief Enable trigger interrupt (TDE). 04655 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG 04656 * @param TIMx Timer instance 04657 * @retval None 04658 */ 04659 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx) 04660 { 04661 SET_BIT(TIMx->DIER, TIM_DIER_TDE); 04662 } 04663 04664 /** 04665 * @brief Disable trigger interrupt (TDE). 04666 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG 04667 * @param TIMx Timer instance 04668 * @retval None 04669 */ 04670 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx) 04671 { 04672 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); 04673 } 04674 04675 /** 04676 * @brief Indicates whether the trigger interrupt (TDE) is enabled. 04677 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG 04678 * @param TIMx Timer instance 04679 * @retval State of bit (1 or 0). 04680 */ 04681 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef * TIMx) 04682 { 04683 return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)); 04684 } 04685 04686 /** 04687 * @} 04688 */ 04689 04690 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management 04691 * @{ 04692 */ 04693 /** 04694 * @brief Generate an update event. 04695 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE 04696 * @param TIMx Timer instance 04697 * @retval None 04698 */ 04699 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx) 04700 { 04701 SET_BIT(TIMx->EGR, TIM_EGR_UG); 04702 } 04703 04704 /** 04705 * @brief Generate Capture/Compare 1 event. 04706 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 04707 * @param TIMx Timer instance 04708 * @retval None 04709 */ 04710 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx) 04711 { 04712 SET_BIT(TIMx->EGR, TIM_EGR_CC1G); 04713 } 04714 04715 /** 04716 * @brief Generate Capture/Compare 2 event. 04717 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 04718 * @param TIMx Timer instance 04719 * @retval None 04720 */ 04721 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx) 04722 { 04723 SET_BIT(TIMx->EGR, TIM_EGR_CC2G); 04724 } 04725 04726 /** 04727 * @brief Generate Capture/Compare 3 event. 04728 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 04729 * @param TIMx Timer instance 04730 * @retval None 04731 */ 04732 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx) 04733 { 04734 SET_BIT(TIMx->EGR, TIM_EGR_CC3G); 04735 } 04736 04737 /** 04738 * @brief Generate Capture/Compare 4 event. 04739 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 04740 * @param TIMx Timer instance 04741 * @retval None 04742 */ 04743 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx) 04744 { 04745 SET_BIT(TIMx->EGR, TIM_EGR_CC4G); 04746 } 04747 04748 /** 04749 * @brief Generate commutation event. 04750 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM 04751 * @param TIMx Timer instance 04752 * @retval None 04753 */ 04754 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx) 04755 { 04756 SET_BIT(TIMx->EGR, TIM_EGR_COMG); 04757 } 04758 04759 /** 04760 * @brief Generate trigger event. 04761 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG 04762 * @param TIMx Timer instance 04763 * @retval None 04764 */ 04765 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx) 04766 { 04767 SET_BIT(TIMx->EGR, TIM_EGR_TG); 04768 } 04769 04770 /** 04771 * @brief Generate break event. 04772 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK 04773 * @param TIMx Timer instance 04774 * @retval None 04775 */ 04776 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx) 04777 { 04778 SET_BIT(TIMx->EGR, TIM_EGR_BG); 04779 } 04780 04781 /** 04782 * @brief Generate break 2 event. 04783 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 04784 * @param TIMx Timer instance 04785 * @retval None 04786 */ 04787 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx) 04788 { 04789 SET_BIT(TIMx->EGR, TIM_EGR_B2G); 04790 } 04791 04792 /** 04793 * @} 04794 */ 04795 04796 #if defined(USE_FULL_LL_DRIVER) 04797 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions 04798 * @{ 04799 */ 04800 04801 ErrorStatus LL_TIM_DeInit(TIM_TypeDef* TIMx); 04802 void LL_TIM_StructInit(LL_TIM_InitTypeDef* TIM_InitStruct); 04803 ErrorStatus LL_TIM_Init(TIM_TypeDef* TIMx, LL_TIM_InitTypeDef* TIM_InitStruct); 04804 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef* TIM_OC_InitStruct); 04805 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef* TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef* TIM_OC_InitStruct); 04806 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef* TIM_ICInitStruct); 04807 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef* TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef* TIM_IC_InitStruct); 04808 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef* TIM_EncoderInitStruct); 04809 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef* TIMx, LL_TIM_ENCODER_InitTypeDef* TIM_EncoderInitStruct); 04810 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef* TIM_HallSensorInitStruct); 04811 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef* TIMx, LL_TIM_HALLSENSOR_InitTypeDef* TIM_HallSensorInitStruct); 04812 /** 04813 * @} 04814 */ 04815 #endif /* USE_FULL_LL_DRIVER */ 04816 04817 /** 04818 * @} 04819 */ 04820 04821 /** 04822 * @} 04823 */ 04824 04825 #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */ 04826 04827 /** 04828 * @} 04829 */ 04830 04831 #ifdef __cplusplus 04832 } 04833 #endif 04834 04835 #endif /* __STM32L4xx_LL_TIM_H */ 04836 04837 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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