Configuration
[WWDG Exported Functions]

Enable Window Watchdog.

The watchdog is always disabled after a reset.

Note:

It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot be disabled again except by a reset. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. CR WDGA LL_WWDG_Enable

Parameters:

WWDGx

WWDG Instance

Return values:

None

Definition at line 147 of file stm32l4xx_ll_wwdg.h.

Return current Watchdog Counter Value (7 bits counter value) CR T LL_WWDG_GetCounter.

Parameters:

WWDGx

WWDG Instance

Return values:

7	bit Watchdog Counter value

Definition at line 185 of file stm32l4xx_ll_wwdg.h.

Return current Watchdog Prescaler Value CFR WDGTB LL_WWDG_GetPrescaler.

Parameters:

WWDGx

WWDG Instance

Return values:

Returned

value can be one of the following values: LL_WWDG_PRESCALER_1 LL_WWDG_PRESCALER_2 LL_WWDG_PRESCALER_4 LL_WWDG_PRESCALER_8

Definition at line 218 of file stm32l4xx_ll_wwdg.h.

Return current Watchdog Window Value (7 bits value) CFR W LL_WWDG_GetWindow.

Parameters:

WWDGx

WWDG Instance

Return values:

7	bit Watchdog Window value

Definition at line 250 of file stm32l4xx_ll_wwdg.h.

Checks if Window Watchdog is enabled CR WDGA LL_WWDG_IsEnabled.

Parameters:

WWDGx

WWDG Instance

Return values:

State

of bit (1 or 0).

Definition at line 158 of file stm32l4xx_ll_wwdg.h.

Set the Watchdog counter value to provided value (7-bits T[6:0])

Note:

When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset This counter is decremented every (4096 x 2expWDGTB) PCLK cycles A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared) Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled) CR T LL_WWDG_SetCounter

Parameters:

WWDGx	WWDG Instance
Counter	0..0x7F (7 bit counter value)

Return values:

None

Definition at line 174 of file stm32l4xx_ll_wwdg.h.

Set the time base of the prescaler (WDGTB).

Note:

Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter is decremented every (4096 x 2expWDGTB) PCLK cycles CFR WDGTB LL_WWDG_SetPrescaler

Parameters:

WWDGx	WWDG Instance
Prescaler	This parameter can be one of the following values: LL_WWDG_PRESCALER_1 LL_WWDG_PRESCALER_2 LL_WWDG_PRESCALER_4 LL_WWDG_PRESCALER_8

Return values:

None

Definition at line 203 of file stm32l4xx_ll_wwdg.h.

Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).

Note:

This window value defines when write in the WWDG_CR register to program Watchdog counter is allowed. Watchdog counter value update must occur only when the counter value is lower than the Watchdog window register value. Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value (in the control register) is refreshed before the downcounter has reached the watchdog window register value. Physically is possible to set the Window lower then 0x40 but it is not recommended. To generate an immediate reset, it is possible to set the Counter lower than 0x40. CFR W LL_WWDG_SetWindow

Parameters:

WWDGx	WWDG Instance
Window	0x00..0x7F (7 bit Window value)

Return values:

None

Definition at line 239 of file stm32l4xx_ll_wwdg.h.