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HAL_L476/stm32l4xx_ll_system.h@1:d0dfbce63a89, 2017-02-24 (annotated)

Committer:: elmot
Date:: Fri Feb 24 21:13:56 2017 +0000
Revision:: 1:d0dfbce63a89

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elmot	1:d0dfbce63a89	1	/**
elmot	1:d0dfbce63a89	2	******************************************************************************
elmot	1:d0dfbce63a89	3	* @file stm32l4xx_ll_system.h
elmot	1:d0dfbce63a89	4	* @author MCD Application Team
elmot	1:d0dfbce63a89	5	* @version V1.5.1
elmot	1:d0dfbce63a89	6	* @date 31-May-2016
elmot	1:d0dfbce63a89	7	* @brief Header file of SYSTEM LL module.
elmot	1:d0dfbce63a89	8	@verbatim
elmot	1:d0dfbce63a89	9	==============================================================================
elmot	1:d0dfbce63a89	10	##### How to use this driver #####
elmot	1:d0dfbce63a89	11	==============================================================================
elmot	1:d0dfbce63a89	12	[..]
elmot	1:d0dfbce63a89	13	The LL SYSTEM driver contains a set of generic APIs that can be
elmot	1:d0dfbce63a89	14	used by user:
elmot	1:d0dfbce63a89	15	(+) Some of the FLASH features need to be handled in the SYSTEM file.
elmot	1:d0dfbce63a89	16	(+) Access to DBGCMU registers
elmot	1:d0dfbce63a89	17	(+) Access to SYSCFG registers
elmot	1:d0dfbce63a89	18	(+) Access to VREFBUF registers
elmot	1:d0dfbce63a89	19
elmot	1:d0dfbce63a89	20	@endverbatim
elmot	1:d0dfbce63a89	21	******************************************************************************
elmot	1:d0dfbce63a89	22	* @attention
elmot	1:d0dfbce63a89	23	*
elmot	1:d0dfbce63a89	24	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
elmot	1:d0dfbce63a89	25	*
elmot	1:d0dfbce63a89	26	* Redistribution and use in source and binary forms, with or without modification,
elmot	1:d0dfbce63a89	27	* are permitted provided that the following conditions are met:
elmot	1:d0dfbce63a89	28	* 1. Redistributions of source code must retain the above copyright notice,
elmot	1:d0dfbce63a89	29	* this list of conditions and the following disclaimer.
elmot	1:d0dfbce63a89	30	* 2. Redistributions in binary form must reproduce the above copyright notice,
elmot	1:d0dfbce63a89	31	* this list of conditions and the following disclaimer in the documentation
elmot	1:d0dfbce63a89	32	* and/or other materials provided with the distribution.
elmot	1:d0dfbce63a89	33	* 3. Neither the name of STMicroelectronics nor the names of its contributors
elmot	1:d0dfbce63a89	34	* may be used to endorse or promote products derived from this software
elmot	1:d0dfbce63a89	35	* without specific prior written permission.
elmot	1:d0dfbce63a89	36	*
elmot	1:d0dfbce63a89	37	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elmot	1:d0dfbce63a89	38	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elmot	1:d0dfbce63a89	39	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elmot	1:d0dfbce63a89	40	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
elmot	1:d0dfbce63a89	41	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
elmot	1:d0dfbce63a89	42	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
elmot	1:d0dfbce63a89	43	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
elmot	1:d0dfbce63a89	44	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
elmot	1:d0dfbce63a89	45	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
elmot	1:d0dfbce63a89	46	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elmot	1:d0dfbce63a89	47	*
elmot	1:d0dfbce63a89	48	******************************************************************************
elmot	1:d0dfbce63a89	49	*/
elmot	1:d0dfbce63a89	50
elmot	1:d0dfbce63a89	51	/* Define to prevent recursive inclusion -------------------------------------*/
elmot	1:d0dfbce63a89	52	#ifndef __STM32L4xx_LL_SYSTEM_H
elmot	1:d0dfbce63a89	53	#define __STM32L4xx_LL_SYSTEM_H
elmot	1:d0dfbce63a89	54
elmot	1:d0dfbce63a89	55	#ifdef __cplusplus
elmot	1:d0dfbce63a89	56	extern "C" {
elmot	1:d0dfbce63a89	57	#endif
elmot	1:d0dfbce63a89	58
elmot	1:d0dfbce63a89	59	/* Includes ------------------------------------------------------------------*/
elmot	1:d0dfbce63a89	60	#include "stm32l4xx.h"
elmot	1:d0dfbce63a89	61
elmot	1:d0dfbce63a89	62	/** @addtogroup STM32L4xx_LL_Driver
elmot	1:d0dfbce63a89	63	* @{
elmot	1:d0dfbce63a89	64	*/
elmot	1:d0dfbce63a89	65
elmot	1:d0dfbce63a89	66	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) \|\| defined (VREFBUF)
elmot	1:d0dfbce63a89	67
elmot	1:d0dfbce63a89	68	/** @defgroup SYSTEM_LL SYSTEM
elmot	1:d0dfbce63a89	69	* @{
elmot	1:d0dfbce63a89	70	*/
elmot	1:d0dfbce63a89	71
elmot	1:d0dfbce63a89	72	/* Private types -------------------------------------------------------------*/
elmot	1:d0dfbce63a89	73	/* Private variables ---------------------------------------------------------*/
elmot	1:d0dfbce63a89	74
elmot	1:d0dfbce63a89	75	/* Private constants ---------------------------------------------------------*/
elmot	1:d0dfbce63a89	76	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
elmot	1:d0dfbce63a89	77	* @{
elmot	1:d0dfbce63a89	78	*/
elmot	1:d0dfbce63a89	79
elmot	1:d0dfbce63a89	80	/* Defines used for position in the register */
elmot	1:d0dfbce63a89	81	#define DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
elmot	1:d0dfbce63a89	82
elmot	1:d0dfbce63a89	83	/**
elmot	1:d0dfbce63a89	84	* @brief Power-down in Run mode Flash key
elmot	1:d0dfbce63a89	85	*/
elmot	1:d0dfbce63a89	86	#define FLASH_PDKEY1 ((uint32_t)0x04152637U) /!< Flash power down key1 /
elmot	1:d0dfbce63a89	87	#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
elmot	1:d0dfbce63a89	88	to unlock the RUN_PD bit in FLASH_ACR */
elmot	1:d0dfbce63a89	89
elmot	1:d0dfbce63a89	90	/**
elmot	1:d0dfbce63a89	91	* @}
elmot	1:d0dfbce63a89	92	*/
elmot	1:d0dfbce63a89	93
elmot	1:d0dfbce63a89	94	/* Private macros ------------------------------------------------------------*/
elmot	1:d0dfbce63a89	95
elmot	1:d0dfbce63a89	96	/* Exported types ------------------------------------------------------------*/
elmot	1:d0dfbce63a89	97	/* Exported constants --------------------------------------------------------*/
elmot	1:d0dfbce63a89	98	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
elmot	1:d0dfbce63a89	99	* @{
elmot	1:d0dfbce63a89	100	*/
elmot	1:d0dfbce63a89	101
elmot	1:d0dfbce63a89	102	/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
elmot	1:d0dfbce63a89	103	* @{
elmot	1:d0dfbce63a89	104	*/
elmot	1:d0dfbce63a89	105	#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /!< Main Flash memory mapped at 0x00000000 /
elmot	1:d0dfbce63a89	106	#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /!< System Flash memory mapped at 0x00000000 /
elmot	1:d0dfbce63a89	107	#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 \| SYSCFG_MEMRMP_MEM_MODE_0) /!< SRAM1 mapped at 0x00000000 /
elmot	1:d0dfbce63a89	108	#if defined(FMC_Bank1_R)
elmot	1:d0dfbce63a89	109	#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 /
elmot	1:d0dfbce63a89	110	#endif /* FMC_Bank1_R */
elmot	1:d0dfbce63a89	111	#define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 \| SYSCFG_MEMRMP_MEM_MODE_1) /!< QUADSPI memory mapped at 0x00000000 /
elmot	1:d0dfbce63a89	112	/**
elmot	1:d0dfbce63a89	113	* @}
elmot	1:d0dfbce63a89	114	*/
elmot	1:d0dfbce63a89	115
elmot	1:d0dfbce63a89	116	#if defined(SYSCFG_MEMRMP_FB_MODE)
elmot	1:d0dfbce63a89	117	/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
elmot	1:d0dfbce63a89	118	* @{
elmot	1:d0dfbce63a89	119	*/
elmot	1:d0dfbce63a89	120	#define LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000 /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
elmot	1:d0dfbce63a89	121	and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */
elmot	1:d0dfbce63a89	122	#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
elmot	1:d0dfbce63a89	123	and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */
elmot	1:d0dfbce63a89	124	/**
elmot	1:d0dfbce63a89	125	* @}
elmot	1:d0dfbce63a89	126	*/
elmot	1:d0dfbce63a89	127
elmot	1:d0dfbce63a89	128	#endif /* SYSCFG_MEMRMP_FB_MODE */
elmot	1:d0dfbce63a89	129	/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
elmot	1:d0dfbce63a89	130	* @{
elmot	1:d0dfbce63a89	131	*/
elmot	1:d0dfbce63a89	132	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /!< Enable Fast Mode Plus on PB6 /
elmot	1:d0dfbce63a89	133	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /!< Enable Fast Mode Plus on PB7 /
elmot	1:d0dfbce63a89	134	#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
elmot	1:d0dfbce63a89	135	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /!< Enable Fast Mode Plus on PB8 /
elmot	1:d0dfbce63a89	136	#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
elmot	1:d0dfbce63a89	137	#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
elmot	1:d0dfbce63a89	138	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /!< Enable Fast Mode Plus on PB9 /
elmot	1:d0dfbce63a89	139	#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
elmot	1:d0dfbce63a89	140	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /!< Enable Fast Mode Plus on I2C1 pins /
elmot	1:d0dfbce63a89	141	#if defined(I2C2)
elmot	1:d0dfbce63a89	142	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /!< Enable Fast Mode Plus on I2C2 pins /
elmot	1:d0dfbce63a89	143	#endif /* I2C2 */
elmot	1:d0dfbce63a89	144	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /!< Enable Fast Mode Plus on I2C3 pins /
elmot	1:d0dfbce63a89	145	/**
elmot	1:d0dfbce63a89	146	* @}
elmot	1:d0dfbce63a89	147	*/
elmot	1:d0dfbce63a89	148
elmot	1:d0dfbce63a89	149	/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
elmot	1:d0dfbce63a89	150	* @{
elmot	1:d0dfbce63a89	151	*/
elmot	1:d0dfbce63a89	152	#define LL_SYSCFG_EXTI_PORTA (uint32_t)0 /!< EXTI PORT A /
elmot	1:d0dfbce63a89	153	#define LL_SYSCFG_EXTI_PORTB (uint32_t)1 /!< EXTI PORT B /
elmot	1:d0dfbce63a89	154	#define LL_SYSCFG_EXTI_PORTC (uint32_t)2 /!< EXTI PORT C /
elmot	1:d0dfbce63a89	155	#define LL_SYSCFG_EXTI_PORTD (uint32_t)3 /!< EXTI PORT D /
elmot	1:d0dfbce63a89	156	#define LL_SYSCFG_EXTI_PORTE (uint32_t)4 /!< EXTI PORT E /
elmot	1:d0dfbce63a89	157	#if defined(GPIOF)
elmot	1:d0dfbce63a89	158	#define LL_SYSCFG_EXTI_PORTF (uint32_t)5 /!< EXTI PORT F /
elmot	1:d0dfbce63a89	159	#endif /* GPIOF */
elmot	1:d0dfbce63a89	160	#if defined(GPIOG)
elmot	1:d0dfbce63a89	161	#define LL_SYSCFG_EXTI_PORTG (uint32_t)6 /!< EXTI PORT G /
elmot	1:d0dfbce63a89	162	#endif /* GPIOG */
elmot	1:d0dfbce63a89	163	#define LL_SYSCFG_EXTI_PORTH (uint32_t)7 /!< EXTI PORT H /
elmot	1:d0dfbce63a89	164	/**
elmot	1:d0dfbce63a89	165	* @}
elmot	1:d0dfbce63a89	166	*/
elmot	1:d0dfbce63a89	167
elmot	1:d0dfbce63a89	168	/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
elmot	1:d0dfbce63a89	169	* @{
elmot	1:d0dfbce63a89	170	*/
elmot	1:d0dfbce63a89	171	#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 \| 0) /* !< EXTI_POSITION_0 \| EXTICR[0] */
elmot	1:d0dfbce63a89	172	#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 \| 0) /* !< EXTI_POSITION_4 \| EXTICR[0] */
elmot	1:d0dfbce63a89	173	#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 \| 0) /* !< EXTI_POSITION_8 \| EXTICR[0] */
elmot	1:d0dfbce63a89	174	#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 \| 0) /* !< EXTI_POSITION_12 \| EXTICR[0] */
elmot	1:d0dfbce63a89	175	#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 \| 1) /* !< EXTI_POSITION_0 \| EXTICR[1] */
elmot	1:d0dfbce63a89	176	#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 \| 1) /* !< EXTI_POSITION_4 \| EXTICR[1] */
elmot	1:d0dfbce63a89	177	#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 \| 1) /* !< EXTI_POSITION_8 \| EXTICR[1] */
elmot	1:d0dfbce63a89	178	#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 \| 1) /* !< EXTI_POSITION_12 \| EXTICR[1] */
elmot	1:d0dfbce63a89	179	#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 \| 2) /* !< EXTI_POSITION_0 \| EXTICR[2] */
elmot	1:d0dfbce63a89	180	#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 \| 2) /* !< EXTI_POSITION_4 \| EXTICR[2] */
elmot	1:d0dfbce63a89	181	#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 \| 2) /* !< EXTI_POSITION_8 \| EXTICR[2] */
elmot	1:d0dfbce63a89	182	#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 \| 2) /* !< EXTI_POSITION_12 \| EXTICR[2] */
elmot	1:d0dfbce63a89	183	#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 \| 3) /* !< EXTI_POSITION_0 \| EXTICR[3] */
elmot	1:d0dfbce63a89	184	#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 \| 3) /* !< EXTI_POSITION_4 \| EXTICR[3] */
elmot	1:d0dfbce63a89	185	#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 \| 3) /* !< EXTI_POSITION_8 \| EXTICR[3] */
elmot	1:d0dfbce63a89	186	#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 \| 3) /* !< EXTI_POSITION_12 \| EXTICR[3] */
elmot	1:d0dfbce63a89	187	/**
elmot	1:d0dfbce63a89	188	* @}
elmot	1:d0dfbce63a89	189	*/
elmot	1:d0dfbce63a89	190
elmot	1:d0dfbce63a89	191	/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
elmot	1:d0dfbce63a89	192	* @{
elmot	1:d0dfbce63a89	193	*/
elmot	1:d0dfbce63a89	194	#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
elmot	1:d0dfbce63a89	195	with Break Input of TIM1/8/15/16/17 */
elmot	1:d0dfbce63a89	196	#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
elmot	1:d0dfbce63a89	197	with TIM1/8/15/16/17 Break Input
elmot	1:d0dfbce63a89	198	and also the PVDE and PLS bits of the Power Control Interface */
elmot	1:d0dfbce63a89	199	#define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal
elmot	1:d0dfbce63a89	200	with Break Input of TIM1/8/15/16/17 */
elmot	1:d0dfbce63a89	201	#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
elmot	1:d0dfbce63a89	202	with Break Input of TIM1/15/16/17 */
elmot	1:d0dfbce63a89	203	/**
elmot	1:d0dfbce63a89	204	* @}
elmot	1:d0dfbce63a89	205	*/
elmot	1:d0dfbce63a89	206
elmot	1:d0dfbce63a89	207	/** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP
elmot	1:d0dfbce63a89	208	* @{
elmot	1:d0dfbce63a89	209	*/
elmot	1:d0dfbce63a89	210	#define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /!< SRAM2 Write protection page 0 /
elmot	1:d0dfbce63a89	211	#define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /!< SRAM2 Write protection page 1 /
elmot	1:d0dfbce63a89	212	#define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /!< SRAM2 Write protection page 2 /
elmot	1:d0dfbce63a89	213	#define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /!< SRAM2 Write protection page 3 /
elmot	1:d0dfbce63a89	214	#define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /!< SRAM2 Write protection page 4 /
elmot	1:d0dfbce63a89	215	#define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /!< SRAM2 Write protection page 5 /
elmot	1:d0dfbce63a89	216	#define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /!< SRAM2 Write protection page 6 /
elmot	1:d0dfbce63a89	217	#define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /!< SRAM2 Write protection page 7 /
elmot	1:d0dfbce63a89	218	#define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /!< SRAM2 Write protection page 8 /
elmot	1:d0dfbce63a89	219	#define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /!< SRAM2 Write protection page 9 /
elmot	1:d0dfbce63a89	220	#define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /!< SRAM2 Write protection page 10 /
elmot	1:d0dfbce63a89	221	#define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /!< SRAM2 Write protection page 11 /
elmot	1:d0dfbce63a89	222	#define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /!< SRAM2 Write protection page 12 /
elmot	1:d0dfbce63a89	223	#define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /!< SRAM2 Write protection page 13 /
elmot	1:d0dfbce63a89	224	#define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /!< SRAM2 Write protection page 14 /
elmot	1:d0dfbce63a89	225	#define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /!< SRAM2 Write protection page 15 /
elmot	1:d0dfbce63a89	226	#if defined(SYSCFG_SWPR_PAGE16)
elmot	1:d0dfbce63a89	227	#define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /!< SRAM2 Write protection page 16 /
elmot	1:d0dfbce63a89	228	#define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /!< SRAM2 Write protection page 17 /
elmot	1:d0dfbce63a89	229	#define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /!< SRAM2 Write protection page 18 /
elmot	1:d0dfbce63a89	230	#define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /!< SRAM2 Write protection page 19 /
elmot	1:d0dfbce63a89	231	#define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /!< SRAM2 Write protection page 20 /
elmot	1:d0dfbce63a89	232	#define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /!< SRAM2 Write protection page 21 /
elmot	1:d0dfbce63a89	233	#define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /!< SRAM2 Write protection page 22 /
elmot	1:d0dfbce63a89	234	#define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /!< SRAM2 Write protection page 23 /
elmot	1:d0dfbce63a89	235	#define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /!< SRAM2 Write protection page 24 /
elmot	1:d0dfbce63a89	236	#define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /!< SRAM2 Write protection page 25 /
elmot	1:d0dfbce63a89	237	#define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /!< SRAM2 Write protection page 26 /
elmot	1:d0dfbce63a89	238	#define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /!< SRAM2 Write protection page 27 /
elmot	1:d0dfbce63a89	239	#define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /!< SRAM2 Write protection page 28 /
elmot	1:d0dfbce63a89	240	#define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /!< SRAM2 Write protection page 29 /
elmot	1:d0dfbce63a89	241	#define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /!< SRAM2 Write protection page 30 /
elmot	1:d0dfbce63a89	242	#define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /!< SRAM2 Write protection page 31 /
elmot	1:d0dfbce63a89	243	#endif /* SYSCFG_SWPR_PAGE16 */
elmot	1:d0dfbce63a89	244	/**
elmot	1:d0dfbce63a89	245	* @}
elmot	1:d0dfbce63a89	246	*/
elmot	1:d0dfbce63a89	247
elmot	1:d0dfbce63a89	248	/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
elmot	1:d0dfbce63a89	249	* @{
elmot	1:d0dfbce63a89	250	*/
elmot	1:d0dfbce63a89	251	#define LL_DBGMCU_TRACE_NONE (uint32_t)0x00000000U /!< TRACE pins not assigned (default state) /
elmot	1:d0dfbce63a89	252	#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /!< TRACE pin assignment for Asynchronous Mode /
elmot	1:d0dfbce63a89	253	#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_0) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 /
elmot	1:d0dfbce63a89	254	#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_1) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 /
elmot	1:d0dfbce63a89	255	#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 /
elmot	1:d0dfbce63a89	256	/**
elmot	1:d0dfbce63a89	257	* @}
elmot	1:d0dfbce63a89	258	*/
elmot	1:d0dfbce63a89	259
elmot	1:d0dfbce63a89	260	/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
elmot	1:d0dfbce63a89	261	* @{
elmot	1:d0dfbce63a89	262	*/
elmot	1:d0dfbce63a89	263	#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /!< The counter clock of TIM2 is stopped when the core is halted/
elmot	1:d0dfbce63a89	264	#if defined(TIM3)
elmot	1:d0dfbce63a89	265	#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /!< The counter clock of TIM3 is stopped when the core is halted/
elmot	1:d0dfbce63a89	266	#endif /* TIM3 */
elmot	1:d0dfbce63a89	267	#if defined(TIM4)
elmot	1:d0dfbce63a89	268	#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /!< The counter clock of TIM4 is stopped when the core is halted/
elmot	1:d0dfbce63a89	269	#endif /* TIM4 */
elmot	1:d0dfbce63a89	270	#if defined(TIM5)
elmot	1:d0dfbce63a89	271	#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /!< The counter clock of TIM5 is stopped when the core is halted/
elmot	1:d0dfbce63a89	272	#endif /* TIM5 */
elmot	1:d0dfbce63a89	273	#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /!< The counter clock of TIM6 is stopped when the core is halted/
elmot	1:d0dfbce63a89	274	#if defined(TIM7)
elmot	1:d0dfbce63a89	275	#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /!< The counter clock of TIM7 is stopped when the core is halted/
elmot	1:d0dfbce63a89	276	#endif /* TIM7 */
elmot	1:d0dfbce63a89	277	#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /!< The clock of the RTC counter is stopped when the core is halted/
elmot	1:d0dfbce63a89	278	#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /!< The window watchdog counter clock is stopped when the core is halted/
elmot	1:d0dfbce63a89	279	#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /!< The independent watchdog counter clock is stopped when the core is halted/
elmot	1:d0dfbce63a89	280	#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /!< The I2C1 SMBus timeout is frozen/
elmot	1:d0dfbce63a89	281	#if defined(I2C2)
elmot	1:d0dfbce63a89	282	#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /!< The I2C2 SMBus timeout is frozen/
elmot	1:d0dfbce63a89	283	#endif /* I2C2 */
elmot	1:d0dfbce63a89	284	#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /!< The I2C3 SMBus timeout is frozen/
elmot	1:d0dfbce63a89	285	#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP /!< The bxCAN receive registers are frozen/
elmot	1:d0dfbce63a89	286	#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /!< The counter clock of LPTIM1 is stopped when the core is halted/
elmot	1:d0dfbce63a89	287	/**
elmot	1:d0dfbce63a89	288	* @}
elmot	1:d0dfbce63a89	289	*/
elmot	1:d0dfbce63a89	290
elmot	1:d0dfbce63a89	291	/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
elmot	1:d0dfbce63a89	292	* @{
elmot	1:d0dfbce63a89	293	*/
elmot	1:d0dfbce63a89	294	#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /!< The counter clock of LPTIM2 is stopped when the core is halted/
elmot	1:d0dfbce63a89	295	/**
elmot	1:d0dfbce63a89	296	* @}
elmot	1:d0dfbce63a89	297	*/
elmot	1:d0dfbce63a89	298
elmot	1:d0dfbce63a89	299	/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
elmot	1:d0dfbce63a89	300	* @{
elmot	1:d0dfbce63a89	301	*/
elmot	1:d0dfbce63a89	302	#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP /!< The counter clock of TIM1 is stopped when the core is halted/
elmot	1:d0dfbce63a89	303	#if defined(TIM8)
elmot	1:d0dfbce63a89	304	#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP /!< The counter clock of TIM8 is stopped when the core is halted/
elmot	1:d0dfbce63a89	305	#endif /* TIM8 */
elmot	1:d0dfbce63a89	306	#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP /!< The counter clock of TIM15 is stopped when the core is halted/
elmot	1:d0dfbce63a89	307	#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP /!< The counter clock of TIM16 is stopped when the core is halted/
elmot	1:d0dfbce63a89	308	#if defined(TIM17)
elmot	1:d0dfbce63a89	309	#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP /!< The counter clock of TIM17 is stopped when the core is halted/
elmot	1:d0dfbce63a89	310	#endif /* TIM17 */
elmot	1:d0dfbce63a89	311	/**
elmot	1:d0dfbce63a89	312	* @}
elmot	1:d0dfbce63a89	313	*/
elmot	1:d0dfbce63a89	314
elmot	1:d0dfbce63a89	315	#if defined(VREFBUF)
elmot	1:d0dfbce63a89	316	/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
elmot	1:d0dfbce63a89	317	* @{
elmot	1:d0dfbce63a89	318	*/
elmot	1:d0dfbce63a89	319	#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /!< Voltage reference scale 0 (VREF_OUT1) /
elmot	1:d0dfbce63a89	320	#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /!< Voltage reference scale 1 (VREF_OUT2) /
elmot	1:d0dfbce63a89	321	/**
elmot	1:d0dfbce63a89	322	* @}
elmot	1:d0dfbce63a89	323	*/
elmot	1:d0dfbce63a89	324	#endif /* VREFBUF */
elmot	1:d0dfbce63a89	325
elmot	1:d0dfbce63a89	326	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
elmot	1:d0dfbce63a89	327	* @{
elmot	1:d0dfbce63a89	328	*/
elmot	1:d0dfbce63a89	329	#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /!< FLASH Zero wait state /
elmot	1:d0dfbce63a89	330	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /!< FLASH One wait state /
elmot	1:d0dfbce63a89	331	#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /!< FLASH Two wait states /
elmot	1:d0dfbce63a89	332	#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /!< FLASH Three wait states /
elmot	1:d0dfbce63a89	333	#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /!< FLASH Four wait states /
elmot	1:d0dfbce63a89	334	/**
elmot	1:d0dfbce63a89	335	* @}
elmot	1:d0dfbce63a89	336	*/
elmot	1:d0dfbce63a89	337
elmot	1:d0dfbce63a89	338	/**
elmot	1:d0dfbce63a89	339	* @}
elmot	1:d0dfbce63a89	340	*/
elmot	1:d0dfbce63a89	341
elmot	1:d0dfbce63a89	342	/* Exported macro ------------------------------------------------------------*/
elmot	1:d0dfbce63a89	343
elmot	1:d0dfbce63a89	344	/* Exported functions --------------------------------------------------------*/
elmot	1:d0dfbce63a89	345	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
elmot	1:d0dfbce63a89	346	* @{
elmot	1:d0dfbce63a89	347	*/
elmot	1:d0dfbce63a89	348
elmot	1:d0dfbce63a89	349	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
elmot	1:d0dfbce63a89	350	* @{
elmot	1:d0dfbce63a89	351	*/
elmot	1:d0dfbce63a89	352
elmot	1:d0dfbce63a89	353	/**
elmot	1:d0dfbce63a89	354	* @brief Set memory mapping at address 0x00000000
elmot	1:d0dfbce63a89	355	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
elmot	1:d0dfbce63a89	356	* @param Memory This parameter can be one of the following values:
elmot	1:d0dfbce63a89	357	* @arg @ref LL_SYSCFG_REMAP_FLASH
elmot	1:d0dfbce63a89	358	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
elmot	1:d0dfbce63a89	359	* @arg @ref LL_SYSCFG_REMAP_SRAM
elmot	1:d0dfbce63a89	360	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
elmot	1:d0dfbce63a89	361	* @arg @ref LL_SYSCFG_REMAP_QUADSPI
elmot	1:d0dfbce63a89	362	*
elmot	1:d0dfbce63a89	363	* (*) value not defined in all devices
elmot	1:d0dfbce63a89	364	* @retval None
elmot	1:d0dfbce63a89	365	*/
elmot	1:d0dfbce63a89	366	__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
elmot	1:d0dfbce63a89	367	{
elmot	1:d0dfbce63a89	368	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
elmot	1:d0dfbce63a89	369	}
elmot	1:d0dfbce63a89	370
elmot	1:d0dfbce63a89	371	/**
elmot	1:d0dfbce63a89	372	* @brief Get memory mapping at address 0x00000000
elmot	1:d0dfbce63a89	373	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
elmot	1:d0dfbce63a89	374	* @retval Returned value can be one of the following values:
elmot	1:d0dfbce63a89	375	* @arg @ref LL_SYSCFG_REMAP_FLASH
elmot	1:d0dfbce63a89	376	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
elmot	1:d0dfbce63a89	377	* @arg @ref LL_SYSCFG_REMAP_SRAM
elmot	1:d0dfbce63a89	378	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
elmot	1:d0dfbce63a89	379	* @arg @ref LL_SYSCFG_REMAP_QUADSPI
elmot	1:d0dfbce63a89	380	*
elmot	1:d0dfbce63a89	381	* (*) value not defined in all devices
elmot	1:d0dfbce63a89	382	*/
elmot	1:d0dfbce63a89	383	__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
elmot	1:d0dfbce63a89	384	{
elmot	1:d0dfbce63a89	385	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
elmot	1:d0dfbce63a89	386	}
elmot	1:d0dfbce63a89	387
elmot	1:d0dfbce63a89	388	#if defined(SYSCFG_MEMRMP_FB_MODE)
elmot	1:d0dfbce63a89	389	/**
elmot	1:d0dfbce63a89	390	* @brief Select Flash bank mode (Bank flashed at 0x08000000)
elmot	1:d0dfbce63a89	391	* @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
elmot	1:d0dfbce63a89	392	* @param Bank This parameter can be one of the following values:
elmot	1:d0dfbce63a89	393	* @arg @ref LL_SYSCFG_BANKMODE_BANK1
elmot	1:d0dfbce63a89	394	* @arg @ref LL_SYSCFG_BANKMODE_BANK2
elmot	1:d0dfbce63a89	395	* @retval None
elmot	1:d0dfbce63a89	396	*/
elmot	1:d0dfbce63a89	397	__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
elmot	1:d0dfbce63a89	398	{
elmot	1:d0dfbce63a89	399	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
elmot	1:d0dfbce63a89	400	}
elmot	1:d0dfbce63a89	401
elmot	1:d0dfbce63a89	402	/**
elmot	1:d0dfbce63a89	403	* @brief Get Flash bank mode (Bank flashed at 0x08000000)
elmot	1:d0dfbce63a89	404	* @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
elmot	1:d0dfbce63a89	405	* @retval Returned value can be one of the following values:
elmot	1:d0dfbce63a89	406	* @arg @ref LL_SYSCFG_BANKMODE_BANK1
elmot	1:d0dfbce63a89	407	* @arg @ref LL_SYSCFG_BANKMODE_BANK2
elmot	1:d0dfbce63a89	408	*/
elmot	1:d0dfbce63a89	409	__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
elmot	1:d0dfbce63a89	410	{
elmot	1:d0dfbce63a89	411	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
elmot	1:d0dfbce63a89	412	}
elmot	1:d0dfbce63a89	413	#endif /* SYSCFG_MEMRMP_FB_MODE */
elmot	1:d0dfbce63a89	414
elmot	1:d0dfbce63a89	415	/**
elmot	1:d0dfbce63a89	416	* @brief Firewall protection enabled
elmot	1:d0dfbce63a89	417	* @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_EnableFirewall
elmot	1:d0dfbce63a89	418	* @retval None
elmot	1:d0dfbce63a89	419	*/
elmot	1:d0dfbce63a89	420	__STATIC_INLINE void LL_SYSCFG_EnableFirewall(void)
elmot	1:d0dfbce63a89	421	{
elmot	1:d0dfbce63a89	422	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS);
elmot	1:d0dfbce63a89	423	}
elmot	1:d0dfbce63a89	424
elmot	1:d0dfbce63a89	425	/**
elmot	1:d0dfbce63a89	426	* @brief Check if Firewall protection is enabled or not
elmot	1:d0dfbce63a89	427	* @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_IsEnabledFirewall
elmot	1:d0dfbce63a89	428	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	429	*/
elmot	1:d0dfbce63a89	430	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void)
elmot	1:d0dfbce63a89	431	{
elmot	1:d0dfbce63a89	432	return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS);
elmot	1:d0dfbce63a89	433	}
elmot	1:d0dfbce63a89	434
elmot	1:d0dfbce63a89	435	/**
elmot	1:d0dfbce63a89	436	* @brief Enable I/O analog switch voltage booster.
elmot	1:d0dfbce63a89	437	* @note When voltage booster is enabled, I/O analog switches are supplied
elmot	1:d0dfbce63a89	438	* by a dedicated voltage booster, from VDD power domain. This is
elmot	1:d0dfbce63a89	439	* the recommended configuration with low VDDA voltage operation.
elmot	1:d0dfbce63a89	440	* @note The I/O analog switch voltage booster is relevant for peripherals
elmot	1:d0dfbce63a89	441	* using I/O in analog input: ADC, COMP, OPAMP.
elmot	1:d0dfbce63a89	442	* However, COMP and OPAMP inputs have a high impedance and
elmot	1:d0dfbce63a89	443	* voltage booster do not impact performance significantly.
elmot	1:d0dfbce63a89	444	* Therefore, the voltage booster is mainly intended for
elmot	1:d0dfbce63a89	445	* usage with ADC.
elmot	1:d0dfbce63a89	446	* @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
elmot	1:d0dfbce63a89	447	* @retval None
elmot	1:d0dfbce63a89	448	*/
elmot	1:d0dfbce63a89	449	__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
elmot	1:d0dfbce63a89	450	{
elmot	1:d0dfbce63a89	451	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
elmot	1:d0dfbce63a89	452	}
elmot	1:d0dfbce63a89	453
elmot	1:d0dfbce63a89	454	/**
elmot	1:d0dfbce63a89	455	* @brief Disable I/O analog switch voltage booster.
elmot	1:d0dfbce63a89	456	* @note When voltage booster is enabled, I/O analog switches are supplied
elmot	1:d0dfbce63a89	457	* by a dedicated voltage booster, from VDD power domain. This is
elmot	1:d0dfbce63a89	458	* the recommended configuration with low VDDA voltage operation.
elmot	1:d0dfbce63a89	459	* @note The I/O analog switch voltage booster is relevant for peripherals
elmot	1:d0dfbce63a89	460	* using I/O in analog input: ADC, COMP, OPAMP.
elmot	1:d0dfbce63a89	461	* However, COMP and OPAMP inputs have a high impedance and
elmot	1:d0dfbce63a89	462	* voltage booster do not impact performance significantly.
elmot	1:d0dfbce63a89	463	* Therefore, the voltage booster is mainly intended for
elmot	1:d0dfbce63a89	464	* usage with ADC.
elmot	1:d0dfbce63a89	465	* @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
elmot	1:d0dfbce63a89	466	* @retval None
elmot	1:d0dfbce63a89	467	*/
elmot	1:d0dfbce63a89	468	__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
elmot	1:d0dfbce63a89	469	{
elmot	1:d0dfbce63a89	470	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
elmot	1:d0dfbce63a89	471	}
elmot	1:d0dfbce63a89	472
elmot	1:d0dfbce63a89	473	/**
elmot	1:d0dfbce63a89	474	* @brief Enable the I2C fast mode plus driving capability.
elmot	1:d0dfbce63a89	475	* @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
elmot	1:d0dfbce63a89	476	* SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
elmot	1:d0dfbce63a89	477	* @param ConfigFastModePlus This parameter can be a combination of the following values:
elmot	1:d0dfbce63a89	478	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
elmot	1:d0dfbce63a89	479	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
elmot	1:d0dfbce63a89	480	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
elmot	1:d0dfbce63a89	481	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
elmot	1:d0dfbce63a89	482	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
elmot	1:d0dfbce63a89	483	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
elmot	1:d0dfbce63a89	484	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
elmot	1:d0dfbce63a89	485	*
elmot	1:d0dfbce63a89	486	* (*) value not defined in all devices
elmot	1:d0dfbce63a89	487	* @retval None
elmot	1:d0dfbce63a89	488	*/
elmot	1:d0dfbce63a89	489	__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
elmot	1:d0dfbce63a89	490	{
elmot	1:d0dfbce63a89	491	SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
elmot	1:d0dfbce63a89	492	}
elmot	1:d0dfbce63a89	493
elmot	1:d0dfbce63a89	494	/**
elmot	1:d0dfbce63a89	495	* @brief Disable the I2C fast mode plus driving capability.
elmot	1:d0dfbce63a89	496	* @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
elmot	1:d0dfbce63a89	497	* SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
elmot	1:d0dfbce63a89	498	* @param ConfigFastModePlus This parameter can be a combination of the following values:
elmot	1:d0dfbce63a89	499	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
elmot	1:d0dfbce63a89	500	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
elmot	1:d0dfbce63a89	501	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
elmot	1:d0dfbce63a89	502	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
elmot	1:d0dfbce63a89	503	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
elmot	1:d0dfbce63a89	504	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
elmot	1:d0dfbce63a89	505	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
elmot	1:d0dfbce63a89	506	*
elmot	1:d0dfbce63a89	507	* (*) value not defined in all devices
elmot	1:d0dfbce63a89	508	* @retval None
elmot	1:d0dfbce63a89	509	*/
elmot	1:d0dfbce63a89	510	__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
elmot	1:d0dfbce63a89	511	{
elmot	1:d0dfbce63a89	512	CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
elmot	1:d0dfbce63a89	513	}
elmot	1:d0dfbce63a89	514
elmot	1:d0dfbce63a89	515	/**
elmot	1:d0dfbce63a89	516	* @brief Enable Floating Point Unit Invalid operation Interrupt
elmot	1:d0dfbce63a89	517	* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
elmot	1:d0dfbce63a89	518	* @retval None
elmot	1:d0dfbce63a89	519	*/
elmot	1:d0dfbce63a89	520	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
elmot	1:d0dfbce63a89	521	{
elmot	1:d0dfbce63a89	522	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
elmot	1:d0dfbce63a89	523	}
elmot	1:d0dfbce63a89	524
elmot	1:d0dfbce63a89	525	/**
elmot	1:d0dfbce63a89	526	* @brief Enable Floating Point Unit Divide-by-zero Interrupt
elmot	1:d0dfbce63a89	527	* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
elmot	1:d0dfbce63a89	528	* @retval None
elmot	1:d0dfbce63a89	529	*/
elmot	1:d0dfbce63a89	530	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
elmot	1:d0dfbce63a89	531	{
elmot	1:d0dfbce63a89	532	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
elmot	1:d0dfbce63a89	533	}
elmot	1:d0dfbce63a89	534
elmot	1:d0dfbce63a89	535	/**
elmot	1:d0dfbce63a89	536	* @brief Enable Floating Point Unit Underflow Interrupt
elmot	1:d0dfbce63a89	537	* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
elmot	1:d0dfbce63a89	538	* @retval None
elmot	1:d0dfbce63a89	539	*/
elmot	1:d0dfbce63a89	540	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
elmot	1:d0dfbce63a89	541	{
elmot	1:d0dfbce63a89	542	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
elmot	1:d0dfbce63a89	543	}
elmot	1:d0dfbce63a89	544
elmot	1:d0dfbce63a89	545	/**
elmot	1:d0dfbce63a89	546	* @brief Enable Floating Point Unit Overflow Interrupt
elmot	1:d0dfbce63a89	547	* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
elmot	1:d0dfbce63a89	548	* @retval None
elmot	1:d0dfbce63a89	549	*/
elmot	1:d0dfbce63a89	550	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
elmot	1:d0dfbce63a89	551	{
elmot	1:d0dfbce63a89	552	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
elmot	1:d0dfbce63a89	553	}
elmot	1:d0dfbce63a89	554
elmot	1:d0dfbce63a89	555	/**
elmot	1:d0dfbce63a89	556	* @brief Enable Floating Point Unit Input denormal Interrupt
elmot	1:d0dfbce63a89	557	* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
elmot	1:d0dfbce63a89	558	* @retval None
elmot	1:d0dfbce63a89	559	*/
elmot	1:d0dfbce63a89	560	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
elmot	1:d0dfbce63a89	561	{
elmot	1:d0dfbce63a89	562	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
elmot	1:d0dfbce63a89	563	}
elmot	1:d0dfbce63a89	564
elmot	1:d0dfbce63a89	565	/**
elmot	1:d0dfbce63a89	566	* @brief Enable Floating Point Unit Inexact Interrupt
elmot	1:d0dfbce63a89	567	* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
elmot	1:d0dfbce63a89	568	* @retval None
elmot	1:d0dfbce63a89	569	*/
elmot	1:d0dfbce63a89	570	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
elmot	1:d0dfbce63a89	571	{
elmot	1:d0dfbce63a89	572	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
elmot	1:d0dfbce63a89	573	}
elmot	1:d0dfbce63a89	574
elmot	1:d0dfbce63a89	575	/**
elmot	1:d0dfbce63a89	576	* @brief Disable Floating Point Unit Invalid operation Interrupt
elmot	1:d0dfbce63a89	577	* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
elmot	1:d0dfbce63a89	578	* @retval None
elmot	1:d0dfbce63a89	579	*/
elmot	1:d0dfbce63a89	580	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
elmot	1:d0dfbce63a89	581	{
elmot	1:d0dfbce63a89	582	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
elmot	1:d0dfbce63a89	583	}
elmot	1:d0dfbce63a89	584
elmot	1:d0dfbce63a89	585	/**
elmot	1:d0dfbce63a89	586	* @brief Disable Floating Point Unit Divide-by-zero Interrupt
elmot	1:d0dfbce63a89	587	* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
elmot	1:d0dfbce63a89	588	* @retval None
elmot	1:d0dfbce63a89	589	*/
elmot	1:d0dfbce63a89	590	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
elmot	1:d0dfbce63a89	591	{
elmot	1:d0dfbce63a89	592	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
elmot	1:d0dfbce63a89	593	}
elmot	1:d0dfbce63a89	594
elmot	1:d0dfbce63a89	595	/**
elmot	1:d0dfbce63a89	596	* @brief Disable Floating Point Unit Underflow Interrupt
elmot	1:d0dfbce63a89	597	* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
elmot	1:d0dfbce63a89	598	* @retval None
elmot	1:d0dfbce63a89	599	*/
elmot	1:d0dfbce63a89	600	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
elmot	1:d0dfbce63a89	601	{
elmot	1:d0dfbce63a89	602	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
elmot	1:d0dfbce63a89	603	}
elmot	1:d0dfbce63a89	604
elmot	1:d0dfbce63a89	605	/**
elmot	1:d0dfbce63a89	606	* @brief Disable Floating Point Unit Overflow Interrupt
elmot	1:d0dfbce63a89	607	* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
elmot	1:d0dfbce63a89	608	* @retval None
elmot	1:d0dfbce63a89	609	*/
elmot	1:d0dfbce63a89	610	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
elmot	1:d0dfbce63a89	611	{
elmot	1:d0dfbce63a89	612	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
elmot	1:d0dfbce63a89	613	}
elmot	1:d0dfbce63a89	614
elmot	1:d0dfbce63a89	615	/**
elmot	1:d0dfbce63a89	616	* @brief Disable Floating Point Unit Input denormal Interrupt
elmot	1:d0dfbce63a89	617	* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
elmot	1:d0dfbce63a89	618	* @retval None
elmot	1:d0dfbce63a89	619	*/
elmot	1:d0dfbce63a89	620	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
elmot	1:d0dfbce63a89	621	{
elmot	1:d0dfbce63a89	622	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
elmot	1:d0dfbce63a89	623	}
elmot	1:d0dfbce63a89	624
elmot	1:d0dfbce63a89	625	/**
elmot	1:d0dfbce63a89	626	* @brief Disable Floating Point Unit Inexact Interrupt
elmot	1:d0dfbce63a89	627	* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
elmot	1:d0dfbce63a89	628	* @retval None
elmot	1:d0dfbce63a89	629	*/
elmot	1:d0dfbce63a89	630	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
elmot	1:d0dfbce63a89	631	{
elmot	1:d0dfbce63a89	632	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
elmot	1:d0dfbce63a89	633	}
elmot	1:d0dfbce63a89	634
elmot	1:d0dfbce63a89	635	/**
elmot	1:d0dfbce63a89	636	* @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
elmot	1:d0dfbce63a89	637	* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
elmot	1:d0dfbce63a89	638	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	639	*/
elmot	1:d0dfbce63a89	640	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
elmot	1:d0dfbce63a89	641	{
elmot	1:d0dfbce63a89	642	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
elmot	1:d0dfbce63a89	643	}
elmot	1:d0dfbce63a89	644
elmot	1:d0dfbce63a89	645	/**
elmot	1:d0dfbce63a89	646	* @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
elmot	1:d0dfbce63a89	647	* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
elmot	1:d0dfbce63a89	648	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	649	*/
elmot	1:d0dfbce63a89	650	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
elmot	1:d0dfbce63a89	651	{
elmot	1:d0dfbce63a89	652	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
elmot	1:d0dfbce63a89	653	}
elmot	1:d0dfbce63a89	654
elmot	1:d0dfbce63a89	655	/**
elmot	1:d0dfbce63a89	656	* @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
elmot	1:d0dfbce63a89	657	* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
elmot	1:d0dfbce63a89	658	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	659	*/
elmot	1:d0dfbce63a89	660	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
elmot	1:d0dfbce63a89	661	{
elmot	1:d0dfbce63a89	662	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
elmot	1:d0dfbce63a89	663	}
elmot	1:d0dfbce63a89	664
elmot	1:d0dfbce63a89	665	/**
elmot	1:d0dfbce63a89	666	* @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
elmot	1:d0dfbce63a89	667	* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
elmot	1:d0dfbce63a89	668	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	669	*/
elmot	1:d0dfbce63a89	670	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
elmot	1:d0dfbce63a89	671	{
elmot	1:d0dfbce63a89	672	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
elmot	1:d0dfbce63a89	673	}
elmot	1:d0dfbce63a89	674
elmot	1:d0dfbce63a89	675	/**
elmot	1:d0dfbce63a89	676	* @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
elmot	1:d0dfbce63a89	677	* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
elmot	1:d0dfbce63a89	678	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	679	*/
elmot	1:d0dfbce63a89	680	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
elmot	1:d0dfbce63a89	681	{
elmot	1:d0dfbce63a89	682	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
elmot	1:d0dfbce63a89	683	}
elmot	1:d0dfbce63a89	684
elmot	1:d0dfbce63a89	685	/**
elmot	1:d0dfbce63a89	686	* @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
elmot	1:d0dfbce63a89	687	* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
elmot	1:d0dfbce63a89	688	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	689	*/
elmot	1:d0dfbce63a89	690	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
elmot	1:d0dfbce63a89	691	{
elmot	1:d0dfbce63a89	692	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
elmot	1:d0dfbce63a89	693	}
elmot	1:d0dfbce63a89	694
elmot	1:d0dfbce63a89	695	/**
elmot	1:d0dfbce63a89	696	* @brief Configure source input for the EXTI external interrupt.
elmot	1:d0dfbce63a89	697	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
elmot	1:d0dfbce63a89	698	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
elmot	1:d0dfbce63a89	699	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
elmot	1:d0dfbce63a89	700	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
elmot	1:d0dfbce63a89	701	* @param Port This parameter can be one of the following values:
elmot	1:d0dfbce63a89	702	* @arg @ref LL_SYSCFG_EXTI_PORTA
elmot	1:d0dfbce63a89	703	* @arg @ref LL_SYSCFG_EXTI_PORTB
elmot	1:d0dfbce63a89	704	* @arg @ref LL_SYSCFG_EXTI_PORTC
elmot	1:d0dfbce63a89	705	* @arg @ref LL_SYSCFG_EXTI_PORTD
elmot	1:d0dfbce63a89	706	* @arg @ref LL_SYSCFG_EXTI_PORTE
elmot	1:d0dfbce63a89	707	* @arg @ref LL_SYSCFG_EXTI_PORTF (*)
elmot	1:d0dfbce63a89	708	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
elmot	1:d0dfbce63a89	709	* @arg @ref LL_SYSCFG_EXTI_PORTH
elmot	1:d0dfbce63a89	710	*
elmot	1:d0dfbce63a89	711	* (*) value not defined in all devices
elmot	1:d0dfbce63a89	712	* @param Line This parameter can be one of the following values:
elmot	1:d0dfbce63a89	713	* @arg @ref LL_SYSCFG_EXTI_LINE0
elmot	1:d0dfbce63a89	714	* @arg @ref LL_SYSCFG_EXTI_LINE1
elmot	1:d0dfbce63a89	715	* @arg @ref LL_SYSCFG_EXTI_LINE2
elmot	1:d0dfbce63a89	716	* @arg @ref LL_SYSCFG_EXTI_LINE3
elmot	1:d0dfbce63a89	717	* @arg @ref LL_SYSCFG_EXTI_LINE4
elmot	1:d0dfbce63a89	718	* @arg @ref LL_SYSCFG_EXTI_LINE5
elmot	1:d0dfbce63a89	719	* @arg @ref LL_SYSCFG_EXTI_LINE6
elmot	1:d0dfbce63a89	720	* @arg @ref LL_SYSCFG_EXTI_LINE7
elmot	1:d0dfbce63a89	721	* @arg @ref LL_SYSCFG_EXTI_LINE8
elmot	1:d0dfbce63a89	722	* @arg @ref LL_SYSCFG_EXTI_LINE9
elmot	1:d0dfbce63a89	723	* @arg @ref LL_SYSCFG_EXTI_LINE10
elmot	1:d0dfbce63a89	724	* @arg @ref LL_SYSCFG_EXTI_LINE11
elmot	1:d0dfbce63a89	725	* @arg @ref LL_SYSCFG_EXTI_LINE12
elmot	1:d0dfbce63a89	726	* @arg @ref LL_SYSCFG_EXTI_LINE13
elmot	1:d0dfbce63a89	727	* @arg @ref LL_SYSCFG_EXTI_LINE14
elmot	1:d0dfbce63a89	728	* @arg @ref LL_SYSCFG_EXTI_LINE15
elmot	1:d0dfbce63a89	729	* @retval None
elmot	1:d0dfbce63a89	730	*/
elmot	1:d0dfbce63a89	731	__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
elmot	1:d0dfbce63a89	732	{
elmot	1:d0dfbce63a89	733	MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
elmot	1:d0dfbce63a89	734	}
elmot	1:d0dfbce63a89	735
elmot	1:d0dfbce63a89	736	/**
elmot	1:d0dfbce63a89	737	* @brief Get the configured defined for specific EXTI Line
elmot	1:d0dfbce63a89	738	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
elmot	1:d0dfbce63a89	739	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
elmot	1:d0dfbce63a89	740	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
elmot	1:d0dfbce63a89	741	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
elmot	1:d0dfbce63a89	742	* @param Line This parameter can be one of the following values:
elmot	1:d0dfbce63a89	743	* @arg @ref LL_SYSCFG_EXTI_LINE0
elmot	1:d0dfbce63a89	744	* @arg @ref LL_SYSCFG_EXTI_LINE1
elmot	1:d0dfbce63a89	745	* @arg @ref LL_SYSCFG_EXTI_LINE2
elmot	1:d0dfbce63a89	746	* @arg @ref LL_SYSCFG_EXTI_LINE3
elmot	1:d0dfbce63a89	747	* @arg @ref LL_SYSCFG_EXTI_LINE4
elmot	1:d0dfbce63a89	748	* @arg @ref LL_SYSCFG_EXTI_LINE5
elmot	1:d0dfbce63a89	749	* @arg @ref LL_SYSCFG_EXTI_LINE6
elmot	1:d0dfbce63a89	750	* @arg @ref LL_SYSCFG_EXTI_LINE7
elmot	1:d0dfbce63a89	751	* @arg @ref LL_SYSCFG_EXTI_LINE8
elmot	1:d0dfbce63a89	752	* @arg @ref LL_SYSCFG_EXTI_LINE9
elmot	1:d0dfbce63a89	753	* @arg @ref LL_SYSCFG_EXTI_LINE10
elmot	1:d0dfbce63a89	754	* @arg @ref LL_SYSCFG_EXTI_LINE11
elmot	1:d0dfbce63a89	755	* @arg @ref LL_SYSCFG_EXTI_LINE12
elmot	1:d0dfbce63a89	756	* @arg @ref LL_SYSCFG_EXTI_LINE13
elmot	1:d0dfbce63a89	757	* @arg @ref LL_SYSCFG_EXTI_LINE14
elmot	1:d0dfbce63a89	758	* @arg @ref LL_SYSCFG_EXTI_LINE15
elmot	1:d0dfbce63a89	759	* @retval Returned value can be one of the following values:
elmot	1:d0dfbce63a89	760	* @arg @ref LL_SYSCFG_EXTI_PORTA
elmot	1:d0dfbce63a89	761	* @arg @ref LL_SYSCFG_EXTI_PORTB
elmot	1:d0dfbce63a89	762	* @arg @ref LL_SYSCFG_EXTI_PORTC
elmot	1:d0dfbce63a89	763	* @arg @ref LL_SYSCFG_EXTI_PORTD
elmot	1:d0dfbce63a89	764	* @arg @ref LL_SYSCFG_EXTI_PORTE
elmot	1:d0dfbce63a89	765	* @arg @ref LL_SYSCFG_EXTI_PORTF (*)
elmot	1:d0dfbce63a89	766	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
elmot	1:d0dfbce63a89	767	* @arg @ref LL_SYSCFG_EXTI_PORTH
elmot	1:d0dfbce63a89	768	*
elmot	1:d0dfbce63a89	769	* (*) value not defined in all devices
elmot	1:d0dfbce63a89	770	*/
elmot	1:d0dfbce63a89	771	__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
elmot	1:d0dfbce63a89	772	{
elmot	1:d0dfbce63a89	773	return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
elmot	1:d0dfbce63a89	774	}
elmot	1:d0dfbce63a89	775
elmot	1:d0dfbce63a89	776	/**
elmot	1:d0dfbce63a89	777	* @brief Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
elmot	1:d0dfbce63a89	778	* automatically cleared at the end of the SRAM2 erase operation.)
elmot	1:d0dfbce63a89	779	* @note This bit is write-protected: setting this bit is possible only after the
elmot	1:d0dfbce63a89	780	* correct key sequence is written in the SYSCFG_SKR register.
elmot	1:d0dfbce63a89	781	* @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase
elmot	1:d0dfbce63a89	782	* @retval None
elmot	1:d0dfbce63a89	783	*/
elmot	1:d0dfbce63a89	784	__STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
elmot	1:d0dfbce63a89	785	{
elmot	1:d0dfbce63a89	786	/* unlock the write protection of the SRAM2ER bit */
elmot	1:d0dfbce63a89	787	WRITE_REG(SYSCFG->SKR, 0xCA);
elmot	1:d0dfbce63a89	788	WRITE_REG(SYSCFG->SKR, 0x53);
elmot	1:d0dfbce63a89	789
elmot	1:d0dfbce63a89	790	/* Starts a hardware SRAM2 erase operation*/
elmot	1:d0dfbce63a89	791	SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
elmot	1:d0dfbce63a89	792	}
elmot	1:d0dfbce63a89	793
elmot	1:d0dfbce63a89	794	/**
elmot	1:d0dfbce63a89	795	* @brief Check if SRAM2 erase operation is on going
elmot	1:d0dfbce63a89	796	* @rmtoll SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing
elmot	1:d0dfbce63a89	797	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	798	*/
elmot	1:d0dfbce63a89	799	__STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
elmot	1:d0dfbce63a89	800	{
elmot	1:d0dfbce63a89	801	return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY));
elmot	1:d0dfbce63a89	802	}
elmot	1:d0dfbce63a89	803
elmot	1:d0dfbce63a89	804	/**
elmot	1:d0dfbce63a89	805	* @brief Set connections to TIM1/8/15/16/17 Break inputs
elmot	1:d0dfbce63a89	806	* @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
elmot	1:d0dfbce63a89	807	* SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
elmot	1:d0dfbce63a89	808	* SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
elmot	1:d0dfbce63a89	809	* SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
elmot	1:d0dfbce63a89	810	* @param Break This parameter can be a combination of the following values:
elmot	1:d0dfbce63a89	811	* @arg @ref LL_SYSCFG_TIMBREAK_ECC
elmot	1:d0dfbce63a89	812	* @arg @ref LL_SYSCFG_TIMBREAK_PVD
elmot	1:d0dfbce63a89	813	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
elmot	1:d0dfbce63a89	814	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
elmot	1:d0dfbce63a89	815	* @retval None
elmot	1:d0dfbce63a89	816	*/
elmot	1:d0dfbce63a89	817	__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
elmot	1:d0dfbce63a89	818	{
elmot	1:d0dfbce63a89	819	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL \| SYSCFG_CFGR2_SPL \| SYSCFG_CFGR2_PVDL \| SYSCFG_CFGR2_ECCL, Break);
elmot	1:d0dfbce63a89	820	}
elmot	1:d0dfbce63a89	821
elmot	1:d0dfbce63a89	822	/**
elmot	1:d0dfbce63a89	823	* @brief Get connections to TIM1/8/15/16/17 Break inputs
elmot	1:d0dfbce63a89	824	* @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
elmot	1:d0dfbce63a89	825	* SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
elmot	1:d0dfbce63a89	826	* SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
elmot	1:d0dfbce63a89	827	* SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
elmot	1:d0dfbce63a89	828	* @retval Returned value can be can be a combination of the following values:
elmot	1:d0dfbce63a89	829	* @arg @ref LL_SYSCFG_TIMBREAK_ECC
elmot	1:d0dfbce63a89	830	* @arg @ref LL_SYSCFG_TIMBREAK_PVD
elmot	1:d0dfbce63a89	831	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
elmot	1:d0dfbce63a89	832	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
elmot	1:d0dfbce63a89	833	*/
elmot	1:d0dfbce63a89	834	__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
elmot	1:d0dfbce63a89	835	{
elmot	1:d0dfbce63a89	836	return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL \| SYSCFG_CFGR2_SPL \| SYSCFG_CFGR2_PVDL \| SYSCFG_CFGR2_ECCL));
elmot	1:d0dfbce63a89	837	}
elmot	1:d0dfbce63a89	838
elmot	1:d0dfbce63a89	839	/**
elmot	1:d0dfbce63a89	840	* @brief Check if SRAM2 parity error detected
elmot	1:d0dfbce63a89	841	* @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
elmot	1:d0dfbce63a89	842	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	843	*/
elmot	1:d0dfbce63a89	844	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
elmot	1:d0dfbce63a89	845	{
elmot	1:d0dfbce63a89	846	return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF));
elmot	1:d0dfbce63a89	847	}
elmot	1:d0dfbce63a89	848
elmot	1:d0dfbce63a89	849	/**
elmot	1:d0dfbce63a89	850	* @brief Clear SRAM2 parity error flag
elmot	1:d0dfbce63a89	851	* @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
elmot	1:d0dfbce63a89	852	* @retval None
elmot	1:d0dfbce63a89	853	*/
elmot	1:d0dfbce63a89	854	__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
elmot	1:d0dfbce63a89	855	{
elmot	1:d0dfbce63a89	856	SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
elmot	1:d0dfbce63a89	857	}
elmot	1:d0dfbce63a89	858
elmot	1:d0dfbce63a89	859	/**
elmot	1:d0dfbce63a89	860	* @brief Enable SRAM2 page write protection
elmot	1:d0dfbce63a89	861	* @note Write protection is cleared only by a system reset
elmot	1:d0dfbce63a89	862	* @rmtoll SYSCFG_SWPR PAGEx LL_SYSCFG_EnableSRAM2PageWRP
elmot	1:d0dfbce63a89	863	* @param SRAM2WRP This parameter can be a combination of the following values:
elmot	1:d0dfbce63a89	864	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
elmot	1:d0dfbce63a89	865	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
elmot	1:d0dfbce63a89	866	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
elmot	1:d0dfbce63a89	867	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
elmot	1:d0dfbce63a89	868	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
elmot	1:d0dfbce63a89	869	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
elmot	1:d0dfbce63a89	870	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
elmot	1:d0dfbce63a89	871	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
elmot	1:d0dfbce63a89	872	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
elmot	1:d0dfbce63a89	873	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
elmot	1:d0dfbce63a89	874	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
elmot	1:d0dfbce63a89	875	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
elmot	1:d0dfbce63a89	876	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
elmot	1:d0dfbce63a89	877	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
elmot	1:d0dfbce63a89	878	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
elmot	1:d0dfbce63a89	879	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
elmot	1:d0dfbce63a89	880	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 (*)
elmot	1:d0dfbce63a89	881	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 (*)
elmot	1:d0dfbce63a89	882	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 (*)
elmot	1:d0dfbce63a89	883	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 (*)
elmot	1:d0dfbce63a89	884	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 (*)
elmot	1:d0dfbce63a89	885	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 (*)
elmot	1:d0dfbce63a89	886	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 (*)
elmot	1:d0dfbce63a89	887	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 (*)
elmot	1:d0dfbce63a89	888	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 (*)
elmot	1:d0dfbce63a89	889	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 (*)
elmot	1:d0dfbce63a89	890	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 (*)
elmot	1:d0dfbce63a89	891	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 (*)
elmot	1:d0dfbce63a89	892	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 (*)
elmot	1:d0dfbce63a89	893	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 (*)
elmot	1:d0dfbce63a89	894	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 (*)
elmot	1:d0dfbce63a89	895	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 (*)
elmot	1:d0dfbce63a89	896	*
elmot	1:d0dfbce63a89	897	* (*) value not defined in all devices
elmot	1:d0dfbce63a89	898	* @retval None
elmot	1:d0dfbce63a89	899	*/
elmot	1:d0dfbce63a89	900	__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP(uint32_t SRAM2WRP)
elmot	1:d0dfbce63a89	901	{
elmot	1:d0dfbce63a89	902	SET_BIT(SYSCFG->SWPR, SRAM2WRP);
elmot	1:d0dfbce63a89	903	}
elmot	1:d0dfbce63a89	904
elmot	1:d0dfbce63a89	905	/**
elmot	1:d0dfbce63a89	906	* @brief SRAM2 page write protection lock prior to erase
elmot	1:d0dfbce63a89	907	* @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP
elmot	1:d0dfbce63a89	908	* @retval None
elmot	1:d0dfbce63a89	909	*/
elmot	1:d0dfbce63a89	910	__STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
elmot	1:d0dfbce63a89	911	{
elmot	1:d0dfbce63a89	912	/* Writing a wrong key reactivates the write protection */
elmot	1:d0dfbce63a89	913	WRITE_REG(SYSCFG->SKR, 0x00);
elmot	1:d0dfbce63a89	914	}
elmot	1:d0dfbce63a89	915
elmot	1:d0dfbce63a89	916	/**
elmot	1:d0dfbce63a89	917	* @brief SRAM2 page write protection unlock prior to erase
elmot	1:d0dfbce63a89	918	* @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP
elmot	1:d0dfbce63a89	919	* @retval None
elmot	1:d0dfbce63a89	920	*/
elmot	1:d0dfbce63a89	921	__STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
elmot	1:d0dfbce63a89	922	{
elmot	1:d0dfbce63a89	923	/* unlock the write protection of the SRAM2ER bit */
elmot	1:d0dfbce63a89	924	WRITE_REG(SYSCFG->SKR, 0xCA);
elmot	1:d0dfbce63a89	925	WRITE_REG(SYSCFG->SKR, 0x53);
elmot	1:d0dfbce63a89	926	}
elmot	1:d0dfbce63a89	927
elmot	1:d0dfbce63a89	928	/**
elmot	1:d0dfbce63a89	929	* @}
elmot	1:d0dfbce63a89	930	*/
elmot	1:d0dfbce63a89	931
elmot	1:d0dfbce63a89	932
elmot	1:d0dfbce63a89	933	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
elmot	1:d0dfbce63a89	934	* @{
elmot	1:d0dfbce63a89	935	*/
elmot	1:d0dfbce63a89	936
elmot	1:d0dfbce63a89	937	/**
elmot	1:d0dfbce63a89	938	* @brief Return the device identifier
elmot	1:d0dfbce63a89	939	* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
elmot	1:d0dfbce63a89	940	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
elmot	1:d0dfbce63a89	941	*/
elmot	1:d0dfbce63a89	942	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
elmot	1:d0dfbce63a89	943	{
elmot	1:d0dfbce63a89	944	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
elmot	1:d0dfbce63a89	945	}
elmot	1:d0dfbce63a89	946
elmot	1:d0dfbce63a89	947	/**
elmot	1:d0dfbce63a89	948	* @brief Return the device revision identifier
elmot	1:d0dfbce63a89	949	* @note This field indicates the revision of the device.
elmot	1:d0dfbce63a89	950	* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
elmot	1:d0dfbce63a89	951	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
elmot	1:d0dfbce63a89	952	*/
elmot	1:d0dfbce63a89	953	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
elmot	1:d0dfbce63a89	954	{
elmot	1:d0dfbce63a89	955	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION);
elmot	1:d0dfbce63a89	956	}
elmot	1:d0dfbce63a89	957
elmot	1:d0dfbce63a89	958	/**
elmot	1:d0dfbce63a89	959	* @brief Enable the Debug Module during SLEEP mode
elmot	1:d0dfbce63a89	960	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
elmot	1:d0dfbce63a89	961	* @retval None
elmot	1:d0dfbce63a89	962	*/
elmot	1:d0dfbce63a89	963	__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
elmot	1:d0dfbce63a89	964	{
elmot	1:d0dfbce63a89	965	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
elmot	1:d0dfbce63a89	966	}
elmot	1:d0dfbce63a89	967
elmot	1:d0dfbce63a89	968	/**
elmot	1:d0dfbce63a89	969	* @brief Disable the Debug Module during SLEEP mode
elmot	1:d0dfbce63a89	970	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
elmot	1:d0dfbce63a89	971	* @retval None
elmot	1:d0dfbce63a89	972	*/
elmot	1:d0dfbce63a89	973	__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
elmot	1:d0dfbce63a89	974	{
elmot	1:d0dfbce63a89	975	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
elmot	1:d0dfbce63a89	976	}
elmot	1:d0dfbce63a89	977
elmot	1:d0dfbce63a89	978	/**
elmot	1:d0dfbce63a89	979	* @brief Enable the Debug Module during STOP mode
elmot	1:d0dfbce63a89	980	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
elmot	1:d0dfbce63a89	981	* @retval None
elmot	1:d0dfbce63a89	982	*/
elmot	1:d0dfbce63a89	983	__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
elmot	1:d0dfbce63a89	984	{
elmot	1:d0dfbce63a89	985	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
elmot	1:d0dfbce63a89	986	}
elmot	1:d0dfbce63a89	987
elmot	1:d0dfbce63a89	988	/**
elmot	1:d0dfbce63a89	989	* @brief Disable the Debug Module during STOP mode
elmot	1:d0dfbce63a89	990	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
elmot	1:d0dfbce63a89	991	* @retval None
elmot	1:d0dfbce63a89	992	*/
elmot	1:d0dfbce63a89	993	__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
elmot	1:d0dfbce63a89	994	{
elmot	1:d0dfbce63a89	995	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
elmot	1:d0dfbce63a89	996	}
elmot	1:d0dfbce63a89	997
elmot	1:d0dfbce63a89	998	/**
elmot	1:d0dfbce63a89	999	* @brief Enable the Debug Module during STANDBY mode
elmot	1:d0dfbce63a89	1000	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
elmot	1:d0dfbce63a89	1001	* @retval None
elmot	1:d0dfbce63a89	1002	*/
elmot	1:d0dfbce63a89	1003	__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
elmot	1:d0dfbce63a89	1004	{
elmot	1:d0dfbce63a89	1005	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
elmot	1:d0dfbce63a89	1006	}
elmot	1:d0dfbce63a89	1007
elmot	1:d0dfbce63a89	1008	/**
elmot	1:d0dfbce63a89	1009	* @brief Disable the Debug Module during STANDBY mode
elmot	1:d0dfbce63a89	1010	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
elmot	1:d0dfbce63a89	1011	* @retval None
elmot	1:d0dfbce63a89	1012	*/
elmot	1:d0dfbce63a89	1013	__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
elmot	1:d0dfbce63a89	1014	{
elmot	1:d0dfbce63a89	1015	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
elmot	1:d0dfbce63a89	1016	}
elmot	1:d0dfbce63a89	1017
elmot	1:d0dfbce63a89	1018	/**
elmot	1:d0dfbce63a89	1019	* @brief Set Trace pin assignment control
elmot	1:d0dfbce63a89	1020	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
elmot	1:d0dfbce63a89	1021	* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
elmot	1:d0dfbce63a89	1022	* @param PinAssignment This parameter can be one of the following values:
elmot	1:d0dfbce63a89	1023	* @arg @ref LL_DBGMCU_TRACE_NONE
elmot	1:d0dfbce63a89	1024	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
elmot	1:d0dfbce63a89	1025	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
elmot	1:d0dfbce63a89	1026	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
elmot	1:d0dfbce63a89	1027	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
elmot	1:d0dfbce63a89	1028	* @retval None
elmot	1:d0dfbce63a89	1029	*/
elmot	1:d0dfbce63a89	1030	__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
elmot	1:d0dfbce63a89	1031	{
elmot	1:d0dfbce63a89	1032	MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE, PinAssignment);
elmot	1:d0dfbce63a89	1033	}
elmot	1:d0dfbce63a89	1034
elmot	1:d0dfbce63a89	1035	/**
elmot	1:d0dfbce63a89	1036	* @brief Get Trace pin assignment control
elmot	1:d0dfbce63a89	1037	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
elmot	1:d0dfbce63a89	1038	* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
elmot	1:d0dfbce63a89	1039	* @retval Returned value can be one of the following values:
elmot	1:d0dfbce63a89	1040	* @arg @ref LL_DBGMCU_TRACE_NONE
elmot	1:d0dfbce63a89	1041	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
elmot	1:d0dfbce63a89	1042	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
elmot	1:d0dfbce63a89	1043	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
elmot	1:d0dfbce63a89	1044	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
elmot	1:d0dfbce63a89	1045	*/
elmot	1:d0dfbce63a89	1046	__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
elmot	1:d0dfbce63a89	1047	{
elmot	1:d0dfbce63a89	1048	return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE));
elmot	1:d0dfbce63a89	1049	}
elmot	1:d0dfbce63a89	1050
elmot	1:d0dfbce63a89	1051	/**
elmot	1:d0dfbce63a89	1052	* @brief Freeze APB1 peripherals (group1 peripherals)
elmot	1:d0dfbce63a89	1053	* @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
elmot	1:d0dfbce63a89	1054	* @param Periphs This parameter can be a combination of the following values:
elmot	1:d0dfbce63a89	1055	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
elmot	1:d0dfbce63a89	1056	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
elmot	1:d0dfbce63a89	1057	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
elmot	1:d0dfbce63a89	1058	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
elmot	1:d0dfbce63a89	1059	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
elmot	1:d0dfbce63a89	1060	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
elmot	1:d0dfbce63a89	1061	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
elmot	1:d0dfbce63a89	1062	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
elmot	1:d0dfbce63a89	1063	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
elmot	1:d0dfbce63a89	1064	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
elmot	1:d0dfbce63a89	1065	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
elmot	1:d0dfbce63a89	1066	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
elmot	1:d0dfbce63a89	1067	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
elmot	1:d0dfbce63a89	1068	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
elmot	1:d0dfbce63a89	1069	*
elmot	1:d0dfbce63a89	1070	* (*) value not defined in all devices.
elmot	1:d0dfbce63a89	1071	* @retval None
elmot	1:d0dfbce63a89	1072	*/
elmot	1:d0dfbce63a89	1073	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
elmot	1:d0dfbce63a89	1074	{
elmot	1:d0dfbce63a89	1075	SET_BIT(DBGMCU->APB1FZR1, Periphs);
elmot	1:d0dfbce63a89	1076	}
elmot	1:d0dfbce63a89	1077
elmot	1:d0dfbce63a89	1078	/**
elmot	1:d0dfbce63a89	1079	* @brief Freeze APB1 peripherals (group2 peripherals)
elmot	1:d0dfbce63a89	1080	* @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
elmot	1:d0dfbce63a89	1081	* @param Periphs This parameter can be a combination of the following values:
elmot	1:d0dfbce63a89	1082	* @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
elmot	1:d0dfbce63a89	1083	* @retval None
elmot	1:d0dfbce63a89	1084	*/
elmot	1:d0dfbce63a89	1085	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
elmot	1:d0dfbce63a89	1086	{
elmot	1:d0dfbce63a89	1087	SET_BIT(DBGMCU->APB1FZR2, Periphs);
elmot	1:d0dfbce63a89	1088	}
elmot	1:d0dfbce63a89	1089
elmot	1:d0dfbce63a89	1090	/**
elmot	1:d0dfbce63a89	1091	* @brief Unfreeze APB1 peripherals (group1 peripherals)
elmot	1:d0dfbce63a89	1092	* @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
elmot	1:d0dfbce63a89	1093	* @param Periphs This parameter can be a combination of the following values:
elmot	1:d0dfbce63a89	1094	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
elmot	1:d0dfbce63a89	1095	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
elmot	1:d0dfbce63a89	1096	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
elmot	1:d0dfbce63a89	1097	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
elmot	1:d0dfbce63a89	1098	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
elmot	1:d0dfbce63a89	1099	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
elmot	1:d0dfbce63a89	1100	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
elmot	1:d0dfbce63a89	1101	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
elmot	1:d0dfbce63a89	1102	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
elmot	1:d0dfbce63a89	1103	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
elmot	1:d0dfbce63a89	1104	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
elmot	1:d0dfbce63a89	1105	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
elmot	1:d0dfbce63a89	1106	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
elmot	1:d0dfbce63a89	1107	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
elmot	1:d0dfbce63a89	1108	*
elmot	1:d0dfbce63a89	1109	* (*) value not defined in all devices.
elmot	1:d0dfbce63a89	1110	* @retval None
elmot	1:d0dfbce63a89	1111	*/
elmot	1:d0dfbce63a89	1112	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
elmot	1:d0dfbce63a89	1113	{
elmot	1:d0dfbce63a89	1114	CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
elmot	1:d0dfbce63a89	1115	}
elmot	1:d0dfbce63a89	1116
elmot	1:d0dfbce63a89	1117	/**
elmot	1:d0dfbce63a89	1118	* @brief Unfreeze APB1 peripherals (group2 peripherals)
elmot	1:d0dfbce63a89	1119	* @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
elmot	1:d0dfbce63a89	1120	* @param Periphs This parameter can be a combination of the following values:
elmot	1:d0dfbce63a89	1121	* @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
elmot	1:d0dfbce63a89	1122	* @retval None
elmot	1:d0dfbce63a89	1123	*/
elmot	1:d0dfbce63a89	1124	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
elmot	1:d0dfbce63a89	1125	{
elmot	1:d0dfbce63a89	1126	CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
elmot	1:d0dfbce63a89	1127	}
elmot	1:d0dfbce63a89	1128
elmot	1:d0dfbce63a89	1129	/**
elmot	1:d0dfbce63a89	1130	* @brief Freeze APB2 peripherals
elmot	1:d0dfbce63a89	1131	* @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
elmot	1:d0dfbce63a89	1132	* @param Periphs This parameter can be a combination of the following values:
elmot	1:d0dfbce63a89	1133	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
elmot	1:d0dfbce63a89	1134	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
elmot	1:d0dfbce63a89	1135	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
elmot	1:d0dfbce63a89	1136	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
elmot	1:d0dfbce63a89	1137	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
elmot	1:d0dfbce63a89	1138	*
elmot	1:d0dfbce63a89	1139	* (*) value not defined in all devices.
elmot	1:d0dfbce63a89	1140	* @retval None
elmot	1:d0dfbce63a89	1141	*/
elmot	1:d0dfbce63a89	1142	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
elmot	1:d0dfbce63a89	1143	{
elmot	1:d0dfbce63a89	1144	SET_BIT(DBGMCU->APB2FZ, Periphs);
elmot	1:d0dfbce63a89	1145	}
elmot	1:d0dfbce63a89	1146
elmot	1:d0dfbce63a89	1147	/**
elmot	1:d0dfbce63a89	1148	* @brief Unfreeze APB2 peripherals
elmot	1:d0dfbce63a89	1149	* @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
elmot	1:d0dfbce63a89	1150	* @param Periphs This parameter can be a combination of the following values:
elmot	1:d0dfbce63a89	1151	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
elmot	1:d0dfbce63a89	1152	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
elmot	1:d0dfbce63a89	1153	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
elmot	1:d0dfbce63a89	1154	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
elmot	1:d0dfbce63a89	1155	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
elmot	1:d0dfbce63a89	1156	*
elmot	1:d0dfbce63a89	1157	* (*) value not defined in all devices.
elmot	1:d0dfbce63a89	1158	* @retval None
elmot	1:d0dfbce63a89	1159	*/
elmot	1:d0dfbce63a89	1160	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
elmot	1:d0dfbce63a89	1161	{
elmot	1:d0dfbce63a89	1162	CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
elmot	1:d0dfbce63a89	1163	}
elmot	1:d0dfbce63a89	1164
elmot	1:d0dfbce63a89	1165	/**
elmot	1:d0dfbce63a89	1166	* @}
elmot	1:d0dfbce63a89	1167	*/
elmot	1:d0dfbce63a89	1168
elmot	1:d0dfbce63a89	1169	#if defined(VREFBUF)
elmot	1:d0dfbce63a89	1170	/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
elmot	1:d0dfbce63a89	1171	* @{
elmot	1:d0dfbce63a89	1172	*/
elmot	1:d0dfbce63a89	1173
elmot	1:d0dfbce63a89	1174	/**
elmot	1:d0dfbce63a89	1175	* @brief Enable Internal voltage reference
elmot	1:d0dfbce63a89	1176	* @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
elmot	1:d0dfbce63a89	1177	* @retval None
elmot	1:d0dfbce63a89	1178	*/
elmot	1:d0dfbce63a89	1179	__STATIC_INLINE void LL_VREFBUF_Enable(void)
elmot	1:d0dfbce63a89	1180	{
elmot	1:d0dfbce63a89	1181	SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
elmot	1:d0dfbce63a89	1182	}
elmot	1:d0dfbce63a89	1183
elmot	1:d0dfbce63a89	1184	/**
elmot	1:d0dfbce63a89	1185	* @brief Disable Internal voltage reference
elmot	1:d0dfbce63a89	1186	* @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
elmot	1:d0dfbce63a89	1187	* @retval None
elmot	1:d0dfbce63a89	1188	*/
elmot	1:d0dfbce63a89	1189	__STATIC_INLINE void LL_VREFBUF_Disable(void)
elmot	1:d0dfbce63a89	1190	{
elmot	1:d0dfbce63a89	1191	CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
elmot	1:d0dfbce63a89	1192	}
elmot	1:d0dfbce63a89	1193
elmot	1:d0dfbce63a89	1194	/**
elmot	1:d0dfbce63a89	1195	* @brief Enable high impedance (VREF+pin is high impedance)
elmot	1:d0dfbce63a89	1196	* @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
elmot	1:d0dfbce63a89	1197	* @retval None
elmot	1:d0dfbce63a89	1198	*/
elmot	1:d0dfbce63a89	1199	__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
elmot	1:d0dfbce63a89	1200	{
elmot	1:d0dfbce63a89	1201	SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
elmot	1:d0dfbce63a89	1202	}
elmot	1:d0dfbce63a89	1203
elmot	1:d0dfbce63a89	1204	/**
elmot	1:d0dfbce63a89	1205	* @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
elmot	1:d0dfbce63a89	1206	* @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
elmot	1:d0dfbce63a89	1207	* @retval None
elmot	1:d0dfbce63a89	1208	*/
elmot	1:d0dfbce63a89	1209	__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
elmot	1:d0dfbce63a89	1210	{
elmot	1:d0dfbce63a89	1211	CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
elmot	1:d0dfbce63a89	1212	}
elmot	1:d0dfbce63a89	1213
elmot	1:d0dfbce63a89	1214	/**
elmot	1:d0dfbce63a89	1215	* @brief Set the Voltage reference scale
elmot	1:d0dfbce63a89	1216	* @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
elmot	1:d0dfbce63a89	1217	* @param Scale This parameter can be one of the following values:
elmot	1:d0dfbce63a89	1218	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
elmot	1:d0dfbce63a89	1219	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
elmot	1:d0dfbce63a89	1220	* @retval None
elmot	1:d0dfbce63a89	1221	*/
elmot	1:d0dfbce63a89	1222	__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
elmot	1:d0dfbce63a89	1223	{
elmot	1:d0dfbce63a89	1224	MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
elmot	1:d0dfbce63a89	1225	}
elmot	1:d0dfbce63a89	1226
elmot	1:d0dfbce63a89	1227	/**
elmot	1:d0dfbce63a89	1228	* @brief Get the Voltage reference scale
elmot	1:d0dfbce63a89	1229	* @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
elmot	1:d0dfbce63a89	1230	* @retval Returned value can be one of the following values:
elmot	1:d0dfbce63a89	1231	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
elmot	1:d0dfbce63a89	1232	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
elmot	1:d0dfbce63a89	1233	*/
elmot	1:d0dfbce63a89	1234	__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
elmot	1:d0dfbce63a89	1235	{
elmot	1:d0dfbce63a89	1236	return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
elmot	1:d0dfbce63a89	1237	}
elmot	1:d0dfbce63a89	1238
elmot	1:d0dfbce63a89	1239	/**
elmot	1:d0dfbce63a89	1240	* @brief Check if Voltage reference buffer is ready
elmot	1:d0dfbce63a89	1241	* @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
elmot	1:d0dfbce63a89	1242	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1243	*/
elmot	1:d0dfbce63a89	1244	__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
elmot	1:d0dfbce63a89	1245	{
elmot	1:d0dfbce63a89	1246	return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR));
elmot	1:d0dfbce63a89	1247	}
elmot	1:d0dfbce63a89	1248
elmot	1:d0dfbce63a89	1249	/**
elmot	1:d0dfbce63a89	1250	* @brief Get the trimming code for VREFBUF calibration
elmot	1:d0dfbce63a89	1251	* @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
elmot	1:d0dfbce63a89	1252	* @retval Between 0 and 0x3F
elmot	1:d0dfbce63a89	1253	*/
elmot	1:d0dfbce63a89	1254	__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
elmot	1:d0dfbce63a89	1255	{
elmot	1:d0dfbce63a89	1256	return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
elmot	1:d0dfbce63a89	1257	}
elmot	1:d0dfbce63a89	1258
elmot	1:d0dfbce63a89	1259	/**
elmot	1:d0dfbce63a89	1260	* @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
elmot	1:d0dfbce63a89	1261	* @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
elmot	1:d0dfbce63a89	1262	* @param Value Between 0 and 0x3F
elmot	1:d0dfbce63a89	1263	* @retval None
elmot	1:d0dfbce63a89	1264	*/
elmot	1:d0dfbce63a89	1265	__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
elmot	1:d0dfbce63a89	1266	{
elmot	1:d0dfbce63a89	1267	WRITE_REG(VREFBUF->CCR, Value);
elmot	1:d0dfbce63a89	1268	}
elmot	1:d0dfbce63a89	1269
elmot	1:d0dfbce63a89	1270	/**
elmot	1:d0dfbce63a89	1271	* @}
elmot	1:d0dfbce63a89	1272	*/
elmot	1:d0dfbce63a89	1273	#endif /* VREFBUF */
elmot	1:d0dfbce63a89	1274
elmot	1:d0dfbce63a89	1275	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
elmot	1:d0dfbce63a89	1276	* @{
elmot	1:d0dfbce63a89	1277	*/
elmot	1:d0dfbce63a89	1278
elmot	1:d0dfbce63a89	1279	/**
elmot	1:d0dfbce63a89	1280	* @brief Set FLASH Latency
elmot	1:d0dfbce63a89	1281	* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
elmot	1:d0dfbce63a89	1282	* @param Latency This parameter can be one of the following values:
elmot	1:d0dfbce63a89	1283	* @arg @ref LL_FLASH_LATENCY_0
elmot	1:d0dfbce63a89	1284	* @arg @ref LL_FLASH_LATENCY_1
elmot	1:d0dfbce63a89	1285	* @arg @ref LL_FLASH_LATENCY_2
elmot	1:d0dfbce63a89	1286	* @arg @ref LL_FLASH_LATENCY_3
elmot	1:d0dfbce63a89	1287	* @arg @ref LL_FLASH_LATENCY_4
elmot	1:d0dfbce63a89	1288	* @retval None
elmot	1:d0dfbce63a89	1289	*/
elmot	1:d0dfbce63a89	1290	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
elmot	1:d0dfbce63a89	1291	{
elmot	1:d0dfbce63a89	1292	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
elmot	1:d0dfbce63a89	1293	}
elmot	1:d0dfbce63a89	1294
elmot	1:d0dfbce63a89	1295	/**
elmot	1:d0dfbce63a89	1296	* @brief Get FLASH Latency
elmot	1:d0dfbce63a89	1297	* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
elmot	1:d0dfbce63a89	1298	* @retval Returned value can be one of the following values:
elmot	1:d0dfbce63a89	1299	* @arg @ref LL_FLASH_LATENCY_0
elmot	1:d0dfbce63a89	1300	* @arg @ref LL_FLASH_LATENCY_1
elmot	1:d0dfbce63a89	1301	* @arg @ref LL_FLASH_LATENCY_2
elmot	1:d0dfbce63a89	1302	* @arg @ref LL_FLASH_LATENCY_3
elmot	1:d0dfbce63a89	1303	* @arg @ref LL_FLASH_LATENCY_4
elmot	1:d0dfbce63a89	1304	*/
elmot	1:d0dfbce63a89	1305	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
elmot	1:d0dfbce63a89	1306	{
elmot	1:d0dfbce63a89	1307	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
elmot	1:d0dfbce63a89	1308	}
elmot	1:d0dfbce63a89	1309
elmot	1:d0dfbce63a89	1310	/**
elmot	1:d0dfbce63a89	1311	* @brief Enable Prefetch
elmot	1:d0dfbce63a89	1312	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
elmot	1:d0dfbce63a89	1313	* @retval None
elmot	1:d0dfbce63a89	1314	*/
elmot	1:d0dfbce63a89	1315	__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
elmot	1:d0dfbce63a89	1316	{
elmot	1:d0dfbce63a89	1317	SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
elmot	1:d0dfbce63a89	1318	}
elmot	1:d0dfbce63a89	1319
elmot	1:d0dfbce63a89	1320	/**
elmot	1:d0dfbce63a89	1321	* @brief Disable Prefetch
elmot	1:d0dfbce63a89	1322	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
elmot	1:d0dfbce63a89	1323	* @retval None
elmot	1:d0dfbce63a89	1324	*/
elmot	1:d0dfbce63a89	1325	__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
elmot	1:d0dfbce63a89	1326	{
elmot	1:d0dfbce63a89	1327	CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
elmot	1:d0dfbce63a89	1328	}
elmot	1:d0dfbce63a89	1329
elmot	1:d0dfbce63a89	1330	/**
elmot	1:d0dfbce63a89	1331	* @brief Check if Prefetch buffer is enabled
elmot	1:d0dfbce63a89	1332	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
elmot	1:d0dfbce63a89	1333	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1334	*/
elmot	1:d0dfbce63a89	1335	__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
elmot	1:d0dfbce63a89	1336	{
elmot	1:d0dfbce63a89	1337	return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
elmot	1:d0dfbce63a89	1338	}
elmot	1:d0dfbce63a89	1339
elmot	1:d0dfbce63a89	1340	/**
elmot	1:d0dfbce63a89	1341	* @brief Enable Instruction cache
elmot	1:d0dfbce63a89	1342	* @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
elmot	1:d0dfbce63a89	1343	* @retval None
elmot	1:d0dfbce63a89	1344	*/
elmot	1:d0dfbce63a89	1345	__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
elmot	1:d0dfbce63a89	1346	{
elmot	1:d0dfbce63a89	1347	SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
elmot	1:d0dfbce63a89	1348	}
elmot	1:d0dfbce63a89	1349
elmot	1:d0dfbce63a89	1350	/**
elmot	1:d0dfbce63a89	1351	* @brief Disable Instruction cache
elmot	1:d0dfbce63a89	1352	* @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
elmot	1:d0dfbce63a89	1353	* @retval None
elmot	1:d0dfbce63a89	1354	*/
elmot	1:d0dfbce63a89	1355	__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
elmot	1:d0dfbce63a89	1356	{
elmot	1:d0dfbce63a89	1357	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
elmot	1:d0dfbce63a89	1358	}
elmot	1:d0dfbce63a89	1359
elmot	1:d0dfbce63a89	1360	/**
elmot	1:d0dfbce63a89	1361	* @brief Enable Data cache
elmot	1:d0dfbce63a89	1362	* @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
elmot	1:d0dfbce63a89	1363	* @retval None
elmot	1:d0dfbce63a89	1364	*/
elmot	1:d0dfbce63a89	1365	__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
elmot	1:d0dfbce63a89	1366	{
elmot	1:d0dfbce63a89	1367	SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
elmot	1:d0dfbce63a89	1368	}
elmot	1:d0dfbce63a89	1369
elmot	1:d0dfbce63a89	1370	/**
elmot	1:d0dfbce63a89	1371	* @brief Disable Data cache
elmot	1:d0dfbce63a89	1372	* @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
elmot	1:d0dfbce63a89	1373	* @retval None
elmot	1:d0dfbce63a89	1374	*/
elmot	1:d0dfbce63a89	1375	__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
elmot	1:d0dfbce63a89	1376	{
elmot	1:d0dfbce63a89	1377	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
elmot	1:d0dfbce63a89	1378	}
elmot	1:d0dfbce63a89	1379
elmot	1:d0dfbce63a89	1380	/**
elmot	1:d0dfbce63a89	1381	* @brief Enable Instruction cache reset
elmot	1:d0dfbce63a89	1382	* @note bit can be written only when the instruction cache is disabled
elmot	1:d0dfbce63a89	1383	* @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
elmot	1:d0dfbce63a89	1384	* @retval None
elmot	1:d0dfbce63a89	1385	*/
elmot	1:d0dfbce63a89	1386	__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
elmot	1:d0dfbce63a89	1387	{
elmot	1:d0dfbce63a89	1388	SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
elmot	1:d0dfbce63a89	1389	}
elmot	1:d0dfbce63a89	1390
elmot	1:d0dfbce63a89	1391	/**
elmot	1:d0dfbce63a89	1392	* @brief Disable Instruction cache reset
elmot	1:d0dfbce63a89	1393	* @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
elmot	1:d0dfbce63a89	1394	* @retval None
elmot	1:d0dfbce63a89	1395	*/
elmot	1:d0dfbce63a89	1396	__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
elmot	1:d0dfbce63a89	1397	{
elmot	1:d0dfbce63a89	1398	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
elmot	1:d0dfbce63a89	1399	}
elmot	1:d0dfbce63a89	1400
elmot	1:d0dfbce63a89	1401	/**
elmot	1:d0dfbce63a89	1402	* @brief Enable Data cache reset
elmot	1:d0dfbce63a89	1403	* @note bit can be written only when the data cache is disabled
elmot	1:d0dfbce63a89	1404	* @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
elmot	1:d0dfbce63a89	1405	* @retval None
elmot	1:d0dfbce63a89	1406	*/
elmot	1:d0dfbce63a89	1407	__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
elmot	1:d0dfbce63a89	1408	{
elmot	1:d0dfbce63a89	1409	SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
elmot	1:d0dfbce63a89	1410	}
elmot	1:d0dfbce63a89	1411
elmot	1:d0dfbce63a89	1412	/**
elmot	1:d0dfbce63a89	1413	* @brief Disable Data cache reset
elmot	1:d0dfbce63a89	1414	* @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
elmot	1:d0dfbce63a89	1415	* @retval None
elmot	1:d0dfbce63a89	1416	*/
elmot	1:d0dfbce63a89	1417	__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
elmot	1:d0dfbce63a89	1418	{
elmot	1:d0dfbce63a89	1419	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
elmot	1:d0dfbce63a89	1420	}
elmot	1:d0dfbce63a89	1421
elmot	1:d0dfbce63a89	1422	/**
elmot	1:d0dfbce63a89	1423	* @brief Enable Flash Power-down mode during run mode or Low-power run mode
elmot	1:d0dfbce63a89	1424	* @note Flash memory can be put in power-down mode only when the code is executed
elmot	1:d0dfbce63a89	1425	* from RAM
elmot	1:d0dfbce63a89	1426	* @note Flash must not be accessed when power down is enabled
elmot	1:d0dfbce63a89	1427	* @note Flash must not be put in power-down while a program or an erase operation
elmot	1:d0dfbce63a89	1428	* is on-going
elmot	1:d0dfbce63a89	1429	* @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
elmot	1:d0dfbce63a89	1430	* FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
elmot	1:d0dfbce63a89	1431	* FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
elmot	1:d0dfbce63a89	1432	* @retval None
elmot	1:d0dfbce63a89	1433	*/
elmot	1:d0dfbce63a89	1434	__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
elmot	1:d0dfbce63a89	1435	{
elmot	1:d0dfbce63a89	1436	/* Following values must be written consecutively to unlock the RUN_PD bit in
elmot	1:d0dfbce63a89	1437	FLASH_ACR */
elmot	1:d0dfbce63a89	1438	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
elmot	1:d0dfbce63a89	1439	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
elmot	1:d0dfbce63a89	1440	SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
elmot	1:d0dfbce63a89	1441	}
elmot	1:d0dfbce63a89	1442
elmot	1:d0dfbce63a89	1443	/**
elmot	1:d0dfbce63a89	1444	* @brief Disable Flash Power-down mode during run mode or Low-power run mode
elmot	1:d0dfbce63a89	1445	* @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
elmot	1:d0dfbce63a89	1446	* FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
elmot	1:d0dfbce63a89	1447	* FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
elmot	1:d0dfbce63a89	1448	* @retval None
elmot	1:d0dfbce63a89	1449	*/
elmot	1:d0dfbce63a89	1450	__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
elmot	1:d0dfbce63a89	1451	{
elmot	1:d0dfbce63a89	1452	/* Following values must be written consecutively to unlock the RUN_PD bit in
elmot	1:d0dfbce63a89	1453	FLASH_ACR */
elmot	1:d0dfbce63a89	1454	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
elmot	1:d0dfbce63a89	1455	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
elmot	1:d0dfbce63a89	1456	CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
elmot	1:d0dfbce63a89	1457	}
elmot	1:d0dfbce63a89	1458
elmot	1:d0dfbce63a89	1459	/**
elmot	1:d0dfbce63a89	1460	* @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
elmot	1:d0dfbce63a89	1461	* @note Flash must not be put in power-down while a program or an erase operation
elmot	1:d0dfbce63a89	1462	* is on-going
elmot	1:d0dfbce63a89	1463	* @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
elmot	1:d0dfbce63a89	1464	* @retval None
elmot	1:d0dfbce63a89	1465	*/
elmot	1:d0dfbce63a89	1466	__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
elmot	1:d0dfbce63a89	1467	{
elmot	1:d0dfbce63a89	1468	SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
elmot	1:d0dfbce63a89	1469	}
elmot	1:d0dfbce63a89	1470
elmot	1:d0dfbce63a89	1471	/**
elmot	1:d0dfbce63a89	1472	* @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
elmot	1:d0dfbce63a89	1473	* @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
elmot	1:d0dfbce63a89	1474	* @retval None
elmot	1:d0dfbce63a89	1475	*/
elmot	1:d0dfbce63a89	1476	__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
elmot	1:d0dfbce63a89	1477	{
elmot	1:d0dfbce63a89	1478	CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
elmot	1:d0dfbce63a89	1479	}
elmot	1:d0dfbce63a89	1480
elmot	1:d0dfbce63a89	1481	/**
elmot	1:d0dfbce63a89	1482	* @}
elmot	1:d0dfbce63a89	1483	*/
elmot	1:d0dfbce63a89	1484
elmot	1:d0dfbce63a89	1485	/**
elmot	1:d0dfbce63a89	1486	* @}
elmot	1:d0dfbce63a89	1487	*/
elmot	1:d0dfbce63a89	1488
elmot	1:d0dfbce63a89	1489	/**
elmot	1:d0dfbce63a89	1490	* @}
elmot	1:d0dfbce63a89	1491	*/
elmot	1:d0dfbce63a89	1492
elmot	1:d0dfbce63a89	1493	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) \|\| defined (VREFBUF) */
elmot	1:d0dfbce63a89	1494
elmot	1:d0dfbce63a89	1495	/**
elmot	1:d0dfbce63a89	1496	* @}
elmot	1:d0dfbce63a89	1497	*/
elmot	1:d0dfbce63a89	1498
elmot	1:d0dfbce63a89	1499	#ifdef __cplusplus
elmot	1:d0dfbce63a89	1500	}
elmot	1:d0dfbce63a89	1501	#endif
elmot	1:d0dfbce63a89	1502
elmot	1:d0dfbce63a89	1503	#endif /* __STM32L4xx_LL_SYSTEM_H */
elmot	1:d0dfbce63a89	1504
elmot	1:d0dfbce63a89	1505	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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