TUKS MCU Introductory course / TUKS-COURSE-THERMOMETER

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of TUKS-COURSE-TIMER by TUKS MCU Introductory course

HAL_L476/stm32l4xx_hal_rcc_ex.h@1:d0dfbce63a89, 2017-02-24 (annotated)

Committer:
elmot
Date:
Fri Feb 24 21:13:56 2017 +0000
Revision:
1:d0dfbce63a89
Ready-to-copy

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elmot 1:d0dfbce63a89 1 /**
elmot 1:d0dfbce63a89 2 ******************************************************************************
elmot 1:d0dfbce63a89 3 * @file stm32l4xx_hal_rcc_ex.h
elmot 1:d0dfbce63a89 4 * @author MCD Application Team
elmot 1:d0dfbce63a89 5 * @version V1.5.1
elmot 1:d0dfbce63a89 6 * @date 31-May-2016
elmot 1:d0dfbce63a89 7 * @brief Header file of RCC HAL Extended module.
elmot 1:d0dfbce63a89 8 ******************************************************************************
elmot 1:d0dfbce63a89 9 * @attention
elmot 1:d0dfbce63a89 10 *
elmot 1:d0dfbce63a89 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
elmot 1:d0dfbce63a89 12 *
elmot 1:d0dfbce63a89 13 * Redistribution and use in source and binary forms, with or without modification,
elmot 1:d0dfbce63a89 14 * are permitted provided that the following conditions are met:
elmot 1:d0dfbce63a89 15 * 1. Redistributions of source code must retain the above copyright notice,
elmot 1:d0dfbce63a89 16 * this list of conditions and the following disclaimer.
elmot 1:d0dfbce63a89 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
elmot 1:d0dfbce63a89 18 * this list of conditions and the following disclaimer in the documentation
elmot 1:d0dfbce63a89 19 * and/or other materials provided with the distribution.
elmot 1:d0dfbce63a89 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
elmot 1:d0dfbce63a89 21 * may be used to endorse or promote products derived from this software
elmot 1:d0dfbce63a89 22 * without specific prior written permission.
elmot 1:d0dfbce63a89 23 *
elmot 1:d0dfbce63a89 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elmot 1:d0dfbce63a89 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elmot 1:d0dfbce63a89 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elmot 1:d0dfbce63a89 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
elmot 1:d0dfbce63a89 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
elmot 1:d0dfbce63a89 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
elmot 1:d0dfbce63a89 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
elmot 1:d0dfbce63a89 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
elmot 1:d0dfbce63a89 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
elmot 1:d0dfbce63a89 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elmot 1:d0dfbce63a89 34 *
elmot 1:d0dfbce63a89 35 ******************************************************************************
elmot 1:d0dfbce63a89 36 */
elmot 1:d0dfbce63a89 37
elmot 1:d0dfbce63a89 38 /* Define to prevent recursive inclusion -------------------------------------*/
elmot 1:d0dfbce63a89 39 #ifndef __STM32L4xx_HAL_RCC_EX_H
elmot 1:d0dfbce63a89 40 #define __STM32L4xx_HAL_RCC_EX_H
elmot 1:d0dfbce63a89 41
elmot 1:d0dfbce63a89 42 #ifdef __cplusplus
elmot 1:d0dfbce63a89 43 extern "C" {
elmot 1:d0dfbce63a89 44 #endif
elmot 1:d0dfbce63a89 45
elmot 1:d0dfbce63a89 46 /* Includes ------------------------------------------------------------------*/
elmot 1:d0dfbce63a89 47 #include "stm32l4xx_hal_def.h"
elmot 1:d0dfbce63a89 48
elmot 1:d0dfbce63a89 49 /** @addtogroup STM32L4xx_HAL_Driver
elmot 1:d0dfbce63a89 50 * @{
elmot 1:d0dfbce63a89 51 */
elmot 1:d0dfbce63a89 52
elmot 1:d0dfbce63a89 53 /** @addtogroup RCCEx
elmot 1:d0dfbce63a89 54 * @{
elmot 1:d0dfbce63a89 55 */
elmot 1:d0dfbce63a89 56
elmot 1:d0dfbce63a89 57 /* Exported types ------------------------------------------------------------*/
elmot 1:d0dfbce63a89 58
elmot 1:d0dfbce63a89 59 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
elmot 1:d0dfbce63a89 60 * @{
elmot 1:d0dfbce63a89 61 */
elmot 1:d0dfbce63a89 62
elmot 1:d0dfbce63a89 63 /**
elmot 1:d0dfbce63a89 64 * @brief PLLSAI1 Clock structure definition
elmot 1:d0dfbce63a89 65 */
elmot 1:d0dfbce63a89 66 typedef struct
elmot 1:d0dfbce63a89 67 {
elmot 1:d0dfbce63a89 68
elmot 1:d0dfbce63a89 69 uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source.
elmot 1:d0dfbce63a89 70 This parameter must be a value of @ref RCC_PLL_Clock_Source */
elmot 1:d0dfbce63a89 71
elmot 1:d0dfbce63a89 72 uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock.
elmot 1:d0dfbce63a89 73 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
elmot 1:d0dfbce63a89 74
elmot 1:d0dfbce63a89 75 uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock.
elmot 1:d0dfbce63a89 76 This parameter must be a number between 8 and 86 or 127 depending on devices. */
elmot 1:d0dfbce63a89 77
elmot 1:d0dfbce63a89 78 uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock.
elmot 1:d0dfbce63a89 79 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
elmot 1:d0dfbce63a89 80
elmot 1:d0dfbce63a89 81 uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock.
elmot 1:d0dfbce63a89 82 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
elmot 1:d0dfbce63a89 83
elmot 1:d0dfbce63a89 84 uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock.
elmot 1:d0dfbce63a89 85 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
elmot 1:d0dfbce63a89 86
elmot 1:d0dfbce63a89 87 uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled.
elmot 1:d0dfbce63a89 88 This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */
elmot 1:d0dfbce63a89 89 }RCC_PLLSAI1InitTypeDef;
elmot 1:d0dfbce63a89 90
elmot 1:d0dfbce63a89 91 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 92
elmot 1:d0dfbce63a89 93 /**
elmot 1:d0dfbce63a89 94 * @brief PLLSAI2 Clock structure definition
elmot 1:d0dfbce63a89 95 */
elmot 1:d0dfbce63a89 96 typedef struct
elmot 1:d0dfbce63a89 97 {
elmot 1:d0dfbce63a89 98
elmot 1:d0dfbce63a89 99 uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source.
elmot 1:d0dfbce63a89 100 This parameter must be a value of @ref RCC_PLL_Clock_Source */
elmot 1:d0dfbce63a89 101
elmot 1:d0dfbce63a89 102 uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock.
elmot 1:d0dfbce63a89 103 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
elmot 1:d0dfbce63a89 104
elmot 1:d0dfbce63a89 105 uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock.
elmot 1:d0dfbce63a89 106 This parameter must be a number between 8 and 86 or 127 depending on devices. */
elmot 1:d0dfbce63a89 107
elmot 1:d0dfbce63a89 108 uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock.
elmot 1:d0dfbce63a89 109 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
elmot 1:d0dfbce63a89 110
elmot 1:d0dfbce63a89 111 uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock.
elmot 1:d0dfbce63a89 112 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
elmot 1:d0dfbce63a89 113
elmot 1:d0dfbce63a89 114 uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled.
elmot 1:d0dfbce63a89 115 This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */
elmot 1:d0dfbce63a89 116 }RCC_PLLSAI2InitTypeDef;
elmot 1:d0dfbce63a89 117
elmot 1:d0dfbce63a89 118 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 119
elmot 1:d0dfbce63a89 120 /**
elmot 1:d0dfbce63a89 121 * @brief RCC extended clocks structure definition
elmot 1:d0dfbce63a89 122 */
elmot 1:d0dfbce63a89 123 typedef struct
elmot 1:d0dfbce63a89 124 {
elmot 1:d0dfbce63a89 125 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
elmot 1:d0dfbce63a89 126 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
elmot 1:d0dfbce63a89 127
elmot 1:d0dfbce63a89 128 RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters.
elmot 1:d0dfbce63a89 129 This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */
elmot 1:d0dfbce63a89 130
elmot 1:d0dfbce63a89 131 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 132
elmot 1:d0dfbce63a89 133 RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters.
elmot 1:d0dfbce63a89 134 This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */
elmot 1:d0dfbce63a89 135
elmot 1:d0dfbce63a89 136 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 137
elmot 1:d0dfbce63a89 138 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source.
elmot 1:d0dfbce63a89 139 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
elmot 1:d0dfbce63a89 140
elmot 1:d0dfbce63a89 141 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source.
elmot 1:d0dfbce63a89 142 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
elmot 1:d0dfbce63a89 143
elmot 1:d0dfbce63a89 144 #if defined(USART3)
elmot 1:d0dfbce63a89 145
elmot 1:d0dfbce63a89 146 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source.
elmot 1:d0dfbce63a89 147 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
elmot 1:d0dfbce63a89 148
elmot 1:d0dfbce63a89 149 #endif /* USART3 */
elmot 1:d0dfbce63a89 150
elmot 1:d0dfbce63a89 151 #if defined(UART4)
elmot 1:d0dfbce63a89 152
elmot 1:d0dfbce63a89 153 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source.
elmot 1:d0dfbce63a89 154 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
elmot 1:d0dfbce63a89 155
elmot 1:d0dfbce63a89 156 #endif /* UART4 */
elmot 1:d0dfbce63a89 157
elmot 1:d0dfbce63a89 158 #if defined(UART5)
elmot 1:d0dfbce63a89 159
elmot 1:d0dfbce63a89 160 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source.
elmot 1:d0dfbce63a89 161 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
elmot 1:d0dfbce63a89 162
elmot 1:d0dfbce63a89 163 #endif /* UART5 */
elmot 1:d0dfbce63a89 164
elmot 1:d0dfbce63a89 165 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source.
elmot 1:d0dfbce63a89 166 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
elmot 1:d0dfbce63a89 167
elmot 1:d0dfbce63a89 168 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source.
elmot 1:d0dfbce63a89 169 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
elmot 1:d0dfbce63a89 170
elmot 1:d0dfbce63a89 171 #if defined(I2C2)
elmot 1:d0dfbce63a89 172
elmot 1:d0dfbce63a89 173 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source.
elmot 1:d0dfbce63a89 174 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
elmot 1:d0dfbce63a89 175
elmot 1:d0dfbce63a89 176 #endif /* I2C2 */
elmot 1:d0dfbce63a89 177
elmot 1:d0dfbce63a89 178 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source.
elmot 1:d0dfbce63a89 179 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
elmot 1:d0dfbce63a89 180
elmot 1:d0dfbce63a89 181 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source.
elmot 1:d0dfbce63a89 182 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
elmot 1:d0dfbce63a89 183
elmot 1:d0dfbce63a89 184 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source.
elmot 1:d0dfbce63a89 185 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
elmot 1:d0dfbce63a89 186
elmot 1:d0dfbce63a89 187 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source.
elmot 1:d0dfbce63a89 188 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
elmot 1:d0dfbce63a89 189
elmot 1:d0dfbce63a89 190 #if defined(SAI2)
elmot 1:d0dfbce63a89 191
elmot 1:d0dfbce63a89 192 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source.
elmot 1:d0dfbce63a89 193 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
elmot 1:d0dfbce63a89 194
elmot 1:d0dfbce63a89 195 #endif /* SAI2 */
elmot 1:d0dfbce63a89 196
elmot 1:d0dfbce63a89 197 #if defined(USB_OTG_FS) || defined(USB)
elmot 1:d0dfbce63a89 198
elmot 1:d0dfbce63a89 199 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG).
elmot 1:d0dfbce63a89 200 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
elmot 1:d0dfbce63a89 201
elmot 1:d0dfbce63a89 202 #endif /* USB_OTG_FS || USB */
elmot 1:d0dfbce63a89 203
elmot 1:d0dfbce63a89 204 #if defined(SDMMC1)
elmot 1:d0dfbce63a89 205
elmot 1:d0dfbce63a89 206 uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG).
elmot 1:d0dfbce63a89 207 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
elmot 1:d0dfbce63a89 208
elmot 1:d0dfbce63a89 209 #endif /* SDMMC1 */
elmot 1:d0dfbce63a89 210
elmot 1:d0dfbce63a89 211 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1).
elmot 1:d0dfbce63a89 212 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
elmot 1:d0dfbce63a89 213
elmot 1:d0dfbce63a89 214 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source.
elmot 1:d0dfbce63a89 215 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
elmot 1:d0dfbce63a89 216
elmot 1:d0dfbce63a89 217 #if defined(SWPMI1)
elmot 1:d0dfbce63a89 218
elmot 1:d0dfbce63a89 219 uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source.
elmot 1:d0dfbce63a89 220 This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */
elmot 1:d0dfbce63a89 221
elmot 1:d0dfbce63a89 222 #endif /* SWPMI1 */
elmot 1:d0dfbce63a89 223
elmot 1:d0dfbce63a89 224 #if defined(DFSDM1_Filter0)
elmot 1:d0dfbce63a89 225
elmot 1:d0dfbce63a89 226 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source.
elmot 1:d0dfbce63a89 227 This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */
elmot 1:d0dfbce63a89 228
elmot 1:d0dfbce63a89 229 #endif /* DFSDM1_Filter0 */
elmot 1:d0dfbce63a89 230
elmot 1:d0dfbce63a89 231 uint32_t RTCClockSelection; /*!< Specifies RTC clock source.
elmot 1:d0dfbce63a89 232 This parameter can be a value of @ref RCC_RTC_Clock_Source */
elmot 1:d0dfbce63a89 233 }RCC_PeriphCLKInitTypeDef;
elmot 1:d0dfbce63a89 234
elmot 1:d0dfbce63a89 235 #if defined(CRS)
elmot 1:d0dfbce63a89 236
elmot 1:d0dfbce63a89 237 /**
elmot 1:d0dfbce63a89 238 * @brief RCC_CRS Init structure definition
elmot 1:d0dfbce63a89 239 */
elmot 1:d0dfbce63a89 240 typedef struct
elmot 1:d0dfbce63a89 241 {
elmot 1:d0dfbce63a89 242 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
elmot 1:d0dfbce63a89 243 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
elmot 1:d0dfbce63a89 244
elmot 1:d0dfbce63a89 245 uint32_t Source; /*!< Specifies the SYNC signal source.
elmot 1:d0dfbce63a89 246 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
elmot 1:d0dfbce63a89 247
elmot 1:d0dfbce63a89 248 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
elmot 1:d0dfbce63a89 249 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
elmot 1:d0dfbce63a89 250
elmot 1:d0dfbce63a89 251 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
elmot 1:d0dfbce63a89 252 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
elmot 1:d0dfbce63a89 253 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
elmot 1:d0dfbce63a89 254
elmot 1:d0dfbce63a89 255 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
elmot 1:d0dfbce63a89 256 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
elmot 1:d0dfbce63a89 257
elmot 1:d0dfbce63a89 258 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
elmot 1:d0dfbce63a89 259 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
elmot 1:d0dfbce63a89 260
elmot 1:d0dfbce63a89 261 }RCC_CRSInitTypeDef;
elmot 1:d0dfbce63a89 262
elmot 1:d0dfbce63a89 263 /**
elmot 1:d0dfbce63a89 264 * @brief RCC_CRS Synchronization structure definition
elmot 1:d0dfbce63a89 265 */
elmot 1:d0dfbce63a89 266 typedef struct
elmot 1:d0dfbce63a89 267 {
elmot 1:d0dfbce63a89 268 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
elmot 1:d0dfbce63a89 269 This parameter must be a number between 0 and 0xFFFF */
elmot 1:d0dfbce63a89 270
elmot 1:d0dfbce63a89 271 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
elmot 1:d0dfbce63a89 272 This parameter must be a number between 0 and 0x3F */
elmot 1:d0dfbce63a89 273
elmot 1:d0dfbce63a89 274 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
elmot 1:d0dfbce63a89 275 value latched in the time of the last SYNC event.
elmot 1:d0dfbce63a89 276 This parameter must be a number between 0 and 0xFFFF */
elmot 1:d0dfbce63a89 277
elmot 1:d0dfbce63a89 278 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
elmot 1:d0dfbce63a89 279 frequency error counter latched in the time of the last SYNC event.
elmot 1:d0dfbce63a89 280 It shows whether the actual frequency is below or above the target.
elmot 1:d0dfbce63a89 281 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
elmot 1:d0dfbce63a89 282
elmot 1:d0dfbce63a89 283 }RCC_CRSSynchroInfoTypeDef;
elmot 1:d0dfbce63a89 284
elmot 1:d0dfbce63a89 285 #endif /* CRS */
elmot 1:d0dfbce63a89 286 /**
elmot 1:d0dfbce63a89 287 * @}
elmot 1:d0dfbce63a89 288 */
elmot 1:d0dfbce63a89 289
elmot 1:d0dfbce63a89 290 /* Exported constants --------------------------------------------------------*/
elmot 1:d0dfbce63a89 291 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
elmot 1:d0dfbce63a89 292 * @{
elmot 1:d0dfbce63a89 293 */
elmot 1:d0dfbce63a89 294
elmot 1:d0dfbce63a89 295 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
elmot 1:d0dfbce63a89 296 * @{
elmot 1:d0dfbce63a89 297 */
elmot 1:d0dfbce63a89 298 #define RCC_LSCOSOURCE_LSI (uint32_t)0x00000000U /*!< LSI selection for low speed clock output */
elmot 1:d0dfbce63a89 299 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */
elmot 1:d0dfbce63a89 300 /**
elmot 1:d0dfbce63a89 301 * @}
elmot 1:d0dfbce63a89 302 */
elmot 1:d0dfbce63a89 303
elmot 1:d0dfbce63a89 304 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
elmot 1:d0dfbce63a89 305 * @{
elmot 1:d0dfbce63a89 306 */
elmot 1:d0dfbce63a89 307 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U)
elmot 1:d0dfbce63a89 308 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U)
elmot 1:d0dfbce63a89 309 #if defined(USART3)
elmot 1:d0dfbce63a89 310 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004U)
elmot 1:d0dfbce63a89 311 #endif
elmot 1:d0dfbce63a89 312 #if defined(UART4)
elmot 1:d0dfbce63a89 313 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008U)
elmot 1:d0dfbce63a89 314 #endif
elmot 1:d0dfbce63a89 315 #if defined(UART5)
elmot 1:d0dfbce63a89 316 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010U)
elmot 1:d0dfbce63a89 317 #endif
elmot 1:d0dfbce63a89 318 #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020U)
elmot 1:d0dfbce63a89 319 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040U)
elmot 1:d0dfbce63a89 320 #if defined(I2C2)
elmot 1:d0dfbce63a89 321 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080U)
elmot 1:d0dfbce63a89 322 #endif
elmot 1:d0dfbce63a89 323 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U)
elmot 1:d0dfbce63a89 324 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200U)
elmot 1:d0dfbce63a89 325 #define RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400U)
elmot 1:d0dfbce63a89 326 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800U)
elmot 1:d0dfbce63a89 327 #if defined(SAI2)
elmot 1:d0dfbce63a89 328 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000U)
elmot 1:d0dfbce63a89 329 #endif
elmot 1:d0dfbce63a89 330 #if defined(USB_OTG_FS) || defined(USB)
elmot 1:d0dfbce63a89 331 #define RCC_PERIPHCLK_USB ((uint32_t)0x00002000U)
elmot 1:d0dfbce63a89 332 #endif
elmot 1:d0dfbce63a89 333 #define RCC_PERIPHCLK_ADC ((uint32_t)0x00004000U)
elmot 1:d0dfbce63a89 334 #define RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000U)
elmot 1:d0dfbce63a89 335 #if defined(DFSDM1_Filter0)
elmot 1:d0dfbce63a89 336 #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00010000U)
elmot 1:d0dfbce63a89 337 #endif
elmot 1:d0dfbce63a89 338 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00020000U)
elmot 1:d0dfbce63a89 339 #define RCC_PERIPHCLK_RNG ((uint32_t)0x00040000U)
elmot 1:d0dfbce63a89 340 #if defined(SDMMC1)
elmot 1:d0dfbce63a89 341 #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00080000U)
elmot 1:d0dfbce63a89 342 #endif
elmot 1:d0dfbce63a89 343 /**
elmot 1:d0dfbce63a89 344 * @}
elmot 1:d0dfbce63a89 345 */
elmot 1:d0dfbce63a89 346
elmot 1:d0dfbce63a89 347
elmot 1:d0dfbce63a89 348 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
elmot 1:d0dfbce63a89 349 * @{
elmot 1:d0dfbce63a89 350 */
elmot 1:d0dfbce63a89 351 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 352 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
elmot 1:d0dfbce63a89 353 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
elmot 1:d0dfbce63a89 354 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
elmot 1:d0dfbce63a89 355 /**
elmot 1:d0dfbce63a89 356 * @}
elmot 1:d0dfbce63a89 357 */
elmot 1:d0dfbce63a89 358
elmot 1:d0dfbce63a89 359 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
elmot 1:d0dfbce63a89 360 * @{
elmot 1:d0dfbce63a89 361 */
elmot 1:d0dfbce63a89 362 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 363 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
elmot 1:d0dfbce63a89 364 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
elmot 1:d0dfbce63a89 365 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
elmot 1:d0dfbce63a89 366 /**
elmot 1:d0dfbce63a89 367 * @}
elmot 1:d0dfbce63a89 368 */
elmot 1:d0dfbce63a89 369
elmot 1:d0dfbce63a89 370 #if defined(USART3)
elmot 1:d0dfbce63a89 371 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
elmot 1:d0dfbce63a89 372 * @{
elmot 1:d0dfbce63a89 373 */
elmot 1:d0dfbce63a89 374 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 375 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
elmot 1:d0dfbce63a89 376 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
elmot 1:d0dfbce63a89 377 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
elmot 1:d0dfbce63a89 378 /**
elmot 1:d0dfbce63a89 379 * @}
elmot 1:d0dfbce63a89 380 */
elmot 1:d0dfbce63a89 381 #endif /* USART3 */
elmot 1:d0dfbce63a89 382
elmot 1:d0dfbce63a89 383 #if defined(UART4)
elmot 1:d0dfbce63a89 384 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
elmot 1:d0dfbce63a89 385 * @{
elmot 1:d0dfbce63a89 386 */
elmot 1:d0dfbce63a89 387 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 388 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
elmot 1:d0dfbce63a89 389 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
elmot 1:d0dfbce63a89 390 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
elmot 1:d0dfbce63a89 391 /**
elmot 1:d0dfbce63a89 392 * @}
elmot 1:d0dfbce63a89 393 */
elmot 1:d0dfbce63a89 394 #endif /* UART4 */
elmot 1:d0dfbce63a89 395
elmot 1:d0dfbce63a89 396 #if defined(UART5)
elmot 1:d0dfbce63a89 397 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
elmot 1:d0dfbce63a89 398 * @{
elmot 1:d0dfbce63a89 399 */
elmot 1:d0dfbce63a89 400 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 401 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
elmot 1:d0dfbce63a89 402 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
elmot 1:d0dfbce63a89 403 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
elmot 1:d0dfbce63a89 404 /**
elmot 1:d0dfbce63a89 405 * @}
elmot 1:d0dfbce63a89 406 */
elmot 1:d0dfbce63a89 407 #endif /* UART5 */
elmot 1:d0dfbce63a89 408
elmot 1:d0dfbce63a89 409 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
elmot 1:d0dfbce63a89 410 * @{
elmot 1:d0dfbce63a89 411 */
elmot 1:d0dfbce63a89 412 #define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 413 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
elmot 1:d0dfbce63a89 414 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
elmot 1:d0dfbce63a89 415 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
elmot 1:d0dfbce63a89 416 /**
elmot 1:d0dfbce63a89 417 * @}
elmot 1:d0dfbce63a89 418 */
elmot 1:d0dfbce63a89 419
elmot 1:d0dfbce63a89 420 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
elmot 1:d0dfbce63a89 421 * @{
elmot 1:d0dfbce63a89 422 */
elmot 1:d0dfbce63a89 423 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 424 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
elmot 1:d0dfbce63a89 425 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
elmot 1:d0dfbce63a89 426 /**
elmot 1:d0dfbce63a89 427 * @}
elmot 1:d0dfbce63a89 428 */
elmot 1:d0dfbce63a89 429
elmot 1:d0dfbce63a89 430 #if defined(I2C2)
elmot 1:d0dfbce63a89 431 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
elmot 1:d0dfbce63a89 432 * @{
elmot 1:d0dfbce63a89 433 */
elmot 1:d0dfbce63a89 434 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 435 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
elmot 1:d0dfbce63a89 436 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
elmot 1:d0dfbce63a89 437 /**
elmot 1:d0dfbce63a89 438 * @}
elmot 1:d0dfbce63a89 439 */
elmot 1:d0dfbce63a89 440 #endif /* I2C2 */
elmot 1:d0dfbce63a89 441
elmot 1:d0dfbce63a89 442 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
elmot 1:d0dfbce63a89 443 * @{
elmot 1:d0dfbce63a89 444 */
elmot 1:d0dfbce63a89 445 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 446 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
elmot 1:d0dfbce63a89 447 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
elmot 1:d0dfbce63a89 448 /**
elmot 1:d0dfbce63a89 449 * @}
elmot 1:d0dfbce63a89 450 */
elmot 1:d0dfbce63a89 451
elmot 1:d0dfbce63a89 452 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
elmot 1:d0dfbce63a89 453 * @{
elmot 1:d0dfbce63a89 454 */
elmot 1:d0dfbce63a89 455 #define RCC_SAI1CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 456 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 457 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0
elmot 1:d0dfbce63a89 458 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 459 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1
elmot 1:d0dfbce63a89 460 #define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL
elmot 1:d0dfbce63a89 461 /**
elmot 1:d0dfbce63a89 462 * @}
elmot 1:d0dfbce63a89 463 */
elmot 1:d0dfbce63a89 464
elmot 1:d0dfbce63a89 465 #if defined(SAI2)
elmot 1:d0dfbce63a89 466 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
elmot 1:d0dfbce63a89 467 * @{
elmot 1:d0dfbce63a89 468 */
elmot 1:d0dfbce63a89 469 #define RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 470 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0
elmot 1:d0dfbce63a89 471 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1
elmot 1:d0dfbce63a89 472 #define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL
elmot 1:d0dfbce63a89 473 /**
elmot 1:d0dfbce63a89 474 * @}
elmot 1:d0dfbce63a89 475 */
elmot 1:d0dfbce63a89 476 #endif /* SAI2 */
elmot 1:d0dfbce63a89 477
elmot 1:d0dfbce63a89 478 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
elmot 1:d0dfbce63a89 479 * @{
elmot 1:d0dfbce63a89 480 */
elmot 1:d0dfbce63a89 481 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 482 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
elmot 1:d0dfbce63a89 483 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
elmot 1:d0dfbce63a89 484 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
elmot 1:d0dfbce63a89 485 /**
elmot 1:d0dfbce63a89 486 * @}
elmot 1:d0dfbce63a89 487 */
elmot 1:d0dfbce63a89 488
elmot 1:d0dfbce63a89 489 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
elmot 1:d0dfbce63a89 490 * @{
elmot 1:d0dfbce63a89 491 */
elmot 1:d0dfbce63a89 492 #define RCC_LPTIM2CLKSOURCE_PCLK ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 493 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0
elmot 1:d0dfbce63a89 494 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1
elmot 1:d0dfbce63a89 495 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL
elmot 1:d0dfbce63a89 496 /**
elmot 1:d0dfbce63a89 497 * @}
elmot 1:d0dfbce63a89 498 */
elmot 1:d0dfbce63a89 499
elmot 1:d0dfbce63a89 500 #if defined(SDMMC1)
elmot 1:d0dfbce63a89 501 /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source
elmot 1:d0dfbce63a89 502 * @{
elmot 1:d0dfbce63a89 503 */
elmot 1:d0dfbce63a89 504 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 505 #define RCC_SDMMC1CLKSOURCE_HSI48 ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 506 #else
elmot 1:d0dfbce63a89 507 #define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 508 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 509 #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
elmot 1:d0dfbce63a89 510 #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
elmot 1:d0dfbce63a89 511 #define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
elmot 1:d0dfbce63a89 512 /**
elmot 1:d0dfbce63a89 513 * @}
elmot 1:d0dfbce63a89 514 */
elmot 1:d0dfbce63a89 515 #endif /* SDMMC1 */
elmot 1:d0dfbce63a89 516
elmot 1:d0dfbce63a89 517 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
elmot 1:d0dfbce63a89 518 * @{
elmot 1:d0dfbce63a89 519 */
elmot 1:d0dfbce63a89 520 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 521 #define RCC_RNGCLKSOURCE_HSI48 ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 522 #else
elmot 1:d0dfbce63a89 523 #define RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 524 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 525 #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
elmot 1:d0dfbce63a89 526 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
elmot 1:d0dfbce63a89 527 #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
elmot 1:d0dfbce63a89 528 /**
elmot 1:d0dfbce63a89 529 * @}
elmot 1:d0dfbce63a89 530 */
elmot 1:d0dfbce63a89 531
elmot 1:d0dfbce63a89 532 #if defined(USB_OTG_FS) || defined(USB)
elmot 1:d0dfbce63a89 533 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source
elmot 1:d0dfbce63a89 534 * @{
elmot 1:d0dfbce63a89 535 */
elmot 1:d0dfbce63a89 536 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 537 #define RCC_USBCLKSOURCE_HSI48 ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 538 #else
elmot 1:d0dfbce63a89 539 #define RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 540 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 541 #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
elmot 1:d0dfbce63a89 542 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
elmot 1:d0dfbce63a89 543 #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
elmot 1:d0dfbce63a89 544 /**
elmot 1:d0dfbce63a89 545 * @}
elmot 1:d0dfbce63a89 546 */
elmot 1:d0dfbce63a89 547 #endif /* USB_OTG_FS || USB */
elmot 1:d0dfbce63a89 548
elmot 1:d0dfbce63a89 549 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
elmot 1:d0dfbce63a89 550 * @{
elmot 1:d0dfbce63a89 551 */
elmot 1:d0dfbce63a89 552 #define RCC_ADCCLKSOURCE_NONE ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 553 #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
elmot 1:d0dfbce63a89 554 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
elmot 1:d0dfbce63a89 555 #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1
elmot 1:d0dfbce63a89 556 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
elmot 1:d0dfbce63a89 557 #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL
elmot 1:d0dfbce63a89 558 /**
elmot 1:d0dfbce63a89 559 * @}
elmot 1:d0dfbce63a89 560 */
elmot 1:d0dfbce63a89 561
elmot 1:d0dfbce63a89 562 #if defined(SWPMI1)
elmot 1:d0dfbce63a89 563 /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source
elmot 1:d0dfbce63a89 564 * @{
elmot 1:d0dfbce63a89 565 */
elmot 1:d0dfbce63a89 566 #define RCC_SWPMI1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 567 #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL
elmot 1:d0dfbce63a89 568 /**
elmot 1:d0dfbce63a89 569 * @}
elmot 1:d0dfbce63a89 570 */
elmot 1:d0dfbce63a89 571 #endif /* SWPMI1 */
elmot 1:d0dfbce63a89 572
elmot 1:d0dfbce63a89 573 #if defined(DFSDM1_Filter0)
elmot 1:d0dfbce63a89 574 /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source
elmot 1:d0dfbce63a89 575 * @{
elmot 1:d0dfbce63a89 576 */
elmot 1:d0dfbce63a89 577 #define RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 578 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL
elmot 1:d0dfbce63a89 579 /**
elmot 1:d0dfbce63a89 580 * @}
elmot 1:d0dfbce63a89 581 */
elmot 1:d0dfbce63a89 582 #endif /* DFSDM1_Filter0 */
elmot 1:d0dfbce63a89 583
elmot 1:d0dfbce63a89 584 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
elmot 1:d0dfbce63a89 585 * @{
elmot 1:d0dfbce63a89 586 */
elmot 1:d0dfbce63a89 587 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
elmot 1:d0dfbce63a89 588 /**
elmot 1:d0dfbce63a89 589 * @}
elmot 1:d0dfbce63a89 590 */
elmot 1:d0dfbce63a89 591
elmot 1:d0dfbce63a89 592 #if defined(CRS)
elmot 1:d0dfbce63a89 593
elmot 1:d0dfbce63a89 594 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
elmot 1:d0dfbce63a89 595 * @{
elmot 1:d0dfbce63a89 596 */
elmot 1:d0dfbce63a89 597 #define RCC_CRS_NONE ((uint32_t)0x00000000U)
elmot 1:d0dfbce63a89 598 #define RCC_CRS_TIMEOUT ((uint32_t)0x00000001U)
elmot 1:d0dfbce63a89 599 #define RCC_CRS_SYNCOK ((uint32_t)0x00000002U)
elmot 1:d0dfbce63a89 600 #define RCC_CRS_SYNCWARN ((uint32_t)0x00000004U)
elmot 1:d0dfbce63a89 601 #define RCC_CRS_SYNCERR ((uint32_t)0x00000008U)
elmot 1:d0dfbce63a89 602 #define RCC_CRS_SYNCMISS ((uint32_t)0x00000010U)
elmot 1:d0dfbce63a89 603 #define RCC_CRS_TRIMOVF ((uint32_t)0x00000020U)
elmot 1:d0dfbce63a89 604 /**
elmot 1:d0dfbce63a89 605 * @}
elmot 1:d0dfbce63a89 606 */
elmot 1:d0dfbce63a89 607
elmot 1:d0dfbce63a89 608 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
elmot 1:d0dfbce63a89 609 * @{
elmot 1:d0dfbce63a89 610 */
elmot 1:d0dfbce63a89 611 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */
elmot 1:d0dfbce63a89 612 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
elmot 1:d0dfbce63a89 613 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
elmot 1:d0dfbce63a89 614 /**
elmot 1:d0dfbce63a89 615 * @}
elmot 1:d0dfbce63a89 616 */
elmot 1:d0dfbce63a89 617
elmot 1:d0dfbce63a89 618 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
elmot 1:d0dfbce63a89 619 * @{
elmot 1:d0dfbce63a89 620 */
elmot 1:d0dfbce63a89 621 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */
elmot 1:d0dfbce63a89 622 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
elmot 1:d0dfbce63a89 623 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
elmot 1:d0dfbce63a89 624 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
elmot 1:d0dfbce63a89 625 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
elmot 1:d0dfbce63a89 626 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
elmot 1:d0dfbce63a89 627 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
elmot 1:d0dfbce63a89 628 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
elmot 1:d0dfbce63a89 629 /**
elmot 1:d0dfbce63a89 630 * @}
elmot 1:d0dfbce63a89 631 */
elmot 1:d0dfbce63a89 632
elmot 1:d0dfbce63a89 633 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
elmot 1:d0dfbce63a89 634 * @{
elmot 1:d0dfbce63a89 635 */
elmot 1:d0dfbce63a89 636 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */
elmot 1:d0dfbce63a89 637 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
elmot 1:d0dfbce63a89 638 /**
elmot 1:d0dfbce63a89 639 * @}
elmot 1:d0dfbce63a89 640 */
elmot 1:d0dfbce63a89 641
elmot 1:d0dfbce63a89 642 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
elmot 1:d0dfbce63a89 643 * @{
elmot 1:d0dfbce63a89 644 */
elmot 1:d0dfbce63a89 645 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
elmot 1:d0dfbce63a89 646 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
elmot 1:d0dfbce63a89 647 /**
elmot 1:d0dfbce63a89 648 * @}
elmot 1:d0dfbce63a89 649 */
elmot 1:d0dfbce63a89 650
elmot 1:d0dfbce63a89 651 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
elmot 1:d0dfbce63a89 652 * @{
elmot 1:d0dfbce63a89 653 */
elmot 1:d0dfbce63a89 654 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */
elmot 1:d0dfbce63a89 655 /**
elmot 1:d0dfbce63a89 656 * @}
elmot 1:d0dfbce63a89 657 */
elmot 1:d0dfbce63a89 658
elmot 1:d0dfbce63a89 659 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
elmot 1:d0dfbce63a89 660 * @{
elmot 1:d0dfbce63a89 661 */
elmot 1:d0dfbce63a89 662 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
elmot 1:d0dfbce63a89 663 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
elmot 1:d0dfbce63a89 664 corresponds to a higher output frequency */
elmot 1:d0dfbce63a89 665 /**
elmot 1:d0dfbce63a89 666 * @}
elmot 1:d0dfbce63a89 667 */
elmot 1:d0dfbce63a89 668
elmot 1:d0dfbce63a89 669 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
elmot 1:d0dfbce63a89 670 * @{
elmot 1:d0dfbce63a89 671 */
elmot 1:d0dfbce63a89 672 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */
elmot 1:d0dfbce63a89 673 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
elmot 1:d0dfbce63a89 674 /**
elmot 1:d0dfbce63a89 675 * @}
elmot 1:d0dfbce63a89 676 */
elmot 1:d0dfbce63a89 677
elmot 1:d0dfbce63a89 678 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
elmot 1:d0dfbce63a89 679 * @{
elmot 1:d0dfbce63a89 680 */
elmot 1:d0dfbce63a89 681 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */
elmot 1:d0dfbce63a89 682 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */
elmot 1:d0dfbce63a89 683 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */
elmot 1:d0dfbce63a89 684 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */
elmot 1:d0dfbce63a89 685 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */
elmot 1:d0dfbce63a89 686 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */
elmot 1:d0dfbce63a89 687 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */
elmot 1:d0dfbce63a89 688
elmot 1:d0dfbce63a89 689 /**
elmot 1:d0dfbce63a89 690 * @}
elmot 1:d0dfbce63a89 691 */
elmot 1:d0dfbce63a89 692
elmot 1:d0dfbce63a89 693 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
elmot 1:d0dfbce63a89 694 * @{
elmot 1:d0dfbce63a89 695 */
elmot 1:d0dfbce63a89 696 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */
elmot 1:d0dfbce63a89 697 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */
elmot 1:d0dfbce63a89 698 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */
elmot 1:d0dfbce63a89 699 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */
elmot 1:d0dfbce63a89 700 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
elmot 1:d0dfbce63a89 701 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
elmot 1:d0dfbce63a89 702 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
elmot 1:d0dfbce63a89 703
elmot 1:d0dfbce63a89 704 /**
elmot 1:d0dfbce63a89 705 * @}
elmot 1:d0dfbce63a89 706 */
elmot 1:d0dfbce63a89 707
elmot 1:d0dfbce63a89 708 #endif /* CRS */
elmot 1:d0dfbce63a89 709
elmot 1:d0dfbce63a89 710 /**
elmot 1:d0dfbce63a89 711 * @}
elmot 1:d0dfbce63a89 712 */
elmot 1:d0dfbce63a89 713
elmot 1:d0dfbce63a89 714 /* Exported macros -----------------------------------------------------------*/
elmot 1:d0dfbce63a89 715 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
elmot 1:d0dfbce63a89 716 * @{
elmot 1:d0dfbce63a89 717 */
elmot 1:d0dfbce63a89 718
elmot 1:d0dfbce63a89 719
elmot 1:d0dfbce63a89 720 /**
elmot 1:d0dfbce63a89 721 * @brief Macro to configure the PLLSAI1 clock multiplication and division factors.
elmot 1:d0dfbce63a89 722 *
elmot 1:d0dfbce63a89 723 * @note This function must be used only when the PLLSAI1 is disabled.
elmot 1:d0dfbce63a89 724 * @note PLLSAI1 clock source is common with the main PLL (configured through
elmot 1:d0dfbce63a89 725 * __HAL_RCC_PLL_CONFIG() macro)
elmot 1:d0dfbce63a89 726 *
elmot 1:d0dfbce63a89 727 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
elmot 1:d0dfbce63a89 728 * This parameter must be a number between 8 and 86.
elmot 1:d0dfbce63a89 729 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
elmot 1:d0dfbce63a89 730 * output frequency is between 64 and 344 MHz.
elmot 1:d0dfbce63a89 731 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
elmot 1:d0dfbce63a89 732 *
elmot 1:d0dfbce63a89 733 * @param __PLLSAI1P__ specifies the division factor for SAI clock.
elmot 1:d0dfbce63a89 734 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
elmot 1:d0dfbce63a89 735 * else (2 to 31).
elmot 1:d0dfbce63a89 736 * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
elmot 1:d0dfbce63a89 737 *
elmot 1:d0dfbce63a89 738 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
elmot 1:d0dfbce63a89 739 * This parameter must be in the range (2, 4, 6 or 8).
elmot 1:d0dfbce63a89 740 * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
elmot 1:d0dfbce63a89 741 *
elmot 1:d0dfbce63a89 742 * @param __PLLSAI1R__ specifies the division factor for SAR ADC clock.
elmot 1:d0dfbce63a89 743 * This parameter must be in the range (2, 4, 6 or 8).
elmot 1:d0dfbce63a89 744 * ADC clock frequency = f(PLLSAI1) / PLLSAI1R
elmot 1:d0dfbce63a89 745 *
elmot 1:d0dfbce63a89 746 * @retval None
elmot 1:d0dfbce63a89 747 */
elmot 1:d0dfbce63a89 748 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 749
elmot 1:d0dfbce63a89 750 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
elmot 1:d0dfbce63a89 751 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
elmot 1:d0dfbce63a89 752 ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
elmot 1:d0dfbce63a89 753 ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) | \
elmot 1:d0dfbce63a89 754 ((__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)))
elmot 1:d0dfbce63a89 755
elmot 1:d0dfbce63a89 756 #else
elmot 1:d0dfbce63a89 757
elmot 1:d0dfbce63a89 758 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
elmot 1:d0dfbce63a89 759 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
elmot 1:d0dfbce63a89 760 (((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) | \
elmot 1:d0dfbce63a89 761 ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
elmot 1:d0dfbce63a89 762 ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)))
elmot 1:d0dfbce63a89 763
elmot 1:d0dfbce63a89 764 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 765
elmot 1:d0dfbce63a89 766 /**
elmot 1:d0dfbce63a89 767 * @brief Macro to configure the PLLSAI1 clock multiplication factor N.
elmot 1:d0dfbce63a89 768 *
elmot 1:d0dfbce63a89 769 * @note This function must be used only when the PLLSAI1 is disabled.
elmot 1:d0dfbce63a89 770 * @note PLLSAI1 clock source is common with the main PLL (configured through
elmot 1:d0dfbce63a89 771 * __HAL_RCC_PLL_CONFIG() macro)
elmot 1:d0dfbce63a89 772 *
elmot 1:d0dfbce63a89 773 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
elmot 1:d0dfbce63a89 774 * This parameter must be a number between 8 and 86.
elmot 1:d0dfbce63a89 775 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
elmot 1:d0dfbce63a89 776 * output frequency is between 64 and 344 MHz.
elmot 1:d0dfbce63a89 777 * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
elmot 1:d0dfbce63a89 778 *
elmot 1:d0dfbce63a89 779 * @retval None
elmot 1:d0dfbce63a89 780 */
elmot 1:d0dfbce63a89 781 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
elmot 1:d0dfbce63a89 782 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N))
elmot 1:d0dfbce63a89 783
elmot 1:d0dfbce63a89 784 /** @brief Macro to configure the PLLSAI1 clock division factor P.
elmot 1:d0dfbce63a89 785 *
elmot 1:d0dfbce63a89 786 * @note This function must be used only when the PLLSAI1 is disabled.
elmot 1:d0dfbce63a89 787 * @note PLLSAI1 clock source is common with the main PLL (configured through
elmot 1:d0dfbce63a89 788 * __HAL_RCC_PLL_CONFIG() macro)
elmot 1:d0dfbce63a89 789 *
elmot 1:d0dfbce63a89 790 * @param __PLLSAI1P__ specifies the division factor for SAI clock.
elmot 1:d0dfbce63a89 791 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
elmot 1:d0dfbce63a89 792 * else (2 to 31).
elmot 1:d0dfbce63a89 793 * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
elmot 1:d0dfbce63a89 794 *
elmot 1:d0dfbce63a89 795 * @retval None
elmot 1:d0dfbce63a89 796 */
elmot 1:d0dfbce63a89 797 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 798
elmot 1:d0dfbce63a89 799 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
elmot 1:d0dfbce63a89 800 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV))
elmot 1:d0dfbce63a89 801
elmot 1:d0dfbce63a89 802 #else
elmot 1:d0dfbce63a89 803
elmot 1:d0dfbce63a89 804 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
elmot 1:d0dfbce63a89 805 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))
elmot 1:d0dfbce63a89 806
elmot 1:d0dfbce63a89 807 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 808
elmot 1:d0dfbce63a89 809 /** @brief Macro to configure the PLLSAI1 clock division factor Q.
elmot 1:d0dfbce63a89 810 *
elmot 1:d0dfbce63a89 811 * @note This function must be used only when the PLLSAI1 is disabled.
elmot 1:d0dfbce63a89 812 * @note PLLSAI1 clock source is common with the main PLL (configured through
elmot 1:d0dfbce63a89 813 * __HAL_RCC_PLL_CONFIG() macro)
elmot 1:d0dfbce63a89 814 *
elmot 1:d0dfbce63a89 815 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
elmot 1:d0dfbce63a89 816 * This parameter must be in the range (2, 4, 6 or 8).
elmot 1:d0dfbce63a89 817 * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
elmot 1:d0dfbce63a89 818 *
elmot 1:d0dfbce63a89 819 * @retval None
elmot 1:d0dfbce63a89 820 */
elmot 1:d0dfbce63a89 821 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
elmot 1:d0dfbce63a89 822 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))
elmot 1:d0dfbce63a89 823
elmot 1:d0dfbce63a89 824 /** @brief Macro to configure the PLLSAI1 clock division factor R.
elmot 1:d0dfbce63a89 825 *
elmot 1:d0dfbce63a89 826 * @note This function must be used only when the PLLSAI1 is disabled.
elmot 1:d0dfbce63a89 827 * @note PLLSAI1 clock source is common with the main PLL (configured through
elmot 1:d0dfbce63a89 828 * __HAL_RCC_PLL_CONFIG() macro)
elmot 1:d0dfbce63a89 829 *
elmot 1:d0dfbce63a89 830 * @param __PLLSAI1R__ specifies the division factor for ADC clock.
elmot 1:d0dfbce63a89 831 * This parameter must be in the range (2, 4, 6 or 8)
elmot 1:d0dfbce63a89 832 * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R
elmot 1:d0dfbce63a89 833 *
elmot 1:d0dfbce63a89 834 * @retval None
elmot 1:d0dfbce63a89 835 */
elmot 1:d0dfbce63a89 836 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
elmot 1:d0dfbce63a89 837 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))
elmot 1:d0dfbce63a89 838
elmot 1:d0dfbce63a89 839 /**
elmot 1:d0dfbce63a89 840 * @brief Macros to enable or disable the PLLSAI1.
elmot 1:d0dfbce63a89 841 * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
elmot 1:d0dfbce63a89 842 * @retval None
elmot 1:d0dfbce63a89 843 */
elmot 1:d0dfbce63a89 844
elmot 1:d0dfbce63a89 845 #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
elmot 1:d0dfbce63a89 846
elmot 1:d0dfbce63a89 847 #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
elmot 1:d0dfbce63a89 848
elmot 1:d0dfbce63a89 849 /**
elmot 1:d0dfbce63a89 850 * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
elmot 1:d0dfbce63a89 851 * @note Enabling and disabling those clocks can be done without the need to stop the PLL.
elmot 1:d0dfbce63a89 852 * This is mainly used to save Power.
elmot 1:d0dfbce63a89 853 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
elmot 1:d0dfbce63a89 854 * This parameter can be one or a combination of the following values:
elmot 1:d0dfbce63a89 855 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve
elmot 1:d0dfbce63a89 856 * high-quality audio performance on SAI interface in case.
elmot 1:d0dfbce63a89 857 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz),
elmot 1:d0dfbce63a89 858 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
elmot 1:d0dfbce63a89 859 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
elmot 1:d0dfbce63a89 860 * @retval None
elmot 1:d0dfbce63a89 861 */
elmot 1:d0dfbce63a89 862
elmot 1:d0dfbce63a89 863 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
elmot 1:d0dfbce63a89 864
elmot 1:d0dfbce63a89 865 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
elmot 1:d0dfbce63a89 866
elmot 1:d0dfbce63a89 867 /**
elmot 1:d0dfbce63a89 868 * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
elmot 1:d0dfbce63a89 869 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
elmot 1:d0dfbce63a89 870 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 871 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve
elmot 1:d0dfbce63a89 872 * high-quality audio performance on SAI interface in case.
elmot 1:d0dfbce63a89 873 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz),
elmot 1:d0dfbce63a89 874 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
elmot 1:d0dfbce63a89 875 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
elmot 1:d0dfbce63a89 876 * @retval SET / RESET
elmot 1:d0dfbce63a89 877 */
elmot 1:d0dfbce63a89 878 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
elmot 1:d0dfbce63a89 879
elmot 1:d0dfbce63a89 880 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 881
elmot 1:d0dfbce63a89 882 /**
elmot 1:d0dfbce63a89 883 * @brief Macro to configure the PLLSAI2 clock multiplication and division factors.
elmot 1:d0dfbce63a89 884 *
elmot 1:d0dfbce63a89 885 * @note This function must be used only when the PLLSAI2 is disabled.
elmot 1:d0dfbce63a89 886 * @note PLLSAI2 clock source is common with the main PLL (configured through
elmot 1:d0dfbce63a89 887 * __HAL_RCC_PLL_CONFIG() macro)
elmot 1:d0dfbce63a89 888 *
elmot 1:d0dfbce63a89 889 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
elmot 1:d0dfbce63a89 890 * This parameter must be a number between 8 and 86.
elmot 1:d0dfbce63a89 891 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
elmot 1:d0dfbce63a89 892 * output frequency is between 64 and 344 MHz.
elmot 1:d0dfbce63a89 893 *
elmot 1:d0dfbce63a89 894 * @param __PLLSAI2P__ specifies the division factor for SAI clock.
elmot 1:d0dfbce63a89 895 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
elmot 1:d0dfbce63a89 896 * else (2 to 31).
elmot 1:d0dfbce63a89 897 * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P
elmot 1:d0dfbce63a89 898 *
elmot 1:d0dfbce63a89 899 * @param __PLLSAI2R__ specifies the division factor for SAR ADC clock.
elmot 1:d0dfbce63a89 900 * This parameter must be in the range (2, 4, 6 or 8).
elmot 1:d0dfbce63a89 901 *
elmot 1:d0dfbce63a89 902 * @retval None
elmot 1:d0dfbce63a89 903 */
elmot 1:d0dfbce63a89 904
elmot 1:d0dfbce63a89 905 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 906
elmot 1:d0dfbce63a89 907 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
elmot 1:d0dfbce63a89 908 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
elmot 1:d0dfbce63a89 909 ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) | \
elmot 1:d0dfbce63a89 910 ((__PLLSAI2P__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2PDIV)))
elmot 1:d0dfbce63a89 911
elmot 1:d0dfbce63a89 912 #else
elmot 1:d0dfbce63a89 913
elmot 1:d0dfbce63a89 914 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
elmot 1:d0dfbce63a89 915 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
elmot 1:d0dfbce63a89 916 (((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) | \
elmot 1:d0dfbce63a89 917 ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)))
elmot 1:d0dfbce63a89 918
elmot 1:d0dfbce63a89 919 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 920
elmot 1:d0dfbce63a89 921
elmot 1:d0dfbce63a89 922 /**
elmot 1:d0dfbce63a89 923 * @brief Macro to configure the PLLSAI2 clock multiplication factor N.
elmot 1:d0dfbce63a89 924 *
elmot 1:d0dfbce63a89 925 * @note This function must be used only when the PLLSAI2 is disabled.
elmot 1:d0dfbce63a89 926 * @note PLLSAI2 clock source is common with the main PLL (configured through
elmot 1:d0dfbce63a89 927 * __HAL_RCC_PLL_CONFIG() macro)
elmot 1:d0dfbce63a89 928 *
elmot 1:d0dfbce63a89 929 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
elmot 1:d0dfbce63a89 930 * This parameter must be a number between 8 and 86.
elmot 1:d0dfbce63a89 931 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
elmot 1:d0dfbce63a89 932 * output frequency is between 64 and 344 MHz.
elmot 1:d0dfbce63a89 933 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N
elmot 1:d0dfbce63a89 934 *
elmot 1:d0dfbce63a89 935 * @retval None
elmot 1:d0dfbce63a89 936 */
elmot 1:d0dfbce63a89 937 #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
elmot 1:d0dfbce63a89 938 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N))
elmot 1:d0dfbce63a89 939
elmot 1:d0dfbce63a89 940 /** @brief Macro to configure the PLLSAI2 clock division factor P.
elmot 1:d0dfbce63a89 941 *
elmot 1:d0dfbce63a89 942 * @note This function must be used only when the PLLSAI2 is disabled.
elmot 1:d0dfbce63a89 943 * @note PLLSAI2 clock source is common with the main PLL (configured through
elmot 1:d0dfbce63a89 944 * __HAL_RCC_PLL_CONFIG() macro)
elmot 1:d0dfbce63a89 945 *
elmot 1:d0dfbce63a89 946 * @param __PLLSAI2P__ specifies the division factor.
elmot 1:d0dfbce63a89 947 * This parameter must be a number in the range (7 or 17).
elmot 1:d0dfbce63a89 948 * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__
elmot 1:d0dfbce63a89 949 *
elmot 1:d0dfbce63a89 950 * @retval None
elmot 1:d0dfbce63a89 951 */
elmot 1:d0dfbce63a89 952 #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
elmot 1:d0dfbce63a89 953 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P))
elmot 1:d0dfbce63a89 954
elmot 1:d0dfbce63a89 955 /** @brief Macro to configure the PLLSAI2 clock division factor R.
elmot 1:d0dfbce63a89 956 *
elmot 1:d0dfbce63a89 957 * @note This function must be used only when the PLLSAI2 is disabled.
elmot 1:d0dfbce63a89 958 * @note PLLSAI2 clock source is common with the main PLL (configured through
elmot 1:d0dfbce63a89 959 * __HAL_RCC_PLL_CONFIG() macro)
elmot 1:d0dfbce63a89 960 *
elmot 1:d0dfbce63a89 961 * @param __PLLSAI2R__ specifies the division factor.
elmot 1:d0dfbce63a89 962 * This parameter must be in the range (2, 4, 6 or 8).
elmot 1:d0dfbce63a89 963 * Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__
elmot 1:d0dfbce63a89 964 *
elmot 1:d0dfbce63a89 965 * @retval None
elmot 1:d0dfbce63a89 966 */
elmot 1:d0dfbce63a89 967 #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \
elmot 1:d0dfbce63a89 968 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))
elmot 1:d0dfbce63a89 969
elmot 1:d0dfbce63a89 970 /**
elmot 1:d0dfbce63a89 971 * @brief Macros to enable or disable the PLLSAI2.
elmot 1:d0dfbce63a89 972 * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.
elmot 1:d0dfbce63a89 973 * @retval None
elmot 1:d0dfbce63a89 974 */
elmot 1:d0dfbce63a89 975
elmot 1:d0dfbce63a89 976 #define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
elmot 1:d0dfbce63a89 977
elmot 1:d0dfbce63a89 978 #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
elmot 1:d0dfbce63a89 979
elmot 1:d0dfbce63a89 980 /**
elmot 1:d0dfbce63a89 981 * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2).
elmot 1:d0dfbce63a89 982 * @note Enabling and disabling those clocks can be done without the need to stop the PLL.
elmot 1:d0dfbce63a89 983 * This is mainly used to save Power.
elmot 1:d0dfbce63a89 984 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
elmot 1:d0dfbce63a89 985 * This parameter can be one or a combination of the following values:
elmot 1:d0dfbce63a89 986 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
elmot 1:d0dfbce63a89 987 * high-quality audio performance on SAI interface in case.
elmot 1:d0dfbce63a89 988 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
elmot 1:d0dfbce63a89 989 * @retval None
elmot 1:d0dfbce63a89 990 */
elmot 1:d0dfbce63a89 991
elmot 1:d0dfbce63a89 992 #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
elmot 1:d0dfbce63a89 993
elmot 1:d0dfbce63a89 994 #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
elmot 1:d0dfbce63a89 995
elmot 1:d0dfbce63a89 996 /**
elmot 1:d0dfbce63a89 997 * @brief Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2).
elmot 1:d0dfbce63a89 998 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
elmot 1:d0dfbce63a89 999 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1000 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
elmot 1:d0dfbce63a89 1001 * high-quality audio performance on SAI interface in case.
elmot 1:d0dfbce63a89 1002 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
elmot 1:d0dfbce63a89 1003 * @retval SET / RESET
elmot 1:d0dfbce63a89 1004 */
elmot 1:d0dfbce63a89 1005 #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
elmot 1:d0dfbce63a89 1006
elmot 1:d0dfbce63a89 1007 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 1008
elmot 1:d0dfbce63a89 1009 /**
elmot 1:d0dfbce63a89 1010 * @brief Macro to configure the SAI1 clock source.
elmot 1:d0dfbce63a89 1011 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
elmot 1:d0dfbce63a89 1012 * from the PLLSAI1, system PLL or external clock (through a dedicated pin).
elmot 1:d0dfbce63a89 1013 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1014 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
elmot 1:d0dfbce63a89 1015 @if STM32L486xx
elmot 1:d0dfbce63a89 1016 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
elmot 1:d0dfbce63a89 1017 @endif
elmot 1:d0dfbce63a89 1018 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
elmot 1:d0dfbce63a89 1019 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
elmot 1:d0dfbce63a89 1020 *
elmot 1:d0dfbce63a89 1021 @if STM32L443xx
elmot 1:d0dfbce63a89 1022 * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2.
elmot 1:d0dfbce63a89 1023 @endif
elmot 1:d0dfbce63a89 1024 *
elmot 1:d0dfbce63a89 1025 * @retval None
elmot 1:d0dfbce63a89 1026 */
elmot 1:d0dfbce63a89 1027 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
elmot 1:d0dfbce63a89 1028 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))
elmot 1:d0dfbce63a89 1029
elmot 1:d0dfbce63a89 1030 /** @brief Macro to get the SAI1 clock source.
elmot 1:d0dfbce63a89 1031 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1032 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
elmot 1:d0dfbce63a89 1033 @if STM32L486xx
elmot 1:d0dfbce63a89 1034 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
elmot 1:d0dfbce63a89 1035 @endif
elmot 1:d0dfbce63a89 1036 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
elmot 1:d0dfbce63a89 1037 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
elmot 1:d0dfbce63a89 1038 *
elmot 1:d0dfbce63a89 1039 * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1
elmot 1:d0dfbce63a89 1040 * clock source when PLLs are disabled for devices without PLLSAI2.
elmot 1:d0dfbce63a89 1041 *
elmot 1:d0dfbce63a89 1042 */
elmot 1:d0dfbce63a89 1043 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)))
elmot 1:d0dfbce63a89 1044
elmot 1:d0dfbce63a89 1045 #if defined(SAI2)
elmot 1:d0dfbce63a89 1046
elmot 1:d0dfbce63a89 1047 /**
elmot 1:d0dfbce63a89 1048 * @brief Macro to configure the SAI2 clock source.
elmot 1:d0dfbce63a89 1049 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived
elmot 1:d0dfbce63a89 1050 * from the PLLSAI2, system PLL or external clock (through a dedicated pin).
elmot 1:d0dfbce63a89 1051 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1052 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
elmot 1:d0dfbce63a89 1053 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
elmot 1:d0dfbce63a89 1054 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
elmot 1:d0dfbce63a89 1055 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
elmot 1:d0dfbce63a89 1056 *
elmot 1:d0dfbce63a89 1057 * @retval None
elmot 1:d0dfbce63a89 1058 */
elmot 1:d0dfbce63a89 1059 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
elmot 1:d0dfbce63a89 1060 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))
elmot 1:d0dfbce63a89 1061
elmot 1:d0dfbce63a89 1062 /** @brief Macro to get the SAI2 clock source.
elmot 1:d0dfbce63a89 1063 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1064 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
elmot 1:d0dfbce63a89 1065 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
elmot 1:d0dfbce63a89 1066 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
elmot 1:d0dfbce63a89 1067 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
elmot 1:d0dfbce63a89 1068 */
elmot 1:d0dfbce63a89 1069 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)))
elmot 1:d0dfbce63a89 1070
elmot 1:d0dfbce63a89 1071 #endif /* SAI2 */
elmot 1:d0dfbce63a89 1072
elmot 1:d0dfbce63a89 1073 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
elmot 1:d0dfbce63a89 1074 *
elmot 1:d0dfbce63a89 1075 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
elmot 1:d0dfbce63a89 1076 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1077 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
elmot 1:d0dfbce63a89 1078 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
elmot 1:d0dfbce63a89 1079 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
elmot 1:d0dfbce63a89 1080 * @retval None
elmot 1:d0dfbce63a89 1081 */
elmot 1:d0dfbce63a89 1082 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1083 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
elmot 1:d0dfbce63a89 1084
elmot 1:d0dfbce63a89 1085 /** @brief Macro to get the I2C1 clock source.
elmot 1:d0dfbce63a89 1086 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1087 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
elmot 1:d0dfbce63a89 1088 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
elmot 1:d0dfbce63a89 1089 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
elmot 1:d0dfbce63a89 1090 */
elmot 1:d0dfbce63a89 1091 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
elmot 1:d0dfbce63a89 1092
elmot 1:d0dfbce63a89 1093 #if defined(I2C2)
elmot 1:d0dfbce63a89 1094
elmot 1:d0dfbce63a89 1095 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
elmot 1:d0dfbce63a89 1096 *
elmot 1:d0dfbce63a89 1097 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
elmot 1:d0dfbce63a89 1098 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1099 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
elmot 1:d0dfbce63a89 1100 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
elmot 1:d0dfbce63a89 1101 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
elmot 1:d0dfbce63a89 1102 * @retval None
elmot 1:d0dfbce63a89 1103 */
elmot 1:d0dfbce63a89 1104 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1105 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
elmot 1:d0dfbce63a89 1106
elmot 1:d0dfbce63a89 1107 /** @brief Macro to get the I2C2 clock source.
elmot 1:d0dfbce63a89 1108 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1109 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
elmot 1:d0dfbce63a89 1110 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
elmot 1:d0dfbce63a89 1111 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
elmot 1:d0dfbce63a89 1112 */
elmot 1:d0dfbce63a89 1113 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))
elmot 1:d0dfbce63a89 1114
elmot 1:d0dfbce63a89 1115 #endif /* I2C2 */
elmot 1:d0dfbce63a89 1116
elmot 1:d0dfbce63a89 1117 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
elmot 1:d0dfbce63a89 1118 *
elmot 1:d0dfbce63a89 1119 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
elmot 1:d0dfbce63a89 1120 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1121 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
elmot 1:d0dfbce63a89 1122 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
elmot 1:d0dfbce63a89 1123 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
elmot 1:d0dfbce63a89 1124 * @retval None
elmot 1:d0dfbce63a89 1125 */
elmot 1:d0dfbce63a89 1126 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1127 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
elmot 1:d0dfbce63a89 1128
elmot 1:d0dfbce63a89 1129 /** @brief Macro to get the I2C3 clock source.
elmot 1:d0dfbce63a89 1130 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1131 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
elmot 1:d0dfbce63a89 1132 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
elmot 1:d0dfbce63a89 1133 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
elmot 1:d0dfbce63a89 1134 */
elmot 1:d0dfbce63a89 1135 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
elmot 1:d0dfbce63a89 1136
elmot 1:d0dfbce63a89 1137 /** @brief Macro to configure the USART1 clock (USART1CLK).
elmot 1:d0dfbce63a89 1138 *
elmot 1:d0dfbce63a89 1139 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
elmot 1:d0dfbce63a89 1140 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1141 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
elmot 1:d0dfbce63a89 1142 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
elmot 1:d0dfbce63a89 1143 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
elmot 1:d0dfbce63a89 1144 * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock
elmot 1:d0dfbce63a89 1145 * @retval None
elmot 1:d0dfbce63a89 1146 */
elmot 1:d0dfbce63a89 1147 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1148 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
elmot 1:d0dfbce63a89 1149
elmot 1:d0dfbce63a89 1150 /** @brief Macro to get the USART1 clock source.
elmot 1:d0dfbce63a89 1151 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1152 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
elmot 1:d0dfbce63a89 1153 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
elmot 1:d0dfbce63a89 1154 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
elmot 1:d0dfbce63a89 1155 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
elmot 1:d0dfbce63a89 1156 */
elmot 1:d0dfbce63a89 1157 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
elmot 1:d0dfbce63a89 1158
elmot 1:d0dfbce63a89 1159 /** @brief Macro to configure the USART2 clock (USART2CLK).
elmot 1:d0dfbce63a89 1160 *
elmot 1:d0dfbce63a89 1161 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
elmot 1:d0dfbce63a89 1162 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1163 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
elmot 1:d0dfbce63a89 1164 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
elmot 1:d0dfbce63a89 1165 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
elmot 1:d0dfbce63a89 1166 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
elmot 1:d0dfbce63a89 1167 * @retval None
elmot 1:d0dfbce63a89 1168 */
elmot 1:d0dfbce63a89 1169 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1170 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
elmot 1:d0dfbce63a89 1171
elmot 1:d0dfbce63a89 1172 /** @brief Macro to get the USART2 clock source.
elmot 1:d0dfbce63a89 1173 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1174 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
elmot 1:d0dfbce63a89 1175 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
elmot 1:d0dfbce63a89 1176 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
elmot 1:d0dfbce63a89 1177 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
elmot 1:d0dfbce63a89 1178 */
elmot 1:d0dfbce63a89 1179 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
elmot 1:d0dfbce63a89 1180
elmot 1:d0dfbce63a89 1181 #if defined(USART3)
elmot 1:d0dfbce63a89 1182
elmot 1:d0dfbce63a89 1183 /** @brief Macro to configure the USART3 clock (USART3CLK).
elmot 1:d0dfbce63a89 1184 *
elmot 1:d0dfbce63a89 1185 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source.
elmot 1:d0dfbce63a89 1186 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1187 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
elmot 1:d0dfbce63a89 1188 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
elmot 1:d0dfbce63a89 1189 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
elmot 1:d0dfbce63a89 1190 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
elmot 1:d0dfbce63a89 1191 * @retval None
elmot 1:d0dfbce63a89 1192 */
elmot 1:d0dfbce63a89 1193 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1194 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
elmot 1:d0dfbce63a89 1195
elmot 1:d0dfbce63a89 1196 /** @brief Macro to get the USART3 clock source.
elmot 1:d0dfbce63a89 1197 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1198 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
elmot 1:d0dfbce63a89 1199 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
elmot 1:d0dfbce63a89 1200 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
elmot 1:d0dfbce63a89 1201 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
elmot 1:d0dfbce63a89 1202 */
elmot 1:d0dfbce63a89 1203 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))
elmot 1:d0dfbce63a89 1204
elmot 1:d0dfbce63a89 1205 #endif /* USART3 */
elmot 1:d0dfbce63a89 1206
elmot 1:d0dfbce63a89 1207 #if defined(UART4)
elmot 1:d0dfbce63a89 1208
elmot 1:d0dfbce63a89 1209 /** @brief Macro to configure the UART4 clock (UART4CLK).
elmot 1:d0dfbce63a89 1210 *
elmot 1:d0dfbce63a89 1211 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source.
elmot 1:d0dfbce63a89 1212 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1213 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
elmot 1:d0dfbce63a89 1214 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
elmot 1:d0dfbce63a89 1215 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
elmot 1:d0dfbce63a89 1216 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
elmot 1:d0dfbce63a89 1217 * @retval None
elmot 1:d0dfbce63a89 1218 */
elmot 1:d0dfbce63a89 1219 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1220 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
elmot 1:d0dfbce63a89 1221
elmot 1:d0dfbce63a89 1222 /** @brief Macro to get the UART4 clock source.
elmot 1:d0dfbce63a89 1223 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1224 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
elmot 1:d0dfbce63a89 1225 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
elmot 1:d0dfbce63a89 1226 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
elmot 1:d0dfbce63a89 1227 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
elmot 1:d0dfbce63a89 1228 */
elmot 1:d0dfbce63a89 1229 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)))
elmot 1:d0dfbce63a89 1230
elmot 1:d0dfbce63a89 1231 #endif /* UART4 */
elmot 1:d0dfbce63a89 1232
elmot 1:d0dfbce63a89 1233 #if defined(UART5)
elmot 1:d0dfbce63a89 1234
elmot 1:d0dfbce63a89 1235 /** @brief Macro to configure the UART5 clock (UART5CLK).
elmot 1:d0dfbce63a89 1236 *
elmot 1:d0dfbce63a89 1237 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source.
elmot 1:d0dfbce63a89 1238 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1239 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
elmot 1:d0dfbce63a89 1240 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
elmot 1:d0dfbce63a89 1241 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
elmot 1:d0dfbce63a89 1242 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
elmot 1:d0dfbce63a89 1243 * @retval None
elmot 1:d0dfbce63a89 1244 */
elmot 1:d0dfbce63a89 1245 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1246 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
elmot 1:d0dfbce63a89 1247
elmot 1:d0dfbce63a89 1248 /** @brief Macro to get the UART5 clock source.
elmot 1:d0dfbce63a89 1249 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1250 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
elmot 1:d0dfbce63a89 1251 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
elmot 1:d0dfbce63a89 1252 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
elmot 1:d0dfbce63a89 1253 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
elmot 1:d0dfbce63a89 1254 */
elmot 1:d0dfbce63a89 1255 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)))
elmot 1:d0dfbce63a89 1256
elmot 1:d0dfbce63a89 1257 #endif /* UART5 */
elmot 1:d0dfbce63a89 1258
elmot 1:d0dfbce63a89 1259 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
elmot 1:d0dfbce63a89 1260 *
elmot 1:d0dfbce63a89 1261 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
elmot 1:d0dfbce63a89 1262 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1263 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
elmot 1:d0dfbce63a89 1264 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
elmot 1:d0dfbce63a89 1265 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
elmot 1:d0dfbce63a89 1266 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
elmot 1:d0dfbce63a89 1267 * @retval None
elmot 1:d0dfbce63a89 1268 */
elmot 1:d0dfbce63a89 1269 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1270 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
elmot 1:d0dfbce63a89 1271
elmot 1:d0dfbce63a89 1272 /** @brief Macro to get the LPUART1 clock source.
elmot 1:d0dfbce63a89 1273 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1274 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
elmot 1:d0dfbce63a89 1275 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
elmot 1:d0dfbce63a89 1276 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
elmot 1:d0dfbce63a89 1277 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
elmot 1:d0dfbce63a89 1278 */
elmot 1:d0dfbce63a89 1279 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
elmot 1:d0dfbce63a89 1280
elmot 1:d0dfbce63a89 1281 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
elmot 1:d0dfbce63a89 1282 *
elmot 1:d0dfbce63a89 1283 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
elmot 1:d0dfbce63a89 1284 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1285 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK PCLK selected as LPTIM1 clock
elmot 1:d0dfbce63a89 1286 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
elmot 1:d0dfbce63a89 1287 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
elmot 1:d0dfbce63a89 1288 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
elmot 1:d0dfbce63a89 1289 * @retval None
elmot 1:d0dfbce63a89 1290 */
elmot 1:d0dfbce63a89 1291 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1292 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
elmot 1:d0dfbce63a89 1293
elmot 1:d0dfbce63a89 1294 /** @brief Macro to get the LPTIM1 clock source.
elmot 1:d0dfbce63a89 1295 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1296 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK PCLK selected as LPUART1 clock
elmot 1:d0dfbce63a89 1297 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
elmot 1:d0dfbce63a89 1298 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock
elmot 1:d0dfbce63a89 1299 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock
elmot 1:d0dfbce63a89 1300 */
elmot 1:d0dfbce63a89 1301 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
elmot 1:d0dfbce63a89 1302
elmot 1:d0dfbce63a89 1303 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK).
elmot 1:d0dfbce63a89 1304 *
elmot 1:d0dfbce63a89 1305 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
elmot 1:d0dfbce63a89 1306 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1307 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK PCLK selected as LPTIM2 clock
elmot 1:d0dfbce63a89 1308 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
elmot 1:d0dfbce63a89 1309 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock
elmot 1:d0dfbce63a89 1310 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock
elmot 1:d0dfbce63a89 1311 * @retval None
elmot 1:d0dfbce63a89 1312 */
elmot 1:d0dfbce63a89 1313 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1314 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
elmot 1:d0dfbce63a89 1315
elmot 1:d0dfbce63a89 1316 /** @brief Macro to get the LPTIM2 clock source.
elmot 1:d0dfbce63a89 1317 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1318 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK PCLK selected as LPUART1 clock
elmot 1:d0dfbce63a89 1319 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock
elmot 1:d0dfbce63a89 1320 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock
elmot 1:d0dfbce63a89 1321 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock
elmot 1:d0dfbce63a89 1322 */
elmot 1:d0dfbce63a89 1323 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))
elmot 1:d0dfbce63a89 1324
elmot 1:d0dfbce63a89 1325 #if defined(SDMMC1)
elmot 1:d0dfbce63a89 1326
elmot 1:d0dfbce63a89 1327 /** @brief Macro to configure the SDMMC1 clock.
elmot 1:d0dfbce63a89 1328 *
elmot 1:d0dfbce63a89 1329 @if STM32L486xx
elmot 1:d0dfbce63a89 1330 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
elmot 1:d0dfbce63a89 1331 @endif
elmot 1:d0dfbce63a89 1332 *
elmot 1:d0dfbce63a89 1333 @if STM32L443xx
elmot 1:d0dfbce63a89 1334 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
elmot 1:d0dfbce63a89 1335 @endif
elmot 1:d0dfbce63a89 1336 *
elmot 1:d0dfbce63a89 1337 * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.
elmot 1:d0dfbce63a89 1338 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1339 @if STM32L486xx
elmot 1:d0dfbce63a89 1340 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
elmot 1:d0dfbce63a89 1341 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
elmot 1:d0dfbce63a89 1342 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
elmot 1:d0dfbce63a89 1343 @endif
elmot 1:d0dfbce63a89 1344 @if STM32L443xx
elmot 1:d0dfbce63a89 1345 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
elmot 1:d0dfbce63a89 1346 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
elmot 1:d0dfbce63a89 1347 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
elmot 1:d0dfbce63a89 1348 @endif
elmot 1:d0dfbce63a89 1349 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock
elmot 1:d0dfbce63a89 1350 * @retval None
elmot 1:d0dfbce63a89 1351 */
elmot 1:d0dfbce63a89 1352 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1353 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
elmot 1:d0dfbce63a89 1354
elmot 1:d0dfbce63a89 1355 /** @brief Macro to get the SDMMC1 clock.
elmot 1:d0dfbce63a89 1356 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1357 @if STM32L486xx
elmot 1:d0dfbce63a89 1358 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
elmot 1:d0dfbce63a89 1359 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
elmot 1:d0dfbce63a89 1360 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
elmot 1:d0dfbce63a89 1361 @endif
elmot 1:d0dfbce63a89 1362 @if STM32L443xx
elmot 1:d0dfbce63a89 1363 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
elmot 1:d0dfbce63a89 1364 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
elmot 1:d0dfbce63a89 1365 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
elmot 1:d0dfbce63a89 1366 @endif
elmot 1:d0dfbce63a89 1367 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
elmot 1:d0dfbce63a89 1368 */
elmot 1:d0dfbce63a89 1369 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
elmot 1:d0dfbce63a89 1370
elmot 1:d0dfbce63a89 1371 #endif /* SDMMC1 */
elmot 1:d0dfbce63a89 1372
elmot 1:d0dfbce63a89 1373 /** @brief Macro to configure the RNG clock.
elmot 1:d0dfbce63a89 1374 *
elmot 1:d0dfbce63a89 1375 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
elmot 1:d0dfbce63a89 1376 *
elmot 1:d0dfbce63a89 1377 * @param __RNG_CLKSOURCE__ specifies the RNG clock source.
elmot 1:d0dfbce63a89 1378 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1379 @if STM32L486xx
elmot 1:d0dfbce63a89 1380 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
elmot 1:d0dfbce63a89 1381 @endif
elmot 1:d0dfbce63a89 1382 @if STM32L443xx
elmot 1:d0dfbce63a89 1383 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
elmot 1:d0dfbce63a89 1384 @endif
elmot 1:d0dfbce63a89 1385 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
elmot 1:d0dfbce63a89 1386 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock
elmot 1:d0dfbce63a89 1387 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock
elmot 1:d0dfbce63a89 1388 * @retval None
elmot 1:d0dfbce63a89 1389 */
elmot 1:d0dfbce63a89 1390 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1391 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__))
elmot 1:d0dfbce63a89 1392
elmot 1:d0dfbce63a89 1393 /** @brief Macro to get the RNG clock.
elmot 1:d0dfbce63a89 1394 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1395 @if STM32L486xx
elmot 1:d0dfbce63a89 1396 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
elmot 1:d0dfbce63a89 1397 @endif
elmot 1:d0dfbce63a89 1398 @if STM32L443xx
elmot 1:d0dfbce63a89 1399 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
elmot 1:d0dfbce63a89 1400 @endif
elmot 1:d0dfbce63a89 1401 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
elmot 1:d0dfbce63a89 1402 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock
elmot 1:d0dfbce63a89 1403 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock
elmot 1:d0dfbce63a89 1404 */
elmot 1:d0dfbce63a89 1405 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
elmot 1:d0dfbce63a89 1406
elmot 1:d0dfbce63a89 1407 #if defined(USB_OTG_FS) || defined(USB)
elmot 1:d0dfbce63a89 1408
elmot 1:d0dfbce63a89 1409 /** @brief Macro to configure the USB clock (USBCLK).
elmot 1:d0dfbce63a89 1410 *
elmot 1:d0dfbce63a89 1411 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
elmot 1:d0dfbce63a89 1412 *
elmot 1:d0dfbce63a89 1413 * @param __USB_CLKSOURCE__ specifies the USB clock source.
elmot 1:d0dfbce63a89 1414 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1415 @if STM32L486xx
elmot 1:d0dfbce63a89 1416 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
elmot 1:d0dfbce63a89 1417 @endif
elmot 1:d0dfbce63a89 1418 @if STM32L443xx
elmot 1:d0dfbce63a89 1419 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
elmot 1:d0dfbce63a89 1420 @endif
elmot 1:d0dfbce63a89 1421 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock
elmot 1:d0dfbce63a89 1422 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
elmot 1:d0dfbce63a89 1423 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
elmot 1:d0dfbce63a89 1424 * @retval None
elmot 1:d0dfbce63a89 1425 */
elmot 1:d0dfbce63a89 1426 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1427 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__))
elmot 1:d0dfbce63a89 1428
elmot 1:d0dfbce63a89 1429 /** @brief Macro to get the USB clock source.
elmot 1:d0dfbce63a89 1430 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1431 @if STM32L486xx
elmot 1:d0dfbce63a89 1432 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
elmot 1:d0dfbce63a89 1433 @endif
elmot 1:d0dfbce63a89 1434 @if STM32L443xx
elmot 1:d0dfbce63a89 1435 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
elmot 1:d0dfbce63a89 1436 @endif
elmot 1:d0dfbce63a89 1437 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock
elmot 1:d0dfbce63a89 1438 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
elmot 1:d0dfbce63a89 1439 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
elmot 1:d0dfbce63a89 1440 */
elmot 1:d0dfbce63a89 1441 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
elmot 1:d0dfbce63a89 1442
elmot 1:d0dfbce63a89 1443 #endif /* USB_OTG_FS || USB */
elmot 1:d0dfbce63a89 1444
elmot 1:d0dfbce63a89 1445 /** @brief Macro to configure the ADC interface clock.
elmot 1:d0dfbce63a89 1446 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
elmot 1:d0dfbce63a89 1447 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1448 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
elmot 1:d0dfbce63a89 1449 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
elmot 1:d0dfbce63a89 1450 @if STM32L486xx
elmot 1:d0dfbce63a89 1451 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
elmot 1:d0dfbce63a89 1452 @endif
elmot 1:d0dfbce63a89 1453 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
elmot 1:d0dfbce63a89 1454 * @retval None
elmot 1:d0dfbce63a89 1455 */
elmot 1:d0dfbce63a89 1456 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1457 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
elmot 1:d0dfbce63a89 1458
elmot 1:d0dfbce63a89 1459 /** @brief Macro to get the ADC clock source.
elmot 1:d0dfbce63a89 1460 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1461 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
elmot 1:d0dfbce63a89 1462 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
elmot 1:d0dfbce63a89 1463 @if STM32L486xx
elmot 1:d0dfbce63a89 1464 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
elmot 1:d0dfbce63a89 1465 @endif
elmot 1:d0dfbce63a89 1466 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
elmot 1:d0dfbce63a89 1467 */
elmot 1:d0dfbce63a89 1468 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))
elmot 1:d0dfbce63a89 1469
elmot 1:d0dfbce63a89 1470 #if defined(SWPMI1)
elmot 1:d0dfbce63a89 1471
elmot 1:d0dfbce63a89 1472 /** @brief Macro to configure the SWPMI1 clock.
elmot 1:d0dfbce63a89 1473 * @param __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source.
elmot 1:d0dfbce63a89 1474 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1475 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK PCLK Clock selected as SWPMI1 clock
elmot 1:d0dfbce63a89 1476 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
elmot 1:d0dfbce63a89 1477 * @retval None
elmot 1:d0dfbce63a89 1478 */
elmot 1:d0dfbce63a89 1479 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1480 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__))
elmot 1:d0dfbce63a89 1481
elmot 1:d0dfbce63a89 1482 /** @brief Macro to get the SWPMI1 clock source.
elmot 1:d0dfbce63a89 1483 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1484 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK PCLK Clock selected as SWPMI1 clock
elmot 1:d0dfbce63a89 1485 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
elmot 1:d0dfbce63a89 1486 */
elmot 1:d0dfbce63a89 1487 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)))
elmot 1:d0dfbce63a89 1488
elmot 1:d0dfbce63a89 1489 #endif /* SWPMI1 */
elmot 1:d0dfbce63a89 1490
elmot 1:d0dfbce63a89 1491 #if defined(DFSDM1_Filter0)
elmot 1:d0dfbce63a89 1492 /** @brief Macro to configure the DFSDM1 clock.
elmot 1:d0dfbce63a89 1493 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
elmot 1:d0dfbce63a89 1494 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1495 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK PCLK Clock selected as DFSDM1 clock
elmot 1:d0dfbce63a89 1496 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock
elmot 1:d0dfbce63a89 1497 * @retval None
elmot 1:d0dfbce63a89 1498 */
elmot 1:d0dfbce63a89 1499 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
elmot 1:d0dfbce63a89 1500 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
elmot 1:d0dfbce63a89 1501
elmot 1:d0dfbce63a89 1502 /** @brief Macro to get the DFSDM1 clock source.
elmot 1:d0dfbce63a89 1503 * @retval The clock source can be one of the following values:
elmot 1:d0dfbce63a89 1504 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK PCLK Clock selected as DFSDM1 clock
elmot 1:d0dfbce63a89 1505 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock
elmot 1:d0dfbce63a89 1506 */
elmot 1:d0dfbce63a89 1507 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)))
elmot 1:d0dfbce63a89 1508
elmot 1:d0dfbce63a89 1509 #endif /* DFSDM1_Filter0 */
elmot 1:d0dfbce63a89 1510
elmot 1:d0dfbce63a89 1511
elmot 1:d0dfbce63a89 1512 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
elmot 1:d0dfbce63a89 1513 * @brief macros to manage the specified RCC Flags and interrupts.
elmot 1:d0dfbce63a89 1514 * @{
elmot 1:d0dfbce63a89 1515 */
elmot 1:d0dfbce63a89 1516
elmot 1:d0dfbce63a89 1517 /** @brief Enable PLLSAI1RDY interrupt.
elmot 1:d0dfbce63a89 1518 * @retval None
elmot 1:d0dfbce63a89 1519 */
elmot 1:d0dfbce63a89 1520 #define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
elmot 1:d0dfbce63a89 1521
elmot 1:d0dfbce63a89 1522 /** @brief Disable PLLSAI1RDY interrupt.
elmot 1:d0dfbce63a89 1523 * @retval None
elmot 1:d0dfbce63a89 1524 */
elmot 1:d0dfbce63a89 1525 #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
elmot 1:d0dfbce63a89 1526
elmot 1:d0dfbce63a89 1527 /** @brief Clear the PLLSAI1RDY interrupt pending bit.
elmot 1:d0dfbce63a89 1528 * @retval None
elmot 1:d0dfbce63a89 1529 */
elmot 1:d0dfbce63a89 1530 #define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
elmot 1:d0dfbce63a89 1531
elmot 1:d0dfbce63a89 1532 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not.
elmot 1:d0dfbce63a89 1533 * @retval TRUE or FALSE.
elmot 1:d0dfbce63a89 1534 */
elmot 1:d0dfbce63a89 1535 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
elmot 1:d0dfbce63a89 1536
elmot 1:d0dfbce63a89 1537 /** @brief Check whether the PLLSAI1RDY flag is set or not.
elmot 1:d0dfbce63a89 1538 * @retval TRUE or FALSE.
elmot 1:d0dfbce63a89 1539 */
elmot 1:d0dfbce63a89 1540 #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
elmot 1:d0dfbce63a89 1541
elmot 1:d0dfbce63a89 1542 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 1543
elmot 1:d0dfbce63a89 1544 /** @brief Enable PLLSAI2RDY interrupt.
elmot 1:d0dfbce63a89 1545 * @retval None
elmot 1:d0dfbce63a89 1546 */
elmot 1:d0dfbce63a89 1547 #define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
elmot 1:d0dfbce63a89 1548
elmot 1:d0dfbce63a89 1549 /** @brief Disable PLLSAI2RDY interrupt.
elmot 1:d0dfbce63a89 1550 * @retval None
elmot 1:d0dfbce63a89 1551 */
elmot 1:d0dfbce63a89 1552 #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
elmot 1:d0dfbce63a89 1553
elmot 1:d0dfbce63a89 1554 /** @brief Clear the PLLSAI2RDY interrupt pending bit.
elmot 1:d0dfbce63a89 1555 * @retval None
elmot 1:d0dfbce63a89 1556 */
elmot 1:d0dfbce63a89 1557 #define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
elmot 1:d0dfbce63a89 1558
elmot 1:d0dfbce63a89 1559 /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not.
elmot 1:d0dfbce63a89 1560 * @retval TRUE or FALSE.
elmot 1:d0dfbce63a89 1561 */
elmot 1:d0dfbce63a89 1562 #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
elmot 1:d0dfbce63a89 1563
elmot 1:d0dfbce63a89 1564 /** @brief Check whether the PLLSAI2RDY flag is set or not.
elmot 1:d0dfbce63a89 1565 * @retval TRUE or FALSE.
elmot 1:d0dfbce63a89 1566 */
elmot 1:d0dfbce63a89 1567 #define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
elmot 1:d0dfbce63a89 1568
elmot 1:d0dfbce63a89 1569 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 1570
elmot 1:d0dfbce63a89 1571
elmot 1:d0dfbce63a89 1572 /**
elmot 1:d0dfbce63a89 1573 * @brief Enable the RCC LSE CSS Extended Interrupt Line.
elmot 1:d0dfbce63a89 1574 * @retval None
elmot 1:d0dfbce63a89 1575 */
elmot 1:d0dfbce63a89 1576 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
elmot 1:d0dfbce63a89 1577
elmot 1:d0dfbce63a89 1578 /**
elmot 1:d0dfbce63a89 1579 * @brief Disable the RCC LSE CSS Extended Interrupt Line.
elmot 1:d0dfbce63a89 1580 * @retval None
elmot 1:d0dfbce63a89 1581 */
elmot 1:d0dfbce63a89 1582 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
elmot 1:d0dfbce63a89 1583
elmot 1:d0dfbce63a89 1584 /**
elmot 1:d0dfbce63a89 1585 * @brief Enable the RCC LSE CSS Event Line.
elmot 1:d0dfbce63a89 1586 * @retval None.
elmot 1:d0dfbce63a89 1587 */
elmot 1:d0dfbce63a89 1588 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
elmot 1:d0dfbce63a89 1589
elmot 1:d0dfbce63a89 1590 /**
elmot 1:d0dfbce63a89 1591 * @brief Disable the RCC LSE CSS Event Line.
elmot 1:d0dfbce63a89 1592 * @retval None.
elmot 1:d0dfbce63a89 1593 */
elmot 1:d0dfbce63a89 1594 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
elmot 1:d0dfbce63a89 1595
elmot 1:d0dfbce63a89 1596
elmot 1:d0dfbce63a89 1597 /**
elmot 1:d0dfbce63a89 1598 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
elmot 1:d0dfbce63a89 1599 * @retval None.
elmot 1:d0dfbce63a89 1600 */
elmot 1:d0dfbce63a89 1601 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
elmot 1:d0dfbce63a89 1602
elmot 1:d0dfbce63a89 1603
elmot 1:d0dfbce63a89 1604 /**
elmot 1:d0dfbce63a89 1605 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
elmot 1:d0dfbce63a89 1606 * @retval None.
elmot 1:d0dfbce63a89 1607 */
elmot 1:d0dfbce63a89 1608 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
elmot 1:d0dfbce63a89 1609
elmot 1:d0dfbce63a89 1610
elmot 1:d0dfbce63a89 1611 /**
elmot 1:d0dfbce63a89 1612 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
elmot 1:d0dfbce63a89 1613 * @retval None.
elmot 1:d0dfbce63a89 1614 */
elmot 1:d0dfbce63a89 1615 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
elmot 1:d0dfbce63a89 1616
elmot 1:d0dfbce63a89 1617 /**
elmot 1:d0dfbce63a89 1618 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
elmot 1:d0dfbce63a89 1619 * @retval None.
elmot 1:d0dfbce63a89 1620 */
elmot 1:d0dfbce63a89 1621 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
elmot 1:d0dfbce63a89 1622
elmot 1:d0dfbce63a89 1623 /**
elmot 1:d0dfbce63a89 1624 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
elmot 1:d0dfbce63a89 1625 * @retval None.
elmot 1:d0dfbce63a89 1626 */
elmot 1:d0dfbce63a89 1627 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
elmot 1:d0dfbce63a89 1628 do { \
elmot 1:d0dfbce63a89 1629 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
elmot 1:d0dfbce63a89 1630 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
elmot 1:d0dfbce63a89 1631 } while(0)
elmot 1:d0dfbce63a89 1632
elmot 1:d0dfbce63a89 1633 /**
elmot 1:d0dfbce63a89 1634 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
elmot 1:d0dfbce63a89 1635 * @retval None.
elmot 1:d0dfbce63a89 1636 */
elmot 1:d0dfbce63a89 1637 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
elmot 1:d0dfbce63a89 1638 do { \
elmot 1:d0dfbce63a89 1639 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
elmot 1:d0dfbce63a89 1640 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
elmot 1:d0dfbce63a89 1641 } while(0)
elmot 1:d0dfbce63a89 1642
elmot 1:d0dfbce63a89 1643 /**
elmot 1:d0dfbce63a89 1644 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
elmot 1:d0dfbce63a89 1645 * @retval EXTI RCC LSE CSS Line Status.
elmot 1:d0dfbce63a89 1646 */
elmot 1:d0dfbce63a89 1647 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
elmot 1:d0dfbce63a89 1648
elmot 1:d0dfbce63a89 1649 /**
elmot 1:d0dfbce63a89 1650 * @brief Clear the RCC LSE CSS EXTI flag.
elmot 1:d0dfbce63a89 1651 * @retval None.
elmot 1:d0dfbce63a89 1652 */
elmot 1:d0dfbce63a89 1653 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
elmot 1:d0dfbce63a89 1654
elmot 1:d0dfbce63a89 1655 /**
elmot 1:d0dfbce63a89 1656 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
elmot 1:d0dfbce63a89 1657 * @retval None.
elmot 1:d0dfbce63a89 1658 */
elmot 1:d0dfbce63a89 1659 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
elmot 1:d0dfbce63a89 1660
elmot 1:d0dfbce63a89 1661
elmot 1:d0dfbce63a89 1662 #if defined(CRS)
elmot 1:d0dfbce63a89 1663
elmot 1:d0dfbce63a89 1664 /**
elmot 1:d0dfbce63a89 1665 * @brief Enable the specified CRS interrupts.
elmot 1:d0dfbce63a89 1666 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
elmot 1:d0dfbce63a89 1667 * This parameter can be any combination of the following values:
elmot 1:d0dfbce63a89 1668 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
elmot 1:d0dfbce63a89 1669 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
elmot 1:d0dfbce63a89 1670 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
elmot 1:d0dfbce63a89 1671 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
elmot 1:d0dfbce63a89 1672 * @retval None
elmot 1:d0dfbce63a89 1673 */
elmot 1:d0dfbce63a89 1674 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
elmot 1:d0dfbce63a89 1675
elmot 1:d0dfbce63a89 1676 /**
elmot 1:d0dfbce63a89 1677 * @brief Disable the specified CRS interrupts.
elmot 1:d0dfbce63a89 1678 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
elmot 1:d0dfbce63a89 1679 * This parameter can be any combination of the following values:
elmot 1:d0dfbce63a89 1680 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
elmot 1:d0dfbce63a89 1681 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
elmot 1:d0dfbce63a89 1682 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
elmot 1:d0dfbce63a89 1683 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
elmot 1:d0dfbce63a89 1684 * @retval None
elmot 1:d0dfbce63a89 1685 */
elmot 1:d0dfbce63a89 1686 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
elmot 1:d0dfbce63a89 1687
elmot 1:d0dfbce63a89 1688 /** @brief Check whether the CRS interrupt has occurred or not.
elmot 1:d0dfbce63a89 1689 * @param __INTERRUPT__ specifies the CRS interrupt source to check.
elmot 1:d0dfbce63a89 1690 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1691 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
elmot 1:d0dfbce63a89 1692 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
elmot 1:d0dfbce63a89 1693 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
elmot 1:d0dfbce63a89 1694 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
elmot 1:d0dfbce63a89 1695 * @retval The new state of __INTERRUPT__ (SET or RESET).
elmot 1:d0dfbce63a89 1696 */
elmot 1:d0dfbce63a89 1697 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
elmot 1:d0dfbce63a89 1698
elmot 1:d0dfbce63a89 1699 /** @brief Clear the CRS interrupt pending bits
elmot 1:d0dfbce63a89 1700 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
elmot 1:d0dfbce63a89 1701 * This parameter can be any combination of the following values:
elmot 1:d0dfbce63a89 1702 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
elmot 1:d0dfbce63a89 1703 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
elmot 1:d0dfbce63a89 1704 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
elmot 1:d0dfbce63a89 1705 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
elmot 1:d0dfbce63a89 1706 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
elmot 1:d0dfbce63a89 1707 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
elmot 1:d0dfbce63a89 1708 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
elmot 1:d0dfbce63a89 1709 */
elmot 1:d0dfbce63a89 1710 /* CRS IT Error Mask */
elmot 1:d0dfbce63a89 1711 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
elmot 1:d0dfbce63a89 1712
elmot 1:d0dfbce63a89 1713 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
elmot 1:d0dfbce63a89 1714 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
elmot 1:d0dfbce63a89 1715 { \
elmot 1:d0dfbce63a89 1716 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
elmot 1:d0dfbce63a89 1717 } \
elmot 1:d0dfbce63a89 1718 else \
elmot 1:d0dfbce63a89 1719 { \
elmot 1:d0dfbce63a89 1720 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
elmot 1:d0dfbce63a89 1721 } \
elmot 1:d0dfbce63a89 1722 } while(0)
elmot 1:d0dfbce63a89 1723
elmot 1:d0dfbce63a89 1724 /**
elmot 1:d0dfbce63a89 1725 * @brief Check whether the specified CRS flag is set or not.
elmot 1:d0dfbce63a89 1726 * @param __FLAG__ specifies the flag to check.
elmot 1:d0dfbce63a89 1727 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1728 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
elmot 1:d0dfbce63a89 1729 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
elmot 1:d0dfbce63a89 1730 * @arg @ref RCC_CRS_FLAG_ERR Error
elmot 1:d0dfbce63a89 1731 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
elmot 1:d0dfbce63a89 1732 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
elmot 1:d0dfbce63a89 1733 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
elmot 1:d0dfbce63a89 1734 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
elmot 1:d0dfbce63a89 1735 * @retval The new state of _FLAG_ (TRUE or FALSE).
elmot 1:d0dfbce63a89 1736 */
elmot 1:d0dfbce63a89 1737 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
elmot 1:d0dfbce63a89 1738
elmot 1:d0dfbce63a89 1739 /**
elmot 1:d0dfbce63a89 1740 * @brief Clear the CRS specified FLAG.
elmot 1:d0dfbce63a89 1741 * @param __FLAG__ specifies the flag to clear.
elmot 1:d0dfbce63a89 1742 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1743 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
elmot 1:d0dfbce63a89 1744 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
elmot 1:d0dfbce63a89 1745 * @arg @ref RCC_CRS_FLAG_ERR Error
elmot 1:d0dfbce63a89 1746 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
elmot 1:d0dfbce63a89 1747 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
elmot 1:d0dfbce63a89 1748 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
elmot 1:d0dfbce63a89 1749 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
elmot 1:d0dfbce63a89 1750 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
elmot 1:d0dfbce63a89 1751 * @retval None
elmot 1:d0dfbce63a89 1752 */
elmot 1:d0dfbce63a89 1753
elmot 1:d0dfbce63a89 1754 /* CRS Flag Error Mask */
elmot 1:d0dfbce63a89 1755 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
elmot 1:d0dfbce63a89 1756
elmot 1:d0dfbce63a89 1757 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
elmot 1:d0dfbce63a89 1758 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
elmot 1:d0dfbce63a89 1759 { \
elmot 1:d0dfbce63a89 1760 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
elmot 1:d0dfbce63a89 1761 } \
elmot 1:d0dfbce63a89 1762 else \
elmot 1:d0dfbce63a89 1763 { \
elmot 1:d0dfbce63a89 1764 WRITE_REG(CRS->ICR, (__FLAG__)); \
elmot 1:d0dfbce63a89 1765 } \
elmot 1:d0dfbce63a89 1766 } while(0)
elmot 1:d0dfbce63a89 1767
elmot 1:d0dfbce63a89 1768 #endif /* CRS */
elmot 1:d0dfbce63a89 1769
elmot 1:d0dfbce63a89 1770 /**
elmot 1:d0dfbce63a89 1771 * @}
elmot 1:d0dfbce63a89 1772 */
elmot 1:d0dfbce63a89 1773
elmot 1:d0dfbce63a89 1774 #if defined(CRS)
elmot 1:d0dfbce63a89 1775
elmot 1:d0dfbce63a89 1776 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
elmot 1:d0dfbce63a89 1777 * @{
elmot 1:d0dfbce63a89 1778 */
elmot 1:d0dfbce63a89 1779 /**
elmot 1:d0dfbce63a89 1780 * @brief Enable the oscillator clock for frequency error counter.
elmot 1:d0dfbce63a89 1781 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
elmot 1:d0dfbce63a89 1782 * @retval None
elmot 1:d0dfbce63a89 1783 */
elmot 1:d0dfbce63a89 1784 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
elmot 1:d0dfbce63a89 1785
elmot 1:d0dfbce63a89 1786 /**
elmot 1:d0dfbce63a89 1787 * @brief Disable the oscillator clock for frequency error counter.
elmot 1:d0dfbce63a89 1788 * @retval None
elmot 1:d0dfbce63a89 1789 */
elmot 1:d0dfbce63a89 1790 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
elmot 1:d0dfbce63a89 1791
elmot 1:d0dfbce63a89 1792 /**
elmot 1:d0dfbce63a89 1793 * @brief Enable the automatic hardware adjustement of TRIM bits.
elmot 1:d0dfbce63a89 1794 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
elmot 1:d0dfbce63a89 1795 * @retval None
elmot 1:d0dfbce63a89 1796 */
elmot 1:d0dfbce63a89 1797 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
elmot 1:d0dfbce63a89 1798
elmot 1:d0dfbce63a89 1799 /**
elmot 1:d0dfbce63a89 1800 * @brief Enable or disable the automatic hardware adjustement of TRIM bits.
elmot 1:d0dfbce63a89 1801 * @retval None
elmot 1:d0dfbce63a89 1802 */
elmot 1:d0dfbce63a89 1803 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
elmot 1:d0dfbce63a89 1804
elmot 1:d0dfbce63a89 1805 /**
elmot 1:d0dfbce63a89 1806 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
elmot 1:d0dfbce63a89 1807 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
elmot 1:d0dfbce63a89 1808 * of the synchronization source after prescaling. It is then decreased by one in order to
elmot 1:d0dfbce63a89 1809 * reach the expected synchronization on the zero value. The formula is the following:
elmot 1:d0dfbce63a89 1810 * RELOAD = (fTARGET / fSYNC) -1
elmot 1:d0dfbce63a89 1811 * @param __FTARGET__ Target frequency (value in Hz)
elmot 1:d0dfbce63a89 1812 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
elmot 1:d0dfbce63a89 1813 * @retval None
elmot 1:d0dfbce63a89 1814 */
elmot 1:d0dfbce63a89 1815 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
elmot 1:d0dfbce63a89 1816
elmot 1:d0dfbce63a89 1817 /**
elmot 1:d0dfbce63a89 1818 * @}
elmot 1:d0dfbce63a89 1819 */
elmot 1:d0dfbce63a89 1820
elmot 1:d0dfbce63a89 1821 #endif /* CRS */
elmot 1:d0dfbce63a89 1822
elmot 1:d0dfbce63a89 1823 /**
elmot 1:d0dfbce63a89 1824 * @}
elmot 1:d0dfbce63a89 1825 */
elmot 1:d0dfbce63a89 1826
elmot 1:d0dfbce63a89 1827 /* Exported functions --------------------------------------------------------*/
elmot 1:d0dfbce63a89 1828 /** @addtogroup RCCEx_Exported_Functions
elmot 1:d0dfbce63a89 1829 * @{
elmot 1:d0dfbce63a89 1830 */
elmot 1:d0dfbce63a89 1831
elmot 1:d0dfbce63a89 1832 /** @addtogroup RCCEx_Exported_Functions_Group1
elmot 1:d0dfbce63a89 1833 * @{
elmot 1:d0dfbce63a89 1834 */
elmot 1:d0dfbce63a89 1835
elmot 1:d0dfbce63a89 1836 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
elmot 1:d0dfbce63a89 1837 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
elmot 1:d0dfbce63a89 1838 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
elmot 1:d0dfbce63a89 1839
elmot 1:d0dfbce63a89 1840 /**
elmot 1:d0dfbce63a89 1841 * @}
elmot 1:d0dfbce63a89 1842 */
elmot 1:d0dfbce63a89 1843
elmot 1:d0dfbce63a89 1844 /** @addtogroup RCCEx_Exported_Functions_Group2
elmot 1:d0dfbce63a89 1845 * @{
elmot 1:d0dfbce63a89 1846 */
elmot 1:d0dfbce63a89 1847
elmot 1:d0dfbce63a89 1848 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init);
elmot 1:d0dfbce63a89 1849 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);
elmot 1:d0dfbce63a89 1850
elmot 1:d0dfbce63a89 1851 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 1852
elmot 1:d0dfbce63a89 1853 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init);
elmot 1:d0dfbce63a89 1854 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void);
elmot 1:d0dfbce63a89 1855
elmot 1:d0dfbce63a89 1856 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 1857
elmot 1:d0dfbce63a89 1858 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
elmot 1:d0dfbce63a89 1859 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);
elmot 1:d0dfbce63a89 1860 void HAL_RCCEx_EnableLSECSS(void);
elmot 1:d0dfbce63a89 1861 void HAL_RCCEx_DisableLSECSS(void);
elmot 1:d0dfbce63a89 1862 void HAL_RCCEx_EnableLSECSS_IT(void);
elmot 1:d0dfbce63a89 1863 void HAL_RCCEx_LSECSS_IRQHandler(void);
elmot 1:d0dfbce63a89 1864 void HAL_RCCEx_LSECSS_Callback(void);
elmot 1:d0dfbce63a89 1865 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
elmot 1:d0dfbce63a89 1866 void HAL_RCCEx_DisableLSCO(void);
elmot 1:d0dfbce63a89 1867 void HAL_RCCEx_EnableMSIPLLMode(void);
elmot 1:d0dfbce63a89 1868 void HAL_RCCEx_DisableMSIPLLMode(void);
elmot 1:d0dfbce63a89 1869
elmot 1:d0dfbce63a89 1870 /**
elmot 1:d0dfbce63a89 1871 * @}
elmot 1:d0dfbce63a89 1872 */
elmot 1:d0dfbce63a89 1873
elmot 1:d0dfbce63a89 1874 #if defined(CRS)
elmot 1:d0dfbce63a89 1875
elmot 1:d0dfbce63a89 1876 /** @addtogroup RCCEx_Exported_Functions_Group3
elmot 1:d0dfbce63a89 1877 * @{
elmot 1:d0dfbce63a89 1878 */
elmot 1:d0dfbce63a89 1879
elmot 1:d0dfbce63a89 1880 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
elmot 1:d0dfbce63a89 1881 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
elmot 1:d0dfbce63a89 1882 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
elmot 1:d0dfbce63a89 1883 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
elmot 1:d0dfbce63a89 1884 void HAL_RCCEx_CRS_IRQHandler(void);
elmot 1:d0dfbce63a89 1885 void HAL_RCCEx_CRS_SyncOkCallback(void);
elmot 1:d0dfbce63a89 1886 void HAL_RCCEx_CRS_SyncWarnCallback(void);
elmot 1:d0dfbce63a89 1887 void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
elmot 1:d0dfbce63a89 1888 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
elmot 1:d0dfbce63a89 1889
elmot 1:d0dfbce63a89 1890 /**
elmot 1:d0dfbce63a89 1891 * @}
elmot 1:d0dfbce63a89 1892 */
elmot 1:d0dfbce63a89 1893
elmot 1:d0dfbce63a89 1894 #endif /* CRS */
elmot 1:d0dfbce63a89 1895
elmot 1:d0dfbce63a89 1896 /**
elmot 1:d0dfbce63a89 1897 * @}
elmot 1:d0dfbce63a89 1898 */
elmot 1:d0dfbce63a89 1899
elmot 1:d0dfbce63a89 1900 /* Private macros ------------------------------------------------------------*/
elmot 1:d0dfbce63a89 1901 /** @addtogroup RCCEx_Private_Macros
elmot 1:d0dfbce63a89 1902 * @{
elmot 1:d0dfbce63a89 1903 */
elmot 1:d0dfbce63a89 1904
elmot 1:d0dfbce63a89 1905 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
elmot 1:d0dfbce63a89 1906 ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
elmot 1:d0dfbce63a89 1907
elmot 1:d0dfbce63a89 1908 #if defined(STM32L431xx)
elmot 1:d0dfbce63a89 1909
elmot 1:d0dfbce63a89 1910 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
elmot 1:d0dfbce63a89 1911 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
elmot 1:d0dfbce63a89 1912 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
elmot 1:d0dfbce63a89 1913 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
elmot 1:d0dfbce63a89 1914 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
elmot 1:d0dfbce63a89 1915 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
elmot 1:d0dfbce63a89 1916 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
elmot 1:d0dfbce63a89 1917 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
elmot 1:d0dfbce63a89 1918 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
elmot 1:d0dfbce63a89 1919 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
elmot 1:d0dfbce63a89 1920 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
elmot 1:d0dfbce63a89 1921 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
elmot 1:d0dfbce63a89 1922 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
elmot 1:d0dfbce63a89 1923 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
elmot 1:d0dfbce63a89 1924 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
elmot 1:d0dfbce63a89 1925 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
elmot 1:d0dfbce63a89 1926
elmot 1:d0dfbce63a89 1927 #elif defined(STM32L432xx) || defined(STM32L442xx)
elmot 1:d0dfbce63a89 1928
elmot 1:d0dfbce63a89 1929 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
elmot 1:d0dfbce63a89 1930 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
elmot 1:d0dfbce63a89 1931 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
elmot 1:d0dfbce63a89 1932 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
elmot 1:d0dfbce63a89 1933 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
elmot 1:d0dfbce63a89 1934 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
elmot 1:d0dfbce63a89 1935 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
elmot 1:d0dfbce63a89 1936 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
elmot 1:d0dfbce63a89 1937 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
elmot 1:d0dfbce63a89 1938 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
elmot 1:d0dfbce63a89 1939 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
elmot 1:d0dfbce63a89 1940 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
elmot 1:d0dfbce63a89 1941 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
elmot 1:d0dfbce63a89 1942 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG))
elmot 1:d0dfbce63a89 1943
elmot 1:d0dfbce63a89 1944 #elif defined(STM32L433xx) || defined(STM32L443xx)
elmot 1:d0dfbce63a89 1945
elmot 1:d0dfbce63a89 1946 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
elmot 1:d0dfbce63a89 1947 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
elmot 1:d0dfbce63a89 1948 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
elmot 1:d0dfbce63a89 1949 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
elmot 1:d0dfbce63a89 1950 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
elmot 1:d0dfbce63a89 1951 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
elmot 1:d0dfbce63a89 1952 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
elmot 1:d0dfbce63a89 1953 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
elmot 1:d0dfbce63a89 1954 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
elmot 1:d0dfbce63a89 1955 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
elmot 1:d0dfbce63a89 1956 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
elmot 1:d0dfbce63a89 1957 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
elmot 1:d0dfbce63a89 1958 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
elmot 1:d0dfbce63a89 1959 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
elmot 1:d0dfbce63a89 1960 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
elmot 1:d0dfbce63a89 1961 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
elmot 1:d0dfbce63a89 1962 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
elmot 1:d0dfbce63a89 1963
elmot 1:d0dfbce63a89 1964 #elif defined(STM32L471xx)
elmot 1:d0dfbce63a89 1965
elmot 1:d0dfbce63a89 1966 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
elmot 1:d0dfbce63a89 1967 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
elmot 1:d0dfbce63a89 1968 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
elmot 1:d0dfbce63a89 1969 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
elmot 1:d0dfbce63a89 1970 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
elmot 1:d0dfbce63a89 1971 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
elmot 1:d0dfbce63a89 1972 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
elmot 1:d0dfbce63a89 1973 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
elmot 1:d0dfbce63a89 1974 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
elmot 1:d0dfbce63a89 1975 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
elmot 1:d0dfbce63a89 1976 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
elmot 1:d0dfbce63a89 1977 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
elmot 1:d0dfbce63a89 1978 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
elmot 1:d0dfbce63a89 1979 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
elmot 1:d0dfbce63a89 1980 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
elmot 1:d0dfbce63a89 1981 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
elmot 1:d0dfbce63a89 1982 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
elmot 1:d0dfbce63a89 1983 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
elmot 1:d0dfbce63a89 1984 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
elmot 1:d0dfbce63a89 1985 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
elmot 1:d0dfbce63a89 1986
elmot 1:d0dfbce63a89 1987 #else
elmot 1:d0dfbce63a89 1988
elmot 1:d0dfbce63a89 1989 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
elmot 1:d0dfbce63a89 1990 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
elmot 1:d0dfbce63a89 1991 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
elmot 1:d0dfbce63a89 1992 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
elmot 1:d0dfbce63a89 1993 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
elmot 1:d0dfbce63a89 1994 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
elmot 1:d0dfbce63a89 1995 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
elmot 1:d0dfbce63a89 1996 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
elmot 1:d0dfbce63a89 1997 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
elmot 1:d0dfbce63a89 1998 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
elmot 1:d0dfbce63a89 1999 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
elmot 1:d0dfbce63a89 2000 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
elmot 1:d0dfbce63a89 2001 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
elmot 1:d0dfbce63a89 2002 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
elmot 1:d0dfbce63a89 2003 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
elmot 1:d0dfbce63a89 2004 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
elmot 1:d0dfbce63a89 2005 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
elmot 1:d0dfbce63a89 2006 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
elmot 1:d0dfbce63a89 2007 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
elmot 1:d0dfbce63a89 2008 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
elmot 1:d0dfbce63a89 2009 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
elmot 1:d0dfbce63a89 2010
elmot 1:d0dfbce63a89 2011 #endif /* STM32L431xx */
elmot 1:d0dfbce63a89 2012
elmot 1:d0dfbce63a89 2013 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2014 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
elmot 1:d0dfbce63a89 2015 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
elmot 1:d0dfbce63a89 2016 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
elmot 1:d0dfbce63a89 2017 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
elmot 1:d0dfbce63a89 2018
elmot 1:d0dfbce63a89 2019 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2020 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
elmot 1:d0dfbce63a89 2021 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
elmot 1:d0dfbce63a89 2022 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
elmot 1:d0dfbce63a89 2023 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
elmot 1:d0dfbce63a89 2024
elmot 1:d0dfbce63a89 2025 #if defined(USART3)
elmot 1:d0dfbce63a89 2026
elmot 1:d0dfbce63a89 2027 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2028 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
elmot 1:d0dfbce63a89 2029 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
elmot 1:d0dfbce63a89 2030 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
elmot 1:d0dfbce63a89 2031 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
elmot 1:d0dfbce63a89 2032
elmot 1:d0dfbce63a89 2033 #endif /* USART3 */
elmot 1:d0dfbce63a89 2034
elmot 1:d0dfbce63a89 2035 #if defined(UART4)
elmot 1:d0dfbce63a89 2036
elmot 1:d0dfbce63a89 2037 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2038 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
elmot 1:d0dfbce63a89 2039 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
elmot 1:d0dfbce63a89 2040 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \
elmot 1:d0dfbce63a89 2041 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
elmot 1:d0dfbce63a89 2042
elmot 1:d0dfbce63a89 2043 #endif /* UART4 */
elmot 1:d0dfbce63a89 2044
elmot 1:d0dfbce63a89 2045 #if defined(UART5)
elmot 1:d0dfbce63a89 2046
elmot 1:d0dfbce63a89 2047 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2048 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
elmot 1:d0dfbce63a89 2049 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
elmot 1:d0dfbce63a89 2050 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \
elmot 1:d0dfbce63a89 2051 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
elmot 1:d0dfbce63a89 2052
elmot 1:d0dfbce63a89 2053 #endif /* UART5 */
elmot 1:d0dfbce63a89 2054
elmot 1:d0dfbce63a89 2055 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2056 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
elmot 1:d0dfbce63a89 2057 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
elmot 1:d0dfbce63a89 2058 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
elmot 1:d0dfbce63a89 2059 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
elmot 1:d0dfbce63a89 2060
elmot 1:d0dfbce63a89 2061 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2062 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
elmot 1:d0dfbce63a89 2063 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
elmot 1:d0dfbce63a89 2064 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
elmot 1:d0dfbce63a89 2065
elmot 1:d0dfbce63a89 2066 #if defined(I2C2)
elmot 1:d0dfbce63a89 2067
elmot 1:d0dfbce63a89 2068 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2069 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
elmot 1:d0dfbce63a89 2070 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
elmot 1:d0dfbce63a89 2071 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
elmot 1:d0dfbce63a89 2072
elmot 1:d0dfbce63a89 2073 #endif /* I2C2 */
elmot 1:d0dfbce63a89 2074
elmot 1:d0dfbce63a89 2075 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2076 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
elmot 1:d0dfbce63a89 2077 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
elmot 1:d0dfbce63a89 2078 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
elmot 1:d0dfbce63a89 2079
elmot 1:d0dfbce63a89 2080 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 2081
elmot 1:d0dfbce63a89 2082 #define IS_RCC_SAI1CLK(__SOURCE__) \
elmot 1:d0dfbce63a89 2083 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
elmot 1:d0dfbce63a89 2084 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
elmot 1:d0dfbce63a89 2085 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
elmot 1:d0dfbce63a89 2086 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
elmot 1:d0dfbce63a89 2087
elmot 1:d0dfbce63a89 2088 #else
elmot 1:d0dfbce63a89 2089
elmot 1:d0dfbce63a89 2090 #define IS_RCC_SAI1CLK(__SOURCE__) \
elmot 1:d0dfbce63a89 2091 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
elmot 1:d0dfbce63a89 2092 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
elmot 1:d0dfbce63a89 2093 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
elmot 1:d0dfbce63a89 2094
elmot 1:d0dfbce63a89 2095 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 2096
elmot 1:d0dfbce63a89 2097 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 2098
elmot 1:d0dfbce63a89 2099 #define IS_RCC_SAI2CLK(__SOURCE__) \
elmot 1:d0dfbce63a89 2100 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \
elmot 1:d0dfbce63a89 2101 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
elmot 1:d0dfbce63a89 2102 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \
elmot 1:d0dfbce63a89 2103 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
elmot 1:d0dfbce63a89 2104
elmot 1:d0dfbce63a89 2105 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 2106
elmot 1:d0dfbce63a89 2107 #define IS_RCC_LPTIM1CLK(__SOURCE__) \
elmot 1:d0dfbce63a89 2108 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK) || \
elmot 1:d0dfbce63a89 2109 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
elmot 1:d0dfbce63a89 2110 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
elmot 1:d0dfbce63a89 2111 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
elmot 1:d0dfbce63a89 2112
elmot 1:d0dfbce63a89 2113 #define IS_RCC_LPTIM2CLK(__SOURCE__) \
elmot 1:d0dfbce63a89 2114 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK) || \
elmot 1:d0dfbce63a89 2115 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
elmot 1:d0dfbce63a89 2116 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
elmot 1:d0dfbce63a89 2117 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
elmot 1:d0dfbce63a89 2118
elmot 1:d0dfbce63a89 2119 #if defined(SDMMC1)
elmot 1:d0dfbce63a89 2120 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 2121
elmot 1:d0dfbce63a89 2122 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2123 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \
elmot 1:d0dfbce63a89 2124 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
elmot 1:d0dfbce63a89 2125 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
elmot 1:d0dfbce63a89 2126 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
elmot 1:d0dfbce63a89 2127
elmot 1:d0dfbce63a89 2128 #else
elmot 1:d0dfbce63a89 2129
elmot 1:d0dfbce63a89 2130 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2131 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \
elmot 1:d0dfbce63a89 2132 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
elmot 1:d0dfbce63a89 2133 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
elmot 1:d0dfbce63a89 2134 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
elmot 1:d0dfbce63a89 2135
elmot 1:d0dfbce63a89 2136 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 2137 #endif /* SDMMC1 */
elmot 1:d0dfbce63a89 2138
elmot 1:d0dfbce63a89 2139 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 2140
elmot 1:d0dfbce63a89 2141 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2142 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
elmot 1:d0dfbce63a89 2143 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
elmot 1:d0dfbce63a89 2144 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
elmot 1:d0dfbce63a89 2145 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
elmot 1:d0dfbce63a89 2146
elmot 1:d0dfbce63a89 2147 #else
elmot 1:d0dfbce63a89 2148
elmot 1:d0dfbce63a89 2149 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2150 (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \
elmot 1:d0dfbce63a89 2151 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
elmot 1:d0dfbce63a89 2152 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
elmot 1:d0dfbce63a89 2153 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
elmot 1:d0dfbce63a89 2154
elmot 1:d0dfbce63a89 2155 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 2156
elmot 1:d0dfbce63a89 2157 #if defined(USB_OTG_FS) || defined(USB)
elmot 1:d0dfbce63a89 2158 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 2159
elmot 1:d0dfbce63a89 2160 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2161 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
elmot 1:d0dfbce63a89 2162 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
elmot 1:d0dfbce63a89 2163 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
elmot 1:d0dfbce63a89 2164 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
elmot 1:d0dfbce63a89 2165
elmot 1:d0dfbce63a89 2166 #else
elmot 1:d0dfbce63a89 2167
elmot 1:d0dfbce63a89 2168 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2169 (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \
elmot 1:d0dfbce63a89 2170 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
elmot 1:d0dfbce63a89 2171 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
elmot 1:d0dfbce63a89 2172 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
elmot 1:d0dfbce63a89 2173
elmot 1:d0dfbce63a89 2174 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 2175 #endif /* USB_OTG_FS || USB */
elmot 1:d0dfbce63a89 2176
elmot 1:d0dfbce63a89 2177 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
elmot 1:d0dfbce63a89 2178
elmot 1:d0dfbce63a89 2179 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2180 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
elmot 1:d0dfbce63a89 2181 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
elmot 1:d0dfbce63a89 2182 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \
elmot 1:d0dfbce63a89 2183 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
elmot 1:d0dfbce63a89 2184
elmot 1:d0dfbce63a89 2185 #else
elmot 1:d0dfbce63a89 2186
elmot 1:d0dfbce63a89 2187 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2188 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
elmot 1:d0dfbce63a89 2189 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
elmot 1:d0dfbce63a89 2190 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
elmot 1:d0dfbce63a89 2191
elmot 1:d0dfbce63a89 2192 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
elmot 1:d0dfbce63a89 2193
elmot 1:d0dfbce63a89 2194 #if defined(SWPMI1)
elmot 1:d0dfbce63a89 2195
elmot 1:d0dfbce63a89 2196 #define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2197 (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK) || \
elmot 1:d0dfbce63a89 2198 ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))
elmot 1:d0dfbce63a89 2199
elmot 1:d0dfbce63a89 2200 #endif /* SWPMI1 */
elmot 1:d0dfbce63a89 2201
elmot 1:d0dfbce63a89 2202 #if defined(DFSDM1_Filter0)
elmot 1:d0dfbce63a89 2203
elmot 1:d0dfbce63a89 2204 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \
elmot 1:d0dfbce63a89 2205 (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK) || \
elmot 1:d0dfbce63a89 2206 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
elmot 1:d0dfbce63a89 2207
elmot 1:d0dfbce63a89 2208 #endif /* DFSDM1_Filter0 */
elmot 1:d0dfbce63a89 2209
elmot 1:d0dfbce63a89 2210 #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
elmot 1:d0dfbce63a89 2211
elmot 1:d0dfbce63a89 2212 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
elmot 1:d0dfbce63a89 2213
elmot 1:d0dfbce63a89 2214 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
elmot 1:d0dfbce63a89 2215
elmot 1:d0dfbce63a89 2216 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 2217 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
elmot 1:d0dfbce63a89 2218 #else
elmot 1:d0dfbce63a89 2219 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
elmot 1:d0dfbce63a89 2220 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 2221
elmot 1:d0dfbce63a89 2222 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
elmot 1:d0dfbce63a89 2223 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
elmot 1:d0dfbce63a89 2224
elmot 1:d0dfbce63a89 2225 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
elmot 1:d0dfbce63a89 2226 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
elmot 1:d0dfbce63a89 2227
elmot 1:d0dfbce63a89 2228 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 2229
elmot 1:d0dfbce63a89 2230 #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
elmot 1:d0dfbce63a89 2231
elmot 1:d0dfbce63a89 2232 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
elmot 1:d0dfbce63a89 2233
elmot 1:d0dfbce63a89 2234 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
elmot 1:d0dfbce63a89 2235
elmot 1:d0dfbce63a89 2236 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 2237 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
elmot 1:d0dfbce63a89 2238 #else
elmot 1:d0dfbce63a89 2239 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
elmot 1:d0dfbce63a89 2240 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 2241
elmot 1:d0dfbce63a89 2242 #define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
elmot 1:d0dfbce63a89 2243 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
elmot 1:d0dfbce63a89 2244
elmot 1:d0dfbce63a89 2245 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 2246
elmot 1:d0dfbce63a89 2247 #if defined(CRS)
elmot 1:d0dfbce63a89 2248
elmot 1:d0dfbce63a89 2249 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
elmot 1:d0dfbce63a89 2250 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
elmot 1:d0dfbce63a89 2251 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
elmot 1:d0dfbce63a89 2252
elmot 1:d0dfbce63a89 2253 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
elmot 1:d0dfbce63a89 2254 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
elmot 1:d0dfbce63a89 2255 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
elmot 1:d0dfbce63a89 2256 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
elmot 1:d0dfbce63a89 2257
elmot 1:d0dfbce63a89 2258 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
elmot 1:d0dfbce63a89 2259 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
elmot 1:d0dfbce63a89 2260
elmot 1:d0dfbce63a89 2261 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
elmot 1:d0dfbce63a89 2262
elmot 1:d0dfbce63a89 2263 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
elmot 1:d0dfbce63a89 2264
elmot 1:d0dfbce63a89 2265 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
elmot 1:d0dfbce63a89 2266
elmot 1:d0dfbce63a89 2267 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
elmot 1:d0dfbce63a89 2268 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
elmot 1:d0dfbce63a89 2269
elmot 1:d0dfbce63a89 2270 #endif /* CRS */
elmot 1:d0dfbce63a89 2271
elmot 1:d0dfbce63a89 2272 /**
elmot 1:d0dfbce63a89 2273 * @}
elmot 1:d0dfbce63a89 2274 */
elmot 1:d0dfbce63a89 2275
elmot 1:d0dfbce63a89 2276 /**
elmot 1:d0dfbce63a89 2277 * @}
elmot 1:d0dfbce63a89 2278 */
elmot 1:d0dfbce63a89 2279
elmot 1:d0dfbce63a89 2280 /**
elmot 1:d0dfbce63a89 2281 * @}
elmot 1:d0dfbce63a89 2282 */
elmot 1:d0dfbce63a89 2283
elmot 1:d0dfbce63a89 2284 #ifdef __cplusplus
elmot 1:d0dfbce63a89 2285 }
elmot 1:d0dfbce63a89 2286 #endif
elmot 1:d0dfbce63a89 2287
elmot 1:d0dfbce63a89 2288 #endif /* __STM32L4xx_HAL_RCC_EX_H */
elmot 1:d0dfbce63a89 2289
elmot 1:d0dfbce63a89 2290 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/