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PLLSAI1
Functions

PLLSAI1
[RCC Exported Functions]

Functions

__STATIC_INLINE void LL_RCC_PLLSAI1_Enable (void)
 Enable PLLSAI1 CR PLLSAI1ON LL_RCC_PLLSAI1_Enable.
__STATIC_INLINE void LL_RCC_PLLSAI1_Disable (void)
 Disable PLLSAI1 CR PLLSAI1ON LL_RCC_PLLSAI1_Disable.
__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady (void)
 Check if PLLSAI1 Ready CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady.
__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
 Configure PLLSAI1 used for 48Mhz domain clock.
__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
 Configure PLLSAI1 used for SAI domain clock.
__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
 Configure PLLSAI1 used for ADC domain clock.
__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN (void)
 Get SAI1PLL multiplication factor for VCO PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN.
__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP (void)
 Get SAI1PLL division factor for PLLSAI1P.
__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ (void)
 Get SAI1PLL division factor for PLLSAI1Q.
__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR (void)
 Get PLLSAI1 division factor for PLLSAIR.
__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI (void)
 Enable PLLSAI1 output mapped on SAI domain clock PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI.
__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI (void)
 Disable PLLSAI1 output mapped on SAI domain clock.
__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M (void)
 Enable PLLSAI1 output mapped on 48MHz domain clock PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M.
__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M (void)
 Disable PLLSAI1 output mapped on 48MHz domain clock.
__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC (void)
 Enable PLLSAI1 output mapped on ADC domain clock PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC.
__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC (void)
 Disable PLLSAI1 output mapped on ADC domain clock.

Function Documentation

__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M ( uint32_t  Source,
uint32_t  PLLM,
uint32_t  PLLN,
uint32_t  PLLQ 
)

Configure PLLSAI1 used for 48Mhz domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled
PLLN/PLLQ can be written only when PLLSAI1 is disabled
This can be selected for USB, RNG, SDMMC PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M
PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
Parameters:
SourceThis parameter can be one of the following values:

  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLMThis parameter can be one of the following values:

  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLNBetween 8 and 86
PLLQThis parameter can be one of the following values:

  • LL_RCC_PLLSAI1Q_DIV_2
  • LL_RCC_PLLSAI1Q_DIV_4
  • LL_RCC_PLLSAI1Q_DIV_6
  • LL_RCC_PLLSAI1Q_DIV_8
Return values:
None

Definition at line 3230 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC ( uint32_t  Source,
uint32_t  PLLM,
uint32_t  PLLN,
uint32_t  PLLR 
)

Configure PLLSAI1 used for ADC domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled
PLLN/PLLR can be written only when PLLSAI1 is disabled
This can be selected for ADC PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
Parameters:
SourceThis parameter can be one of the following values:

  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLMThis parameter can be one of the following values:

  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLNBetween 8 and 86
PLLRThis parameter can be one of the following values:

  • LL_RCC_PLLSAI1R_DIV_2
  • LL_RCC_PLLSAI1R_DIV_4
  • LL_RCC_PLLSAI1R_DIV_6
  • LL_RCC_PLLSAI1R_DIV_8
Return values:
None

Definition at line 3370 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI ( uint32_t  Source,
uint32_t  PLLM,
uint32_t  PLLN,
uint32_t  PLLP 
)

Configure PLLSAI1 used for SAI domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled
PLLN/PLLP can be written only when PLLSAI1 is disabled
This can be selected for SAI1 or SAI2 (*) PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
Parameters:
SourceThis parameter can be one of the following values:

  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLMThis parameter can be one of the following values:

  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLNBetween 8 and 86
PLLPThis parameter can be one of the following values:

  • LL_RCC_PLLSAI1P_DIV_2
  • LL_RCC_PLLSAI1P_DIV_3
  • LL_RCC_PLLSAI1P_DIV_4
  • LL_RCC_PLLSAI1P_DIV_5
  • LL_RCC_PLLSAI1P_DIV_6
  • LL_RCC_PLLSAI1P_DIV_7
  • LL_RCC_PLLSAI1P_DIV_8
  • LL_RCC_PLLSAI1P_DIV_9
  • LL_RCC_PLLSAI1P_DIV_10
  • LL_RCC_PLLSAI1P_DIV_11
  • LL_RCC_PLLSAI1P_DIV_12
  • LL_RCC_PLLSAI1P_DIV_13
  • LL_RCC_PLLSAI1P_DIV_14
  • LL_RCC_PLLSAI1P_DIV_15
  • LL_RCC_PLLSAI1P_DIV_16
  • LL_RCC_PLLSAI1P_DIV_17
  • LL_RCC_PLLSAI1P_DIV_18
  • LL_RCC_PLLSAI1P_DIV_19
  • LL_RCC_PLLSAI1P_DIV_20
  • LL_RCC_PLLSAI1P_DIV_21
  • LL_RCC_PLLSAI1P_DIV_22
  • LL_RCC_PLLSAI1P_DIV_23
  • LL_RCC_PLLSAI1P_DIV_24
  • LL_RCC_PLLSAI1P_DIV_25
  • LL_RCC_PLLSAI1P_DIV_26
  • LL_RCC_PLLSAI1P_DIV_27
  • LL_RCC_PLLSAI1P_DIV_28
  • LL_RCC_PLLSAI1P_DIV_29
  • LL_RCC_PLLSAI1P_DIV_30
  • LL_RCC_PLLSAI1P_DIV_31
Return values:
NoneConfigure PLLSAI1 used for SAI domain clock
Note:
PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled
PLLN/PLLP can be written only when PLLSAI1 is disabled
This can be selected for SAI1 or SAI2 (*) PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI
Parameters:
SourceThis parameter can be one of the following values:

  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLMThis parameter can be one of the following values:

  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLNBetween 8 and 86
PLLPThis parameter can be one of the following values:

  • LL_RCC_PLLSAI1P_DIV_7
  • LL_RCC_PLLSAI1P_DIV_17
Return values:
None

Definition at line 3327 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_Disable ( void   )

Disable PLLSAI1 CR PLLSAI1ON LL_RCC_PLLSAI1_Disable.

Return values:
None

Definition at line 3183 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M ( void   )

Disable PLLSAI1 output mapped on 48MHz domain clock.

Note:
In order to save power, when of the PLLSAI1 is not used, should be 0 PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M
Return values:
None

Definition at line 3511 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC ( void   )

Disable PLLSAI1 output mapped on ADC domain clock.

Note:
In order to save power, when of the PLLSAI1 is not used, Main PLLSAI1 should be 0 PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC
Return values:
None

Definition at line 3533 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI ( void   )

Disable PLLSAI1 output mapped on SAI domain clock.

Note:
In order to save power, when of the PLLSAI1 is not used, should be 0 PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI
Return values:
None

Definition at line 3489 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_Enable ( void   )

Enable PLLSAI1 CR PLLSAI1ON LL_RCC_PLLSAI1_Enable.

Return values:
None

Definition at line 3173 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M ( void   )

Enable PLLSAI1 output mapped on 48MHz domain clock PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M.

Return values:
None

Definition at line 3499 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC ( void   )

Enable PLLSAI1 output mapped on ADC domain clock PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC.

Return values:
None

Definition at line 3521 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI ( void   )

Enable PLLSAI1 output mapped on SAI domain clock PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI.

Return values:
None

Definition at line 3477 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN ( void   )

Get SAI1PLL multiplication factor for VCO PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN.

Return values:
Between8 and 86

Definition at line 3381 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP ( void   )

Get SAI1PLL division factor for PLLSAI1P.

Note:
used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP
Return values:
Returnedvalue can be one of the following values:

  • LL_RCC_PLLSAI1P_DIV_2
  • LL_RCC_PLLSAI1P_DIV_3
  • LL_RCC_PLLSAI1P_DIV_4
  • LL_RCC_PLLSAI1P_DIV_5
  • LL_RCC_PLLSAI1P_DIV_6
  • LL_RCC_PLLSAI1P_DIV_7
  • LL_RCC_PLLSAI1P_DIV_8
  • LL_RCC_PLLSAI1P_DIV_9
  • LL_RCC_PLLSAI1P_DIV_10
  • LL_RCC_PLLSAI1P_DIV_11
  • LL_RCC_PLLSAI1P_DIV_12
  • LL_RCC_PLLSAI1P_DIV_13
  • LL_RCC_PLLSAI1P_DIV_14
  • LL_RCC_PLLSAI1P_DIV_15
  • LL_RCC_PLLSAI1P_DIV_16
  • LL_RCC_PLLSAI1P_DIV_17
  • LL_RCC_PLLSAI1P_DIV_18
  • LL_RCC_PLLSAI1P_DIV_19
  • LL_RCC_PLLSAI1P_DIV_20
  • LL_RCC_PLLSAI1P_DIV_21
  • LL_RCC_PLLSAI1P_DIV_22
  • LL_RCC_PLLSAI1P_DIV_23
  • LL_RCC_PLLSAI1P_DIV_24
  • LL_RCC_PLLSAI1P_DIV_25
  • LL_RCC_PLLSAI1P_DIV_26
  • LL_RCC_PLLSAI1P_DIV_27
  • LL_RCC_PLLSAI1P_DIV_28
  • LL_RCC_PLLSAI1P_DIV_29
  • LL_RCC_PLLSAI1P_DIV_30
  • LL_RCC_PLLSAI1P_DIV_31 Get SAI1PLL division factor for PLLSAI1P
Note:
used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP
Return values:
Returnedvalue can be one of the following values:

  • LL_RCC_PLLSAI1P_DIV_7
  • LL_RCC_PLLSAI1P_DIV_17

Definition at line 3433 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ ( void   )

Get SAI1PLL division factor for PLLSAI1Q.

Note:
used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock) PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ
Return values:
Returnedvalue can be one of the following values:

  • LL_RCC_PLLSAI1Q_DIV_2
  • LL_RCC_PLLSAI1Q_DIV_4
  • LL_RCC_PLLSAI1Q_DIV_6
  • LL_RCC_PLLSAI1Q_DIV_8

Definition at line 3452 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR ( void   )

Get PLLSAI1 division factor for PLLSAIR.

Note:
used for PLLADC1CLK (ADC clock) PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR
Return values:
Returnedvalue can be one of the following values:

  • LL_RCC_PLLSAI1R_DIV_2
  • LL_RCC_PLLSAI1R_DIV_4
  • LL_RCC_PLLSAI1R_DIV_6
  • LL_RCC_PLLSAI1R_DIV_8

Definition at line 3467 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady ( void   )

Check if PLLSAI1 Ready CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady.

Return values:
Stateof bit (1 or 0).

Definition at line 3193 of file stm32l4xx_ll_rcc.h.

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