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Functions | |
__STATIC_INLINE void | LL_RCC_PLL_Enable (void) |
Enable PLL CR PLLON LL_RCC_PLL_Enable. | |
__STATIC_INLINE void | LL_RCC_PLL_Disable (void) |
Disable PLL. | |
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsReady (void) |
Check if PLL Ready CR PLLRDY LL_RCC_PLL_IsReady. | |
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) |
Configure PLL used for SYSCLK Domain. | |
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) |
Configure PLL used for SAI domain clock. | |
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) |
Configure PLL used for 48Mhz domain clock. | |
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetN (void) |
Get Main PLL multiplication factor for VCO PLLCFGR PLLN LL_RCC_PLL_GetN. | |
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetP (void) |
Get Main PLL division factor for PLLP. | |
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetQ (void) |
Get Main PLL division factor for PLLQ. | |
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetR (void) |
Get Main PLL division factor for PLLR. | |
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMainSource (void) |
Get the oscillator used as PLL clock source. | |
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetDivider (void) |
Get Division factor for the main PLL and other PLL PLLCFGR PLLM LL_RCC_PLL_GetDivider. | |
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_SAI (void) |
Enable PLL output mapped on SAI domain clock PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI. | |
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_SAI (void) |
Disable PLL output mapped on SAI domain clock. | |
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_48M (void) |
Enable PLL output mapped on 48MHz domain clock PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M. | |
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_48M (void) |
Disable PLL output mapped on 48MHz domain clock. | |
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_SYS (void) |
Enable PLL output mapped on SYSCLK domain PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS. | |
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_SYS (void) |
Disable PLL output mapped on SYSCLK domain. |
Function Documentation
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M | ( | uint32_t | Source, |
uint32_t | PLLM, | ||
uint32_t | PLLN, | ||
uint32_t | PLLQ | ||
) |
Configure PLL used for 48Mhz domain clock.
- Note:
- PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled
- PLLN/PLLQ can be written only when PLL is disabled
-
This can be selected for USB, RNG, SDMMC PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
- Parameters:
-
Source This parameter can be one of the following values: - LL_RCC_PLLSOURCE_NONE
- LL_RCC_PLLSOURCE_MSI
- LL_RCC_PLLSOURCE_HSI
- LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values: - LL_RCC_PLLM_DIV_1
- LL_RCC_PLLM_DIV_2
- LL_RCC_PLLM_DIV_3
- LL_RCC_PLLM_DIV_4
- LL_RCC_PLLM_DIV_5
- LL_RCC_PLLM_DIV_6
- LL_RCC_PLLM_DIV_7
- LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86 PLLQ This parameter can be one of the following values: - LL_RCC_PLLQ_DIV_2
- LL_RCC_PLLQ_DIV_4
- LL_RCC_PLLQ_DIV_6
- LL_RCC_PLLQ_DIV_8
- Return values:
-
None
Definition at line 2954 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI | ( | uint32_t | Source, |
uint32_t | PLLM, | ||
uint32_t | PLLN, | ||
uint32_t | PLLP | ||
) |
Configure PLL used for SAI domain clock.
- Note:
- PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled
- PLLN/PLLP can be written only when PLL is disabled
-
This can be selected for SAI1 or SAI2 (*) PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_SAI
- Parameters:
-
Source This parameter can be one of the following values: - LL_RCC_PLLSOURCE_NONE
- LL_RCC_PLLSOURCE_MSI
- LL_RCC_PLLSOURCE_HSI
- LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values: - LL_RCC_PLLM_DIV_1
- LL_RCC_PLLM_DIV_2
- LL_RCC_PLLM_DIV_3
- LL_RCC_PLLM_DIV_4
- LL_RCC_PLLM_DIV_5
- LL_RCC_PLLM_DIV_6
- LL_RCC_PLLM_DIV_7
- LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86 PLLP This parameter can be one of the following values: - LL_RCC_PLLP_DIV_2
- LL_RCC_PLLP_DIV_3
- LL_RCC_PLLP_DIV_4
- LL_RCC_PLLP_DIV_5
- LL_RCC_PLLP_DIV_6
- LL_RCC_PLLP_DIV_7
- LL_RCC_PLLP_DIV_8
- LL_RCC_PLLP_DIV_9
- LL_RCC_PLLP_DIV_10
- LL_RCC_PLLP_DIV_11
- LL_RCC_PLLP_DIV_12
- LL_RCC_PLLP_DIV_13
- LL_RCC_PLLP_DIV_14
- LL_RCC_PLLP_DIV_15
- LL_RCC_PLLP_DIV_16
- LL_RCC_PLLP_DIV_17
- LL_RCC_PLLP_DIV_18
- LL_RCC_PLLP_DIV_19
- LL_RCC_PLLP_DIV_20
- LL_RCC_PLLP_DIV_21
- LL_RCC_PLLP_DIV_22
- LL_RCC_PLLP_DIV_23
- LL_RCC_PLLP_DIV_24
- LL_RCC_PLLP_DIV_25
- LL_RCC_PLLP_DIV_26
- LL_RCC_PLLP_DIV_27
- LL_RCC_PLLP_DIV_28
- LL_RCC_PLLP_DIV_29
- LL_RCC_PLLP_DIV_30
- LL_RCC_PLLP_DIV_31
- Return values:
-
None Configure PLL used for SAI domain clock
- Note:
- PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled
- PLLN/PLLP can be written only when PLL is disabled
-
This can be selected for SAI1 or SAI2 (*) PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI
- Parameters:
-
Source This parameter can be one of the following values: - LL_RCC_PLLSOURCE_NONE
- LL_RCC_PLLSOURCE_MSI
- LL_RCC_PLLSOURCE_HSI
- LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values: - LL_RCC_PLLM_DIV_1
- LL_RCC_PLLM_DIV_2
- LL_RCC_PLLM_DIV_3
- LL_RCC_PLLM_DIV_4
- LL_RCC_PLLM_DIV_5
- LL_RCC_PLLM_DIV_6
- LL_RCC_PLLM_DIV_7
- LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86 PLLP This parameter can be one of the following values: - LL_RCC_PLLP_DIV_7
- LL_RCC_PLLP_DIV_17
- Return values:
-
None
Definition at line 2911 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS | ( | uint32_t | Source, |
uint32_t | PLLM, | ||
uint32_t | PLLN, | ||
uint32_t | PLLR | ||
) |
Configure PLL used for SYSCLK Domain.
- Note:
- PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled
-
PLLN/PLLR can be written only when PLL is disabled PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
- Parameters:
-
Source This parameter can be one of the following values: - LL_RCC_PLLSOURCE_NONE
- LL_RCC_PLLSOURCE_MSI
- LL_RCC_PLLSOURCE_HSI
- LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values: - LL_RCC_PLLM_DIV_1
- LL_RCC_PLLM_DIV_2
- LL_RCC_PLLM_DIV_3
- LL_RCC_PLLM_DIV_4
- LL_RCC_PLLM_DIV_5
- LL_RCC_PLLM_DIV_6
- LL_RCC_PLLM_DIV_7
- LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86 PLLR This parameter can be one of the following values: - LL_RCC_PLLR_DIV_2
- LL_RCC_PLLR_DIV_4
- LL_RCC_PLLR_DIV_6
- LL_RCC_PLLR_DIV_8
- Return values:
-
None
Definition at line 2814 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE void LL_RCC_PLL_Disable | ( | void | ) |
Disable PLL.
- Note:
- Cannot be disabled if the PLL clock is used as the system clock CR PLLON LL_RCC_PLL_Disable
- Return values:
-
None
Definition at line 2768 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M | ( | void | ) |
Disable PLL output mapped on 48MHz domain clock.
- Note:
- Cannot be disabled if the PLL clock is used as the system clock
- In order to save power, when the PLLCLK of the PLL is not used, should be 0 PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
- Return values:
-
None
Definition at line 3131 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI | ( | void | ) |
Disable PLL output mapped on SAI domain clock.
- Note:
- Cannot be disabled if the PLL clock is used as the system clock
- In order to save power, when the PLLCLK of the PLL is not used, should be 0 PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
- Return values:
-
None
Definition at line 3107 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS | ( | void | ) |
Disable PLL output mapped on SYSCLK domain.
- Note:
- Cannot be disabled if the PLL clock is used as the system clock
- In order to save power, when the PLLCLK of the PLL is not used, Main PLL should be 0 PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
- Return values:
-
None
Definition at line 3155 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE void LL_RCC_PLL_Enable | ( | void | ) |
Enable PLL CR PLLON LL_RCC_PLL_Enable.
- Return values:
-
None
Definition at line 2757 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M | ( | void | ) |
Enable PLL output mapped on 48MHz domain clock PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M.
- Return values:
-
None
Definition at line 3117 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI | ( | void | ) |
Enable PLL output mapped on SAI domain clock PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI.
- Return values:
-
None
Definition at line 3093 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS | ( | void | ) |
Enable PLL output mapped on SYSCLK domain PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS.
- Return values:
-
None
Definition at line 3141 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider | ( | void | ) |
Get Division factor for the main PLL and other PLL PLLCFGR PLLM LL_RCC_PLL_GetDivider.
- Return values:
-
Returned value can be one of the following values: - LL_RCC_PLLM_DIV_1
- LL_RCC_PLLM_DIV_2
- LL_RCC_PLLM_DIV_3
- LL_RCC_PLLM_DIV_4
- LL_RCC_PLLM_DIV_5
- LL_RCC_PLLM_DIV_6
- LL_RCC_PLLM_DIV_7
- LL_RCC_PLLM_DIV_8
Definition at line 3083 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource | ( | void | ) |
Get the oscillator used as PLL clock source.
PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
- Return values:
-
Returned value can be one of the following values: - LL_RCC_PLLSOURCE_NONE
- LL_RCC_PLLSOURCE_MSI
- LL_RCC_PLLSOURCE_HSI
- LL_RCC_PLLSOURCE_HSE
Definition at line 3065 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE uint32_t LL_RCC_PLL_GetN | ( | void | ) |
Get Main PLL multiplication factor for VCO PLLCFGR PLLN LL_RCC_PLL_GetN.
- Return values:
-
Between 8 and 86
Definition at line 2965 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE uint32_t LL_RCC_PLL_GetP | ( | void | ) |
Get Main PLL division factor for PLLP.
- Note:
- used for PLLSAI3CLK (SAI1 and SAI2 clock) PLLCFGR PLLPDIV LL_RCC_PLL_GetP
- Return values:
-
Returned value can be one of the following values: - LL_RCC_PLLP_DIV_2
- LL_RCC_PLLP_DIV_3
- LL_RCC_PLLP_DIV_4
- LL_RCC_PLLP_DIV_5
- LL_RCC_PLLP_DIV_6
- LL_RCC_PLLP_DIV_7
- LL_RCC_PLLP_DIV_8
- LL_RCC_PLLP_DIV_9
- LL_RCC_PLLP_DIV_10
- LL_RCC_PLLP_DIV_11
- LL_RCC_PLLP_DIV_12
- LL_RCC_PLLP_DIV_13
- LL_RCC_PLLP_DIV_14
- LL_RCC_PLLP_DIV_15
- LL_RCC_PLLP_DIV_16
- LL_RCC_PLLP_DIV_17
- LL_RCC_PLLP_DIV_18
- LL_RCC_PLLP_DIV_19
- LL_RCC_PLLP_DIV_20
- LL_RCC_PLLP_DIV_21
- LL_RCC_PLLP_DIV_22
- LL_RCC_PLLP_DIV_23
- LL_RCC_PLLP_DIV_24
- LL_RCC_PLLP_DIV_25
- LL_RCC_PLLP_DIV_26
- LL_RCC_PLLP_DIV_27
- LL_RCC_PLLP_DIV_28
- LL_RCC_PLLP_DIV_29
- LL_RCC_PLLP_DIV_30
- LL_RCC_PLLP_DIV_31
- Note:
- used for PLLSAI3CLK (SAI1 and SAI2 clock) PLLCFGR PLLP LL_RCC_PLL_GetP
- Return values:
-
Returned value can be one of the following values: - LL_RCC_PLLP_DIV_7
- LL_RCC_PLLP_DIV_17
Definition at line 3007 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ | ( | void | ) |
Get Main PLL division factor for PLLQ.
- Note:
- used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock) PLLCFGR PLLQ LL_RCC_PLL_GetQ
- Return values:
-
Returned value can be one of the following values: - LL_RCC_PLLQ_DIV_2
- LL_RCC_PLLQ_DIV_4
- LL_RCC_PLLQ_DIV_6
- LL_RCC_PLLQ_DIV_8
Definition at line 3036 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE uint32_t LL_RCC_PLL_GetR | ( | void | ) |
Get Main PLL division factor for PLLR.
- Note:
- used for PLLCLK (system clock) PLLCFGR PLLR LL_RCC_PLL_GetR
- Return values:
-
Returned value can be one of the following values: - LL_RCC_PLLR_DIV_2
- LL_RCC_PLLR_DIV_4
- LL_RCC_PLLR_DIV_6
- LL_RCC_PLLR_DIV_8
Definition at line 3051 of file stm32l4xx_ll_rcc.h.
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady | ( | void | ) |
Check if PLL Ready CR PLLRDY LL_RCC_PLL_IsReady.
- Return values:
-
State of bit (1 or 0).
Definition at line 2778 of file stm32l4xx_ll_rcc.h.
Generated on Tue Jul 12 2022 11:00:15 by
