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HAL_L476/stm32l4xx_ll_sdmmc.h@1:d0dfbce63a89, 2017-02-24 (annotated)
- Committer:
- elmot
- Date:
- Fri Feb 24 21:13:56 2017 +0000
- Revision:
- 1:d0dfbce63a89
Ready-to-copy
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| elmot | 1:d0dfbce63a89 | 1 | /** |
| elmot | 1:d0dfbce63a89 | 2 | ****************************************************************************** |
| elmot | 1:d0dfbce63a89 | 3 | * @file stm32l4xx_ll_sdmmc.h |
| elmot | 1:d0dfbce63a89 | 4 | * @author MCD Application Team |
| elmot | 1:d0dfbce63a89 | 5 | * @version V1.5.1 |
| elmot | 1:d0dfbce63a89 | 6 | * @date $DATE$ |
| elmot | 1:d0dfbce63a89 | 7 | * @brief Header file of low layer SDMMC HAL module. |
| elmot | 1:d0dfbce63a89 | 8 | ****************************************************************************** |
| elmot | 1:d0dfbce63a89 | 9 | * @attention |
| elmot | 1:d0dfbce63a89 | 10 | * |
| elmot | 1:d0dfbce63a89 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| elmot | 1:d0dfbce63a89 | 12 | * |
| elmot | 1:d0dfbce63a89 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| elmot | 1:d0dfbce63a89 | 14 | * are permitted provided that the following conditions are met: |
| elmot | 1:d0dfbce63a89 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| elmot | 1:d0dfbce63a89 | 16 | * this list of conditions and the following disclaimer. |
| elmot | 1:d0dfbce63a89 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| elmot | 1:d0dfbce63a89 | 18 | * this list of conditions and the following disclaimer in the documentation |
| elmot | 1:d0dfbce63a89 | 19 | * and/or other materials provided with the distribution. |
| elmot | 1:d0dfbce63a89 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| elmot | 1:d0dfbce63a89 | 21 | * may be used to endorse or promote products derived from this software |
| elmot | 1:d0dfbce63a89 | 22 | * without specific prior written permission. |
| elmot | 1:d0dfbce63a89 | 23 | * |
| elmot | 1:d0dfbce63a89 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| elmot | 1:d0dfbce63a89 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| elmot | 1:d0dfbce63a89 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| elmot | 1:d0dfbce63a89 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| elmot | 1:d0dfbce63a89 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| elmot | 1:d0dfbce63a89 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| elmot | 1:d0dfbce63a89 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| elmot | 1:d0dfbce63a89 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| elmot | 1:d0dfbce63a89 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| elmot | 1:d0dfbce63a89 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| elmot | 1:d0dfbce63a89 | 34 | * |
| elmot | 1:d0dfbce63a89 | 35 | ****************************************************************************** |
| elmot | 1:d0dfbce63a89 | 36 | */ |
| elmot | 1:d0dfbce63a89 | 37 | |
| elmot | 1:d0dfbce63a89 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 39 | #ifndef __STM32L4xx_LL_SDMMC_H |
| elmot | 1:d0dfbce63a89 | 40 | #define __STM32L4xx_LL_SDMMC_H |
| elmot | 1:d0dfbce63a89 | 41 | |
| elmot | 1:d0dfbce63a89 | 42 | #ifdef __cplusplus |
| elmot | 1:d0dfbce63a89 | 43 | extern "C" { |
| elmot | 1:d0dfbce63a89 | 44 | #endif |
| elmot | 1:d0dfbce63a89 | 45 | |
| elmot | 1:d0dfbce63a89 | 46 | #if defined(SDMMC1) |
| elmot | 1:d0dfbce63a89 | 47 | |
| elmot | 1:d0dfbce63a89 | 48 | /* Includes ------------------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 49 | #include "stm32l4xx_hal_def.h" |
| elmot | 1:d0dfbce63a89 | 50 | |
| elmot | 1:d0dfbce63a89 | 51 | /** @addtogroup STM32L4xx_Driver |
| elmot | 1:d0dfbce63a89 | 52 | * @{ |
| elmot | 1:d0dfbce63a89 | 53 | */ |
| elmot | 1:d0dfbce63a89 | 54 | |
| elmot | 1:d0dfbce63a89 | 55 | /** @addtogroup SDMMC_LL |
| elmot | 1:d0dfbce63a89 | 56 | * @{ |
| elmot | 1:d0dfbce63a89 | 57 | */ |
| elmot | 1:d0dfbce63a89 | 58 | |
| elmot | 1:d0dfbce63a89 | 59 | /* Exported types ------------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 60 | /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types |
| elmot | 1:d0dfbce63a89 | 61 | * @{ |
| elmot | 1:d0dfbce63a89 | 62 | */ |
| elmot | 1:d0dfbce63a89 | 63 | |
| elmot | 1:d0dfbce63a89 | 64 | /** |
| elmot | 1:d0dfbce63a89 | 65 | * @brief SDMMC Configuration Structure definition |
| elmot | 1:d0dfbce63a89 | 66 | */ |
| elmot | 1:d0dfbce63a89 | 67 | typedef struct |
| elmot | 1:d0dfbce63a89 | 68 | { |
| elmot | 1:d0dfbce63a89 | 69 | uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. |
| elmot | 1:d0dfbce63a89 | 70 | This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ |
| elmot | 1:d0dfbce63a89 | 71 | |
| elmot | 1:d0dfbce63a89 | 72 | uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is |
| elmot | 1:d0dfbce63a89 | 73 | enabled or disabled. |
| elmot | 1:d0dfbce63a89 | 74 | This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ |
| elmot | 1:d0dfbce63a89 | 75 | |
| elmot | 1:d0dfbce63a89 | 76 | uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or |
| elmot | 1:d0dfbce63a89 | 77 | disabled when the bus is idle. |
| elmot | 1:d0dfbce63a89 | 78 | This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ |
| elmot | 1:d0dfbce63a89 | 79 | |
| elmot | 1:d0dfbce63a89 | 80 | uint32_t BusWide; /*!< Specifies the SDMMC bus width. |
| elmot | 1:d0dfbce63a89 | 81 | This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ |
| elmot | 1:d0dfbce63a89 | 82 | |
| elmot | 1:d0dfbce63a89 | 83 | uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. |
| elmot | 1:d0dfbce63a89 | 84 | This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ |
| elmot | 1:d0dfbce63a89 | 85 | |
| elmot | 1:d0dfbce63a89 | 86 | uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. |
| elmot | 1:d0dfbce63a89 | 87 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| elmot | 1:d0dfbce63a89 | 88 | |
| elmot | 1:d0dfbce63a89 | 89 | }SDMMC_InitTypeDef; |
| elmot | 1:d0dfbce63a89 | 90 | |
| elmot | 1:d0dfbce63a89 | 91 | |
| elmot | 1:d0dfbce63a89 | 92 | /** |
| elmot | 1:d0dfbce63a89 | 93 | * @brief SDMMC Command Control structure |
| elmot | 1:d0dfbce63a89 | 94 | */ |
| elmot | 1:d0dfbce63a89 | 95 | typedef struct |
| elmot | 1:d0dfbce63a89 | 96 | { |
| elmot | 1:d0dfbce63a89 | 97 | uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent |
| elmot | 1:d0dfbce63a89 | 98 | to a card as part of a command message. If a command |
| elmot | 1:d0dfbce63a89 | 99 | contains an argument, it must be loaded into this register |
| elmot | 1:d0dfbce63a89 | 100 | before writing the command to the command register. */ |
| elmot | 1:d0dfbce63a89 | 101 | |
| elmot | 1:d0dfbce63a89 | 102 | uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and |
| elmot | 1:d0dfbce63a89 | 103 | Max_Data = 64 */ |
| elmot | 1:d0dfbce63a89 | 104 | |
| elmot | 1:d0dfbce63a89 | 105 | uint32_t Response; /*!< Specifies the SDMMC response type. |
| elmot | 1:d0dfbce63a89 | 106 | This parameter can be a value of @ref SDMMC_LL_Response_Type */ |
| elmot | 1:d0dfbce63a89 | 107 | |
| elmot | 1:d0dfbce63a89 | 108 | uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is |
| elmot | 1:d0dfbce63a89 | 109 | enabled or disabled. |
| elmot | 1:d0dfbce63a89 | 110 | This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ |
| elmot | 1:d0dfbce63a89 | 111 | |
| elmot | 1:d0dfbce63a89 | 112 | uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) |
| elmot | 1:d0dfbce63a89 | 113 | is enabled or disabled. |
| elmot | 1:d0dfbce63a89 | 114 | This parameter can be a value of @ref SDMMC_LL_CPSM_State */ |
| elmot | 1:d0dfbce63a89 | 115 | }SDMMC_CmdInitTypeDef; |
| elmot | 1:d0dfbce63a89 | 116 | |
| elmot | 1:d0dfbce63a89 | 117 | |
| elmot | 1:d0dfbce63a89 | 118 | /** |
| elmot | 1:d0dfbce63a89 | 119 | * @brief SDMMC Data Control structure |
| elmot | 1:d0dfbce63a89 | 120 | */ |
| elmot | 1:d0dfbce63a89 | 121 | typedef struct |
| elmot | 1:d0dfbce63a89 | 122 | { |
| elmot | 1:d0dfbce63a89 | 123 | uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ |
| elmot | 1:d0dfbce63a89 | 124 | |
| elmot | 1:d0dfbce63a89 | 125 | uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ |
| elmot | 1:d0dfbce63a89 | 126 | |
| elmot | 1:d0dfbce63a89 | 127 | uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. |
| elmot | 1:d0dfbce63a89 | 128 | This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ |
| elmot | 1:d0dfbce63a89 | 129 | |
| elmot | 1:d0dfbce63a89 | 130 | uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer |
| elmot | 1:d0dfbce63a89 | 131 | is a read or write. |
| elmot | 1:d0dfbce63a89 | 132 | This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ |
| elmot | 1:d0dfbce63a89 | 133 | |
| elmot | 1:d0dfbce63a89 | 134 | uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. |
| elmot | 1:d0dfbce63a89 | 135 | This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ |
| elmot | 1:d0dfbce63a89 | 136 | |
| elmot | 1:d0dfbce63a89 | 137 | uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) |
| elmot | 1:d0dfbce63a89 | 138 | is enabled or disabled. |
| elmot | 1:d0dfbce63a89 | 139 | This parameter can be a value of @ref SDMMC_LL_DPSM_State */ |
| elmot | 1:d0dfbce63a89 | 140 | }SDMMC_DataInitTypeDef; |
| elmot | 1:d0dfbce63a89 | 141 | |
| elmot | 1:d0dfbce63a89 | 142 | /** |
| elmot | 1:d0dfbce63a89 | 143 | * @} |
| elmot | 1:d0dfbce63a89 | 144 | */ |
| elmot | 1:d0dfbce63a89 | 145 | |
| elmot | 1:d0dfbce63a89 | 146 | /* Exported constants --------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 147 | /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants |
| elmot | 1:d0dfbce63a89 | 148 | * @{ |
| elmot | 1:d0dfbce63a89 | 149 | */ |
| elmot | 1:d0dfbce63a89 | 150 | |
| elmot | 1:d0dfbce63a89 | 151 | /** @defgroup SDMMC_LL_Clock_Edge Clock Edge |
| elmot | 1:d0dfbce63a89 | 152 | * @{ |
| elmot | 1:d0dfbce63a89 | 153 | */ |
| elmot | 1:d0dfbce63a89 | 154 | #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000) |
| elmot | 1:d0dfbce63a89 | 155 | #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE |
| elmot | 1:d0dfbce63a89 | 156 | |
| elmot | 1:d0dfbce63a89 | 157 | #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ |
| elmot | 1:d0dfbce63a89 | 158 | ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) |
| elmot | 1:d0dfbce63a89 | 159 | /** |
| elmot | 1:d0dfbce63a89 | 160 | * @} |
| elmot | 1:d0dfbce63a89 | 161 | */ |
| elmot | 1:d0dfbce63a89 | 162 | |
| elmot | 1:d0dfbce63a89 | 163 | /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass |
| elmot | 1:d0dfbce63a89 | 164 | * @{ |
| elmot | 1:d0dfbce63a89 | 165 | */ |
| elmot | 1:d0dfbce63a89 | 166 | #define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000) |
| elmot | 1:d0dfbce63a89 | 167 | #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS |
| elmot | 1:d0dfbce63a89 | 168 | |
| elmot | 1:d0dfbce63a89 | 169 | #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \ |
| elmot | 1:d0dfbce63a89 | 170 | ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE)) |
| elmot | 1:d0dfbce63a89 | 171 | /** |
| elmot | 1:d0dfbce63a89 | 172 | * @} |
| elmot | 1:d0dfbce63a89 | 173 | */ |
| elmot | 1:d0dfbce63a89 | 174 | |
| elmot | 1:d0dfbce63a89 | 175 | /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving |
| elmot | 1:d0dfbce63a89 | 176 | * @{ |
| elmot | 1:d0dfbce63a89 | 177 | */ |
| elmot | 1:d0dfbce63a89 | 178 | #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000) |
| elmot | 1:d0dfbce63a89 | 179 | #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV |
| elmot | 1:d0dfbce63a89 | 180 | |
| elmot | 1:d0dfbce63a89 | 181 | #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ |
| elmot | 1:d0dfbce63a89 | 182 | ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) |
| elmot | 1:d0dfbce63a89 | 183 | /** |
| elmot | 1:d0dfbce63a89 | 184 | * @} |
| elmot | 1:d0dfbce63a89 | 185 | */ |
| elmot | 1:d0dfbce63a89 | 186 | |
| elmot | 1:d0dfbce63a89 | 187 | /** @defgroup SDMMC_LL_Bus_Wide Bus Width |
| elmot | 1:d0dfbce63a89 | 188 | * @{ |
| elmot | 1:d0dfbce63a89 | 189 | */ |
| elmot | 1:d0dfbce63a89 | 190 | #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000) |
| elmot | 1:d0dfbce63a89 | 191 | #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 |
| elmot | 1:d0dfbce63a89 | 192 | #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 |
| elmot | 1:d0dfbce63a89 | 193 | |
| elmot | 1:d0dfbce63a89 | 194 | #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ |
| elmot | 1:d0dfbce63a89 | 195 | ((WIDE) == SDMMC_BUS_WIDE_4B) || \ |
| elmot | 1:d0dfbce63a89 | 196 | ((WIDE) == SDMMC_BUS_WIDE_8B)) |
| elmot | 1:d0dfbce63a89 | 197 | /** |
| elmot | 1:d0dfbce63a89 | 198 | * @} |
| elmot | 1:d0dfbce63a89 | 199 | */ |
| elmot | 1:d0dfbce63a89 | 200 | |
| elmot | 1:d0dfbce63a89 | 201 | /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control |
| elmot | 1:d0dfbce63a89 | 202 | * @{ |
| elmot | 1:d0dfbce63a89 | 203 | */ |
| elmot | 1:d0dfbce63a89 | 204 | #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000) |
| elmot | 1:d0dfbce63a89 | 205 | #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN |
| elmot | 1:d0dfbce63a89 | 206 | |
| elmot | 1:d0dfbce63a89 | 207 | #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ |
| elmot | 1:d0dfbce63a89 | 208 | ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) |
| elmot | 1:d0dfbce63a89 | 209 | /** |
| elmot | 1:d0dfbce63a89 | 210 | * @} |
| elmot | 1:d0dfbce63a89 | 211 | */ |
| elmot | 1:d0dfbce63a89 | 212 | |
| elmot | 1:d0dfbce63a89 | 213 | /** @defgroup SDMMC_LL_Clock_Division Clock Division |
| elmot | 1:d0dfbce63a89 | 214 | * @{ |
| elmot | 1:d0dfbce63a89 | 215 | */ |
| elmot | 1:d0dfbce63a89 | 216 | #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF) |
| elmot | 1:d0dfbce63a89 | 217 | /** |
| elmot | 1:d0dfbce63a89 | 218 | * @} |
| elmot | 1:d0dfbce63a89 | 219 | */ |
| elmot | 1:d0dfbce63a89 | 220 | |
| elmot | 1:d0dfbce63a89 | 221 | /** @defgroup SDMMC_LL_Command_Index Command Index |
| elmot | 1:d0dfbce63a89 | 222 | * @{ |
| elmot | 1:d0dfbce63a89 | 223 | */ |
| elmot | 1:d0dfbce63a89 | 224 | #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40) |
| elmot | 1:d0dfbce63a89 | 225 | /** |
| elmot | 1:d0dfbce63a89 | 226 | * @} |
| elmot | 1:d0dfbce63a89 | 227 | */ |
| elmot | 1:d0dfbce63a89 | 228 | |
| elmot | 1:d0dfbce63a89 | 229 | /** @defgroup SDMMC_LL_Response_Type Response Type |
| elmot | 1:d0dfbce63a89 | 230 | * @{ |
| elmot | 1:d0dfbce63a89 | 231 | */ |
| elmot | 1:d0dfbce63a89 | 232 | #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000) |
| elmot | 1:d0dfbce63a89 | 233 | #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 |
| elmot | 1:d0dfbce63a89 | 234 | #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP |
| elmot | 1:d0dfbce63a89 | 235 | |
| elmot | 1:d0dfbce63a89 | 236 | #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ |
| elmot | 1:d0dfbce63a89 | 237 | ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ |
| elmot | 1:d0dfbce63a89 | 238 | ((RESPONSE) == SDMMC_RESPONSE_LONG)) |
| elmot | 1:d0dfbce63a89 | 239 | /** |
| elmot | 1:d0dfbce63a89 | 240 | * @} |
| elmot | 1:d0dfbce63a89 | 241 | */ |
| elmot | 1:d0dfbce63a89 | 242 | |
| elmot | 1:d0dfbce63a89 | 243 | /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt |
| elmot | 1:d0dfbce63a89 | 244 | * @{ |
| elmot | 1:d0dfbce63a89 | 245 | */ |
| elmot | 1:d0dfbce63a89 | 246 | #define SDMMC_WAIT_NO ((uint32_t)0x00000000) |
| elmot | 1:d0dfbce63a89 | 247 | #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT |
| elmot | 1:d0dfbce63a89 | 248 | #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND |
| elmot | 1:d0dfbce63a89 | 249 | |
| elmot | 1:d0dfbce63a89 | 250 | #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ |
| elmot | 1:d0dfbce63a89 | 251 | ((WAIT) == SDMMC_WAIT_IT) || \ |
| elmot | 1:d0dfbce63a89 | 252 | ((WAIT) == SDMMC_WAIT_PEND)) |
| elmot | 1:d0dfbce63a89 | 253 | /** |
| elmot | 1:d0dfbce63a89 | 254 | * @} |
| elmot | 1:d0dfbce63a89 | 255 | */ |
| elmot | 1:d0dfbce63a89 | 256 | |
| elmot | 1:d0dfbce63a89 | 257 | /** @defgroup SDMMC_LL_CPSM_State CPSM State |
| elmot | 1:d0dfbce63a89 | 258 | * @{ |
| elmot | 1:d0dfbce63a89 | 259 | */ |
| elmot | 1:d0dfbce63a89 | 260 | #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000) |
| elmot | 1:d0dfbce63a89 | 261 | #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN |
| elmot | 1:d0dfbce63a89 | 262 | |
| elmot | 1:d0dfbce63a89 | 263 | #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ |
| elmot | 1:d0dfbce63a89 | 264 | ((CPSM) == SDMMC_CPSM_ENABLE)) |
| elmot | 1:d0dfbce63a89 | 265 | /** |
| elmot | 1:d0dfbce63a89 | 266 | * @} |
| elmot | 1:d0dfbce63a89 | 267 | */ |
| elmot | 1:d0dfbce63a89 | 268 | |
| elmot | 1:d0dfbce63a89 | 269 | /** @defgroup SDMMC_LL_Response_Registers Response Register |
| elmot | 1:d0dfbce63a89 | 270 | * @{ |
| elmot | 1:d0dfbce63a89 | 271 | */ |
| elmot | 1:d0dfbce63a89 | 272 | #define SDMMC_RESP1 ((uint32_t)0x00000000) |
| elmot | 1:d0dfbce63a89 | 273 | #define SDMMC_RESP2 ((uint32_t)0x00000004) |
| elmot | 1:d0dfbce63a89 | 274 | #define SDMMC_RESP3 ((uint32_t)0x00000008) |
| elmot | 1:d0dfbce63a89 | 275 | #define SDMMC_RESP4 ((uint32_t)0x0000000C) |
| elmot | 1:d0dfbce63a89 | 276 | |
| elmot | 1:d0dfbce63a89 | 277 | #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ |
| elmot | 1:d0dfbce63a89 | 278 | ((RESP) == SDMMC_RESP2) || \ |
| elmot | 1:d0dfbce63a89 | 279 | ((RESP) == SDMMC_RESP3) || \ |
| elmot | 1:d0dfbce63a89 | 280 | ((RESP) == SDMMC_RESP4)) |
| elmot | 1:d0dfbce63a89 | 281 | /** |
| elmot | 1:d0dfbce63a89 | 282 | * @} |
| elmot | 1:d0dfbce63a89 | 283 | */ |
| elmot | 1:d0dfbce63a89 | 284 | |
| elmot | 1:d0dfbce63a89 | 285 | /** @defgroup SDMMC_LL_Data_Length Data Lenght |
| elmot | 1:d0dfbce63a89 | 286 | * @{ |
| elmot | 1:d0dfbce63a89 | 287 | */ |
| elmot | 1:d0dfbce63a89 | 288 | #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) |
| elmot | 1:d0dfbce63a89 | 289 | /** |
| elmot | 1:d0dfbce63a89 | 290 | * @} |
| elmot | 1:d0dfbce63a89 | 291 | */ |
| elmot | 1:d0dfbce63a89 | 292 | |
| elmot | 1:d0dfbce63a89 | 293 | /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size |
| elmot | 1:d0dfbce63a89 | 294 | * @{ |
| elmot | 1:d0dfbce63a89 | 295 | */ |
| elmot | 1:d0dfbce63a89 | 296 | #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000) |
| elmot | 1:d0dfbce63a89 | 297 | #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 |
| elmot | 1:d0dfbce63a89 | 298 | #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 |
| elmot | 1:d0dfbce63a89 | 299 | #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) |
| elmot | 1:d0dfbce63a89 | 300 | #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 |
| elmot | 1:d0dfbce63a89 | 301 | #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) |
| elmot | 1:d0dfbce63a89 | 302 | #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) |
| elmot | 1:d0dfbce63a89 | 303 | #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) |
| elmot | 1:d0dfbce63a89 | 304 | #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 |
| elmot | 1:d0dfbce63a89 | 305 | #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) |
| elmot | 1:d0dfbce63a89 | 306 | #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) |
| elmot | 1:d0dfbce63a89 | 307 | #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) |
| elmot | 1:d0dfbce63a89 | 308 | #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) |
| elmot | 1:d0dfbce63a89 | 309 | #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) |
| elmot | 1:d0dfbce63a89 | 310 | #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) |
| elmot | 1:d0dfbce63a89 | 311 | |
| elmot | 1:d0dfbce63a89 | 312 | #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ |
| elmot | 1:d0dfbce63a89 | 313 | ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ |
| elmot | 1:d0dfbce63a89 | 314 | ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ |
| elmot | 1:d0dfbce63a89 | 315 | ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ |
| elmot | 1:d0dfbce63a89 | 316 | ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ |
| elmot | 1:d0dfbce63a89 | 317 | ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ |
| elmot | 1:d0dfbce63a89 | 318 | ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ |
| elmot | 1:d0dfbce63a89 | 319 | ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ |
| elmot | 1:d0dfbce63a89 | 320 | ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ |
| elmot | 1:d0dfbce63a89 | 321 | ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ |
| elmot | 1:d0dfbce63a89 | 322 | ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ |
| elmot | 1:d0dfbce63a89 | 323 | ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ |
| elmot | 1:d0dfbce63a89 | 324 | ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ |
| elmot | 1:d0dfbce63a89 | 325 | ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ |
| elmot | 1:d0dfbce63a89 | 326 | ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) |
| elmot | 1:d0dfbce63a89 | 327 | /** |
| elmot | 1:d0dfbce63a89 | 328 | * @} |
| elmot | 1:d0dfbce63a89 | 329 | */ |
| elmot | 1:d0dfbce63a89 | 330 | |
| elmot | 1:d0dfbce63a89 | 331 | /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction |
| elmot | 1:d0dfbce63a89 | 332 | * @{ |
| elmot | 1:d0dfbce63a89 | 333 | */ |
| elmot | 1:d0dfbce63a89 | 334 | #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000) |
| elmot | 1:d0dfbce63a89 | 335 | #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR |
| elmot | 1:d0dfbce63a89 | 336 | |
| elmot | 1:d0dfbce63a89 | 337 | #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ |
| elmot | 1:d0dfbce63a89 | 338 | ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) |
| elmot | 1:d0dfbce63a89 | 339 | /** |
| elmot | 1:d0dfbce63a89 | 340 | * @} |
| elmot | 1:d0dfbce63a89 | 341 | */ |
| elmot | 1:d0dfbce63a89 | 342 | |
| elmot | 1:d0dfbce63a89 | 343 | /** @defgroup SDMMC_LL_Transfer_Type Transfer Type |
| elmot | 1:d0dfbce63a89 | 344 | * @{ |
| elmot | 1:d0dfbce63a89 | 345 | */ |
| elmot | 1:d0dfbce63a89 | 346 | #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000) |
| elmot | 1:d0dfbce63a89 | 347 | #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE |
| elmot | 1:d0dfbce63a89 | 348 | |
| elmot | 1:d0dfbce63a89 | 349 | #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ |
| elmot | 1:d0dfbce63a89 | 350 | ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) |
| elmot | 1:d0dfbce63a89 | 351 | /** |
| elmot | 1:d0dfbce63a89 | 352 | * @} |
| elmot | 1:d0dfbce63a89 | 353 | */ |
| elmot | 1:d0dfbce63a89 | 354 | |
| elmot | 1:d0dfbce63a89 | 355 | /** @defgroup SDMMC_LL_DPSM_State DPSM State |
| elmot | 1:d0dfbce63a89 | 356 | * @{ |
| elmot | 1:d0dfbce63a89 | 357 | */ |
| elmot | 1:d0dfbce63a89 | 358 | #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000) |
| elmot | 1:d0dfbce63a89 | 359 | #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN |
| elmot | 1:d0dfbce63a89 | 360 | |
| elmot | 1:d0dfbce63a89 | 361 | #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ |
| elmot | 1:d0dfbce63a89 | 362 | ((DPSM) == SDMMC_DPSM_ENABLE)) |
| elmot | 1:d0dfbce63a89 | 363 | /** |
| elmot | 1:d0dfbce63a89 | 364 | * @} |
| elmot | 1:d0dfbce63a89 | 365 | */ |
| elmot | 1:d0dfbce63a89 | 366 | |
| elmot | 1:d0dfbce63a89 | 367 | /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode |
| elmot | 1:d0dfbce63a89 | 368 | * @{ |
| elmot | 1:d0dfbce63a89 | 369 | */ |
| elmot | 1:d0dfbce63a89 | 370 | #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000) |
| elmot | 1:d0dfbce63a89 | 371 | #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) |
| elmot | 1:d0dfbce63a89 | 372 | |
| elmot | 1:d0dfbce63a89 | 373 | #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ |
| elmot | 1:d0dfbce63a89 | 374 | ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) |
| elmot | 1:d0dfbce63a89 | 375 | /** |
| elmot | 1:d0dfbce63a89 | 376 | * @} |
| elmot | 1:d0dfbce63a89 | 377 | */ |
| elmot | 1:d0dfbce63a89 | 378 | |
| elmot | 1:d0dfbce63a89 | 379 | /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources |
| elmot | 1:d0dfbce63a89 | 380 | * @{ |
| elmot | 1:d0dfbce63a89 | 381 | */ |
| elmot | 1:d0dfbce63a89 | 382 | #define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL |
| elmot | 1:d0dfbce63a89 | 383 | #define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL |
| elmot | 1:d0dfbce63a89 | 384 | #define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT |
| elmot | 1:d0dfbce63a89 | 385 | #define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT |
| elmot | 1:d0dfbce63a89 | 386 | #define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR |
| elmot | 1:d0dfbce63a89 | 387 | #define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR |
| elmot | 1:d0dfbce63a89 | 388 | #define SDMMC_IT_CMDREND SDMMC_STA_CMDREND |
| elmot | 1:d0dfbce63a89 | 389 | #define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT |
| elmot | 1:d0dfbce63a89 | 390 | #define SDMMC_IT_DATAEND SDMMC_STA_DATAEND |
| elmot | 1:d0dfbce63a89 | 391 | #define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND |
| elmot | 1:d0dfbce63a89 | 392 | #define SDMMC_IT_CMDACT SDMMC_STA_CMDACT |
| elmot | 1:d0dfbce63a89 | 393 | #define SDMMC_IT_TXACT SDMMC_STA_TXACT |
| elmot | 1:d0dfbce63a89 | 394 | #define SDMMC_IT_RXACT SDMMC_STA_RXACT |
| elmot | 1:d0dfbce63a89 | 395 | #define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE |
| elmot | 1:d0dfbce63a89 | 396 | #define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF |
| elmot | 1:d0dfbce63a89 | 397 | #define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF |
| elmot | 1:d0dfbce63a89 | 398 | #define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF |
| elmot | 1:d0dfbce63a89 | 399 | #define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE |
| elmot | 1:d0dfbce63a89 | 400 | #define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE |
| elmot | 1:d0dfbce63a89 | 401 | #define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL |
| elmot | 1:d0dfbce63a89 | 402 | #define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL |
| elmot | 1:d0dfbce63a89 | 403 | #define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT |
| elmot | 1:d0dfbce63a89 | 404 | /** |
| elmot | 1:d0dfbce63a89 | 405 | * @} |
| elmot | 1:d0dfbce63a89 | 406 | */ |
| elmot | 1:d0dfbce63a89 | 407 | |
| elmot | 1:d0dfbce63a89 | 408 | /** @defgroup SDMMC_LL_Flags Flags |
| elmot | 1:d0dfbce63a89 | 409 | * @{ |
| elmot | 1:d0dfbce63a89 | 410 | */ |
| elmot | 1:d0dfbce63a89 | 411 | #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL |
| elmot | 1:d0dfbce63a89 | 412 | #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL |
| elmot | 1:d0dfbce63a89 | 413 | #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT |
| elmot | 1:d0dfbce63a89 | 414 | #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT |
| elmot | 1:d0dfbce63a89 | 415 | #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR |
| elmot | 1:d0dfbce63a89 | 416 | #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR |
| elmot | 1:d0dfbce63a89 | 417 | #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND |
| elmot | 1:d0dfbce63a89 | 418 | #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT |
| elmot | 1:d0dfbce63a89 | 419 | #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND |
| elmot | 1:d0dfbce63a89 | 420 | #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND |
| elmot | 1:d0dfbce63a89 | 421 | #define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT |
| elmot | 1:d0dfbce63a89 | 422 | #define SDMMC_FLAG_TXACT SDMMC_STA_TXACT |
| elmot | 1:d0dfbce63a89 | 423 | #define SDMMC_FLAG_RXACT SDMMC_STA_RXACT |
| elmot | 1:d0dfbce63a89 | 424 | #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE |
| elmot | 1:d0dfbce63a89 | 425 | #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF |
| elmot | 1:d0dfbce63a89 | 426 | #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF |
| elmot | 1:d0dfbce63a89 | 427 | #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF |
| elmot | 1:d0dfbce63a89 | 428 | #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE |
| elmot | 1:d0dfbce63a89 | 429 | #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE |
| elmot | 1:d0dfbce63a89 | 430 | #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL |
| elmot | 1:d0dfbce63a89 | 431 | #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL |
| elmot | 1:d0dfbce63a89 | 432 | #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT |
| elmot | 1:d0dfbce63a89 | 433 | /** |
| elmot | 1:d0dfbce63a89 | 434 | * @} |
| elmot | 1:d0dfbce63a89 | 435 | */ |
| elmot | 1:d0dfbce63a89 | 436 | |
| elmot | 1:d0dfbce63a89 | 437 | /** |
| elmot | 1:d0dfbce63a89 | 438 | * @} |
| elmot | 1:d0dfbce63a89 | 439 | */ |
| elmot | 1:d0dfbce63a89 | 440 | |
| elmot | 1:d0dfbce63a89 | 441 | /* Exported macro ------------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 442 | /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros |
| elmot | 1:d0dfbce63a89 | 443 | * @{ |
| elmot | 1:d0dfbce63a89 | 444 | */ |
| elmot | 1:d0dfbce63a89 | 445 | |
| elmot | 1:d0dfbce63a89 | 446 | /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions |
| elmot | 1:d0dfbce63a89 | 447 | * @brief SDMMC_LL registers bit address in the alias region |
| elmot | 1:d0dfbce63a89 | 448 | * @{ |
| elmot | 1:d0dfbce63a89 | 449 | */ |
| elmot | 1:d0dfbce63a89 | 450 | /* ---------------------- SDMMC registers bit mask --------------------------- */ |
| elmot | 1:d0dfbce63a89 | 451 | /* --- CLKCR Register ---*/ |
| elmot | 1:d0dfbce63a89 | 452 | /* CLKCR register clear mask */ |
| elmot | 1:d0dfbce63a89 | 453 | #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ |
| elmot | 1:d0dfbce63a89 | 454 | SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\ |
| elmot | 1:d0dfbce63a89 | 455 | SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) |
| elmot | 1:d0dfbce63a89 | 456 | |
| elmot | 1:d0dfbce63a89 | 457 | /* --- DCTRL Register ---*/ |
| elmot | 1:d0dfbce63a89 | 458 | /* SDMMC DCTRL Clear Mask */ |
| elmot | 1:d0dfbce63a89 | 459 | #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ |
| elmot | 1:d0dfbce63a89 | 460 | SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) |
| elmot | 1:d0dfbce63a89 | 461 | |
| elmot | 1:d0dfbce63a89 | 462 | /* --- CMD Register ---*/ |
| elmot | 1:d0dfbce63a89 | 463 | /* CMD Register clear mask */ |
| elmot | 1:d0dfbce63a89 | 464 | #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ |
| elmot | 1:d0dfbce63a89 | 465 | SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ |
| elmot | 1:d0dfbce63a89 | 466 | SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND)) |
| elmot | 1:d0dfbce63a89 | 467 | |
| elmot | 1:d0dfbce63a89 | 468 | /* SDMMC Intialization Frequency (400KHz max) */ |
| elmot | 1:d0dfbce63a89 | 469 | #define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) |
| elmot | 1:d0dfbce63a89 | 470 | |
| elmot | 1:d0dfbce63a89 | 471 | /* SDMMC Data Transfer Frequency (25MHz max) */ |
| elmot | 1:d0dfbce63a89 | 472 | #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) |
| elmot | 1:d0dfbce63a89 | 473 | |
| elmot | 1:d0dfbce63a89 | 474 | /** |
| elmot | 1:d0dfbce63a89 | 475 | * @} |
| elmot | 1:d0dfbce63a89 | 476 | */ |
| elmot | 1:d0dfbce63a89 | 477 | |
| elmot | 1:d0dfbce63a89 | 478 | /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration |
| elmot | 1:d0dfbce63a89 | 479 | * @brief macros to handle interrupts and specific clock configurations |
| elmot | 1:d0dfbce63a89 | 480 | * @{ |
| elmot | 1:d0dfbce63a89 | 481 | */ |
| elmot | 1:d0dfbce63a89 | 482 | |
| elmot | 1:d0dfbce63a89 | 483 | /** |
| elmot | 1:d0dfbce63a89 | 484 | * @brief Enable the SDMMC device. |
| elmot | 1:d0dfbce63a89 | 485 | * @param __INSTANCE__: SDMMC Instance |
| elmot | 1:d0dfbce63a89 | 486 | * @retval None |
| elmot | 1:d0dfbce63a89 | 487 | */ |
| elmot | 1:d0dfbce63a89 | 488 | #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN) |
| elmot | 1:d0dfbce63a89 | 489 | |
| elmot | 1:d0dfbce63a89 | 490 | /** |
| elmot | 1:d0dfbce63a89 | 491 | * @brief Disable the SDMMC device. |
| elmot | 1:d0dfbce63a89 | 492 | * @param __INSTANCE__: SDMMC Instance |
| elmot | 1:d0dfbce63a89 | 493 | * @retval None |
| elmot | 1:d0dfbce63a89 | 494 | */ |
| elmot | 1:d0dfbce63a89 | 495 | #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN) |
| elmot | 1:d0dfbce63a89 | 496 | |
| elmot | 1:d0dfbce63a89 | 497 | /** |
| elmot | 1:d0dfbce63a89 | 498 | * @brief Enable the SDMMC DMA transfer. |
| elmot | 1:d0dfbce63a89 | 499 | * @param None |
| elmot | 1:d0dfbce63a89 | 500 | * @retval None |
| elmot | 1:d0dfbce63a89 | 501 | */ |
| elmot | 1:d0dfbce63a89 | 502 | #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN) |
| elmot | 1:d0dfbce63a89 | 503 | /** |
| elmot | 1:d0dfbce63a89 | 504 | * @brief Disable the SDMMC DMA transfer. |
| elmot | 1:d0dfbce63a89 | 505 | * @param None |
| elmot | 1:d0dfbce63a89 | 506 | * @retval None |
| elmot | 1:d0dfbce63a89 | 507 | */ |
| elmot | 1:d0dfbce63a89 | 508 | #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) |
| elmot | 1:d0dfbce63a89 | 509 | |
| elmot | 1:d0dfbce63a89 | 510 | /** |
| elmot | 1:d0dfbce63a89 | 511 | * @brief Enable the SDMMC device interrupt. |
| elmot | 1:d0dfbce63a89 | 512 | * @param __INSTANCE__: Pointer to SDMMC register base |
| elmot | 1:d0dfbce63a89 | 513 | * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. |
| elmot | 1:d0dfbce63a89 | 514 | * This parameter can be one or a combination of the following values: |
| elmot | 1:d0dfbce63a89 | 515 | * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
| elmot | 1:d0dfbce63a89 | 516 | * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
| elmot | 1:d0dfbce63a89 | 517 | * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt |
| elmot | 1:d0dfbce63a89 | 518 | * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt |
| elmot | 1:d0dfbce63a89 | 519 | * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| elmot | 1:d0dfbce63a89 | 520 | * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt |
| elmot | 1:d0dfbce63a89 | 521 | * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt |
| elmot | 1:d0dfbce63a89 | 522 | * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt |
| elmot | 1:d0dfbce63a89 | 523 | * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
| elmot | 1:d0dfbce63a89 | 524 | * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
| elmot | 1:d0dfbce63a89 | 525 | * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt |
| elmot | 1:d0dfbce63a89 | 526 | * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt |
| elmot | 1:d0dfbce63a89 | 527 | * @arg SDMMC_IT_RXACT: Data receive in progress interrupt |
| elmot | 1:d0dfbce63a89 | 528 | * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
| elmot | 1:d0dfbce63a89 | 529 | * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
| elmot | 1:d0dfbce63a89 | 530 | * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt |
| elmot | 1:d0dfbce63a89 | 531 | * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt |
| elmot | 1:d0dfbce63a89 | 532 | * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt |
| elmot | 1:d0dfbce63a89 | 533 | * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt |
| elmot | 1:d0dfbce63a89 | 534 | * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt |
| elmot | 1:d0dfbce63a89 | 535 | * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt |
| elmot | 1:d0dfbce63a89 | 536 | * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt |
| elmot | 1:d0dfbce63a89 | 537 | * @retval None |
| elmot | 1:d0dfbce63a89 | 538 | */ |
| elmot | 1:d0dfbce63a89 | 539 | #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) |
| elmot | 1:d0dfbce63a89 | 540 | |
| elmot | 1:d0dfbce63a89 | 541 | /** |
| elmot | 1:d0dfbce63a89 | 542 | * @brief Disable the SDMMC device interrupt. |
| elmot | 1:d0dfbce63a89 | 543 | * @param __INSTANCE__: Pointer to SDMMC register base |
| elmot | 1:d0dfbce63a89 | 544 | * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. |
| elmot | 1:d0dfbce63a89 | 545 | * This parameter can be one or a combination of the following values: |
| elmot | 1:d0dfbce63a89 | 546 | * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
| elmot | 1:d0dfbce63a89 | 547 | * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
| elmot | 1:d0dfbce63a89 | 548 | * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt |
| elmot | 1:d0dfbce63a89 | 549 | * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt |
| elmot | 1:d0dfbce63a89 | 550 | * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| elmot | 1:d0dfbce63a89 | 551 | * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt |
| elmot | 1:d0dfbce63a89 | 552 | * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt |
| elmot | 1:d0dfbce63a89 | 553 | * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt |
| elmot | 1:d0dfbce63a89 | 554 | * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
| elmot | 1:d0dfbce63a89 | 555 | * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
| elmot | 1:d0dfbce63a89 | 556 | * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt |
| elmot | 1:d0dfbce63a89 | 557 | * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt |
| elmot | 1:d0dfbce63a89 | 558 | * @arg SDMMC_IT_RXACT: Data receive in progress interrupt |
| elmot | 1:d0dfbce63a89 | 559 | * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
| elmot | 1:d0dfbce63a89 | 560 | * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
| elmot | 1:d0dfbce63a89 | 561 | * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt |
| elmot | 1:d0dfbce63a89 | 562 | * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt |
| elmot | 1:d0dfbce63a89 | 563 | * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt |
| elmot | 1:d0dfbce63a89 | 564 | * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt |
| elmot | 1:d0dfbce63a89 | 565 | * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt |
| elmot | 1:d0dfbce63a89 | 566 | * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt |
| elmot | 1:d0dfbce63a89 | 567 | * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt |
| elmot | 1:d0dfbce63a89 | 568 | * @retval None |
| elmot | 1:d0dfbce63a89 | 569 | */ |
| elmot | 1:d0dfbce63a89 | 570 | #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) |
| elmot | 1:d0dfbce63a89 | 571 | |
| elmot | 1:d0dfbce63a89 | 572 | /** |
| elmot | 1:d0dfbce63a89 | 573 | * @brief Checks whether the specified SDMMC flag is set or not. |
| elmot | 1:d0dfbce63a89 | 574 | * @param __INSTANCE__: Pointer to SDMMC register base |
| elmot | 1:d0dfbce63a89 | 575 | * @param __FLAG__: specifies the flag to check. |
| elmot | 1:d0dfbce63a89 | 576 | * This parameter can be one of the following values: |
| elmot | 1:d0dfbce63a89 | 577 | * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) |
| elmot | 1:d0dfbce63a89 | 578 | * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
| elmot | 1:d0dfbce63a89 | 579 | * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout |
| elmot | 1:d0dfbce63a89 | 580 | * @arg SDMMC_FLAG_DTIMEOUT: Data timeout |
| elmot | 1:d0dfbce63a89 | 581 | * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error |
| elmot | 1:d0dfbce63a89 | 582 | * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error |
| elmot | 1:d0dfbce63a89 | 583 | * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) |
| elmot | 1:d0dfbce63a89 | 584 | * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) |
| elmot | 1:d0dfbce63a89 | 585 | * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
| elmot | 1:d0dfbce63a89 | 586 | * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
| elmot | 1:d0dfbce63a89 | 587 | * @arg SDMMC_FLAG_CMDACT: Command transfer in progress |
| elmot | 1:d0dfbce63a89 | 588 | * @arg SDMMC_FLAG_TXACT: Data transmit in progress |
| elmot | 1:d0dfbce63a89 | 589 | * @arg SDMMC_FLAG_RXACT: Data receive in progress |
| elmot | 1:d0dfbce63a89 | 590 | * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty |
| elmot | 1:d0dfbce63a89 | 591 | * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full |
| elmot | 1:d0dfbce63a89 | 592 | * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full |
| elmot | 1:d0dfbce63a89 | 593 | * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full |
| elmot | 1:d0dfbce63a89 | 594 | * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty |
| elmot | 1:d0dfbce63a89 | 595 | * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty |
| elmot | 1:d0dfbce63a89 | 596 | * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO |
| elmot | 1:d0dfbce63a89 | 597 | * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO |
| elmot | 1:d0dfbce63a89 | 598 | * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received |
| elmot | 1:d0dfbce63a89 | 599 | * @retval The new state of SDMMC_FLAG (SET or RESET). |
| elmot | 1:d0dfbce63a89 | 600 | */ |
| elmot | 1:d0dfbce63a89 | 601 | #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) |
| elmot | 1:d0dfbce63a89 | 602 | |
| elmot | 1:d0dfbce63a89 | 603 | |
| elmot | 1:d0dfbce63a89 | 604 | /** |
| elmot | 1:d0dfbce63a89 | 605 | * @brief Clears the SDMMC pending flags. |
| elmot | 1:d0dfbce63a89 | 606 | * @param __INSTANCE__: Pointer to SDMMC register base |
| elmot | 1:d0dfbce63a89 | 607 | * @param __FLAG__: specifies the flag to clear. |
| elmot | 1:d0dfbce63a89 | 608 | * This parameter can be one or a combination of the following values: |
| elmot | 1:d0dfbce63a89 | 609 | * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) |
| elmot | 1:d0dfbce63a89 | 610 | * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
| elmot | 1:d0dfbce63a89 | 611 | * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout |
| elmot | 1:d0dfbce63a89 | 612 | * @arg SDMMC_FLAG_DTIMEOUT: Data timeout |
| elmot | 1:d0dfbce63a89 | 613 | * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error |
| elmot | 1:d0dfbce63a89 | 614 | * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error |
| elmot | 1:d0dfbce63a89 | 615 | * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) |
| elmot | 1:d0dfbce63a89 | 616 | * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) |
| elmot | 1:d0dfbce63a89 | 617 | * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
| elmot | 1:d0dfbce63a89 | 618 | * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
| elmot | 1:d0dfbce63a89 | 619 | * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received |
| elmot | 1:d0dfbce63a89 | 620 | * @retval None |
| elmot | 1:d0dfbce63a89 | 621 | */ |
| elmot | 1:d0dfbce63a89 | 622 | #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) |
| elmot | 1:d0dfbce63a89 | 623 | |
| elmot | 1:d0dfbce63a89 | 624 | /** |
| elmot | 1:d0dfbce63a89 | 625 | * @brief Checks whether the specified SDMMC interrupt has occurred or not. |
| elmot | 1:d0dfbce63a89 | 626 | * @param __INSTANCE__: Pointer to SDMMC register base |
| elmot | 1:d0dfbce63a89 | 627 | * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. |
| elmot | 1:d0dfbce63a89 | 628 | * This parameter can be one of the following values: |
| elmot | 1:d0dfbce63a89 | 629 | * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
| elmot | 1:d0dfbce63a89 | 630 | * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
| elmot | 1:d0dfbce63a89 | 631 | * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt |
| elmot | 1:d0dfbce63a89 | 632 | * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt |
| elmot | 1:d0dfbce63a89 | 633 | * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| elmot | 1:d0dfbce63a89 | 634 | * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt |
| elmot | 1:d0dfbce63a89 | 635 | * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt |
| elmot | 1:d0dfbce63a89 | 636 | * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt |
| elmot | 1:d0dfbce63a89 | 637 | * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
| elmot | 1:d0dfbce63a89 | 638 | * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
| elmot | 1:d0dfbce63a89 | 639 | * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt |
| elmot | 1:d0dfbce63a89 | 640 | * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt |
| elmot | 1:d0dfbce63a89 | 641 | * @arg SDMMC_IT_RXACT: Data receive in progress interrupt |
| elmot | 1:d0dfbce63a89 | 642 | * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
| elmot | 1:d0dfbce63a89 | 643 | * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
| elmot | 1:d0dfbce63a89 | 644 | * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt |
| elmot | 1:d0dfbce63a89 | 645 | * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt |
| elmot | 1:d0dfbce63a89 | 646 | * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt |
| elmot | 1:d0dfbce63a89 | 647 | * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt |
| elmot | 1:d0dfbce63a89 | 648 | * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt |
| elmot | 1:d0dfbce63a89 | 649 | * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt |
| elmot | 1:d0dfbce63a89 | 650 | * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt |
| elmot | 1:d0dfbce63a89 | 651 | * @retval The new state of SDMMC_IT (SET or RESET). |
| elmot | 1:d0dfbce63a89 | 652 | */ |
| elmot | 1:d0dfbce63a89 | 653 | #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) |
| elmot | 1:d0dfbce63a89 | 654 | |
| elmot | 1:d0dfbce63a89 | 655 | /** |
| elmot | 1:d0dfbce63a89 | 656 | * @brief Clears the SDMMC's interrupt pending bits. |
| elmot | 1:d0dfbce63a89 | 657 | * @param __INSTANCE__: Pointer to SDMMC register base |
| elmot | 1:d0dfbce63a89 | 658 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
| elmot | 1:d0dfbce63a89 | 659 | * This parameter can be one or a combination of the following values: |
| elmot | 1:d0dfbce63a89 | 660 | * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
| elmot | 1:d0dfbce63a89 | 661 | * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
| elmot | 1:d0dfbce63a89 | 662 | * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt |
| elmot | 1:d0dfbce63a89 | 663 | * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt |
| elmot | 1:d0dfbce63a89 | 664 | * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| elmot | 1:d0dfbce63a89 | 665 | * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt |
| elmot | 1:d0dfbce63a89 | 666 | * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt |
| elmot | 1:d0dfbce63a89 | 667 | * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt |
| elmot | 1:d0dfbce63a89 | 668 | * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt |
| elmot | 1:d0dfbce63a89 | 669 | * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt |
| elmot | 1:d0dfbce63a89 | 670 | * @retval None |
| elmot | 1:d0dfbce63a89 | 671 | */ |
| elmot | 1:d0dfbce63a89 | 672 | #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) |
| elmot | 1:d0dfbce63a89 | 673 | |
| elmot | 1:d0dfbce63a89 | 674 | /** |
| elmot | 1:d0dfbce63a89 | 675 | * @brief Enable Start the SD I/O Read Wait operation. |
| elmot | 1:d0dfbce63a89 | 676 | * @param __INSTANCE__: Pointer to SDMMC register base |
| elmot | 1:d0dfbce63a89 | 677 | * @retval None |
| elmot | 1:d0dfbce63a89 | 678 | */ |
| elmot | 1:d0dfbce63a89 | 679 | #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) |
| elmot | 1:d0dfbce63a89 | 680 | |
| elmot | 1:d0dfbce63a89 | 681 | /** |
| elmot | 1:d0dfbce63a89 | 682 | * @brief Disable Start the SD I/O Read Wait operations. |
| elmot | 1:d0dfbce63a89 | 683 | * @param __INSTANCE__: Pointer to SDMMC register base |
| elmot | 1:d0dfbce63a89 | 684 | * @retval None |
| elmot | 1:d0dfbce63a89 | 685 | */ |
| elmot | 1:d0dfbce63a89 | 686 | #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) |
| elmot | 1:d0dfbce63a89 | 687 | |
| elmot | 1:d0dfbce63a89 | 688 | /** |
| elmot | 1:d0dfbce63a89 | 689 | * @brief Enable Start the SD I/O Read Wait operation. |
| elmot | 1:d0dfbce63a89 | 690 | * @param __INSTANCE__: Pointer to SDMMC register base |
| elmot | 1:d0dfbce63a89 | 691 | * @retval None |
| elmot | 1:d0dfbce63a89 | 692 | */ |
| elmot | 1:d0dfbce63a89 | 693 | #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) |
| elmot | 1:d0dfbce63a89 | 694 | |
| elmot | 1:d0dfbce63a89 | 695 | /** |
| elmot | 1:d0dfbce63a89 | 696 | * @brief Disable Stop the SD I/O Read Wait operations. |
| elmot | 1:d0dfbce63a89 | 697 | * @param __INSTANCE__: Pointer to SDMMC register base |
| elmot | 1:d0dfbce63a89 | 698 | * @retval None |
| elmot | 1:d0dfbce63a89 | 699 | */ |
| elmot | 1:d0dfbce63a89 | 700 | #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) |
| elmot | 1:d0dfbce63a89 | 701 | |
| elmot | 1:d0dfbce63a89 | 702 | /** |
| elmot | 1:d0dfbce63a89 | 703 | * @brief Enable the SD I/O Mode Operation. |
| elmot | 1:d0dfbce63a89 | 704 | * @param __INSTANCE__: Pointer to SDMMC register base |
| elmot | 1:d0dfbce63a89 | 705 | * @retval None |
| elmot | 1:d0dfbce63a89 | 706 | */ |
| elmot | 1:d0dfbce63a89 | 707 | #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) |
| elmot | 1:d0dfbce63a89 | 708 | |
| elmot | 1:d0dfbce63a89 | 709 | /** |
| elmot | 1:d0dfbce63a89 | 710 | * @brief Disable the SD I/O Mode Operation. |
| elmot | 1:d0dfbce63a89 | 711 | * @param __INSTANCE__: Pointer to SDMMC register base |
| elmot | 1:d0dfbce63a89 | 712 | * @retval None |
| elmot | 1:d0dfbce63a89 | 713 | */ |
| elmot | 1:d0dfbce63a89 | 714 | #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) |
| elmot | 1:d0dfbce63a89 | 715 | |
| elmot | 1:d0dfbce63a89 | 716 | /** |
| elmot | 1:d0dfbce63a89 | 717 | * @brief Enable the SD I/O Suspend command sending. |
| elmot | 1:d0dfbce63a89 | 718 | * @param __INSTANCE__: Pointer to SDMMC register base |
| elmot | 1:d0dfbce63a89 | 719 | * @retval None |
| elmot | 1:d0dfbce63a89 | 720 | */ |
| elmot | 1:d0dfbce63a89 | 721 | #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) |
| elmot | 1:d0dfbce63a89 | 722 | |
| elmot | 1:d0dfbce63a89 | 723 | /** |
| elmot | 1:d0dfbce63a89 | 724 | * @brief Disable the SD I/O Suspend command sending. |
| elmot | 1:d0dfbce63a89 | 725 | * @param __INSTANCE__: Pointer to SDMMC register base |
| elmot | 1:d0dfbce63a89 | 726 | * @retval None |
| elmot | 1:d0dfbce63a89 | 727 | */ |
| elmot | 1:d0dfbce63a89 | 728 | #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) |
| elmot | 1:d0dfbce63a89 | 729 | |
| elmot | 1:d0dfbce63a89 | 730 | /** |
| elmot | 1:d0dfbce63a89 | 731 | * @} |
| elmot | 1:d0dfbce63a89 | 732 | */ |
| elmot | 1:d0dfbce63a89 | 733 | |
| elmot | 1:d0dfbce63a89 | 734 | /** |
| elmot | 1:d0dfbce63a89 | 735 | * @} |
| elmot | 1:d0dfbce63a89 | 736 | */ |
| elmot | 1:d0dfbce63a89 | 737 | |
| elmot | 1:d0dfbce63a89 | 738 | /* Exported functions --------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 739 | /** @addtogroup SDMMC_LL_Exported_Functions |
| elmot | 1:d0dfbce63a89 | 740 | * @{ |
| elmot | 1:d0dfbce63a89 | 741 | */ |
| elmot | 1:d0dfbce63a89 | 742 | |
| elmot | 1:d0dfbce63a89 | 743 | /* Initialization/de-initialization functions **********************************/ |
| elmot | 1:d0dfbce63a89 | 744 | /** @addtogroup HAL_SDMMC_LL_Group1 |
| elmot | 1:d0dfbce63a89 | 745 | * @{ |
| elmot | 1:d0dfbce63a89 | 746 | */ |
| elmot | 1:d0dfbce63a89 | 747 | HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); |
| elmot | 1:d0dfbce63a89 | 748 | /** |
| elmot | 1:d0dfbce63a89 | 749 | * @} |
| elmot | 1:d0dfbce63a89 | 750 | */ |
| elmot | 1:d0dfbce63a89 | 751 | |
| elmot | 1:d0dfbce63a89 | 752 | /* I/O operation functions *****************************************************/ |
| elmot | 1:d0dfbce63a89 | 753 | /** @addtogroup HAL_SDMMC_LL_Group2 |
| elmot | 1:d0dfbce63a89 | 754 | * @{ |
| elmot | 1:d0dfbce63a89 | 755 | */ |
| elmot | 1:d0dfbce63a89 | 756 | /* Blocking mode: Polling */ |
| elmot | 1:d0dfbce63a89 | 757 | uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); |
| elmot | 1:d0dfbce63a89 | 758 | HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); |
| elmot | 1:d0dfbce63a89 | 759 | /** |
| elmot | 1:d0dfbce63a89 | 760 | * @} |
| elmot | 1:d0dfbce63a89 | 761 | */ |
| elmot | 1:d0dfbce63a89 | 762 | |
| elmot | 1:d0dfbce63a89 | 763 | /* Peripheral Control functions ************************************************/ |
| elmot | 1:d0dfbce63a89 | 764 | /** @addtogroup HAL_SDMMC_LL_Group3 |
| elmot | 1:d0dfbce63a89 | 765 | * @{ |
| elmot | 1:d0dfbce63a89 | 766 | */ |
| elmot | 1:d0dfbce63a89 | 767 | HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); |
| elmot | 1:d0dfbce63a89 | 768 | HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); |
| elmot | 1:d0dfbce63a89 | 769 | uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); |
| elmot | 1:d0dfbce63a89 | 770 | |
| elmot | 1:d0dfbce63a89 | 771 | /* Command path state machine (CPSM) management functions */ |
| elmot | 1:d0dfbce63a89 | 772 | HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); |
| elmot | 1:d0dfbce63a89 | 773 | uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); |
| elmot | 1:d0dfbce63a89 | 774 | uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); |
| elmot | 1:d0dfbce63a89 | 775 | |
| elmot | 1:d0dfbce63a89 | 776 | /* Data path state machine (DPSM) management functions */ |
| elmot | 1:d0dfbce63a89 | 777 | HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data); |
| elmot | 1:d0dfbce63a89 | 778 | uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); |
| elmot | 1:d0dfbce63a89 | 779 | uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); |
| elmot | 1:d0dfbce63a89 | 780 | |
| elmot | 1:d0dfbce63a89 | 781 | /* SDMMC Cards mode management functions */ |
| elmot | 1:d0dfbce63a89 | 782 | HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); |
| elmot | 1:d0dfbce63a89 | 783 | |
| elmot | 1:d0dfbce63a89 | 784 | /** |
| elmot | 1:d0dfbce63a89 | 785 | * @} |
| elmot | 1:d0dfbce63a89 | 786 | */ |
| elmot | 1:d0dfbce63a89 | 787 | |
| elmot | 1:d0dfbce63a89 | 788 | /** |
| elmot | 1:d0dfbce63a89 | 789 | * @} |
| elmot | 1:d0dfbce63a89 | 790 | */ |
| elmot | 1:d0dfbce63a89 | 791 | |
| elmot | 1:d0dfbce63a89 | 792 | /** |
| elmot | 1:d0dfbce63a89 | 793 | * @} |
| elmot | 1:d0dfbce63a89 | 794 | */ |
| elmot | 1:d0dfbce63a89 | 795 | |
| elmot | 1:d0dfbce63a89 | 796 | /** |
| elmot | 1:d0dfbce63a89 | 797 | * @} |
| elmot | 1:d0dfbce63a89 | 798 | */ |
| elmot | 1:d0dfbce63a89 | 799 | |
| elmot | 1:d0dfbce63a89 | 800 | #endif /* SDMMC1 */ |
| elmot | 1:d0dfbce63a89 | 801 | |
| elmot | 1:d0dfbce63a89 | 802 | #ifdef __cplusplus |
| elmot | 1:d0dfbce63a89 | 803 | } |
| elmot | 1:d0dfbce63a89 | 804 | #endif |
| elmot | 1:d0dfbce63a89 | 805 | |
| elmot | 1:d0dfbce63a89 | 806 | #endif /* __STM32L4xx_LL_SDMMC_H */ |
| elmot | 1:d0dfbce63a89 | 807 | |
| elmot | 1:d0dfbce63a89 | 808 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |