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HAL_L476/stm32l4xx_ll_dma.h@1:d0dfbce63a89, 2017-02-24 (annotated)

Committer:
elmot
Date:
Fri Feb 24 21:13:56 2017 +0000
Revision:
1:d0dfbce63a89
Ready-to-copy

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elmot 1:d0dfbce63a89 1 /**
elmot 1:d0dfbce63a89 2 ******************************************************************************
elmot 1:d0dfbce63a89 3 * @file stm32l4xx_ll_dma.h
elmot 1:d0dfbce63a89 4 * @author MCD Application Team
elmot 1:d0dfbce63a89 5 * @version V1.5.1
elmot 1:d0dfbce63a89 6 * @date 31-May-2016
elmot 1:d0dfbce63a89 7 * @brief Header file of DMA LL module.
elmot 1:d0dfbce63a89 8 ******************************************************************************
elmot 1:d0dfbce63a89 9 * @attention
elmot 1:d0dfbce63a89 10 *
elmot 1:d0dfbce63a89 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
elmot 1:d0dfbce63a89 12 *
elmot 1:d0dfbce63a89 13 * Redistribution and use in source and binary forms, with or without modification,
elmot 1:d0dfbce63a89 14 * are permitted provided that the following conditions are met:
elmot 1:d0dfbce63a89 15 * 1. Redistributions of source code must retain the above copyright notice,
elmot 1:d0dfbce63a89 16 * this list of conditions and the following disclaimer.
elmot 1:d0dfbce63a89 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
elmot 1:d0dfbce63a89 18 * this list of conditions and the following disclaimer in the documentation
elmot 1:d0dfbce63a89 19 * and/or other materials provided with the distribution.
elmot 1:d0dfbce63a89 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
elmot 1:d0dfbce63a89 21 * may be used to endorse or promote products derived from this software
elmot 1:d0dfbce63a89 22 * without specific prior written permission.
elmot 1:d0dfbce63a89 23 *
elmot 1:d0dfbce63a89 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elmot 1:d0dfbce63a89 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elmot 1:d0dfbce63a89 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elmot 1:d0dfbce63a89 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
elmot 1:d0dfbce63a89 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
elmot 1:d0dfbce63a89 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
elmot 1:d0dfbce63a89 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
elmot 1:d0dfbce63a89 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
elmot 1:d0dfbce63a89 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
elmot 1:d0dfbce63a89 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elmot 1:d0dfbce63a89 34 *
elmot 1:d0dfbce63a89 35 ******************************************************************************
elmot 1:d0dfbce63a89 36 */
elmot 1:d0dfbce63a89 37
elmot 1:d0dfbce63a89 38 /* Define to prevent recursive inclusion -------------------------------------*/
elmot 1:d0dfbce63a89 39 #ifndef __STM32L4xx_LL_DMA_H
elmot 1:d0dfbce63a89 40 #define __STM32L4xx_LL_DMA_H
elmot 1:d0dfbce63a89 41
elmot 1:d0dfbce63a89 42 #ifdef __cplusplus
elmot 1:d0dfbce63a89 43 extern "C" {
elmot 1:d0dfbce63a89 44 #endif
elmot 1:d0dfbce63a89 45
elmot 1:d0dfbce63a89 46 /* Includes ------------------------------------------------------------------*/
elmot 1:d0dfbce63a89 47 #include "stm32l4xx.h"
elmot 1:d0dfbce63a89 48
elmot 1:d0dfbce63a89 49 /** @addtogroup STM32L4xx_LL_Driver
elmot 1:d0dfbce63a89 50 * @{
elmot 1:d0dfbce63a89 51 */
elmot 1:d0dfbce63a89 52
elmot 1:d0dfbce63a89 53 #if defined (DMA1) || defined (DMA2)
elmot 1:d0dfbce63a89 54
elmot 1:d0dfbce63a89 55 /** @defgroup DMA_LL DMA
elmot 1:d0dfbce63a89 56 * @{
elmot 1:d0dfbce63a89 57 */
elmot 1:d0dfbce63a89 58
elmot 1:d0dfbce63a89 59 /* Private types -------------------------------------------------------------*/
elmot 1:d0dfbce63a89 60 /* Private variables ---------------------------------------------------------*/
elmot 1:d0dfbce63a89 61 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
elmot 1:d0dfbce63a89 62 * @{
elmot 1:d0dfbce63a89 63 */
elmot 1:d0dfbce63a89 64 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
elmot 1:d0dfbce63a89 65 static const uint8_t CHANNEL_OFFSET_TAB[] =
elmot 1:d0dfbce63a89 66 {
elmot 1:d0dfbce63a89 67 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
elmot 1:d0dfbce63a89 68 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
elmot 1:d0dfbce63a89 69 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
elmot 1:d0dfbce63a89 70 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
elmot 1:d0dfbce63a89 71 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
elmot 1:d0dfbce63a89 72 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
elmot 1:d0dfbce63a89 73 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
elmot 1:d0dfbce63a89 74 };
elmot 1:d0dfbce63a89 75 /**
elmot 1:d0dfbce63a89 76 * @}
elmot 1:d0dfbce63a89 77 */
elmot 1:d0dfbce63a89 78
elmot 1:d0dfbce63a89 79 /* Private constants ---------------------------------------------------------*/
elmot 1:d0dfbce63a89 80 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
elmot 1:d0dfbce63a89 81 * @{
elmot 1:d0dfbce63a89 82 */
elmot 1:d0dfbce63a89 83 /* Define used to get CSELR register offset */
elmot 1:d0dfbce63a89 84 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
elmot 1:d0dfbce63a89 85
elmot 1:d0dfbce63a89 86 /* Defines used for the bit position in the register and perform offsets */
elmot 1:d0dfbce63a89 87 #define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
elmot 1:d0dfbce63a89 88 /**
elmot 1:d0dfbce63a89 89 * @}
elmot 1:d0dfbce63a89 90 */
elmot 1:d0dfbce63a89 91
elmot 1:d0dfbce63a89 92 /* Private macros ------------------------------------------------------------*/
elmot 1:d0dfbce63a89 93 #if defined(USE_FULL_LL_DRIVER)
elmot 1:d0dfbce63a89 94 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
elmot 1:d0dfbce63a89 95 * @{
elmot 1:d0dfbce63a89 96 */
elmot 1:d0dfbce63a89 97 /**
elmot 1:d0dfbce63a89 98 * @}
elmot 1:d0dfbce63a89 99 */
elmot 1:d0dfbce63a89 100 #endif /*USE_FULL_LL_DRIVER*/
elmot 1:d0dfbce63a89 101
elmot 1:d0dfbce63a89 102 /* Exported types ------------------------------------------------------------*/
elmot 1:d0dfbce63a89 103 #if defined(USE_FULL_LL_DRIVER)
elmot 1:d0dfbce63a89 104 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
elmot 1:d0dfbce63a89 105 * @{
elmot 1:d0dfbce63a89 106 */
elmot 1:d0dfbce63a89 107 typedef struct
elmot 1:d0dfbce63a89 108 {
elmot 1:d0dfbce63a89 109 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
elmot 1:d0dfbce63a89 110 or as Source base address in case of memory to memory transfer direction.
elmot 1:d0dfbce63a89 111
elmot 1:d0dfbce63a89 112 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
elmot 1:d0dfbce63a89 113
elmot 1:d0dfbce63a89 114 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
elmot 1:d0dfbce63a89 115 or as Destination base address in case of memory to memory transfer direction.
elmot 1:d0dfbce63a89 116
elmot 1:d0dfbce63a89 117 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
elmot 1:d0dfbce63a89 118
elmot 1:d0dfbce63a89 119 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
elmot 1:d0dfbce63a89 120 from memory to memory or from peripheral to memory.
elmot 1:d0dfbce63a89 121 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
elmot 1:d0dfbce63a89 122
elmot 1:d0dfbce63a89 123 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
elmot 1:d0dfbce63a89 124
elmot 1:d0dfbce63a89 125 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
elmot 1:d0dfbce63a89 126 This parameter can be a value of @ref DMA_LL_EC_MODE
elmot 1:d0dfbce63a89 127 @note: The circular buffer mode cannot be used if the memory to memory
elmot 1:d0dfbce63a89 128 data transfer direction is configured on the selected Channel
elmot 1:d0dfbce63a89 129
elmot 1:d0dfbce63a89 130 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
elmot 1:d0dfbce63a89 131
elmot 1:d0dfbce63a89 132 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
elmot 1:d0dfbce63a89 133 is incremented or not.
elmot 1:d0dfbce63a89 134 This parameter can be a value of @ref DMA_LL_EC_PERIPH
elmot 1:d0dfbce63a89 135
elmot 1:d0dfbce63a89 136 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
elmot 1:d0dfbce63a89 137
elmot 1:d0dfbce63a89 138 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
elmot 1:d0dfbce63a89 139 is incremented or not.
elmot 1:d0dfbce63a89 140 This parameter can be a value of @ref DMA_LL_EC_MEMORY
elmot 1:d0dfbce63a89 141
elmot 1:d0dfbce63a89 142 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
elmot 1:d0dfbce63a89 143
elmot 1:d0dfbce63a89 144 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
elmot 1:d0dfbce63a89 145 in case of memory to memory transfer direction.
elmot 1:d0dfbce63a89 146 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
elmot 1:d0dfbce63a89 147
elmot 1:d0dfbce63a89 148 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
elmot 1:d0dfbce63a89 149
elmot 1:d0dfbce63a89 150 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
elmot 1:d0dfbce63a89 151 in case of memory to memory transfer direction.
elmot 1:d0dfbce63a89 152 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
elmot 1:d0dfbce63a89 153
elmot 1:d0dfbce63a89 154 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
elmot 1:d0dfbce63a89 155
elmot 1:d0dfbce63a89 156 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
elmot 1:d0dfbce63a89 157 The data unit is equal to the source buffer configuration set in PeripheralSize
elmot 1:d0dfbce63a89 158 or MemorySize parameters depending in the transfer direction.
elmot 1:d0dfbce63a89 159 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
elmot 1:d0dfbce63a89 160
elmot 1:d0dfbce63a89 161 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
elmot 1:d0dfbce63a89 162
elmot 1:d0dfbce63a89 163 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
elmot 1:d0dfbce63a89 164 This parameter can be a value of @ref DMA_LL_EC_REQUEST
elmot 1:d0dfbce63a89 165
elmot 1:d0dfbce63a89 166 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
elmot 1:d0dfbce63a89 167
elmot 1:d0dfbce63a89 168 uint32_t Priority; /*!< Specifies the channel priority level.
elmot 1:d0dfbce63a89 169 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
elmot 1:d0dfbce63a89 170
elmot 1:d0dfbce63a89 171 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
elmot 1:d0dfbce63a89 172
elmot 1:d0dfbce63a89 173 } LL_DMA_InitTypeDef;
elmot 1:d0dfbce63a89 174 /**
elmot 1:d0dfbce63a89 175 * @}
elmot 1:d0dfbce63a89 176 */
elmot 1:d0dfbce63a89 177 #endif /*USE_FULL_LL_DRIVER*/
elmot 1:d0dfbce63a89 178
elmot 1:d0dfbce63a89 179 /* Exported constants --------------------------------------------------------*/
elmot 1:d0dfbce63a89 180 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
elmot 1:d0dfbce63a89 181 * @{
elmot 1:d0dfbce63a89 182 */
elmot 1:d0dfbce63a89 183 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
elmot 1:d0dfbce63a89 184 * @brief Flags defines which can be used with LL_DMA_WriteReg function
elmot 1:d0dfbce63a89 185 * @{
elmot 1:d0dfbce63a89 186 */
elmot 1:d0dfbce63a89 187 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
elmot 1:d0dfbce63a89 188 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
elmot 1:d0dfbce63a89 189 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
elmot 1:d0dfbce63a89 190 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
elmot 1:d0dfbce63a89 191 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
elmot 1:d0dfbce63a89 192 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
elmot 1:d0dfbce63a89 193 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
elmot 1:d0dfbce63a89 194 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
elmot 1:d0dfbce63a89 195 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
elmot 1:d0dfbce63a89 196 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
elmot 1:d0dfbce63a89 197 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
elmot 1:d0dfbce63a89 198 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
elmot 1:d0dfbce63a89 199 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
elmot 1:d0dfbce63a89 200 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
elmot 1:d0dfbce63a89 201 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
elmot 1:d0dfbce63a89 202 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
elmot 1:d0dfbce63a89 203 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
elmot 1:d0dfbce63a89 204 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
elmot 1:d0dfbce63a89 205 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
elmot 1:d0dfbce63a89 206 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
elmot 1:d0dfbce63a89 207 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
elmot 1:d0dfbce63a89 208 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
elmot 1:d0dfbce63a89 209 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
elmot 1:d0dfbce63a89 210 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
elmot 1:d0dfbce63a89 211 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
elmot 1:d0dfbce63a89 212 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
elmot 1:d0dfbce63a89 213 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
elmot 1:d0dfbce63a89 214 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
elmot 1:d0dfbce63a89 215 /**
elmot 1:d0dfbce63a89 216 * @}
elmot 1:d0dfbce63a89 217 */
elmot 1:d0dfbce63a89 218
elmot 1:d0dfbce63a89 219 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
elmot 1:d0dfbce63a89 220 * @brief Flags defines which can be used with LL_DMA_ReadReg function
elmot 1:d0dfbce63a89 221 * @{
elmot 1:d0dfbce63a89 222 */
elmot 1:d0dfbce63a89 223 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
elmot 1:d0dfbce63a89 224 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
elmot 1:d0dfbce63a89 225 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
elmot 1:d0dfbce63a89 226 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
elmot 1:d0dfbce63a89 227 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
elmot 1:d0dfbce63a89 228 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
elmot 1:d0dfbce63a89 229 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
elmot 1:d0dfbce63a89 230 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
elmot 1:d0dfbce63a89 231 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
elmot 1:d0dfbce63a89 232 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
elmot 1:d0dfbce63a89 233 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
elmot 1:d0dfbce63a89 234 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
elmot 1:d0dfbce63a89 235 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
elmot 1:d0dfbce63a89 236 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
elmot 1:d0dfbce63a89 237 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
elmot 1:d0dfbce63a89 238 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
elmot 1:d0dfbce63a89 239 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
elmot 1:d0dfbce63a89 240 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
elmot 1:d0dfbce63a89 241 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
elmot 1:d0dfbce63a89 242 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
elmot 1:d0dfbce63a89 243 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
elmot 1:d0dfbce63a89 244 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
elmot 1:d0dfbce63a89 245 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
elmot 1:d0dfbce63a89 246 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
elmot 1:d0dfbce63a89 247 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
elmot 1:d0dfbce63a89 248 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
elmot 1:d0dfbce63a89 249 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
elmot 1:d0dfbce63a89 250 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
elmot 1:d0dfbce63a89 251 /**
elmot 1:d0dfbce63a89 252 * @}
elmot 1:d0dfbce63a89 253 */
elmot 1:d0dfbce63a89 254
elmot 1:d0dfbce63a89 255 /** @defgroup DMA_LL_EC_IT IT Defines
elmot 1:d0dfbce63a89 256 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
elmot 1:d0dfbce63a89 257 * @{
elmot 1:d0dfbce63a89 258 */
elmot 1:d0dfbce63a89 259 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
elmot 1:d0dfbce63a89 260 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
elmot 1:d0dfbce63a89 261 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
elmot 1:d0dfbce63a89 262 /**
elmot 1:d0dfbce63a89 263 * @}
elmot 1:d0dfbce63a89 264 */
elmot 1:d0dfbce63a89 265
elmot 1:d0dfbce63a89 266 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
elmot 1:d0dfbce63a89 267 * @{
elmot 1:d0dfbce63a89 268 */
elmot 1:d0dfbce63a89 269 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /*!< DMA Channel 1 */
elmot 1:d0dfbce63a89 270 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /*!< DMA Channel 2 */
elmot 1:d0dfbce63a89 271 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /*!< DMA Channel 3 */
elmot 1:d0dfbce63a89 272 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /*!< DMA Channel 4 */
elmot 1:d0dfbce63a89 273 #define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /*!< DMA Channel 5 */
elmot 1:d0dfbce63a89 274 #define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /*!< DMA Channel 6 */
elmot 1:d0dfbce63a89 275 #define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /*!< DMA Channel 7 */
elmot 1:d0dfbce63a89 276 #if defined(USE_FULL_LL_DRIVER)
elmot 1:d0dfbce63a89 277 #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
elmot 1:d0dfbce63a89 278 #endif /*USE_FULL_LL_DRIVER*/
elmot 1:d0dfbce63a89 279 /**
elmot 1:d0dfbce63a89 280 * @}
elmot 1:d0dfbce63a89 281 */
elmot 1:d0dfbce63a89 282
elmot 1:d0dfbce63a89 283 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
elmot 1:d0dfbce63a89 284 * @{
elmot 1:d0dfbce63a89 285 */
elmot 1:d0dfbce63a89 286 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
elmot 1:d0dfbce63a89 287 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
elmot 1:d0dfbce63a89 288 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
elmot 1:d0dfbce63a89 289 /**
elmot 1:d0dfbce63a89 290 * @}
elmot 1:d0dfbce63a89 291 */
elmot 1:d0dfbce63a89 292
elmot 1:d0dfbce63a89 293 /** @defgroup DMA_LL_EC_MODE Transfer mode
elmot 1:d0dfbce63a89 294 * @{
elmot 1:d0dfbce63a89 295 */
elmot 1:d0dfbce63a89 296 #define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */
elmot 1:d0dfbce63a89 297 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
elmot 1:d0dfbce63a89 298 /**
elmot 1:d0dfbce63a89 299 * @}
elmot 1:d0dfbce63a89 300 */
elmot 1:d0dfbce63a89 301
elmot 1:d0dfbce63a89 302 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
elmot 1:d0dfbce63a89 303 * @{
elmot 1:d0dfbce63a89 304 */
elmot 1:d0dfbce63a89 305 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
elmot 1:d0dfbce63a89 306 #define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */
elmot 1:d0dfbce63a89 307 /**
elmot 1:d0dfbce63a89 308 * @}
elmot 1:d0dfbce63a89 309 */
elmot 1:d0dfbce63a89 310
elmot 1:d0dfbce63a89 311 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
elmot 1:d0dfbce63a89 312 * @{
elmot 1:d0dfbce63a89 313 */
elmot 1:d0dfbce63a89 314 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
elmot 1:d0dfbce63a89 315 #define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */
elmot 1:d0dfbce63a89 316 /**
elmot 1:d0dfbce63a89 317 * @}
elmot 1:d0dfbce63a89 318 */
elmot 1:d0dfbce63a89 319
elmot 1:d0dfbce63a89 320 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
elmot 1:d0dfbce63a89 321 * @{
elmot 1:d0dfbce63a89 322 */
elmot 1:d0dfbce63a89 323 #define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */
elmot 1:d0dfbce63a89 324 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
elmot 1:d0dfbce63a89 325 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
elmot 1:d0dfbce63a89 326 /**
elmot 1:d0dfbce63a89 327 * @}
elmot 1:d0dfbce63a89 328 */
elmot 1:d0dfbce63a89 329
elmot 1:d0dfbce63a89 330 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
elmot 1:d0dfbce63a89 331 * @{
elmot 1:d0dfbce63a89 332 */
elmot 1:d0dfbce63a89 333 #define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */
elmot 1:d0dfbce63a89 334 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
elmot 1:d0dfbce63a89 335 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
elmot 1:d0dfbce63a89 336 /**
elmot 1:d0dfbce63a89 337 * @}
elmot 1:d0dfbce63a89 338 */
elmot 1:d0dfbce63a89 339
elmot 1:d0dfbce63a89 340 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
elmot 1:d0dfbce63a89 341 * @{
elmot 1:d0dfbce63a89 342 */
elmot 1:d0dfbce63a89 343 #define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */
elmot 1:d0dfbce63a89 344 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
elmot 1:d0dfbce63a89 345 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
elmot 1:d0dfbce63a89 346 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
elmot 1:d0dfbce63a89 347 /**
elmot 1:d0dfbce63a89 348 * @}
elmot 1:d0dfbce63a89 349 */
elmot 1:d0dfbce63a89 350
elmot 1:d0dfbce63a89 351 /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
elmot 1:d0dfbce63a89 352 * @{
elmot 1:d0dfbce63a89 353 */
elmot 1:d0dfbce63a89 354 #define LL_DMA_REQUEST_0 ((uint32_t)0x00000000U) /*!< DMA peripheral request 0 */
elmot 1:d0dfbce63a89 355 #define LL_DMA_REQUEST_1 ((uint32_t)0x00000001U) /*!< DMA peripheral request 1 */
elmot 1:d0dfbce63a89 356 #define LL_DMA_REQUEST_2 ((uint32_t)0x00000002U) /*!< DMA peripheral request 2 */
elmot 1:d0dfbce63a89 357 #define LL_DMA_REQUEST_3 ((uint32_t)0x00000003U) /*!< DMA peripheral request 3 */
elmot 1:d0dfbce63a89 358 #define LL_DMA_REQUEST_4 ((uint32_t)0x00000004U) /*!< DMA peripheral request 4 */
elmot 1:d0dfbce63a89 359 #define LL_DMA_REQUEST_5 ((uint32_t)0x00000005U) /*!< DMA peripheral request 5 */
elmot 1:d0dfbce63a89 360 #define LL_DMA_REQUEST_6 ((uint32_t)0x00000006U) /*!< DMA peripheral request 6 */
elmot 1:d0dfbce63a89 361 #define LL_DMA_REQUEST_7 ((uint32_t)0x00000007U) /*!< DMA peripheral request 7 */
elmot 1:d0dfbce63a89 362 /**
elmot 1:d0dfbce63a89 363 * @}
elmot 1:d0dfbce63a89 364 */
elmot 1:d0dfbce63a89 365
elmot 1:d0dfbce63a89 366 /**
elmot 1:d0dfbce63a89 367 * @}
elmot 1:d0dfbce63a89 368 */
elmot 1:d0dfbce63a89 369
elmot 1:d0dfbce63a89 370 /* Exported macro ------------------------------------------------------------*/
elmot 1:d0dfbce63a89 371 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
elmot 1:d0dfbce63a89 372 * @{
elmot 1:d0dfbce63a89 373 */
elmot 1:d0dfbce63a89 374
elmot 1:d0dfbce63a89 375 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
elmot 1:d0dfbce63a89 376 * @{
elmot 1:d0dfbce63a89 377 */
elmot 1:d0dfbce63a89 378 /**
elmot 1:d0dfbce63a89 379 * @brief Write a value in DMA register
elmot 1:d0dfbce63a89 380 * @param __INSTANCE__ DMA Instance
elmot 1:d0dfbce63a89 381 * @param __REG__ Register to be written
elmot 1:d0dfbce63a89 382 * @param __VALUE__ Value to be written in the register
elmot 1:d0dfbce63a89 383 * @retval None
elmot 1:d0dfbce63a89 384 */
elmot 1:d0dfbce63a89 385 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
elmot 1:d0dfbce63a89 386
elmot 1:d0dfbce63a89 387 /**
elmot 1:d0dfbce63a89 388 * @brief Read a value in DMA register
elmot 1:d0dfbce63a89 389 * @param __INSTANCE__ DMA Instance
elmot 1:d0dfbce63a89 390 * @param __REG__ Register to be read
elmot 1:d0dfbce63a89 391 * @retval Register value
elmot 1:d0dfbce63a89 392 */
elmot 1:d0dfbce63a89 393 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
elmot 1:d0dfbce63a89 394 /**
elmot 1:d0dfbce63a89 395 * @}
elmot 1:d0dfbce63a89 396 */
elmot 1:d0dfbce63a89 397
elmot 1:d0dfbce63a89 398 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
elmot 1:d0dfbce63a89 399 * @{
elmot 1:d0dfbce63a89 400 */
elmot 1:d0dfbce63a89 401 /**
elmot 1:d0dfbce63a89 402 * @brief Convert DMAx_Channely into DMAx
elmot 1:d0dfbce63a89 403 * @param __CHANNEL_INSTANCE__ DMAx_Channely
elmot 1:d0dfbce63a89 404 * @retval DMAx
elmot 1:d0dfbce63a89 405 */
elmot 1:d0dfbce63a89 406 #if defined(DMA2)
elmot 1:d0dfbce63a89 407 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
elmot 1:d0dfbce63a89 408 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
elmot 1:d0dfbce63a89 409 #else
elmot 1:d0dfbce63a89 410 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
elmot 1:d0dfbce63a89 411 #endif
elmot 1:d0dfbce63a89 412
elmot 1:d0dfbce63a89 413 /**
elmot 1:d0dfbce63a89 414 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
elmot 1:d0dfbce63a89 415 * @param __CHANNEL_INSTANCE__ DMAx_Channely
elmot 1:d0dfbce63a89 416 * @retval LL_DMA_CHANNEL_y
elmot 1:d0dfbce63a89 417 */
elmot 1:d0dfbce63a89 418 #if defined (DMA2)
elmot 1:d0dfbce63a89 419 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
elmot 1:d0dfbce63a89 420 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
elmot 1:d0dfbce63a89 421 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
elmot 1:d0dfbce63a89 422 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
elmot 1:d0dfbce63a89 423 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
elmot 1:d0dfbce63a89 424 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
elmot 1:d0dfbce63a89 425 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
elmot 1:d0dfbce63a89 426 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
elmot 1:d0dfbce63a89 427 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
elmot 1:d0dfbce63a89 428 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
elmot 1:d0dfbce63a89 429 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
elmot 1:d0dfbce63a89 430 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
elmot 1:d0dfbce63a89 431 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
elmot 1:d0dfbce63a89 432 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
elmot 1:d0dfbce63a89 433 LL_DMA_CHANNEL_7)
elmot 1:d0dfbce63a89 434 #else
elmot 1:d0dfbce63a89 435 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
elmot 1:d0dfbce63a89 436 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
elmot 1:d0dfbce63a89 437 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
elmot 1:d0dfbce63a89 438 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
elmot 1:d0dfbce63a89 439 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
elmot 1:d0dfbce63a89 440 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
elmot 1:d0dfbce63a89 441 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
elmot 1:d0dfbce63a89 442 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
elmot 1:d0dfbce63a89 443 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
elmot 1:d0dfbce63a89 444 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
elmot 1:d0dfbce63a89 445 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
elmot 1:d0dfbce63a89 446 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
elmot 1:d0dfbce63a89 447 LL_DMA_CHANNEL_7)
elmot 1:d0dfbce63a89 448 #endif
elmot 1:d0dfbce63a89 449 #else
elmot 1:d0dfbce63a89 450 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
elmot 1:d0dfbce63a89 451 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
elmot 1:d0dfbce63a89 452 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
elmot 1:d0dfbce63a89 453 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
elmot 1:d0dfbce63a89 454 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
elmot 1:d0dfbce63a89 455 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
elmot 1:d0dfbce63a89 456 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
elmot 1:d0dfbce63a89 457 LL_DMA_CHANNEL_7)
elmot 1:d0dfbce63a89 458 #endif
elmot 1:d0dfbce63a89 459
elmot 1:d0dfbce63a89 460 /**
elmot 1:d0dfbce63a89 461 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
elmot 1:d0dfbce63a89 462 * @param __DMA_INSTANCE__ DMAx
elmot 1:d0dfbce63a89 463 * @param __CHANNEL__ LL_DMA_CHANNEL_y
elmot 1:d0dfbce63a89 464 * @retval DMAx_Channely
elmot 1:d0dfbce63a89 465 */
elmot 1:d0dfbce63a89 466 #if defined (DMA2)
elmot 1:d0dfbce63a89 467 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
elmot 1:d0dfbce63a89 468 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
elmot 1:d0dfbce63a89 469 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
elmot 1:d0dfbce63a89 470 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
elmot 1:d0dfbce63a89 471 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
elmot 1:d0dfbce63a89 472 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
elmot 1:d0dfbce63a89 473 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
elmot 1:d0dfbce63a89 474 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
elmot 1:d0dfbce63a89 475 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
elmot 1:d0dfbce63a89 476 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
elmot 1:d0dfbce63a89 477 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
elmot 1:d0dfbce63a89 478 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
elmot 1:d0dfbce63a89 479 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
elmot 1:d0dfbce63a89 480 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
elmot 1:d0dfbce63a89 481 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
elmot 1:d0dfbce63a89 482 DMA2_Channel7)
elmot 1:d0dfbce63a89 483 #else
elmot 1:d0dfbce63a89 484 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
elmot 1:d0dfbce63a89 485 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
elmot 1:d0dfbce63a89 486 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
elmot 1:d0dfbce63a89 487 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
elmot 1:d0dfbce63a89 488 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
elmot 1:d0dfbce63a89 489 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
elmot 1:d0dfbce63a89 490 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
elmot 1:d0dfbce63a89 491 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
elmot 1:d0dfbce63a89 492 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
elmot 1:d0dfbce63a89 493 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
elmot 1:d0dfbce63a89 494 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
elmot 1:d0dfbce63a89 495 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
elmot 1:d0dfbce63a89 496 DMA1_Channel7)
elmot 1:d0dfbce63a89 497 #endif
elmot 1:d0dfbce63a89 498 #else
elmot 1:d0dfbce63a89 499 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
elmot 1:d0dfbce63a89 500 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
elmot 1:d0dfbce63a89 501 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
elmot 1:d0dfbce63a89 502 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
elmot 1:d0dfbce63a89 503 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
elmot 1:d0dfbce63a89 504 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
elmot 1:d0dfbce63a89 505 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
elmot 1:d0dfbce63a89 506 DMA1_Channel7)
elmot 1:d0dfbce63a89 507 #endif
elmot 1:d0dfbce63a89 508
elmot 1:d0dfbce63a89 509 /**
elmot 1:d0dfbce63a89 510 * @}
elmot 1:d0dfbce63a89 511 */
elmot 1:d0dfbce63a89 512
elmot 1:d0dfbce63a89 513 /**
elmot 1:d0dfbce63a89 514 * @}
elmot 1:d0dfbce63a89 515 */
elmot 1:d0dfbce63a89 516
elmot 1:d0dfbce63a89 517 /* Exported functions --------------------------------------------------------*/
elmot 1:d0dfbce63a89 518 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
elmot 1:d0dfbce63a89 519 * @{
elmot 1:d0dfbce63a89 520 */
elmot 1:d0dfbce63a89 521
elmot 1:d0dfbce63a89 522 /** @defgroup DMA_LL_EF_Configuration Configuration
elmot 1:d0dfbce63a89 523 * @{
elmot 1:d0dfbce63a89 524 */
elmot 1:d0dfbce63a89 525 /**
elmot 1:d0dfbce63a89 526 * @brief Enable DMA channel.
elmot 1:d0dfbce63a89 527 * @rmtoll CCR EN LL_DMA_EnableChannel
elmot 1:d0dfbce63a89 528 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 529 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 530 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 531 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 532 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 533 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 534 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 535 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 536 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 537 * @retval None
elmot 1:d0dfbce63a89 538 */
elmot 1:d0dfbce63a89 539 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 540 {
elmot 1:d0dfbce63a89 541 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
elmot 1:d0dfbce63a89 542 }
elmot 1:d0dfbce63a89 543
elmot 1:d0dfbce63a89 544 /**
elmot 1:d0dfbce63a89 545 * @brief Disable DMA channel.
elmot 1:d0dfbce63a89 546 * @rmtoll CCR EN LL_DMA_DisableChannel
elmot 1:d0dfbce63a89 547 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 548 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 549 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 550 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 551 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 552 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 553 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 554 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 555 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 556 * @retval None
elmot 1:d0dfbce63a89 557 */
elmot 1:d0dfbce63a89 558 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 559 {
elmot 1:d0dfbce63a89 560 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
elmot 1:d0dfbce63a89 561 }
elmot 1:d0dfbce63a89 562
elmot 1:d0dfbce63a89 563 /**
elmot 1:d0dfbce63a89 564 * @brief Check if DMA channel is enabled or disabled.
elmot 1:d0dfbce63a89 565 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
elmot 1:d0dfbce63a89 566 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 567 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 568 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 569 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 570 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 571 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 572 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 573 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 574 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 575 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 576 */
elmot 1:d0dfbce63a89 577 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 578 {
elmot 1:d0dfbce63a89 579 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
elmot 1:d0dfbce63a89 580 DMA_CCR_EN) == (DMA_CCR_EN));
elmot 1:d0dfbce63a89 581 }
elmot 1:d0dfbce63a89 582
elmot 1:d0dfbce63a89 583 /**
elmot 1:d0dfbce63a89 584 * @brief Configure all parameters link to DMA transfer.
elmot 1:d0dfbce63a89 585 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
elmot 1:d0dfbce63a89 586 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
elmot 1:d0dfbce63a89 587 * CCR CIRC LL_DMA_ConfigTransfer\n
elmot 1:d0dfbce63a89 588 * CCR PINC LL_DMA_ConfigTransfer\n
elmot 1:d0dfbce63a89 589 * CCR MINC LL_DMA_ConfigTransfer\n
elmot 1:d0dfbce63a89 590 * CCR PSIZE LL_DMA_ConfigTransfer\n
elmot 1:d0dfbce63a89 591 * CCR MSIZE LL_DMA_ConfigTransfer\n
elmot 1:d0dfbce63a89 592 * CCR PL LL_DMA_ConfigTransfer
elmot 1:d0dfbce63a89 593 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 594 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 595 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 596 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 597 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 598 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 599 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 600 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 601 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 602 * @param Configuration This parameter must be a combination of all the following values:
elmot 1:d0dfbce63a89 603 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
elmot 1:d0dfbce63a89 604 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
elmot 1:d0dfbce63a89 605 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
elmot 1:d0dfbce63a89 606 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
elmot 1:d0dfbce63a89 607 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
elmot 1:d0dfbce63a89 608 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
elmot 1:d0dfbce63a89 609 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
elmot 1:d0dfbce63a89 610 * @retval None
elmot 1:d0dfbce63a89 611 */
elmot 1:d0dfbce63a89 612 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
elmot 1:d0dfbce63a89 613 {
elmot 1:d0dfbce63a89 614 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
elmot 1:d0dfbce63a89 615 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
elmot 1:d0dfbce63a89 616 Configuration);
elmot 1:d0dfbce63a89 617 }
elmot 1:d0dfbce63a89 618
elmot 1:d0dfbce63a89 619 /**
elmot 1:d0dfbce63a89 620 * @brief Set Data transfer direction (read from peripheral or from memory).
elmot 1:d0dfbce63a89 621 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
elmot 1:d0dfbce63a89 622 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
elmot 1:d0dfbce63a89 623 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 624 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 625 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 626 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 627 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 628 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 629 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 630 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 631 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 632 * @param Direction This parameter can be one of the following values:
elmot 1:d0dfbce63a89 633 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
elmot 1:d0dfbce63a89 634 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
elmot 1:d0dfbce63a89 635 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
elmot 1:d0dfbce63a89 636 * @retval None
elmot 1:d0dfbce63a89 637 */
elmot 1:d0dfbce63a89 638 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
elmot 1:d0dfbce63a89 639 {
elmot 1:d0dfbce63a89 640 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
elmot 1:d0dfbce63a89 641 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
elmot 1:d0dfbce63a89 642 }
elmot 1:d0dfbce63a89 643
elmot 1:d0dfbce63a89 644 /**
elmot 1:d0dfbce63a89 645 * @brief Get Data transfer direction (read from peripheral or from memory).
elmot 1:d0dfbce63a89 646 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
elmot 1:d0dfbce63a89 647 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
elmot 1:d0dfbce63a89 648 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 649 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 650 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 651 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 652 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 653 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 654 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 655 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 656 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 657 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 658 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
elmot 1:d0dfbce63a89 659 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
elmot 1:d0dfbce63a89 660 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
elmot 1:d0dfbce63a89 661 */
elmot 1:d0dfbce63a89 662 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 663 {
elmot 1:d0dfbce63a89 664 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
elmot 1:d0dfbce63a89 665 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
elmot 1:d0dfbce63a89 666 }
elmot 1:d0dfbce63a89 667
elmot 1:d0dfbce63a89 668 /**
elmot 1:d0dfbce63a89 669 * @brief Set DMA mode circular or normal.
elmot 1:d0dfbce63a89 670 * @note The circular buffer mode cannot be used if the memory-to-memory
elmot 1:d0dfbce63a89 671 * data transfer is configured on the selected Channel.
elmot 1:d0dfbce63a89 672 * @rmtoll CCR CIRC LL_DMA_SetMode
elmot 1:d0dfbce63a89 673 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 674 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 675 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 676 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 677 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 678 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 679 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 680 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 681 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 682 * @param Mode This parameter can be one of the following values:
elmot 1:d0dfbce63a89 683 * @arg @ref LL_DMA_MODE_NORMAL
elmot 1:d0dfbce63a89 684 * @arg @ref LL_DMA_MODE_CIRCULAR
elmot 1:d0dfbce63a89 685 * @retval None
elmot 1:d0dfbce63a89 686 */
elmot 1:d0dfbce63a89 687 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
elmot 1:d0dfbce63a89 688 {
elmot 1:d0dfbce63a89 689 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
elmot 1:d0dfbce63a89 690 Mode);
elmot 1:d0dfbce63a89 691 }
elmot 1:d0dfbce63a89 692
elmot 1:d0dfbce63a89 693 /**
elmot 1:d0dfbce63a89 694 * @brief Get DMA mode circular or normal.
elmot 1:d0dfbce63a89 695 * @rmtoll CCR CIRC LL_DMA_GetMode
elmot 1:d0dfbce63a89 696 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 697 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 698 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 699 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 700 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 701 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 702 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 703 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 704 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 705 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 706 * @arg @ref LL_DMA_MODE_NORMAL
elmot 1:d0dfbce63a89 707 * @arg @ref LL_DMA_MODE_CIRCULAR
elmot 1:d0dfbce63a89 708 */
elmot 1:d0dfbce63a89 709 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 710 {
elmot 1:d0dfbce63a89 711 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
elmot 1:d0dfbce63a89 712 DMA_CCR_CIRC));
elmot 1:d0dfbce63a89 713 }
elmot 1:d0dfbce63a89 714
elmot 1:d0dfbce63a89 715 /**
elmot 1:d0dfbce63a89 716 * @brief Set Peripheral increment mode.
elmot 1:d0dfbce63a89 717 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
elmot 1:d0dfbce63a89 718 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 719 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 720 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 721 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 722 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 723 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 724 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 725 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 726 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 727 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
elmot 1:d0dfbce63a89 728 * @arg @ref LL_DMA_PERIPH_INCREMENT
elmot 1:d0dfbce63a89 729 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
elmot 1:d0dfbce63a89 730 * @retval None
elmot 1:d0dfbce63a89 731 */
elmot 1:d0dfbce63a89 732 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
elmot 1:d0dfbce63a89 733 {
elmot 1:d0dfbce63a89 734 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
elmot 1:d0dfbce63a89 735 PeriphOrM2MSrcIncMode);
elmot 1:d0dfbce63a89 736 }
elmot 1:d0dfbce63a89 737
elmot 1:d0dfbce63a89 738 /**
elmot 1:d0dfbce63a89 739 * @brief Get Peripheral increment mode.
elmot 1:d0dfbce63a89 740 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
elmot 1:d0dfbce63a89 741 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 742 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 743 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 744 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 745 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 746 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 747 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 748 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 749 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 750 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 751 * @arg @ref LL_DMA_PERIPH_INCREMENT
elmot 1:d0dfbce63a89 752 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
elmot 1:d0dfbce63a89 753 */
elmot 1:d0dfbce63a89 754 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 755 {
elmot 1:d0dfbce63a89 756 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
elmot 1:d0dfbce63a89 757 DMA_CCR_PINC));
elmot 1:d0dfbce63a89 758 }
elmot 1:d0dfbce63a89 759
elmot 1:d0dfbce63a89 760 /**
elmot 1:d0dfbce63a89 761 * @brief Set Memory increment mode.
elmot 1:d0dfbce63a89 762 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
elmot 1:d0dfbce63a89 763 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 764 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 765 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 766 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 767 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 768 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 769 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 770 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 771 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 772 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
elmot 1:d0dfbce63a89 773 * @arg @ref LL_DMA_MEMORY_INCREMENT
elmot 1:d0dfbce63a89 774 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
elmot 1:d0dfbce63a89 775 * @retval None
elmot 1:d0dfbce63a89 776 */
elmot 1:d0dfbce63a89 777 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
elmot 1:d0dfbce63a89 778 {
elmot 1:d0dfbce63a89 779 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
elmot 1:d0dfbce63a89 780 MemoryOrM2MDstIncMode);
elmot 1:d0dfbce63a89 781 }
elmot 1:d0dfbce63a89 782
elmot 1:d0dfbce63a89 783 /**
elmot 1:d0dfbce63a89 784 * @brief Get Memory increment mode.
elmot 1:d0dfbce63a89 785 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
elmot 1:d0dfbce63a89 786 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 787 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 788 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 789 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 790 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 791 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 792 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 793 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 794 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 795 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 796 * @arg @ref LL_DMA_MEMORY_INCREMENT
elmot 1:d0dfbce63a89 797 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
elmot 1:d0dfbce63a89 798 */
elmot 1:d0dfbce63a89 799 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 800 {
elmot 1:d0dfbce63a89 801 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
elmot 1:d0dfbce63a89 802 DMA_CCR_MINC));
elmot 1:d0dfbce63a89 803 }
elmot 1:d0dfbce63a89 804
elmot 1:d0dfbce63a89 805 /**
elmot 1:d0dfbce63a89 806 * @brief Set Peripheral size.
elmot 1:d0dfbce63a89 807 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
elmot 1:d0dfbce63a89 808 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 809 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 810 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 811 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 812 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 813 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 814 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 815 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 816 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 817 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
elmot 1:d0dfbce63a89 818 * @arg @ref LL_DMA_PDATAALIGN_BYTE
elmot 1:d0dfbce63a89 819 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
elmot 1:d0dfbce63a89 820 * @arg @ref LL_DMA_PDATAALIGN_WORD
elmot 1:d0dfbce63a89 821 * @retval None
elmot 1:d0dfbce63a89 822 */
elmot 1:d0dfbce63a89 823 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
elmot 1:d0dfbce63a89 824 {
elmot 1:d0dfbce63a89 825 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
elmot 1:d0dfbce63a89 826 PeriphOrM2MSrcDataSize);
elmot 1:d0dfbce63a89 827 }
elmot 1:d0dfbce63a89 828
elmot 1:d0dfbce63a89 829 /**
elmot 1:d0dfbce63a89 830 * @brief Get Peripheral size.
elmot 1:d0dfbce63a89 831 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
elmot 1:d0dfbce63a89 832 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 833 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 834 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 835 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 836 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 837 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 838 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 839 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 840 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 841 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 842 * @arg @ref LL_DMA_PDATAALIGN_BYTE
elmot 1:d0dfbce63a89 843 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
elmot 1:d0dfbce63a89 844 * @arg @ref LL_DMA_PDATAALIGN_WORD
elmot 1:d0dfbce63a89 845 */
elmot 1:d0dfbce63a89 846 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 847 {
elmot 1:d0dfbce63a89 848 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
elmot 1:d0dfbce63a89 849 DMA_CCR_PSIZE));
elmot 1:d0dfbce63a89 850 }
elmot 1:d0dfbce63a89 851
elmot 1:d0dfbce63a89 852 /**
elmot 1:d0dfbce63a89 853 * @brief Set Memory size.
elmot 1:d0dfbce63a89 854 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
elmot 1:d0dfbce63a89 855 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 856 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 857 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 858 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 859 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 860 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 861 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 862 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 863 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 864 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
elmot 1:d0dfbce63a89 865 * @arg @ref LL_DMA_MDATAALIGN_BYTE
elmot 1:d0dfbce63a89 866 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
elmot 1:d0dfbce63a89 867 * @arg @ref LL_DMA_MDATAALIGN_WORD
elmot 1:d0dfbce63a89 868 * @retval None
elmot 1:d0dfbce63a89 869 */
elmot 1:d0dfbce63a89 870 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
elmot 1:d0dfbce63a89 871 {
elmot 1:d0dfbce63a89 872 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
elmot 1:d0dfbce63a89 873 MemoryOrM2MDstDataSize);
elmot 1:d0dfbce63a89 874 }
elmot 1:d0dfbce63a89 875
elmot 1:d0dfbce63a89 876 /**
elmot 1:d0dfbce63a89 877 * @brief Get Memory size.
elmot 1:d0dfbce63a89 878 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
elmot 1:d0dfbce63a89 879 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 880 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 881 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 882 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 883 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 884 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 885 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 886 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 887 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 888 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 889 * @arg @ref LL_DMA_MDATAALIGN_BYTE
elmot 1:d0dfbce63a89 890 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
elmot 1:d0dfbce63a89 891 * @arg @ref LL_DMA_MDATAALIGN_WORD
elmot 1:d0dfbce63a89 892 */
elmot 1:d0dfbce63a89 893 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 894 {
elmot 1:d0dfbce63a89 895 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
elmot 1:d0dfbce63a89 896 DMA_CCR_MSIZE));
elmot 1:d0dfbce63a89 897 }
elmot 1:d0dfbce63a89 898
elmot 1:d0dfbce63a89 899 /**
elmot 1:d0dfbce63a89 900 * @brief Set Channel priority level.
elmot 1:d0dfbce63a89 901 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
elmot 1:d0dfbce63a89 902 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 903 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 904 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 905 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 906 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 907 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 908 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 909 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 910 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 911 * @param Priority This parameter can be one of the following values:
elmot 1:d0dfbce63a89 912 * @arg @ref LL_DMA_PRIORITY_LOW
elmot 1:d0dfbce63a89 913 * @arg @ref LL_DMA_PRIORITY_MEDIUM
elmot 1:d0dfbce63a89 914 * @arg @ref LL_DMA_PRIORITY_HIGH
elmot 1:d0dfbce63a89 915 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
elmot 1:d0dfbce63a89 916 * @retval None
elmot 1:d0dfbce63a89 917 */
elmot 1:d0dfbce63a89 918 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
elmot 1:d0dfbce63a89 919 {
elmot 1:d0dfbce63a89 920 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
elmot 1:d0dfbce63a89 921 Priority);
elmot 1:d0dfbce63a89 922 }
elmot 1:d0dfbce63a89 923
elmot 1:d0dfbce63a89 924 /**
elmot 1:d0dfbce63a89 925 * @brief Get Channel priority level.
elmot 1:d0dfbce63a89 926 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
elmot 1:d0dfbce63a89 927 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 928 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 929 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 930 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 931 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 932 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 933 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 934 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 935 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 936 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 937 * @arg @ref LL_DMA_PRIORITY_LOW
elmot 1:d0dfbce63a89 938 * @arg @ref LL_DMA_PRIORITY_MEDIUM
elmot 1:d0dfbce63a89 939 * @arg @ref LL_DMA_PRIORITY_HIGH
elmot 1:d0dfbce63a89 940 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
elmot 1:d0dfbce63a89 941 */
elmot 1:d0dfbce63a89 942 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 943 {
elmot 1:d0dfbce63a89 944 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
elmot 1:d0dfbce63a89 945 DMA_CCR_PL));
elmot 1:d0dfbce63a89 946 }
elmot 1:d0dfbce63a89 947
elmot 1:d0dfbce63a89 948 /**
elmot 1:d0dfbce63a89 949 * @brief Set Number of data to transfer.
elmot 1:d0dfbce63a89 950 * @note This action has no effect if
elmot 1:d0dfbce63a89 951 * channel is enabled.
elmot 1:d0dfbce63a89 952 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
elmot 1:d0dfbce63a89 953 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 954 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 955 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 956 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 957 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 958 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 959 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 960 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 961 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 962 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
elmot 1:d0dfbce63a89 963 * @retval None
elmot 1:d0dfbce63a89 964 */
elmot 1:d0dfbce63a89 965 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
elmot 1:d0dfbce63a89 966 {
elmot 1:d0dfbce63a89 967 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
elmot 1:d0dfbce63a89 968 DMA_CNDTR_NDT, NbData);
elmot 1:d0dfbce63a89 969 }
elmot 1:d0dfbce63a89 970
elmot 1:d0dfbce63a89 971 /**
elmot 1:d0dfbce63a89 972 * @brief Get Number of data to transfer.
elmot 1:d0dfbce63a89 973 * @note Once the channel is enabled, the return value indicate the
elmot 1:d0dfbce63a89 974 * remaining bytes to be transmitted.
elmot 1:d0dfbce63a89 975 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
elmot 1:d0dfbce63a89 976 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 977 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 978 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 979 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 980 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 981 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 982 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 983 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 984 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 985 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
elmot 1:d0dfbce63a89 986 */
elmot 1:d0dfbce63a89 987 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 988 {
elmot 1:d0dfbce63a89 989 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
elmot 1:d0dfbce63a89 990 DMA_CNDTR_NDT));
elmot 1:d0dfbce63a89 991 }
elmot 1:d0dfbce63a89 992
elmot 1:d0dfbce63a89 993 /**
elmot 1:d0dfbce63a89 994 * @brief Configure the Source and Destination addresses.
elmot 1:d0dfbce63a89 995 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
elmot 1:d0dfbce63a89 996 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
elmot 1:d0dfbce63a89 997 * CMAR MA LL_DMA_ConfigAddresses
elmot 1:d0dfbce63a89 998 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 999 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1000 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 1001 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 1002 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 1003 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 1004 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 1005 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 1006 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 1007 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
elmot 1:d0dfbce63a89 1008 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
elmot 1:d0dfbce63a89 1009 * @param Direction This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1010 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
elmot 1:d0dfbce63a89 1011 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
elmot 1:d0dfbce63a89 1012 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
elmot 1:d0dfbce63a89 1013 * @retval None
elmot 1:d0dfbce63a89 1014 */
elmot 1:d0dfbce63a89 1015 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
elmot 1:d0dfbce63a89 1016 uint32_t DstAddress, uint32_t Direction)
elmot 1:d0dfbce63a89 1017 {
elmot 1:d0dfbce63a89 1018 /* Direction Memory to Periph */
elmot 1:d0dfbce63a89 1019 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
elmot 1:d0dfbce63a89 1020 {
elmot 1:d0dfbce63a89 1021 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
elmot 1:d0dfbce63a89 1022 SrcAddress);
elmot 1:d0dfbce63a89 1023 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
elmot 1:d0dfbce63a89 1024 DstAddress);
elmot 1:d0dfbce63a89 1025 }
elmot 1:d0dfbce63a89 1026 /* Direction Periph to Memory and Memory to Memory */
elmot 1:d0dfbce63a89 1027 else
elmot 1:d0dfbce63a89 1028 {
elmot 1:d0dfbce63a89 1029 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
elmot 1:d0dfbce63a89 1030 SrcAddress);
elmot 1:d0dfbce63a89 1031 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
elmot 1:d0dfbce63a89 1032 DstAddress);
elmot 1:d0dfbce63a89 1033 }
elmot 1:d0dfbce63a89 1034 }
elmot 1:d0dfbce63a89 1035
elmot 1:d0dfbce63a89 1036 /**
elmot 1:d0dfbce63a89 1037 * @brief Set the Memory address.
elmot 1:d0dfbce63a89 1038 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
elmot 1:d0dfbce63a89 1039 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
elmot 1:d0dfbce63a89 1040 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1041 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1042 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 1043 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 1044 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 1045 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 1046 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 1047 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 1048 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 1049 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
elmot 1:d0dfbce63a89 1050 * @retval None
elmot 1:d0dfbce63a89 1051 */
elmot 1:d0dfbce63a89 1052 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
elmot 1:d0dfbce63a89 1053 {
elmot 1:d0dfbce63a89 1054 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
elmot 1:d0dfbce63a89 1055 MemoryAddress);
elmot 1:d0dfbce63a89 1056 }
elmot 1:d0dfbce63a89 1057
elmot 1:d0dfbce63a89 1058 /**
elmot 1:d0dfbce63a89 1059 * @brief Set the Peripheral address.
elmot 1:d0dfbce63a89 1060 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
elmot 1:d0dfbce63a89 1061 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
elmot 1:d0dfbce63a89 1062 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1063 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1064 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 1065 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 1066 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 1067 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 1068 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 1069 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 1070 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 1071 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
elmot 1:d0dfbce63a89 1072 * @retval None
elmot 1:d0dfbce63a89 1073 */
elmot 1:d0dfbce63a89 1074 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
elmot 1:d0dfbce63a89 1075 {
elmot 1:d0dfbce63a89 1076 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
elmot 1:d0dfbce63a89 1077 PeriphAddress);
elmot 1:d0dfbce63a89 1078 }
elmot 1:d0dfbce63a89 1079
elmot 1:d0dfbce63a89 1080 /**
elmot 1:d0dfbce63a89 1081 * @brief Get Memory address.
elmot 1:d0dfbce63a89 1082 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
elmot 1:d0dfbce63a89 1083 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
elmot 1:d0dfbce63a89 1084 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1085 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1086 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 1087 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 1088 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 1089 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 1090 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 1091 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 1092 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 1093 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
elmot 1:d0dfbce63a89 1094 */
elmot 1:d0dfbce63a89 1095 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 1096 {
elmot 1:d0dfbce63a89 1097 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
elmot 1:d0dfbce63a89 1098 DMA_CMAR_MA));
elmot 1:d0dfbce63a89 1099 }
elmot 1:d0dfbce63a89 1100
elmot 1:d0dfbce63a89 1101 /**
elmot 1:d0dfbce63a89 1102 * @brief Get Peripheral address.
elmot 1:d0dfbce63a89 1103 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
elmot 1:d0dfbce63a89 1104 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
elmot 1:d0dfbce63a89 1105 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1106 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1107 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 1108 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 1109 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 1110 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 1111 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 1112 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 1113 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 1114 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
elmot 1:d0dfbce63a89 1115 */
elmot 1:d0dfbce63a89 1116 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 1117 {
elmot 1:d0dfbce63a89 1118 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
elmot 1:d0dfbce63a89 1119 DMA_CPAR_PA));
elmot 1:d0dfbce63a89 1120 }
elmot 1:d0dfbce63a89 1121
elmot 1:d0dfbce63a89 1122 /**
elmot 1:d0dfbce63a89 1123 * @brief Set the Memory to Memory Source address.
elmot 1:d0dfbce63a89 1124 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
elmot 1:d0dfbce63a89 1125 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
elmot 1:d0dfbce63a89 1126 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1127 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1128 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 1129 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 1130 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 1131 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 1132 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 1133 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 1134 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 1135 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
elmot 1:d0dfbce63a89 1136 * @retval None
elmot 1:d0dfbce63a89 1137 */
elmot 1:d0dfbce63a89 1138 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
elmot 1:d0dfbce63a89 1139 {
elmot 1:d0dfbce63a89 1140 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
elmot 1:d0dfbce63a89 1141 MemoryAddress);
elmot 1:d0dfbce63a89 1142 }
elmot 1:d0dfbce63a89 1143
elmot 1:d0dfbce63a89 1144 /**
elmot 1:d0dfbce63a89 1145 * @brief Set the Memory to Memory Destination address.
elmot 1:d0dfbce63a89 1146 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
elmot 1:d0dfbce63a89 1147 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
elmot 1:d0dfbce63a89 1148 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1149 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1150 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 1151 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 1152 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 1153 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 1154 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 1155 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 1156 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 1157 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
elmot 1:d0dfbce63a89 1158 * @retval None
elmot 1:d0dfbce63a89 1159 */
elmot 1:d0dfbce63a89 1160 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
elmot 1:d0dfbce63a89 1161 {
elmot 1:d0dfbce63a89 1162 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
elmot 1:d0dfbce63a89 1163 MemoryAddress);
elmot 1:d0dfbce63a89 1164 }
elmot 1:d0dfbce63a89 1165
elmot 1:d0dfbce63a89 1166 /**
elmot 1:d0dfbce63a89 1167 * @brief Get the Memory to Memory Source address.
elmot 1:d0dfbce63a89 1168 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
elmot 1:d0dfbce63a89 1169 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
elmot 1:d0dfbce63a89 1170 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1171 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1172 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 1173 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 1174 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 1175 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 1176 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 1177 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 1178 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 1179 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
elmot 1:d0dfbce63a89 1180 */
elmot 1:d0dfbce63a89 1181 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 1182 {
elmot 1:d0dfbce63a89 1183 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
elmot 1:d0dfbce63a89 1184 DMA_CPAR_PA));
elmot 1:d0dfbce63a89 1185 }
elmot 1:d0dfbce63a89 1186
elmot 1:d0dfbce63a89 1187 /**
elmot 1:d0dfbce63a89 1188 * @brief Get the Memory to Memory Destination address.
elmot 1:d0dfbce63a89 1189 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
elmot 1:d0dfbce63a89 1190 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
elmot 1:d0dfbce63a89 1191 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1192 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1193 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 1194 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 1195 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 1196 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 1197 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 1198 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 1199 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 1200 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
elmot 1:d0dfbce63a89 1201 */
elmot 1:d0dfbce63a89 1202 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 1203 {
elmot 1:d0dfbce63a89 1204 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
elmot 1:d0dfbce63a89 1205 DMA_CMAR_MA));
elmot 1:d0dfbce63a89 1206 }
elmot 1:d0dfbce63a89 1207
elmot 1:d0dfbce63a89 1208 /**
elmot 1:d0dfbce63a89 1209 * @brief Set DMA request for DMA instance on Channel x.
elmot 1:d0dfbce63a89 1210 * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
elmot 1:d0dfbce63a89 1211 * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
elmot 1:d0dfbce63a89 1212 * CSELR C2S LL_DMA_SetPeriphRequest\n
elmot 1:d0dfbce63a89 1213 * CSELR C3S LL_DMA_SetPeriphRequest\n
elmot 1:d0dfbce63a89 1214 * CSELR C4S LL_DMA_SetPeriphRequest\n
elmot 1:d0dfbce63a89 1215 * CSELR C5S LL_DMA_SetPeriphRequest\n
elmot 1:d0dfbce63a89 1216 * CSELR C6S LL_DMA_SetPeriphRequest\n
elmot 1:d0dfbce63a89 1217 * CSELR C7S LL_DMA_SetPeriphRequest
elmot 1:d0dfbce63a89 1218 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1219 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1220 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 1221 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 1222 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 1223 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 1224 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 1225 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 1226 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 1227 * @param PeriphRequest This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1228 * @arg @ref LL_DMA_REQUEST_0
elmot 1:d0dfbce63a89 1229 * @arg @ref LL_DMA_REQUEST_1
elmot 1:d0dfbce63a89 1230 * @arg @ref LL_DMA_REQUEST_2
elmot 1:d0dfbce63a89 1231 * @arg @ref LL_DMA_REQUEST_3
elmot 1:d0dfbce63a89 1232 * @arg @ref LL_DMA_REQUEST_4
elmot 1:d0dfbce63a89 1233 * @arg @ref LL_DMA_REQUEST_5
elmot 1:d0dfbce63a89 1234 * @arg @ref LL_DMA_REQUEST_6
elmot 1:d0dfbce63a89 1235 * @arg @ref LL_DMA_REQUEST_7
elmot 1:d0dfbce63a89 1236 * @retval None
elmot 1:d0dfbce63a89 1237 */
elmot 1:d0dfbce63a89 1238 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
elmot 1:d0dfbce63a89 1239 {
elmot 1:d0dfbce63a89 1240 MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
elmot 1:d0dfbce63a89 1241 DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
elmot 1:d0dfbce63a89 1242 }
elmot 1:d0dfbce63a89 1243
elmot 1:d0dfbce63a89 1244 /**
elmot 1:d0dfbce63a89 1245 * @brief Get DMA request for DMA instance on Channel x.
elmot 1:d0dfbce63a89 1246 * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
elmot 1:d0dfbce63a89 1247 * CSELR C2S LL_DMA_GetPeriphRequest\n
elmot 1:d0dfbce63a89 1248 * CSELR C3S LL_DMA_GetPeriphRequest\n
elmot 1:d0dfbce63a89 1249 * CSELR C4S LL_DMA_GetPeriphRequest\n
elmot 1:d0dfbce63a89 1250 * CSELR C5S LL_DMA_GetPeriphRequest\n
elmot 1:d0dfbce63a89 1251 * CSELR C6S LL_DMA_GetPeriphRequest\n
elmot 1:d0dfbce63a89 1252 * CSELR C7S LL_DMA_GetPeriphRequest
elmot 1:d0dfbce63a89 1253 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1254 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1255 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 1256 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 1257 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 1258 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 1259 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 1260 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 1261 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 1262 * @retval Returned value can be one of the following values:
elmot 1:d0dfbce63a89 1263 * @arg @ref LL_DMA_REQUEST_0
elmot 1:d0dfbce63a89 1264 * @arg @ref LL_DMA_REQUEST_1
elmot 1:d0dfbce63a89 1265 * @arg @ref LL_DMA_REQUEST_2
elmot 1:d0dfbce63a89 1266 * @arg @ref LL_DMA_REQUEST_3
elmot 1:d0dfbce63a89 1267 * @arg @ref LL_DMA_REQUEST_4
elmot 1:d0dfbce63a89 1268 * @arg @ref LL_DMA_REQUEST_5
elmot 1:d0dfbce63a89 1269 * @arg @ref LL_DMA_REQUEST_6
elmot 1:d0dfbce63a89 1270 * @arg @ref LL_DMA_REQUEST_7
elmot 1:d0dfbce63a89 1271 */
elmot 1:d0dfbce63a89 1272 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 1273 {
elmot 1:d0dfbce63a89 1274 return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
elmot 1:d0dfbce63a89 1275 DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
elmot 1:d0dfbce63a89 1276 }
elmot 1:d0dfbce63a89 1277
elmot 1:d0dfbce63a89 1278 /**
elmot 1:d0dfbce63a89 1279 * @}
elmot 1:d0dfbce63a89 1280 */
elmot 1:d0dfbce63a89 1281
elmot 1:d0dfbce63a89 1282 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
elmot 1:d0dfbce63a89 1283 * @{
elmot 1:d0dfbce63a89 1284 */
elmot 1:d0dfbce63a89 1285
elmot 1:d0dfbce63a89 1286 /**
elmot 1:d0dfbce63a89 1287 * @brief Get Channel 1 global interrupt flag.
elmot 1:d0dfbce63a89 1288 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
elmot 1:d0dfbce63a89 1289 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1290 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1291 */
elmot 1:d0dfbce63a89 1292 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1293 {
elmot 1:d0dfbce63a89 1294 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
elmot 1:d0dfbce63a89 1295 }
elmot 1:d0dfbce63a89 1296
elmot 1:d0dfbce63a89 1297 /**
elmot 1:d0dfbce63a89 1298 * @brief Get Channel 2 global interrupt flag.
elmot 1:d0dfbce63a89 1299 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
elmot 1:d0dfbce63a89 1300 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1301 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1302 */
elmot 1:d0dfbce63a89 1303 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1304 {
elmot 1:d0dfbce63a89 1305 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
elmot 1:d0dfbce63a89 1306 }
elmot 1:d0dfbce63a89 1307
elmot 1:d0dfbce63a89 1308 /**
elmot 1:d0dfbce63a89 1309 * @brief Get Channel 3 global interrupt flag.
elmot 1:d0dfbce63a89 1310 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
elmot 1:d0dfbce63a89 1311 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1312 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1313 */
elmot 1:d0dfbce63a89 1314 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1315 {
elmot 1:d0dfbce63a89 1316 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
elmot 1:d0dfbce63a89 1317 }
elmot 1:d0dfbce63a89 1318
elmot 1:d0dfbce63a89 1319 /**
elmot 1:d0dfbce63a89 1320 * @brief Get Channel 4 global interrupt flag.
elmot 1:d0dfbce63a89 1321 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
elmot 1:d0dfbce63a89 1322 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1323 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1324 */
elmot 1:d0dfbce63a89 1325 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1326 {
elmot 1:d0dfbce63a89 1327 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
elmot 1:d0dfbce63a89 1328 }
elmot 1:d0dfbce63a89 1329
elmot 1:d0dfbce63a89 1330 /**
elmot 1:d0dfbce63a89 1331 * @brief Get Channel 5 global interrupt flag.
elmot 1:d0dfbce63a89 1332 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
elmot 1:d0dfbce63a89 1333 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1334 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1335 */
elmot 1:d0dfbce63a89 1336 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1337 {
elmot 1:d0dfbce63a89 1338 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
elmot 1:d0dfbce63a89 1339 }
elmot 1:d0dfbce63a89 1340
elmot 1:d0dfbce63a89 1341 /**
elmot 1:d0dfbce63a89 1342 * @brief Get Channel 6 global interrupt flag.
elmot 1:d0dfbce63a89 1343 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
elmot 1:d0dfbce63a89 1344 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1345 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1346 */
elmot 1:d0dfbce63a89 1347 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1348 {
elmot 1:d0dfbce63a89 1349 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
elmot 1:d0dfbce63a89 1350 }
elmot 1:d0dfbce63a89 1351
elmot 1:d0dfbce63a89 1352 /**
elmot 1:d0dfbce63a89 1353 * @brief Get Channel 7 global interrupt flag.
elmot 1:d0dfbce63a89 1354 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
elmot 1:d0dfbce63a89 1355 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1356 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1357 */
elmot 1:d0dfbce63a89 1358 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1359 {
elmot 1:d0dfbce63a89 1360 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
elmot 1:d0dfbce63a89 1361 }
elmot 1:d0dfbce63a89 1362
elmot 1:d0dfbce63a89 1363 /**
elmot 1:d0dfbce63a89 1364 * @brief Get Channel 1 transfer complete flag.
elmot 1:d0dfbce63a89 1365 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
elmot 1:d0dfbce63a89 1366 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1367 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1368 */
elmot 1:d0dfbce63a89 1369 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1370 {
elmot 1:d0dfbce63a89 1371 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
elmot 1:d0dfbce63a89 1372 }
elmot 1:d0dfbce63a89 1373
elmot 1:d0dfbce63a89 1374 /**
elmot 1:d0dfbce63a89 1375 * @brief Get Channel 2 transfer complete flag.
elmot 1:d0dfbce63a89 1376 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
elmot 1:d0dfbce63a89 1377 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1378 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1379 */
elmot 1:d0dfbce63a89 1380 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1381 {
elmot 1:d0dfbce63a89 1382 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
elmot 1:d0dfbce63a89 1383 }
elmot 1:d0dfbce63a89 1384
elmot 1:d0dfbce63a89 1385 /**
elmot 1:d0dfbce63a89 1386 * @brief Get Channel 3 transfer complete flag.
elmot 1:d0dfbce63a89 1387 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
elmot 1:d0dfbce63a89 1388 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1389 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1390 */
elmot 1:d0dfbce63a89 1391 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1392 {
elmot 1:d0dfbce63a89 1393 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
elmot 1:d0dfbce63a89 1394 }
elmot 1:d0dfbce63a89 1395
elmot 1:d0dfbce63a89 1396 /**
elmot 1:d0dfbce63a89 1397 * @brief Get Channel 4 transfer complete flag.
elmot 1:d0dfbce63a89 1398 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
elmot 1:d0dfbce63a89 1399 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1400 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1401 */
elmot 1:d0dfbce63a89 1402 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1403 {
elmot 1:d0dfbce63a89 1404 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
elmot 1:d0dfbce63a89 1405 }
elmot 1:d0dfbce63a89 1406
elmot 1:d0dfbce63a89 1407 /**
elmot 1:d0dfbce63a89 1408 * @brief Get Channel 5 transfer complete flag.
elmot 1:d0dfbce63a89 1409 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
elmot 1:d0dfbce63a89 1410 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1411 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1412 */
elmot 1:d0dfbce63a89 1413 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1414 {
elmot 1:d0dfbce63a89 1415 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
elmot 1:d0dfbce63a89 1416 }
elmot 1:d0dfbce63a89 1417
elmot 1:d0dfbce63a89 1418 /**
elmot 1:d0dfbce63a89 1419 * @brief Get Channel 6 transfer complete flag.
elmot 1:d0dfbce63a89 1420 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
elmot 1:d0dfbce63a89 1421 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1422 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1423 */
elmot 1:d0dfbce63a89 1424 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1425 {
elmot 1:d0dfbce63a89 1426 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
elmot 1:d0dfbce63a89 1427 }
elmot 1:d0dfbce63a89 1428
elmot 1:d0dfbce63a89 1429 /**
elmot 1:d0dfbce63a89 1430 * @brief Get Channel 7 transfer complete flag.
elmot 1:d0dfbce63a89 1431 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
elmot 1:d0dfbce63a89 1432 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1433 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1434 */
elmot 1:d0dfbce63a89 1435 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1436 {
elmot 1:d0dfbce63a89 1437 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
elmot 1:d0dfbce63a89 1438 }
elmot 1:d0dfbce63a89 1439
elmot 1:d0dfbce63a89 1440 /**
elmot 1:d0dfbce63a89 1441 * @brief Get Channel 1 half transfer flag.
elmot 1:d0dfbce63a89 1442 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
elmot 1:d0dfbce63a89 1443 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1444 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1445 */
elmot 1:d0dfbce63a89 1446 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1447 {
elmot 1:d0dfbce63a89 1448 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
elmot 1:d0dfbce63a89 1449 }
elmot 1:d0dfbce63a89 1450
elmot 1:d0dfbce63a89 1451 /**
elmot 1:d0dfbce63a89 1452 * @brief Get Channel 2 half transfer flag.
elmot 1:d0dfbce63a89 1453 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
elmot 1:d0dfbce63a89 1454 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1455 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1456 */
elmot 1:d0dfbce63a89 1457 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1458 {
elmot 1:d0dfbce63a89 1459 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
elmot 1:d0dfbce63a89 1460 }
elmot 1:d0dfbce63a89 1461
elmot 1:d0dfbce63a89 1462 /**
elmot 1:d0dfbce63a89 1463 * @brief Get Channel 3 half transfer flag.
elmot 1:d0dfbce63a89 1464 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
elmot 1:d0dfbce63a89 1465 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1466 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1467 */
elmot 1:d0dfbce63a89 1468 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1469 {
elmot 1:d0dfbce63a89 1470 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
elmot 1:d0dfbce63a89 1471 }
elmot 1:d0dfbce63a89 1472
elmot 1:d0dfbce63a89 1473 /**
elmot 1:d0dfbce63a89 1474 * @brief Get Channel 4 half transfer flag.
elmot 1:d0dfbce63a89 1475 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
elmot 1:d0dfbce63a89 1476 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1477 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1478 */
elmot 1:d0dfbce63a89 1479 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1480 {
elmot 1:d0dfbce63a89 1481 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
elmot 1:d0dfbce63a89 1482 }
elmot 1:d0dfbce63a89 1483
elmot 1:d0dfbce63a89 1484 /**
elmot 1:d0dfbce63a89 1485 * @brief Get Channel 5 half transfer flag.
elmot 1:d0dfbce63a89 1486 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
elmot 1:d0dfbce63a89 1487 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1488 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1489 */
elmot 1:d0dfbce63a89 1490 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1491 {
elmot 1:d0dfbce63a89 1492 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
elmot 1:d0dfbce63a89 1493 }
elmot 1:d0dfbce63a89 1494
elmot 1:d0dfbce63a89 1495 /**
elmot 1:d0dfbce63a89 1496 * @brief Get Channel 6 half transfer flag.
elmot 1:d0dfbce63a89 1497 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
elmot 1:d0dfbce63a89 1498 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1499 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1500 */
elmot 1:d0dfbce63a89 1501 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1502 {
elmot 1:d0dfbce63a89 1503 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
elmot 1:d0dfbce63a89 1504 }
elmot 1:d0dfbce63a89 1505
elmot 1:d0dfbce63a89 1506 /**
elmot 1:d0dfbce63a89 1507 * @brief Get Channel 7 half transfer flag.
elmot 1:d0dfbce63a89 1508 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
elmot 1:d0dfbce63a89 1509 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1510 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1511 */
elmot 1:d0dfbce63a89 1512 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1513 {
elmot 1:d0dfbce63a89 1514 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
elmot 1:d0dfbce63a89 1515 }
elmot 1:d0dfbce63a89 1516
elmot 1:d0dfbce63a89 1517 /**
elmot 1:d0dfbce63a89 1518 * @brief Get Channel 1 transfer error flag.
elmot 1:d0dfbce63a89 1519 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
elmot 1:d0dfbce63a89 1520 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1521 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1522 */
elmot 1:d0dfbce63a89 1523 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1524 {
elmot 1:d0dfbce63a89 1525 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
elmot 1:d0dfbce63a89 1526 }
elmot 1:d0dfbce63a89 1527
elmot 1:d0dfbce63a89 1528 /**
elmot 1:d0dfbce63a89 1529 * @brief Get Channel 2 transfer error flag.
elmot 1:d0dfbce63a89 1530 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
elmot 1:d0dfbce63a89 1531 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1532 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1533 */
elmot 1:d0dfbce63a89 1534 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1535 {
elmot 1:d0dfbce63a89 1536 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
elmot 1:d0dfbce63a89 1537 }
elmot 1:d0dfbce63a89 1538
elmot 1:d0dfbce63a89 1539 /**
elmot 1:d0dfbce63a89 1540 * @brief Get Channel 3 transfer error flag.
elmot 1:d0dfbce63a89 1541 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
elmot 1:d0dfbce63a89 1542 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1543 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1544 */
elmot 1:d0dfbce63a89 1545 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1546 {
elmot 1:d0dfbce63a89 1547 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
elmot 1:d0dfbce63a89 1548 }
elmot 1:d0dfbce63a89 1549
elmot 1:d0dfbce63a89 1550 /**
elmot 1:d0dfbce63a89 1551 * @brief Get Channel 4 transfer error flag.
elmot 1:d0dfbce63a89 1552 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
elmot 1:d0dfbce63a89 1553 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1554 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1555 */
elmot 1:d0dfbce63a89 1556 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1557 {
elmot 1:d0dfbce63a89 1558 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
elmot 1:d0dfbce63a89 1559 }
elmot 1:d0dfbce63a89 1560
elmot 1:d0dfbce63a89 1561 /**
elmot 1:d0dfbce63a89 1562 * @brief Get Channel 5 transfer error flag.
elmot 1:d0dfbce63a89 1563 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
elmot 1:d0dfbce63a89 1564 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1565 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1566 */
elmot 1:d0dfbce63a89 1567 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1568 {
elmot 1:d0dfbce63a89 1569 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
elmot 1:d0dfbce63a89 1570 }
elmot 1:d0dfbce63a89 1571
elmot 1:d0dfbce63a89 1572 /**
elmot 1:d0dfbce63a89 1573 * @brief Get Channel 6 transfer error flag.
elmot 1:d0dfbce63a89 1574 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
elmot 1:d0dfbce63a89 1575 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1576 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1577 */
elmot 1:d0dfbce63a89 1578 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1579 {
elmot 1:d0dfbce63a89 1580 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
elmot 1:d0dfbce63a89 1581 }
elmot 1:d0dfbce63a89 1582
elmot 1:d0dfbce63a89 1583 /**
elmot 1:d0dfbce63a89 1584 * @brief Get Channel 7 transfer error flag.
elmot 1:d0dfbce63a89 1585 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
elmot 1:d0dfbce63a89 1586 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1587 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 1588 */
elmot 1:d0dfbce63a89 1589 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1590 {
elmot 1:d0dfbce63a89 1591 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
elmot 1:d0dfbce63a89 1592 }
elmot 1:d0dfbce63a89 1593
elmot 1:d0dfbce63a89 1594 /**
elmot 1:d0dfbce63a89 1595 * @brief Clear Channel 1 global interrupt flag.
elmot 1:d0dfbce63a89 1596 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
elmot 1:d0dfbce63a89 1597 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1598 * @retval None
elmot 1:d0dfbce63a89 1599 */
elmot 1:d0dfbce63a89 1600 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1601 {
elmot 1:d0dfbce63a89 1602 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
elmot 1:d0dfbce63a89 1603 }
elmot 1:d0dfbce63a89 1604
elmot 1:d0dfbce63a89 1605 /**
elmot 1:d0dfbce63a89 1606 * @brief Clear Channel 2 global interrupt flag.
elmot 1:d0dfbce63a89 1607 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
elmot 1:d0dfbce63a89 1608 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1609 * @retval None
elmot 1:d0dfbce63a89 1610 */
elmot 1:d0dfbce63a89 1611 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1612 {
elmot 1:d0dfbce63a89 1613 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
elmot 1:d0dfbce63a89 1614 }
elmot 1:d0dfbce63a89 1615
elmot 1:d0dfbce63a89 1616 /**
elmot 1:d0dfbce63a89 1617 * @brief Clear Channel 3 global interrupt flag.
elmot 1:d0dfbce63a89 1618 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
elmot 1:d0dfbce63a89 1619 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1620 * @retval None
elmot 1:d0dfbce63a89 1621 */
elmot 1:d0dfbce63a89 1622 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1623 {
elmot 1:d0dfbce63a89 1624 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
elmot 1:d0dfbce63a89 1625 }
elmot 1:d0dfbce63a89 1626
elmot 1:d0dfbce63a89 1627 /**
elmot 1:d0dfbce63a89 1628 * @brief Clear Channel 4 global interrupt flag.
elmot 1:d0dfbce63a89 1629 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
elmot 1:d0dfbce63a89 1630 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1631 * @retval None
elmot 1:d0dfbce63a89 1632 */
elmot 1:d0dfbce63a89 1633 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1634 {
elmot 1:d0dfbce63a89 1635 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
elmot 1:d0dfbce63a89 1636 }
elmot 1:d0dfbce63a89 1637
elmot 1:d0dfbce63a89 1638 /**
elmot 1:d0dfbce63a89 1639 * @brief Clear Channel 5 global interrupt flag.
elmot 1:d0dfbce63a89 1640 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
elmot 1:d0dfbce63a89 1641 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1642 * @retval None
elmot 1:d0dfbce63a89 1643 */
elmot 1:d0dfbce63a89 1644 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1645 {
elmot 1:d0dfbce63a89 1646 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
elmot 1:d0dfbce63a89 1647 }
elmot 1:d0dfbce63a89 1648
elmot 1:d0dfbce63a89 1649 /**
elmot 1:d0dfbce63a89 1650 * @brief Clear Channel 6 global interrupt flag.
elmot 1:d0dfbce63a89 1651 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
elmot 1:d0dfbce63a89 1652 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1653 * @retval None
elmot 1:d0dfbce63a89 1654 */
elmot 1:d0dfbce63a89 1655 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1656 {
elmot 1:d0dfbce63a89 1657 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
elmot 1:d0dfbce63a89 1658 }
elmot 1:d0dfbce63a89 1659
elmot 1:d0dfbce63a89 1660 /**
elmot 1:d0dfbce63a89 1661 * @brief Clear Channel 7 global interrupt flag.
elmot 1:d0dfbce63a89 1662 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
elmot 1:d0dfbce63a89 1663 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1664 * @retval None
elmot 1:d0dfbce63a89 1665 */
elmot 1:d0dfbce63a89 1666 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1667 {
elmot 1:d0dfbce63a89 1668 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
elmot 1:d0dfbce63a89 1669 }
elmot 1:d0dfbce63a89 1670
elmot 1:d0dfbce63a89 1671 /**
elmot 1:d0dfbce63a89 1672 * @brief Clear Channel 1 transfer complete flag.
elmot 1:d0dfbce63a89 1673 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
elmot 1:d0dfbce63a89 1674 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1675 * @retval None
elmot 1:d0dfbce63a89 1676 */
elmot 1:d0dfbce63a89 1677 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1678 {
elmot 1:d0dfbce63a89 1679 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
elmot 1:d0dfbce63a89 1680 }
elmot 1:d0dfbce63a89 1681
elmot 1:d0dfbce63a89 1682 /**
elmot 1:d0dfbce63a89 1683 * @brief Clear Channel 2 transfer complete flag.
elmot 1:d0dfbce63a89 1684 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
elmot 1:d0dfbce63a89 1685 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1686 * @retval None
elmot 1:d0dfbce63a89 1687 */
elmot 1:d0dfbce63a89 1688 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1689 {
elmot 1:d0dfbce63a89 1690 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
elmot 1:d0dfbce63a89 1691 }
elmot 1:d0dfbce63a89 1692
elmot 1:d0dfbce63a89 1693 /**
elmot 1:d0dfbce63a89 1694 * @brief Clear Channel 3 transfer complete flag.
elmot 1:d0dfbce63a89 1695 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
elmot 1:d0dfbce63a89 1696 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1697 * @retval None
elmot 1:d0dfbce63a89 1698 */
elmot 1:d0dfbce63a89 1699 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1700 {
elmot 1:d0dfbce63a89 1701 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
elmot 1:d0dfbce63a89 1702 }
elmot 1:d0dfbce63a89 1703
elmot 1:d0dfbce63a89 1704 /**
elmot 1:d0dfbce63a89 1705 * @brief Clear Channel 4 transfer complete flag.
elmot 1:d0dfbce63a89 1706 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
elmot 1:d0dfbce63a89 1707 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1708 * @retval None
elmot 1:d0dfbce63a89 1709 */
elmot 1:d0dfbce63a89 1710 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1711 {
elmot 1:d0dfbce63a89 1712 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
elmot 1:d0dfbce63a89 1713 }
elmot 1:d0dfbce63a89 1714
elmot 1:d0dfbce63a89 1715 /**
elmot 1:d0dfbce63a89 1716 * @brief Clear Channel 5 transfer complete flag.
elmot 1:d0dfbce63a89 1717 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
elmot 1:d0dfbce63a89 1718 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1719 * @retval None
elmot 1:d0dfbce63a89 1720 */
elmot 1:d0dfbce63a89 1721 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1722 {
elmot 1:d0dfbce63a89 1723 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
elmot 1:d0dfbce63a89 1724 }
elmot 1:d0dfbce63a89 1725
elmot 1:d0dfbce63a89 1726 /**
elmot 1:d0dfbce63a89 1727 * @brief Clear Channel 6 transfer complete flag.
elmot 1:d0dfbce63a89 1728 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
elmot 1:d0dfbce63a89 1729 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1730 * @retval None
elmot 1:d0dfbce63a89 1731 */
elmot 1:d0dfbce63a89 1732 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1733 {
elmot 1:d0dfbce63a89 1734 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
elmot 1:d0dfbce63a89 1735 }
elmot 1:d0dfbce63a89 1736
elmot 1:d0dfbce63a89 1737 /**
elmot 1:d0dfbce63a89 1738 * @brief Clear Channel 7 transfer complete flag.
elmot 1:d0dfbce63a89 1739 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
elmot 1:d0dfbce63a89 1740 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1741 * @retval None
elmot 1:d0dfbce63a89 1742 */
elmot 1:d0dfbce63a89 1743 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1744 {
elmot 1:d0dfbce63a89 1745 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
elmot 1:d0dfbce63a89 1746 }
elmot 1:d0dfbce63a89 1747
elmot 1:d0dfbce63a89 1748 /**
elmot 1:d0dfbce63a89 1749 * @brief Clear Channel 1 half transfer flag.
elmot 1:d0dfbce63a89 1750 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
elmot 1:d0dfbce63a89 1751 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1752 * @retval None
elmot 1:d0dfbce63a89 1753 */
elmot 1:d0dfbce63a89 1754 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1755 {
elmot 1:d0dfbce63a89 1756 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
elmot 1:d0dfbce63a89 1757 }
elmot 1:d0dfbce63a89 1758
elmot 1:d0dfbce63a89 1759 /**
elmot 1:d0dfbce63a89 1760 * @brief Clear Channel 2 half transfer flag.
elmot 1:d0dfbce63a89 1761 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
elmot 1:d0dfbce63a89 1762 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1763 * @retval None
elmot 1:d0dfbce63a89 1764 */
elmot 1:d0dfbce63a89 1765 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1766 {
elmot 1:d0dfbce63a89 1767 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
elmot 1:d0dfbce63a89 1768 }
elmot 1:d0dfbce63a89 1769
elmot 1:d0dfbce63a89 1770 /**
elmot 1:d0dfbce63a89 1771 * @brief Clear Channel 3 half transfer flag.
elmot 1:d0dfbce63a89 1772 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
elmot 1:d0dfbce63a89 1773 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1774 * @retval None
elmot 1:d0dfbce63a89 1775 */
elmot 1:d0dfbce63a89 1776 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1777 {
elmot 1:d0dfbce63a89 1778 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
elmot 1:d0dfbce63a89 1779 }
elmot 1:d0dfbce63a89 1780
elmot 1:d0dfbce63a89 1781 /**
elmot 1:d0dfbce63a89 1782 * @brief Clear Channel 4 half transfer flag.
elmot 1:d0dfbce63a89 1783 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
elmot 1:d0dfbce63a89 1784 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1785 * @retval None
elmot 1:d0dfbce63a89 1786 */
elmot 1:d0dfbce63a89 1787 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1788 {
elmot 1:d0dfbce63a89 1789 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
elmot 1:d0dfbce63a89 1790 }
elmot 1:d0dfbce63a89 1791
elmot 1:d0dfbce63a89 1792 /**
elmot 1:d0dfbce63a89 1793 * @brief Clear Channel 5 half transfer flag.
elmot 1:d0dfbce63a89 1794 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
elmot 1:d0dfbce63a89 1795 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1796 * @retval None
elmot 1:d0dfbce63a89 1797 */
elmot 1:d0dfbce63a89 1798 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1799 {
elmot 1:d0dfbce63a89 1800 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
elmot 1:d0dfbce63a89 1801 }
elmot 1:d0dfbce63a89 1802
elmot 1:d0dfbce63a89 1803 /**
elmot 1:d0dfbce63a89 1804 * @brief Clear Channel 6 half transfer flag.
elmot 1:d0dfbce63a89 1805 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
elmot 1:d0dfbce63a89 1806 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1807 * @retval None
elmot 1:d0dfbce63a89 1808 */
elmot 1:d0dfbce63a89 1809 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1810 {
elmot 1:d0dfbce63a89 1811 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
elmot 1:d0dfbce63a89 1812 }
elmot 1:d0dfbce63a89 1813
elmot 1:d0dfbce63a89 1814 /**
elmot 1:d0dfbce63a89 1815 * @brief Clear Channel 7 half transfer flag.
elmot 1:d0dfbce63a89 1816 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
elmot 1:d0dfbce63a89 1817 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1818 * @retval None
elmot 1:d0dfbce63a89 1819 */
elmot 1:d0dfbce63a89 1820 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1821 {
elmot 1:d0dfbce63a89 1822 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
elmot 1:d0dfbce63a89 1823 }
elmot 1:d0dfbce63a89 1824
elmot 1:d0dfbce63a89 1825 /**
elmot 1:d0dfbce63a89 1826 * @brief Clear Channel 1 transfer error flag.
elmot 1:d0dfbce63a89 1827 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
elmot 1:d0dfbce63a89 1828 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1829 * @retval None
elmot 1:d0dfbce63a89 1830 */
elmot 1:d0dfbce63a89 1831 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1832 {
elmot 1:d0dfbce63a89 1833 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
elmot 1:d0dfbce63a89 1834 }
elmot 1:d0dfbce63a89 1835
elmot 1:d0dfbce63a89 1836 /**
elmot 1:d0dfbce63a89 1837 * @brief Clear Channel 2 transfer error flag.
elmot 1:d0dfbce63a89 1838 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
elmot 1:d0dfbce63a89 1839 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1840 * @retval None
elmot 1:d0dfbce63a89 1841 */
elmot 1:d0dfbce63a89 1842 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1843 {
elmot 1:d0dfbce63a89 1844 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
elmot 1:d0dfbce63a89 1845 }
elmot 1:d0dfbce63a89 1846
elmot 1:d0dfbce63a89 1847 /**
elmot 1:d0dfbce63a89 1848 * @brief Clear Channel 3 transfer error flag.
elmot 1:d0dfbce63a89 1849 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
elmot 1:d0dfbce63a89 1850 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1851 * @retval None
elmot 1:d0dfbce63a89 1852 */
elmot 1:d0dfbce63a89 1853 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1854 {
elmot 1:d0dfbce63a89 1855 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
elmot 1:d0dfbce63a89 1856 }
elmot 1:d0dfbce63a89 1857
elmot 1:d0dfbce63a89 1858 /**
elmot 1:d0dfbce63a89 1859 * @brief Clear Channel 4 transfer error flag.
elmot 1:d0dfbce63a89 1860 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
elmot 1:d0dfbce63a89 1861 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1862 * @retval None
elmot 1:d0dfbce63a89 1863 */
elmot 1:d0dfbce63a89 1864 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1865 {
elmot 1:d0dfbce63a89 1866 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
elmot 1:d0dfbce63a89 1867 }
elmot 1:d0dfbce63a89 1868
elmot 1:d0dfbce63a89 1869 /**
elmot 1:d0dfbce63a89 1870 * @brief Clear Channel 5 transfer error flag.
elmot 1:d0dfbce63a89 1871 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
elmot 1:d0dfbce63a89 1872 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1873 * @retval None
elmot 1:d0dfbce63a89 1874 */
elmot 1:d0dfbce63a89 1875 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1876 {
elmot 1:d0dfbce63a89 1877 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
elmot 1:d0dfbce63a89 1878 }
elmot 1:d0dfbce63a89 1879
elmot 1:d0dfbce63a89 1880 /**
elmot 1:d0dfbce63a89 1881 * @brief Clear Channel 6 transfer error flag.
elmot 1:d0dfbce63a89 1882 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
elmot 1:d0dfbce63a89 1883 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1884 * @retval None
elmot 1:d0dfbce63a89 1885 */
elmot 1:d0dfbce63a89 1886 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1887 {
elmot 1:d0dfbce63a89 1888 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
elmot 1:d0dfbce63a89 1889 }
elmot 1:d0dfbce63a89 1890
elmot 1:d0dfbce63a89 1891 /**
elmot 1:d0dfbce63a89 1892 * @brief Clear Channel 7 transfer error flag.
elmot 1:d0dfbce63a89 1893 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
elmot 1:d0dfbce63a89 1894 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1895 * @retval None
elmot 1:d0dfbce63a89 1896 */
elmot 1:d0dfbce63a89 1897 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
elmot 1:d0dfbce63a89 1898 {
elmot 1:d0dfbce63a89 1899 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
elmot 1:d0dfbce63a89 1900 }
elmot 1:d0dfbce63a89 1901
elmot 1:d0dfbce63a89 1902 /**
elmot 1:d0dfbce63a89 1903 * @}
elmot 1:d0dfbce63a89 1904 */
elmot 1:d0dfbce63a89 1905
elmot 1:d0dfbce63a89 1906 /** @defgroup DMA_LL_EF_IT_Management IT_Management
elmot 1:d0dfbce63a89 1907 * @{
elmot 1:d0dfbce63a89 1908 */
elmot 1:d0dfbce63a89 1909 /**
elmot 1:d0dfbce63a89 1910 * @brief Enable Transfer complete interrupt.
elmot 1:d0dfbce63a89 1911 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
elmot 1:d0dfbce63a89 1912 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1913 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1914 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 1915 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 1916 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 1917 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 1918 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 1919 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 1920 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 1921 * @retval None
elmot 1:d0dfbce63a89 1922 */
elmot 1:d0dfbce63a89 1923 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 1924 {
elmot 1:d0dfbce63a89 1925 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
elmot 1:d0dfbce63a89 1926 }
elmot 1:d0dfbce63a89 1927
elmot 1:d0dfbce63a89 1928 /**
elmot 1:d0dfbce63a89 1929 * @brief Enable Half transfer interrupt.
elmot 1:d0dfbce63a89 1930 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
elmot 1:d0dfbce63a89 1931 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1932 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1933 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 1934 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 1935 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 1936 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 1937 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 1938 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 1939 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 1940 * @retval None
elmot 1:d0dfbce63a89 1941 */
elmot 1:d0dfbce63a89 1942 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 1943 {
elmot 1:d0dfbce63a89 1944 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
elmot 1:d0dfbce63a89 1945 }
elmot 1:d0dfbce63a89 1946
elmot 1:d0dfbce63a89 1947 /**
elmot 1:d0dfbce63a89 1948 * @brief Enable Transfer error interrupt.
elmot 1:d0dfbce63a89 1949 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
elmot 1:d0dfbce63a89 1950 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1951 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1952 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 1953 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 1954 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 1955 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 1956 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 1957 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 1958 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 1959 * @retval None
elmot 1:d0dfbce63a89 1960 */
elmot 1:d0dfbce63a89 1961 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 1962 {
elmot 1:d0dfbce63a89 1963 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
elmot 1:d0dfbce63a89 1964 }
elmot 1:d0dfbce63a89 1965
elmot 1:d0dfbce63a89 1966 /**
elmot 1:d0dfbce63a89 1967 * @brief Disable Transfer complete interrupt.
elmot 1:d0dfbce63a89 1968 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
elmot 1:d0dfbce63a89 1969 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1970 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1971 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 1972 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 1973 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 1974 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 1975 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 1976 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 1977 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 1978 * @retval None
elmot 1:d0dfbce63a89 1979 */
elmot 1:d0dfbce63a89 1980 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 1981 {
elmot 1:d0dfbce63a89 1982 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
elmot 1:d0dfbce63a89 1983 }
elmot 1:d0dfbce63a89 1984
elmot 1:d0dfbce63a89 1985 /**
elmot 1:d0dfbce63a89 1986 * @brief Disable Half transfer interrupt.
elmot 1:d0dfbce63a89 1987 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
elmot 1:d0dfbce63a89 1988 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 1989 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1990 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 1991 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 1992 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 1993 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 1994 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 1995 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 1996 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 1997 * @retval None
elmot 1:d0dfbce63a89 1998 */
elmot 1:d0dfbce63a89 1999 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 2000 {
elmot 1:d0dfbce63a89 2001 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
elmot 1:d0dfbce63a89 2002 }
elmot 1:d0dfbce63a89 2003
elmot 1:d0dfbce63a89 2004 /**
elmot 1:d0dfbce63a89 2005 * @brief Disable Transfer error interrupt.
elmot 1:d0dfbce63a89 2006 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
elmot 1:d0dfbce63a89 2007 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 2008 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2009 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 2010 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 2011 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 2012 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 2013 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 2014 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 2015 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 2016 * @retval None
elmot 1:d0dfbce63a89 2017 */
elmot 1:d0dfbce63a89 2018 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 2019 {
elmot 1:d0dfbce63a89 2020 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
elmot 1:d0dfbce63a89 2021 }
elmot 1:d0dfbce63a89 2022
elmot 1:d0dfbce63a89 2023 /**
elmot 1:d0dfbce63a89 2024 * @brief Check if Transfer complete Interrupt is enabled.
elmot 1:d0dfbce63a89 2025 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
elmot 1:d0dfbce63a89 2026 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 2027 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2028 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 2029 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 2030 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 2031 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 2032 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 2033 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 2034 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 2035 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 2036 */
elmot 1:d0dfbce63a89 2037 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 2038 {
elmot 1:d0dfbce63a89 2039 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
elmot 1:d0dfbce63a89 2040 DMA_CCR_TCIE) == (DMA_CCR_TCIE));
elmot 1:d0dfbce63a89 2041 }
elmot 1:d0dfbce63a89 2042
elmot 1:d0dfbce63a89 2043 /**
elmot 1:d0dfbce63a89 2044 * @brief Check if Half transfer Interrupt is enabled.
elmot 1:d0dfbce63a89 2045 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
elmot 1:d0dfbce63a89 2046 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 2047 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2048 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 2049 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 2050 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 2051 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 2052 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 2053 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 2054 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 2055 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 2056 */
elmot 1:d0dfbce63a89 2057 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 2058 {
elmot 1:d0dfbce63a89 2059 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
elmot 1:d0dfbce63a89 2060 DMA_CCR_HTIE) == (DMA_CCR_HTIE));
elmot 1:d0dfbce63a89 2061 }
elmot 1:d0dfbce63a89 2062
elmot 1:d0dfbce63a89 2063 /**
elmot 1:d0dfbce63a89 2064 * @brief Check if Transfer error Interrupt is enabled.
elmot 1:d0dfbce63a89 2065 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
elmot 1:d0dfbce63a89 2066 * @param DMAx DMAx Instance
elmot 1:d0dfbce63a89 2067 * @param Channel This parameter can be one of the following values:
elmot 1:d0dfbce63a89 2068 * @arg @ref LL_DMA_CHANNEL_1
elmot 1:d0dfbce63a89 2069 * @arg @ref LL_DMA_CHANNEL_2
elmot 1:d0dfbce63a89 2070 * @arg @ref LL_DMA_CHANNEL_3
elmot 1:d0dfbce63a89 2071 * @arg @ref LL_DMA_CHANNEL_4
elmot 1:d0dfbce63a89 2072 * @arg @ref LL_DMA_CHANNEL_5
elmot 1:d0dfbce63a89 2073 * @arg @ref LL_DMA_CHANNEL_6
elmot 1:d0dfbce63a89 2074 * @arg @ref LL_DMA_CHANNEL_7
elmot 1:d0dfbce63a89 2075 * @retval State of bit (1 or 0).
elmot 1:d0dfbce63a89 2076 */
elmot 1:d0dfbce63a89 2077 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
elmot 1:d0dfbce63a89 2078 {
elmot 1:d0dfbce63a89 2079 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
elmot 1:d0dfbce63a89 2080 DMA_CCR_TEIE) == (DMA_CCR_TEIE));
elmot 1:d0dfbce63a89 2081 }
elmot 1:d0dfbce63a89 2082
elmot 1:d0dfbce63a89 2083 /**
elmot 1:d0dfbce63a89 2084 * @}
elmot 1:d0dfbce63a89 2085 */
elmot 1:d0dfbce63a89 2086
elmot 1:d0dfbce63a89 2087 #if defined(USE_FULL_LL_DRIVER)
elmot 1:d0dfbce63a89 2088 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
elmot 1:d0dfbce63a89 2089 * @{
elmot 1:d0dfbce63a89 2090 */
elmot 1:d0dfbce63a89 2091
elmot 1:d0dfbce63a89 2092 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
elmot 1:d0dfbce63a89 2093 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
elmot 1:d0dfbce63a89 2094 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
elmot 1:d0dfbce63a89 2095
elmot 1:d0dfbce63a89 2096 /**
elmot 1:d0dfbce63a89 2097 * @}
elmot 1:d0dfbce63a89 2098 */
elmot 1:d0dfbce63a89 2099 #endif /* USE_FULL_LL_DRIVER */
elmot 1:d0dfbce63a89 2100
elmot 1:d0dfbce63a89 2101 /**
elmot 1:d0dfbce63a89 2102 * @}
elmot 1:d0dfbce63a89 2103 */
elmot 1:d0dfbce63a89 2104
elmot 1:d0dfbce63a89 2105 /**
elmot 1:d0dfbce63a89 2106 * @}
elmot 1:d0dfbce63a89 2107 */
elmot 1:d0dfbce63a89 2108
elmot 1:d0dfbce63a89 2109 #endif /* DMA1 || DMA2 */
elmot 1:d0dfbce63a89 2110
elmot 1:d0dfbce63a89 2111 /**
elmot 1:d0dfbce63a89 2112 * @}
elmot 1:d0dfbce63a89 2113 */
elmot 1:d0dfbce63a89 2114
elmot 1:d0dfbce63a89 2115 #ifdef __cplusplus
elmot 1:d0dfbce63a89 2116 }
elmot 1:d0dfbce63a89 2117 #endif
elmot 1:d0dfbce63a89 2118
elmot 1:d0dfbce63a89 2119 #endif /* __STM32L4xx_LL_DMA_H */
elmot 1:d0dfbce63a89 2120
elmot 1:d0dfbce63a89 2121 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/