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HAL_L476/stm32l4xx_ll_tim.c@6:0018763974d3, 2017-02-25 (annotated)
- Committer:
- elmot
- Date:
- Sat Feb 25 08:59:21 2017 +0000
- Revision:
- 6:0018763974d3
- Parent:
- 1:d0dfbce63a89
No comment
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| elmot | 1:d0dfbce63a89 | 1 | /** |
| elmot | 1:d0dfbce63a89 | 2 | ****************************************************************************** |
| elmot | 1:d0dfbce63a89 | 3 | * @file stm32l4xx_ll_tim.c |
| elmot | 1:d0dfbce63a89 | 4 | * @author MCD Application Team |
| elmot | 1:d0dfbce63a89 | 5 | * @version V1.5.1 |
| elmot | 1:d0dfbce63a89 | 6 | * @date 31-May-2016 |
| elmot | 1:d0dfbce63a89 | 7 | * @brief TIM LL module driver. |
| elmot | 1:d0dfbce63a89 | 8 | ****************************************************************************** |
| elmot | 1:d0dfbce63a89 | 9 | * @attention |
| elmot | 1:d0dfbce63a89 | 10 | * |
| elmot | 1:d0dfbce63a89 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| elmot | 1:d0dfbce63a89 | 12 | * |
| elmot | 1:d0dfbce63a89 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| elmot | 1:d0dfbce63a89 | 14 | * are permitted provided that the following conditions are met: |
| elmot | 1:d0dfbce63a89 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| elmot | 1:d0dfbce63a89 | 16 | * this list of conditions and the following disclaimer. |
| elmot | 1:d0dfbce63a89 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| elmot | 1:d0dfbce63a89 | 18 | * this list of conditions and the following disclaimer in the documentation |
| elmot | 1:d0dfbce63a89 | 19 | * and/or other materials provided with the distribution. |
| elmot | 1:d0dfbce63a89 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| elmot | 1:d0dfbce63a89 | 21 | * may be used to endorse or promote products derived from this software |
| elmot | 1:d0dfbce63a89 | 22 | * without specific prior written permission. |
| elmot | 1:d0dfbce63a89 | 23 | * |
| elmot | 1:d0dfbce63a89 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| elmot | 1:d0dfbce63a89 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| elmot | 1:d0dfbce63a89 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| elmot | 1:d0dfbce63a89 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| elmot | 1:d0dfbce63a89 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| elmot | 1:d0dfbce63a89 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| elmot | 1:d0dfbce63a89 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| elmot | 1:d0dfbce63a89 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| elmot | 1:d0dfbce63a89 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| elmot | 1:d0dfbce63a89 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| elmot | 1:d0dfbce63a89 | 34 | * |
| elmot | 1:d0dfbce63a89 | 35 | ****************************************************************************** |
| elmot | 1:d0dfbce63a89 | 36 | */ |
| elmot | 1:d0dfbce63a89 | 37 | #if defined(USE_FULL_LL_DRIVER) |
| elmot | 1:d0dfbce63a89 | 38 | |
| elmot | 1:d0dfbce63a89 | 39 | /* Includes ------------------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 40 | #include "stm32l4xx_ll_tim.h" |
| elmot | 1:d0dfbce63a89 | 41 | #include "stm32l4xx_ll_bus.h" |
| elmot | 1:d0dfbce63a89 | 42 | |
| elmot | 1:d0dfbce63a89 | 43 | #ifdef USE_FULL_ASSERT |
| elmot | 1:d0dfbce63a89 | 44 | #include "stm32_assert.h" |
| elmot | 1:d0dfbce63a89 | 45 | #else |
| elmot | 1:d0dfbce63a89 | 46 | #define assert_param(expr) ((void)0U) |
| elmot | 1:d0dfbce63a89 | 47 | #endif |
| elmot | 1:d0dfbce63a89 | 48 | |
| elmot | 1:d0dfbce63a89 | 49 | /** @addtogroup STM32L4xx_LL_Driver |
| elmot | 1:d0dfbce63a89 | 50 | * @{ |
| elmot | 1:d0dfbce63a89 | 51 | */ |
| elmot | 1:d0dfbce63a89 | 52 | |
| elmot | 1:d0dfbce63a89 | 53 | #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7) |
| elmot | 1:d0dfbce63a89 | 54 | |
| elmot | 1:d0dfbce63a89 | 55 | /** @addtogroup TIM_LL |
| elmot | 1:d0dfbce63a89 | 56 | * @{ |
| elmot | 1:d0dfbce63a89 | 57 | */ |
| elmot | 1:d0dfbce63a89 | 58 | |
| elmot | 1:d0dfbce63a89 | 59 | /* Private types -------------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 60 | /* Private variables ---------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 61 | /* Private constants ---------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 62 | /* Private macros ------------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 63 | /** @addtogroup TIM_LL_Private_Macros |
| elmot | 1:d0dfbce63a89 | 64 | * @{ |
| elmot | 1:d0dfbce63a89 | 65 | */ |
| elmot | 1:d0dfbce63a89 | 66 | #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ |
| elmot | 1:d0dfbce63a89 | 67 | || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ |
| elmot | 1:d0dfbce63a89 | 68 | || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ |
| elmot | 1:d0dfbce63a89 | 69 | || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ |
| elmot | 1:d0dfbce63a89 | 70 | || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) |
| elmot | 1:d0dfbce63a89 | 71 | |
| elmot | 1:d0dfbce63a89 | 72 | #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ |
| elmot | 1:d0dfbce63a89 | 73 | || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ |
| elmot | 1:d0dfbce63a89 | 74 | || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) |
| elmot | 1:d0dfbce63a89 | 75 | |
| elmot | 1:d0dfbce63a89 | 76 | #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ |
| elmot | 1:d0dfbce63a89 | 77 | || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ |
| elmot | 1:d0dfbce63a89 | 78 | || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ |
| elmot | 1:d0dfbce63a89 | 79 | || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ |
| elmot | 1:d0dfbce63a89 | 80 | || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ |
| elmot | 1:d0dfbce63a89 | 81 | || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ |
| elmot | 1:d0dfbce63a89 | 82 | || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ |
| elmot | 1:d0dfbce63a89 | 83 | || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ |
| elmot | 1:d0dfbce63a89 | 84 | || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ |
| elmot | 1:d0dfbce63a89 | 85 | || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ |
| elmot | 1:d0dfbce63a89 | 86 | || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ |
| elmot | 1:d0dfbce63a89 | 87 | || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ |
| elmot | 1:d0dfbce63a89 | 88 | || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ |
| elmot | 1:d0dfbce63a89 | 89 | || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2)) |
| elmot | 1:d0dfbce63a89 | 90 | |
| elmot | 1:d0dfbce63a89 | 91 | #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ |
| elmot | 1:d0dfbce63a89 | 92 | || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) |
| elmot | 1:d0dfbce63a89 | 93 | |
| elmot | 1:d0dfbce63a89 | 94 | #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ |
| elmot | 1:d0dfbce63a89 | 95 | || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) |
| elmot | 1:d0dfbce63a89 | 96 | |
| elmot | 1:d0dfbce63a89 | 97 | #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ |
| elmot | 1:d0dfbce63a89 | 98 | || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) |
| elmot | 1:d0dfbce63a89 | 99 | |
| elmot | 1:d0dfbce63a89 | 100 | #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ |
| elmot | 1:d0dfbce63a89 | 101 | || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ |
| elmot | 1:d0dfbce63a89 | 102 | || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) |
| elmot | 1:d0dfbce63a89 | 103 | |
| elmot | 1:d0dfbce63a89 | 104 | #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ |
| elmot | 1:d0dfbce63a89 | 105 | || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ |
| elmot | 1:d0dfbce63a89 | 106 | || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ |
| elmot | 1:d0dfbce63a89 | 107 | || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) |
| elmot | 1:d0dfbce63a89 | 108 | |
| elmot | 1:d0dfbce63a89 | 109 | #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ |
| elmot | 1:d0dfbce63a89 | 110 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ |
| elmot | 1:d0dfbce63a89 | 111 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ |
| elmot | 1:d0dfbce63a89 | 112 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ |
| elmot | 1:d0dfbce63a89 | 113 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ |
| elmot | 1:d0dfbce63a89 | 114 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ |
| elmot | 1:d0dfbce63a89 | 115 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ |
| elmot | 1:d0dfbce63a89 | 116 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ |
| elmot | 1:d0dfbce63a89 | 117 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ |
| elmot | 1:d0dfbce63a89 | 118 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ |
| elmot | 1:d0dfbce63a89 | 119 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ |
| elmot | 1:d0dfbce63a89 | 120 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ |
| elmot | 1:d0dfbce63a89 | 121 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ |
| elmot | 1:d0dfbce63a89 | 122 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ |
| elmot | 1:d0dfbce63a89 | 123 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ |
| elmot | 1:d0dfbce63a89 | 124 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) |
| elmot | 1:d0dfbce63a89 | 125 | |
| elmot | 1:d0dfbce63a89 | 126 | #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ |
| elmot | 1:d0dfbce63a89 | 127 | || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ |
| elmot | 1:d0dfbce63a89 | 128 | || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) |
| elmot | 1:d0dfbce63a89 | 129 | |
| elmot | 1:d0dfbce63a89 | 130 | #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ |
| elmot | 1:d0dfbce63a89 | 131 | || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ |
| elmot | 1:d0dfbce63a89 | 132 | || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) |
| elmot | 1:d0dfbce63a89 | 133 | |
| elmot | 1:d0dfbce63a89 | 134 | #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ |
| elmot | 1:d0dfbce63a89 | 135 | || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) |
| elmot | 1:d0dfbce63a89 | 136 | /** |
| elmot | 1:d0dfbce63a89 | 137 | * @} |
| elmot | 1:d0dfbce63a89 | 138 | */ |
| elmot | 1:d0dfbce63a89 | 139 | |
| elmot | 1:d0dfbce63a89 | 140 | |
| elmot | 1:d0dfbce63a89 | 141 | /* Private function prototypes -----------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 142 | /** @defgroup TIM_LL_Private_Functions TIM Private Functions |
| elmot | 1:d0dfbce63a89 | 143 | * @{ |
| elmot | 1:d0dfbce63a89 | 144 | */ |
| elmot | 1:d0dfbce63a89 | 145 | static ErrorStatus OC1Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct); |
| elmot | 1:d0dfbce63a89 | 146 | static ErrorStatus OC2Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct); |
| elmot | 1:d0dfbce63a89 | 147 | static ErrorStatus OC3Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct); |
| elmot | 1:d0dfbce63a89 | 148 | static ErrorStatus OC4Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct); |
| elmot | 1:d0dfbce63a89 | 149 | static ErrorStatus OC5Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct); |
| elmot | 1:d0dfbce63a89 | 150 | static ErrorStatus OC6Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct); |
| elmot | 1:d0dfbce63a89 | 151 | static ErrorStatus IC1Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct); |
| elmot | 1:d0dfbce63a89 | 152 | static ErrorStatus IC2Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct); |
| elmot | 1:d0dfbce63a89 | 153 | static ErrorStatus IC3Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct); |
| elmot | 1:d0dfbce63a89 | 154 | static ErrorStatus IC4Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct); |
| elmot | 1:d0dfbce63a89 | 155 | /** |
| elmot | 1:d0dfbce63a89 | 156 | * @} |
| elmot | 1:d0dfbce63a89 | 157 | */ |
| elmot | 1:d0dfbce63a89 | 158 | |
| elmot | 1:d0dfbce63a89 | 159 | /* Exported functions --------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 160 | /** @addtogroup TIM_LL_Exported_Functions |
| elmot | 1:d0dfbce63a89 | 161 | * @{ |
| elmot | 1:d0dfbce63a89 | 162 | */ |
| elmot | 1:d0dfbce63a89 | 163 | |
| elmot | 1:d0dfbce63a89 | 164 | /** @addtogroup TIM_LL_EF_Init |
| elmot | 1:d0dfbce63a89 | 165 | * @{ |
| elmot | 1:d0dfbce63a89 | 166 | */ |
| elmot | 1:d0dfbce63a89 | 167 | |
| elmot | 1:d0dfbce63a89 | 168 | /** |
| elmot | 1:d0dfbce63a89 | 169 | * @brief Set TIMx registers to their reset values. |
| elmot | 1:d0dfbce63a89 | 170 | * @param TIMx Timer instance |
| elmot | 1:d0dfbce63a89 | 171 | * @retval An ErrorStatus enumeration value: |
| elmot | 1:d0dfbce63a89 | 172 | * - SUCCESS: TIMx registers are de-initialized |
| elmot | 1:d0dfbce63a89 | 173 | * - ERROR: invalid TIMx instance |
| elmot | 1:d0dfbce63a89 | 174 | */ |
| elmot | 1:d0dfbce63a89 | 175 | ErrorStatus LL_TIM_DeInit(TIM_TypeDef* TIMx) |
| elmot | 1:d0dfbce63a89 | 176 | { |
| elmot | 1:d0dfbce63a89 | 177 | ErrorStatus result = SUCCESS; |
| elmot | 1:d0dfbce63a89 | 178 | |
| elmot | 1:d0dfbce63a89 | 179 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 180 | assert_param(IS_TIM_INSTANCE(TIMx)); |
| elmot | 1:d0dfbce63a89 | 181 | |
| elmot | 1:d0dfbce63a89 | 182 | if (TIMx == TIM1) |
| elmot | 1:d0dfbce63a89 | 183 | { |
| elmot | 1:d0dfbce63a89 | 184 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); |
| elmot | 1:d0dfbce63a89 | 185 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); |
| elmot | 1:d0dfbce63a89 | 186 | } |
| elmot | 1:d0dfbce63a89 | 187 | else if (TIMx == TIM2) |
| elmot | 1:d0dfbce63a89 | 188 | { |
| elmot | 1:d0dfbce63a89 | 189 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); |
| elmot | 1:d0dfbce63a89 | 190 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); |
| elmot | 1:d0dfbce63a89 | 191 | } |
| elmot | 1:d0dfbce63a89 | 192 | #if defined(TIM3) |
| elmot | 1:d0dfbce63a89 | 193 | else if (TIMx == TIM3) |
| elmot | 1:d0dfbce63a89 | 194 | { |
| elmot | 1:d0dfbce63a89 | 195 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); |
| elmot | 1:d0dfbce63a89 | 196 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); |
| elmot | 1:d0dfbce63a89 | 197 | } |
| elmot | 1:d0dfbce63a89 | 198 | #endif |
| elmot | 1:d0dfbce63a89 | 199 | #if defined(TIM4) |
| elmot | 1:d0dfbce63a89 | 200 | else if (TIMx == TIM4) |
| elmot | 1:d0dfbce63a89 | 201 | { |
| elmot | 1:d0dfbce63a89 | 202 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); |
| elmot | 1:d0dfbce63a89 | 203 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); |
| elmot | 1:d0dfbce63a89 | 204 | } |
| elmot | 1:d0dfbce63a89 | 205 | #endif |
| elmot | 1:d0dfbce63a89 | 206 | #if defined(TIM5) |
| elmot | 1:d0dfbce63a89 | 207 | else if (TIMx == TIM5) |
| elmot | 1:d0dfbce63a89 | 208 | { |
| elmot | 1:d0dfbce63a89 | 209 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); |
| elmot | 1:d0dfbce63a89 | 210 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); |
| elmot | 1:d0dfbce63a89 | 211 | } |
| elmot | 1:d0dfbce63a89 | 212 | #endif |
| elmot | 1:d0dfbce63a89 | 213 | else if (TIMx == TIM6) |
| elmot | 1:d0dfbce63a89 | 214 | { |
| elmot | 1:d0dfbce63a89 | 215 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); |
| elmot | 1:d0dfbce63a89 | 216 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); |
| elmot | 1:d0dfbce63a89 | 217 | } |
| elmot | 1:d0dfbce63a89 | 218 | else if (TIMx == TIM7) |
| elmot | 1:d0dfbce63a89 | 219 | { |
| elmot | 1:d0dfbce63a89 | 220 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); |
| elmot | 1:d0dfbce63a89 | 221 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); |
| elmot | 1:d0dfbce63a89 | 222 | } |
| elmot | 1:d0dfbce63a89 | 223 | #if defined(TIM8) |
| elmot | 1:d0dfbce63a89 | 224 | else if (TIMx == TIM8) |
| elmot | 1:d0dfbce63a89 | 225 | { |
| elmot | 1:d0dfbce63a89 | 226 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8); |
| elmot | 1:d0dfbce63a89 | 227 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); |
| elmot | 1:d0dfbce63a89 | 228 | } |
| elmot | 1:d0dfbce63a89 | 229 | #endif |
| elmot | 1:d0dfbce63a89 | 230 | else if (TIMx == TIM15) |
| elmot | 1:d0dfbce63a89 | 231 | { |
| elmot | 1:d0dfbce63a89 | 232 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15); |
| elmot | 1:d0dfbce63a89 | 233 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15); |
| elmot | 1:d0dfbce63a89 | 234 | } |
| elmot | 1:d0dfbce63a89 | 235 | else if (TIMx == TIM16) |
| elmot | 1:d0dfbce63a89 | 236 | { |
| elmot | 1:d0dfbce63a89 | 237 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16); |
| elmot | 1:d0dfbce63a89 | 238 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16); |
| elmot | 1:d0dfbce63a89 | 239 | } |
| elmot | 1:d0dfbce63a89 | 240 | #if defined(TIM17) |
| elmot | 1:d0dfbce63a89 | 241 | else if (TIMx == TIM17) |
| elmot | 1:d0dfbce63a89 | 242 | { |
| elmot | 1:d0dfbce63a89 | 243 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17); |
| elmot | 1:d0dfbce63a89 | 244 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17); |
| elmot | 1:d0dfbce63a89 | 245 | } |
| elmot | 1:d0dfbce63a89 | 246 | #endif |
| elmot | 1:d0dfbce63a89 | 247 | else |
| elmot | 1:d0dfbce63a89 | 248 | { |
| elmot | 1:d0dfbce63a89 | 249 | result = ERROR; |
| elmot | 1:d0dfbce63a89 | 250 | } |
| elmot | 1:d0dfbce63a89 | 251 | |
| elmot | 1:d0dfbce63a89 | 252 | return result; |
| elmot | 1:d0dfbce63a89 | 253 | } |
| elmot | 1:d0dfbce63a89 | 254 | |
| elmot | 1:d0dfbce63a89 | 255 | /** |
| elmot | 1:d0dfbce63a89 | 256 | * @brief Set the fields of the time base unit configuration data structure |
| elmot | 1:d0dfbce63a89 | 257 | * to their default values. |
| elmot | 1:d0dfbce63a89 | 258 | * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) |
| elmot | 1:d0dfbce63a89 | 259 | * @retval None |
| elmot | 1:d0dfbce63a89 | 260 | */ |
| elmot | 1:d0dfbce63a89 | 261 | void LL_TIM_StructInit(LL_TIM_InitTypeDef* TIM_InitStruct) |
| elmot | 1:d0dfbce63a89 | 262 | { |
| elmot | 1:d0dfbce63a89 | 263 | /* Set the default configuration */ |
| elmot | 1:d0dfbce63a89 | 264 | TIM_InitStruct->Prescaler = (uint16_t)0x0000U; |
| elmot | 1:d0dfbce63a89 | 265 | TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; |
| elmot | 1:d0dfbce63a89 | 266 | TIM_InitStruct->Autoreload = (uint32_t)0xFFFFFFFFU; |
| elmot | 1:d0dfbce63a89 | 267 | TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; |
| elmot | 1:d0dfbce63a89 | 268 | TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U; |
| elmot | 1:d0dfbce63a89 | 269 | } |
| elmot | 1:d0dfbce63a89 | 270 | |
| elmot | 1:d0dfbce63a89 | 271 | /** |
| elmot | 1:d0dfbce63a89 | 272 | * @brief Configure the TIMx time base unit. |
| elmot | 1:d0dfbce63a89 | 273 | * @param TIMx Timer Instance |
| elmot | 1:d0dfbce63a89 | 274 | * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure) |
| elmot | 1:d0dfbce63a89 | 275 | * @retval An ErrorStatus enumeration value: |
| elmot | 1:d0dfbce63a89 | 276 | * - SUCCESS: TIMx registers are de-initialized |
| elmot | 1:d0dfbce63a89 | 277 | * - ERROR: not applicable |
| elmot | 1:d0dfbce63a89 | 278 | */ |
| elmot | 1:d0dfbce63a89 | 279 | ErrorStatus LL_TIM_Init(TIM_TypeDef * TIMx, LL_TIM_InitTypeDef* TIM_InitStruct) |
| elmot | 1:d0dfbce63a89 | 280 | { |
| elmot | 1:d0dfbce63a89 | 281 | uint16_t tmpcr1 = 0U; |
| elmot | 1:d0dfbce63a89 | 282 | |
| elmot | 1:d0dfbce63a89 | 283 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 284 | assert_param(IS_TIM_INSTANCE(TIMx)); |
| elmot | 1:d0dfbce63a89 | 285 | assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); |
| elmot | 1:d0dfbce63a89 | 286 | assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); |
| elmot | 1:d0dfbce63a89 | 287 | |
| elmot | 1:d0dfbce63a89 | 288 | tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); |
| elmot | 1:d0dfbce63a89 | 289 | |
| elmot | 1:d0dfbce63a89 | 290 | if(IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) |
| elmot | 1:d0dfbce63a89 | 291 | { |
| elmot | 1:d0dfbce63a89 | 292 | /* Select the Counter Mode */ |
| elmot | 1:d0dfbce63a89 | 293 | tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); |
| elmot | 1:d0dfbce63a89 | 294 | tmpcr1 |= (uint32_t)TIM_InitStruct->CounterMode; |
| elmot | 1:d0dfbce63a89 | 295 | } |
| elmot | 1:d0dfbce63a89 | 296 | |
| elmot | 1:d0dfbce63a89 | 297 | if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) |
| elmot | 1:d0dfbce63a89 | 298 | { |
| elmot | 1:d0dfbce63a89 | 299 | /* Set the clock division */ |
| elmot | 1:d0dfbce63a89 | 300 | tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); |
| elmot | 1:d0dfbce63a89 | 301 | tmpcr1 |= (uint32_t)TIM_InitStruct->ClockDivision; |
| elmot | 1:d0dfbce63a89 | 302 | } |
| elmot | 1:d0dfbce63a89 | 303 | |
| elmot | 1:d0dfbce63a89 | 304 | /* Write to TIMx CR1 */ |
| elmot | 1:d0dfbce63a89 | 305 | LL_TIM_WriteReg(TIMx, CR1, tmpcr1); |
| elmot | 1:d0dfbce63a89 | 306 | |
| elmot | 1:d0dfbce63a89 | 307 | /* Set the Autoreload value */ |
| elmot | 1:d0dfbce63a89 | 308 | LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); |
| elmot | 1:d0dfbce63a89 | 309 | |
| elmot | 1:d0dfbce63a89 | 310 | /* Set the Prescaler value */ |
| elmot | 1:d0dfbce63a89 | 311 | LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); |
| elmot | 1:d0dfbce63a89 | 312 | |
| elmot | 1:d0dfbce63a89 | 313 | if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) |
| elmot | 1:d0dfbce63a89 | 314 | { |
| elmot | 1:d0dfbce63a89 | 315 | /* Set the Repetition Counter value */ |
| elmot | 1:d0dfbce63a89 | 316 | LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); |
| elmot | 1:d0dfbce63a89 | 317 | } |
| elmot | 1:d0dfbce63a89 | 318 | |
| elmot | 1:d0dfbce63a89 | 319 | /* Generate an update event to reload the Prescaler |
| elmot | 1:d0dfbce63a89 | 320 | and the repetition counter value (if applicable) immediately */ |
| elmot | 1:d0dfbce63a89 | 321 | LL_TIM_GenerateEvent_UPDATE(TIMx); |
| elmot | 1:d0dfbce63a89 | 322 | |
| elmot | 1:d0dfbce63a89 | 323 | return SUCCESS; |
| elmot | 1:d0dfbce63a89 | 324 | } |
| elmot | 1:d0dfbce63a89 | 325 | |
| elmot | 1:d0dfbce63a89 | 326 | /** |
| elmot | 1:d0dfbce63a89 | 327 | * @brief Set the fields of the TIMx output channel configuration data |
| elmot | 1:d0dfbce63a89 | 328 | * structure to their default values. |
| elmot | 1:d0dfbce63a89 | 329 | * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure) |
| elmot | 1:d0dfbce63a89 | 330 | * @retval None |
| elmot | 1:d0dfbce63a89 | 331 | */ |
| elmot | 1:d0dfbce63a89 | 332 | void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef* TIM_OC_InitStruct) |
| elmot | 1:d0dfbce63a89 | 333 | { |
| elmot | 1:d0dfbce63a89 | 334 | /* Set the default configuration */ |
| elmot | 1:d0dfbce63a89 | 335 | TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; |
| elmot | 1:d0dfbce63a89 | 336 | TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; |
| elmot | 1:d0dfbce63a89 | 337 | TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; |
| elmot | 1:d0dfbce63a89 | 338 | TIM_OC_InitStruct->CompareValue = (uint32_t)0x00000000U; |
| elmot | 1:d0dfbce63a89 | 339 | TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; |
| elmot | 1:d0dfbce63a89 | 340 | TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; |
| elmot | 1:d0dfbce63a89 | 341 | TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; |
| elmot | 1:d0dfbce63a89 | 342 | TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; |
| elmot | 1:d0dfbce63a89 | 343 | } |
| elmot | 1:d0dfbce63a89 | 344 | |
| elmot | 1:d0dfbce63a89 | 345 | /** |
| elmot | 1:d0dfbce63a89 | 346 | * @brief Configure the TIMx output channel. |
| elmot | 1:d0dfbce63a89 | 347 | * @param TIMx Timer Instance |
| elmot | 1:d0dfbce63a89 | 348 | * @param Channel This parameter can be one of the following values: |
| elmot | 1:d0dfbce63a89 | 349 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| elmot | 1:d0dfbce63a89 | 350 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| elmot | 1:d0dfbce63a89 | 351 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| elmot | 1:d0dfbce63a89 | 352 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| elmot | 1:d0dfbce63a89 | 353 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| elmot | 1:d0dfbce63a89 | 354 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| elmot | 1:d0dfbce63a89 | 355 | * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure) |
| elmot | 1:d0dfbce63a89 | 356 | * @retval An ErrorStatus enumeration value: |
| elmot | 1:d0dfbce63a89 | 357 | * - SUCCESS: TIMx output channel is initialized |
| elmot | 1:d0dfbce63a89 | 358 | * - ERROR: TIMx output channel is not initialized |
| elmot | 1:d0dfbce63a89 | 359 | */ |
| elmot | 1:d0dfbce63a89 | 360 | ErrorStatus LL_TIM_OC_Init(TIM_TypeDef* TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef* TIM_OC_InitStruct) |
| elmot | 1:d0dfbce63a89 | 361 | { |
| elmot | 1:d0dfbce63a89 | 362 | ErrorStatus result = SUCCESS; |
| elmot | 1:d0dfbce63a89 | 363 | |
| elmot | 1:d0dfbce63a89 | 364 | switch(Channel) |
| elmot | 1:d0dfbce63a89 | 365 | { |
| elmot | 1:d0dfbce63a89 | 366 | case LL_TIM_CHANNEL_CH1: |
| elmot | 1:d0dfbce63a89 | 367 | result = OC1Config(TIMx, TIM_OC_InitStruct); |
| elmot | 1:d0dfbce63a89 | 368 | break; |
| elmot | 1:d0dfbce63a89 | 369 | case LL_TIM_CHANNEL_CH2: |
| elmot | 1:d0dfbce63a89 | 370 | result = OC2Config(TIMx, TIM_OC_InitStruct); |
| elmot | 1:d0dfbce63a89 | 371 | break; |
| elmot | 1:d0dfbce63a89 | 372 | case LL_TIM_CHANNEL_CH3: |
| elmot | 1:d0dfbce63a89 | 373 | result = OC3Config(TIMx, TIM_OC_InitStruct); |
| elmot | 1:d0dfbce63a89 | 374 | break; |
| elmot | 1:d0dfbce63a89 | 375 | case LL_TIM_CHANNEL_CH4: |
| elmot | 1:d0dfbce63a89 | 376 | result = OC4Config(TIMx, TIM_OC_InitStruct); |
| elmot | 1:d0dfbce63a89 | 377 | break; |
| elmot | 1:d0dfbce63a89 | 378 | case LL_TIM_CHANNEL_CH5: |
| elmot | 1:d0dfbce63a89 | 379 | result = OC5Config(TIMx, TIM_OC_InitStruct); |
| elmot | 1:d0dfbce63a89 | 380 | break; |
| elmot | 1:d0dfbce63a89 | 381 | case LL_TIM_CHANNEL_CH6: |
| elmot | 1:d0dfbce63a89 | 382 | result = OC6Config(TIMx, TIM_OC_InitStruct); |
| elmot | 1:d0dfbce63a89 | 383 | break; |
| elmot | 1:d0dfbce63a89 | 384 | default: |
| elmot | 1:d0dfbce63a89 | 385 | result = ERROR; |
| elmot | 1:d0dfbce63a89 | 386 | break; |
| elmot | 1:d0dfbce63a89 | 387 | } |
| elmot | 1:d0dfbce63a89 | 388 | |
| elmot | 1:d0dfbce63a89 | 389 | return result; |
| elmot | 1:d0dfbce63a89 | 390 | } |
| elmot | 1:d0dfbce63a89 | 391 | |
| elmot | 1:d0dfbce63a89 | 392 | /** |
| elmot | 1:d0dfbce63a89 | 393 | * @brief Set the fields of the TIMx input channel configuration data |
| elmot | 1:d0dfbce63a89 | 394 | * structure to their default values. |
| elmot | 1:d0dfbce63a89 | 395 | * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure) |
| elmot | 1:d0dfbce63a89 | 396 | * @retval None |
| elmot | 1:d0dfbce63a89 | 397 | */ |
| elmot | 1:d0dfbce63a89 | 398 | void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef* TIM_ICInitStruct) |
| elmot | 1:d0dfbce63a89 | 399 | { |
| elmot | 1:d0dfbce63a89 | 400 | /* Set the default configuration */ |
| elmot | 1:d0dfbce63a89 | 401 | TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; |
| elmot | 1:d0dfbce63a89 | 402 | TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; |
| elmot | 1:d0dfbce63a89 | 403 | TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; |
| elmot | 1:d0dfbce63a89 | 404 | TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; |
| elmot | 1:d0dfbce63a89 | 405 | } |
| elmot | 1:d0dfbce63a89 | 406 | |
| elmot | 1:d0dfbce63a89 | 407 | /** |
| elmot | 1:d0dfbce63a89 | 408 | * @brief Configure the TIMx input channel. |
| elmot | 1:d0dfbce63a89 | 409 | * @param TIMx Timer Instance |
| elmot | 1:d0dfbce63a89 | 410 | * @param Channel This parameter can be one of the following values: |
| elmot | 1:d0dfbce63a89 | 411 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| elmot | 1:d0dfbce63a89 | 412 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| elmot | 1:d0dfbce63a89 | 413 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| elmot | 1:d0dfbce63a89 | 414 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| elmot | 1:d0dfbce63a89 | 415 | * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure) |
| elmot | 1:d0dfbce63a89 | 416 | * @retval An ErrorStatus enumeration value: |
| elmot | 1:d0dfbce63a89 | 417 | * - SUCCESS: TIMx output channel is initialized |
| elmot | 1:d0dfbce63a89 | 418 | * - ERROR: TIMx output channel is not initialized |
| elmot | 1:d0dfbce63a89 | 419 | */ |
| elmot | 1:d0dfbce63a89 | 420 | ErrorStatus LL_TIM_IC_Init(TIM_TypeDef* TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef* TIM_IC_InitStruct) |
| elmot | 1:d0dfbce63a89 | 421 | { |
| elmot | 1:d0dfbce63a89 | 422 | ErrorStatus result = SUCCESS; |
| elmot | 1:d0dfbce63a89 | 423 | |
| elmot | 1:d0dfbce63a89 | 424 | switch(Channel) |
| elmot | 1:d0dfbce63a89 | 425 | { |
| elmot | 1:d0dfbce63a89 | 426 | case LL_TIM_CHANNEL_CH1: |
| elmot | 1:d0dfbce63a89 | 427 | result = IC1Config(TIMx, TIM_IC_InitStruct); |
| elmot | 1:d0dfbce63a89 | 428 | break; |
| elmot | 1:d0dfbce63a89 | 429 | case LL_TIM_CHANNEL_CH2: |
| elmot | 1:d0dfbce63a89 | 430 | result = IC2Config(TIMx, TIM_IC_InitStruct); |
| elmot | 1:d0dfbce63a89 | 431 | break; |
| elmot | 1:d0dfbce63a89 | 432 | case LL_TIM_CHANNEL_CH3: |
| elmot | 1:d0dfbce63a89 | 433 | result = IC3Config(TIMx, TIM_IC_InitStruct); |
| elmot | 1:d0dfbce63a89 | 434 | break; |
| elmot | 1:d0dfbce63a89 | 435 | case LL_TIM_CHANNEL_CH4: |
| elmot | 1:d0dfbce63a89 | 436 | result = IC4Config(TIMx, TIM_IC_InitStruct); |
| elmot | 1:d0dfbce63a89 | 437 | break; |
| elmot | 1:d0dfbce63a89 | 438 | default: |
| elmot | 1:d0dfbce63a89 | 439 | result = ERROR; |
| elmot | 1:d0dfbce63a89 | 440 | break; |
| elmot | 1:d0dfbce63a89 | 441 | } |
| elmot | 1:d0dfbce63a89 | 442 | |
| elmot | 1:d0dfbce63a89 | 443 | return result; |
| elmot | 1:d0dfbce63a89 | 444 | } |
| elmot | 1:d0dfbce63a89 | 445 | |
| elmot | 1:d0dfbce63a89 | 446 | /** |
| elmot | 1:d0dfbce63a89 | 447 | * @brief Fills each TIM_EncoderInitStruct field with its default value |
| elmot | 1:d0dfbce63a89 | 448 | * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure) |
| elmot | 1:d0dfbce63a89 | 449 | * @retval None |
| elmot | 1:d0dfbce63a89 | 450 | */ |
| elmot | 1:d0dfbce63a89 | 451 | void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef* TIM_EncoderInitStruct) |
| elmot | 1:d0dfbce63a89 | 452 | { |
| elmot | 1:d0dfbce63a89 | 453 | /* Set the default configuration */ |
| elmot | 1:d0dfbce63a89 | 454 | TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; |
| elmot | 1:d0dfbce63a89 | 455 | TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; |
| elmot | 1:d0dfbce63a89 | 456 | TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; |
| elmot | 1:d0dfbce63a89 | 457 | TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; |
| elmot | 1:d0dfbce63a89 | 458 | TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; |
| elmot | 1:d0dfbce63a89 | 459 | TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; |
| elmot | 1:d0dfbce63a89 | 460 | TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; |
| elmot | 1:d0dfbce63a89 | 461 | TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; |
| elmot | 1:d0dfbce63a89 | 462 | TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; |
| elmot | 1:d0dfbce63a89 | 463 | } |
| elmot | 1:d0dfbce63a89 | 464 | |
| elmot | 1:d0dfbce63a89 | 465 | /** |
| elmot | 1:d0dfbce63a89 | 466 | * @brief Configure the encoder interface of the timer instance. |
| elmot | 1:d0dfbce63a89 | 467 | * @param TIMx Timer Instance |
| elmot | 1:d0dfbce63a89 | 468 | * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure) |
| elmot | 1:d0dfbce63a89 | 469 | * @retval An ErrorStatus enumeration value: |
| elmot | 1:d0dfbce63a89 | 470 | * - SUCCESS: TIMx registers are de-initialized |
| elmot | 1:d0dfbce63a89 | 471 | * - ERROR: not applicable |
| elmot | 1:d0dfbce63a89 | 472 | */ |
| elmot | 1:d0dfbce63a89 | 473 | ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef* TIMx, LL_TIM_ENCODER_InitTypeDef* TIM_EncoderInitStruct) |
| elmot | 1:d0dfbce63a89 | 474 | { |
| elmot | 1:d0dfbce63a89 | 475 | uint32_t tmpccmr1 = 0U; |
| elmot | 1:d0dfbce63a89 | 476 | uint32_t tmpccer = 0U; |
| elmot | 1:d0dfbce63a89 | 477 | |
| elmot | 1:d0dfbce63a89 | 478 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 479 | assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); |
| elmot | 1:d0dfbce63a89 | 480 | assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); |
| elmot | 1:d0dfbce63a89 | 481 | assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); |
| elmot | 1:d0dfbce63a89 | 482 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); |
| elmot | 1:d0dfbce63a89 | 483 | assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); |
| elmot | 1:d0dfbce63a89 | 484 | assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); |
| elmot | 1:d0dfbce63a89 | 485 | assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); |
| elmot | 1:d0dfbce63a89 | 486 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); |
| elmot | 1:d0dfbce63a89 | 487 | assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); |
| elmot | 1:d0dfbce63a89 | 488 | assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); |
| elmot | 1:d0dfbce63a89 | 489 | |
| elmot | 1:d0dfbce63a89 | 490 | /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ |
| elmot | 1:d0dfbce63a89 | 491 | TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); |
| elmot | 1:d0dfbce63a89 | 492 | |
| elmot | 1:d0dfbce63a89 | 493 | /* Get the TIMx CCMR1 register value */ |
| elmot | 1:d0dfbce63a89 | 494 | tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); |
| elmot | 1:d0dfbce63a89 | 495 | |
| elmot | 1:d0dfbce63a89 | 496 | /* Get the TIMx CCER register value */ |
| elmot | 1:d0dfbce63a89 | 497 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
| elmot | 1:d0dfbce63a89 | 498 | |
| elmot | 1:d0dfbce63a89 | 499 | /* Configure TI1 */ |
| elmot | 1:d0dfbce63a89 | 500 | tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); |
| elmot | 1:d0dfbce63a89 | 501 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); |
| elmot | 1:d0dfbce63a89 | 502 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); |
| elmot | 1:d0dfbce63a89 | 503 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); |
| elmot | 1:d0dfbce63a89 | 504 | |
| elmot | 1:d0dfbce63a89 | 505 | /* Configure TI2 */ |
| elmot | 1:d0dfbce63a89 | 506 | tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); |
| elmot | 1:d0dfbce63a89 | 507 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); |
| elmot | 1:d0dfbce63a89 | 508 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); |
| elmot | 1:d0dfbce63a89 | 509 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); |
| elmot | 1:d0dfbce63a89 | 510 | |
| elmot | 1:d0dfbce63a89 | 511 | /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ |
| elmot | 1:d0dfbce63a89 | 512 | tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); |
| elmot | 1:d0dfbce63a89 | 513 | tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); |
| elmot | 1:d0dfbce63a89 | 514 | tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); |
| elmot | 1:d0dfbce63a89 | 515 | tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); |
| elmot | 1:d0dfbce63a89 | 516 | |
| elmot | 1:d0dfbce63a89 | 517 | /* Set encoder mode */ |
| elmot | 1:d0dfbce63a89 | 518 | LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); |
| elmot | 1:d0dfbce63a89 | 519 | |
| elmot | 1:d0dfbce63a89 | 520 | /* Write to TIMx CCMR1 */ |
| elmot | 1:d0dfbce63a89 | 521 | LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); |
| elmot | 1:d0dfbce63a89 | 522 | |
| elmot | 1:d0dfbce63a89 | 523 | /* Write to TIMx CCER */ |
| elmot | 1:d0dfbce63a89 | 524 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
| elmot | 1:d0dfbce63a89 | 525 | |
| elmot | 1:d0dfbce63a89 | 526 | return SUCCESS; |
| elmot | 1:d0dfbce63a89 | 527 | } |
| elmot | 1:d0dfbce63a89 | 528 | |
| elmot | 1:d0dfbce63a89 | 529 | /** |
| elmot | 1:d0dfbce63a89 | 530 | * @brief Set the fields of the TIMx Hall sensor interface configuration data |
| elmot | 1:d0dfbce63a89 | 531 | * structure to their default values. |
| elmot | 1:d0dfbce63a89 | 532 | * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure) |
| elmot | 1:d0dfbce63a89 | 533 | * @retval None |
| elmot | 1:d0dfbce63a89 | 534 | */ |
| elmot | 1:d0dfbce63a89 | 535 | void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef* TIM_HallSensorInitStruct) |
| elmot | 1:d0dfbce63a89 | 536 | { |
| elmot | 1:d0dfbce63a89 | 537 | /* Set the default configuration */ |
| elmot | 1:d0dfbce63a89 | 538 | TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; |
| elmot | 1:d0dfbce63a89 | 539 | TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; |
| elmot | 1:d0dfbce63a89 | 540 | TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; |
| elmot | 1:d0dfbce63a89 | 541 | TIM_HallSensorInitStruct->CommutationDelay = (uint32_t)0U; |
| elmot | 1:d0dfbce63a89 | 542 | } |
| elmot | 1:d0dfbce63a89 | 543 | |
| elmot | 1:d0dfbce63a89 | 544 | /** |
| elmot | 1:d0dfbce63a89 | 545 | * @brief Configure the Hall sensor interface of the timer instance. |
| elmot | 1:d0dfbce63a89 | 546 | * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR |
| elmot | 1:d0dfbce63a89 | 547 | * to the TI1 input channel |
| elmot | 1:d0dfbce63a89 | 548 | * @note TIMx slave mode controller is configured in reset mode. |
| elmot | 1:d0dfbce63a89 | 549 | Selected internal trigger is TI1F_ED. |
| elmot | 1:d0dfbce63a89 | 550 | * @note Channel 1 is configured as input, IC1 is mapped on TRC. |
| elmot | 1:d0dfbce63a89 | 551 | * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed |
| elmot | 1:d0dfbce63a89 | 552 | * between 2 changes on the inputs. It gives information about motor speed. |
| elmot | 1:d0dfbce63a89 | 553 | * @note Channel 2 is configured in output PWM 2 mode. |
| elmot | 1:d0dfbce63a89 | 554 | * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. |
| elmot | 1:d0dfbce63a89 | 555 | * @note OC2REF is selected as trigger output on TRGO. |
| elmot | 1:d0dfbce63a89 | 556 | * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used |
| elmot | 1:d0dfbce63a89 | 557 | * when TIMx operates in Hall sensor interface mode. |
| elmot | 1:d0dfbce63a89 | 558 | * @param TIMx Timer Instance |
| elmot | 1:d0dfbce63a89 | 559 | * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure) |
| elmot | 1:d0dfbce63a89 | 560 | * @retval An ErrorStatus enumeration value: |
| elmot | 1:d0dfbce63a89 | 561 | * - SUCCESS: TIMx registers are de-initialized |
| elmot | 1:d0dfbce63a89 | 562 | * - ERROR: not applicable |
| elmot | 1:d0dfbce63a89 | 563 | */ |
| elmot | 1:d0dfbce63a89 | 564 | ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef* TIMx, LL_TIM_HALLSENSOR_InitTypeDef* TIM_HallSensorInitStruct) |
| elmot | 1:d0dfbce63a89 | 565 | { |
| elmot | 1:d0dfbce63a89 | 566 | uint32_t tmpcr2 = 0U; |
| elmot | 1:d0dfbce63a89 | 567 | uint32_t tmpccmr1 = 0U; |
| elmot | 1:d0dfbce63a89 | 568 | uint32_t tmpccer = 0U; |
| elmot | 1:d0dfbce63a89 | 569 | uint32_t tmpsmcr = 0U; |
| elmot | 1:d0dfbce63a89 | 570 | |
| elmot | 1:d0dfbce63a89 | 571 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 572 | assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); |
| elmot | 1:d0dfbce63a89 | 573 | assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); |
| elmot | 1:d0dfbce63a89 | 574 | assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); |
| elmot | 1:d0dfbce63a89 | 575 | assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); |
| elmot | 1:d0dfbce63a89 | 576 | |
| elmot | 1:d0dfbce63a89 | 577 | /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ |
| elmot | 1:d0dfbce63a89 | 578 | TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); |
| elmot | 1:d0dfbce63a89 | 579 | |
| elmot | 1:d0dfbce63a89 | 580 | /* Get the TIMx CR2 register value */ |
| elmot | 1:d0dfbce63a89 | 581 | tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); |
| elmot | 1:d0dfbce63a89 | 582 | |
| elmot | 1:d0dfbce63a89 | 583 | /* Get the TIMx CCMR1 register value */ |
| elmot | 1:d0dfbce63a89 | 584 | tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); |
| elmot | 1:d0dfbce63a89 | 585 | |
| elmot | 1:d0dfbce63a89 | 586 | /* Get the TIMx CCER register value */ |
| elmot | 1:d0dfbce63a89 | 587 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
| elmot | 1:d0dfbce63a89 | 588 | |
| elmot | 1:d0dfbce63a89 | 589 | /* Get the TIMx SMCR register value */ |
| elmot | 1:d0dfbce63a89 | 590 | tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); |
| elmot | 1:d0dfbce63a89 | 591 | |
| elmot | 1:d0dfbce63a89 | 592 | /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ |
| elmot | 1:d0dfbce63a89 | 593 | tmpcr2 |= TIM_CR2_TI1S; |
| elmot | 1:d0dfbce63a89 | 594 | |
| elmot | 1:d0dfbce63a89 | 595 | /* OC2REF signal is used as trigger output (TRGO) */ |
| elmot | 1:d0dfbce63a89 | 596 | tmpcr2 |= LL_TIM_TRGO_OC2REF; |
| elmot | 1:d0dfbce63a89 | 597 | |
| elmot | 1:d0dfbce63a89 | 598 | /* Configure the slave mode controller */ |
| elmot | 1:d0dfbce63a89 | 599 | tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); |
| elmot | 1:d0dfbce63a89 | 600 | tmpsmcr |= LL_TIM_TS_TI1F_ED; |
| elmot | 1:d0dfbce63a89 | 601 | tmpsmcr |= LL_TIM_SLAVEMODE_RESET; |
| elmot | 1:d0dfbce63a89 | 602 | |
| elmot | 1:d0dfbce63a89 | 603 | /* Configure input channel 1 */ |
| elmot | 1:d0dfbce63a89 | 604 | tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); |
| elmot | 1:d0dfbce63a89 | 605 | tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); |
| elmot | 1:d0dfbce63a89 | 606 | tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); |
| elmot | 1:d0dfbce63a89 | 607 | tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); |
| elmot | 1:d0dfbce63a89 | 608 | |
| elmot | 1:d0dfbce63a89 | 609 | /* Configure input channel 2 */ |
| elmot | 1:d0dfbce63a89 | 610 | tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); |
| elmot | 1:d0dfbce63a89 | 611 | tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); |
| elmot | 1:d0dfbce63a89 | 612 | |
| elmot | 1:d0dfbce63a89 | 613 | /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ |
| elmot | 1:d0dfbce63a89 | 614 | tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); |
| elmot | 1:d0dfbce63a89 | 615 | tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); |
| elmot | 1:d0dfbce63a89 | 616 | tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); |
| elmot | 1:d0dfbce63a89 | 617 | |
| elmot | 1:d0dfbce63a89 | 618 | /* Write to TIMx CR2 */ |
| elmot | 1:d0dfbce63a89 | 619 | LL_TIM_WriteReg(TIMx, CR2, tmpcr2); |
| elmot | 1:d0dfbce63a89 | 620 | |
| elmot | 1:d0dfbce63a89 | 621 | /* Write to TIMx SMCR */ |
| elmot | 1:d0dfbce63a89 | 622 | LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); |
| elmot | 1:d0dfbce63a89 | 623 | |
| elmot | 1:d0dfbce63a89 | 624 | /* Write to TIMx CCMR1 */ |
| elmot | 1:d0dfbce63a89 | 625 | LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); |
| elmot | 1:d0dfbce63a89 | 626 | |
| elmot | 1:d0dfbce63a89 | 627 | /* Write to TIMx CCER */ |
| elmot | 1:d0dfbce63a89 | 628 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
| elmot | 1:d0dfbce63a89 | 629 | |
| elmot | 1:d0dfbce63a89 | 630 | /* Write to TIMx CCR2 */ |
| elmot | 1:d0dfbce63a89 | 631 | LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay); |
| elmot | 1:d0dfbce63a89 | 632 | |
| elmot | 1:d0dfbce63a89 | 633 | return SUCCESS; |
| elmot | 1:d0dfbce63a89 | 634 | } |
| elmot | 1:d0dfbce63a89 | 635 | |
| elmot | 1:d0dfbce63a89 | 636 | /** |
| elmot | 1:d0dfbce63a89 | 637 | * @} |
| elmot | 1:d0dfbce63a89 | 638 | */ |
| elmot | 1:d0dfbce63a89 | 639 | |
| elmot | 1:d0dfbce63a89 | 640 | /** |
| elmot | 1:d0dfbce63a89 | 641 | * @} |
| elmot | 1:d0dfbce63a89 | 642 | */ |
| elmot | 1:d0dfbce63a89 | 643 | |
| elmot | 1:d0dfbce63a89 | 644 | /** @addtogroup TIM_LL_Private_Functions TIM Private Functions |
| elmot | 1:d0dfbce63a89 | 645 | * @brief Private functions |
| elmot | 1:d0dfbce63a89 | 646 | * @{ |
| elmot | 1:d0dfbce63a89 | 647 | */ |
| elmot | 1:d0dfbce63a89 | 648 | /** |
| elmot | 1:d0dfbce63a89 | 649 | * @brief Configure the TIMx output channel 1. |
| elmot | 1:d0dfbce63a89 | 650 | * @param TIMx Timer Instance |
| elmot | 1:d0dfbce63a89 | 651 | * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure |
| elmot | 1:d0dfbce63a89 | 652 | * @retval An ErrorStatus enumeration value: |
| elmot | 1:d0dfbce63a89 | 653 | * - SUCCESS: TIMx registers are de-initialized |
| elmot | 1:d0dfbce63a89 | 654 | * - ERROR: not applicable |
| elmot | 1:d0dfbce63a89 | 655 | */ |
| elmot | 1:d0dfbce63a89 | 656 | static ErrorStatus OC1Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct) |
| elmot | 1:d0dfbce63a89 | 657 | { |
| elmot | 1:d0dfbce63a89 | 658 | uint32_t tmpccmr1 = 0U; |
| elmot | 1:d0dfbce63a89 | 659 | uint32_t tmpccer = 0U; |
| elmot | 1:d0dfbce63a89 | 660 | uint32_t tmpcr2 = 0U; |
| elmot | 1:d0dfbce63a89 | 661 | |
| elmot | 1:d0dfbce63a89 | 662 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 663 | assert_param(IS_TIM_CC1_INSTANCE(TIMx)); |
| elmot | 1:d0dfbce63a89 | 664 | assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); |
| elmot | 1:d0dfbce63a89 | 665 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); |
| elmot | 1:d0dfbce63a89 | 666 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); |
| elmot | 1:d0dfbce63a89 | 667 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); |
| elmot | 1:d0dfbce63a89 | 668 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); |
| elmot | 1:d0dfbce63a89 | 669 | |
| elmot | 1:d0dfbce63a89 | 670 | /* Disable the Channel 1: Reset the CC1E Bit */ |
| elmot | 1:d0dfbce63a89 | 671 | CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); |
| elmot | 1:d0dfbce63a89 | 672 | |
| elmot | 1:d0dfbce63a89 | 673 | /* Get the TIMx CCER register value */ |
| elmot | 1:d0dfbce63a89 | 674 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
| elmot | 1:d0dfbce63a89 | 675 | |
| elmot | 1:d0dfbce63a89 | 676 | /* Get the TIMx CR2 register value */ |
| elmot | 1:d0dfbce63a89 | 677 | tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); |
| elmot | 1:d0dfbce63a89 | 678 | |
| elmot | 1:d0dfbce63a89 | 679 | /* Get the TIMx CCMR1 register value */ |
| elmot | 1:d0dfbce63a89 | 680 | tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); |
| elmot | 1:d0dfbce63a89 | 681 | |
| elmot | 1:d0dfbce63a89 | 682 | /* Reset Capture/Compare selection Bits */ |
| elmot | 1:d0dfbce63a89 | 683 | CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); |
| elmot | 1:d0dfbce63a89 | 684 | |
| elmot | 1:d0dfbce63a89 | 685 | /* Set the Output Compare Mode */ |
| elmot | 1:d0dfbce63a89 | 686 | MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); |
| elmot | 1:d0dfbce63a89 | 687 | |
| elmot | 1:d0dfbce63a89 | 688 | /* Set the Output Compare Polarity */ |
| elmot | 1:d0dfbce63a89 | 689 | MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); |
| elmot | 1:d0dfbce63a89 | 690 | |
| elmot | 1:d0dfbce63a89 | 691 | /* Set the Output State */ |
| elmot | 1:d0dfbce63a89 | 692 | MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); |
| elmot | 1:d0dfbce63a89 | 693 | |
| elmot | 1:d0dfbce63a89 | 694 | if(IS_TIM_BREAK_INSTANCE(TIMx)) |
| elmot | 1:d0dfbce63a89 | 695 | { |
| elmot | 1:d0dfbce63a89 | 696 | assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); |
| elmot | 1:d0dfbce63a89 | 697 | assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); |
| elmot | 1:d0dfbce63a89 | 698 | |
| elmot | 1:d0dfbce63a89 | 699 | /* Set the complementary output Polarity */ |
| elmot | 1:d0dfbce63a89 | 700 | MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); |
| elmot | 1:d0dfbce63a89 | 701 | |
| elmot | 1:d0dfbce63a89 | 702 | /* Set the complementary output State */ |
| elmot | 1:d0dfbce63a89 | 703 | MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); |
| elmot | 1:d0dfbce63a89 | 704 | |
| elmot | 1:d0dfbce63a89 | 705 | /* Set the Output Idle state */ |
| elmot | 1:d0dfbce63a89 | 706 | MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); |
| elmot | 1:d0dfbce63a89 | 707 | |
| elmot | 1:d0dfbce63a89 | 708 | /* Set the complementary output Idle state */ |
| elmot | 1:d0dfbce63a89 | 709 | MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); |
| elmot | 1:d0dfbce63a89 | 710 | } |
| elmot | 1:d0dfbce63a89 | 711 | |
| elmot | 1:d0dfbce63a89 | 712 | /* Write to TIMx CR2 */ |
| elmot | 1:d0dfbce63a89 | 713 | LL_TIM_WriteReg(TIMx, CR2, tmpcr2); |
| elmot | 1:d0dfbce63a89 | 714 | |
| elmot | 1:d0dfbce63a89 | 715 | /* Write to TIMx CCMR1 */ |
| elmot | 1:d0dfbce63a89 | 716 | LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); |
| elmot | 1:d0dfbce63a89 | 717 | |
| elmot | 1:d0dfbce63a89 | 718 | /* Set the Capture Compare Register value */ |
| elmot | 1:d0dfbce63a89 | 719 | LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); |
| elmot | 1:d0dfbce63a89 | 720 | |
| elmot | 1:d0dfbce63a89 | 721 | /* Write to TIMx CCER */ |
| elmot | 1:d0dfbce63a89 | 722 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
| elmot | 1:d0dfbce63a89 | 723 | |
| elmot | 1:d0dfbce63a89 | 724 | return SUCCESS; |
| elmot | 1:d0dfbce63a89 | 725 | } |
| elmot | 1:d0dfbce63a89 | 726 | |
| elmot | 1:d0dfbce63a89 | 727 | /** |
| elmot | 1:d0dfbce63a89 | 728 | * @brief Configure the TIMx output channel 2. |
| elmot | 1:d0dfbce63a89 | 729 | * @param TIMx Timer Instance |
| elmot | 1:d0dfbce63a89 | 730 | * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure |
| elmot | 1:d0dfbce63a89 | 731 | * @retval An ErrorStatus enumeration value: |
| elmot | 1:d0dfbce63a89 | 732 | * - SUCCESS: TIMx registers are de-initialized |
| elmot | 1:d0dfbce63a89 | 733 | * - ERROR: not applicable |
| elmot | 1:d0dfbce63a89 | 734 | */ |
| elmot | 1:d0dfbce63a89 | 735 | static ErrorStatus OC2Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct) |
| elmot | 1:d0dfbce63a89 | 736 | { |
| elmot | 1:d0dfbce63a89 | 737 | uint32_t tmpccmr1 = 0U; |
| elmot | 1:d0dfbce63a89 | 738 | uint32_t tmpccer = 0U; |
| elmot | 1:d0dfbce63a89 | 739 | uint32_t tmpcr2 = 0U; |
| elmot | 1:d0dfbce63a89 | 740 | |
| elmot | 1:d0dfbce63a89 | 741 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 742 | assert_param(IS_TIM_CC2_INSTANCE(TIMx)); |
| elmot | 1:d0dfbce63a89 | 743 | assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); |
| elmot | 1:d0dfbce63a89 | 744 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); |
| elmot | 1:d0dfbce63a89 | 745 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); |
| elmot | 1:d0dfbce63a89 | 746 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); |
| elmot | 1:d0dfbce63a89 | 747 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); |
| elmot | 1:d0dfbce63a89 | 748 | |
| elmot | 1:d0dfbce63a89 | 749 | /* Disable the Channel 2: Reset the CC2E Bit */ |
| elmot | 1:d0dfbce63a89 | 750 | CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); |
| elmot | 1:d0dfbce63a89 | 751 | |
| elmot | 1:d0dfbce63a89 | 752 | /* Get the TIMx CCER register value */ |
| elmot | 1:d0dfbce63a89 | 753 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
| elmot | 1:d0dfbce63a89 | 754 | |
| elmot | 1:d0dfbce63a89 | 755 | /* Get the TIMx CR2 register value */ |
| elmot | 1:d0dfbce63a89 | 756 | tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); |
| elmot | 1:d0dfbce63a89 | 757 | |
| elmot | 1:d0dfbce63a89 | 758 | /* Get the TIMx CCMR1 register value */ |
| elmot | 1:d0dfbce63a89 | 759 | tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); |
| elmot | 1:d0dfbce63a89 | 760 | |
| elmot | 1:d0dfbce63a89 | 761 | /* Reset Capture/Compare selection Bits */ |
| elmot | 1:d0dfbce63a89 | 762 | CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); |
| elmot | 1:d0dfbce63a89 | 763 | |
| elmot | 1:d0dfbce63a89 | 764 | /* Select the Output Compare Mode */ |
| elmot | 1:d0dfbce63a89 | 765 | MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); |
| elmot | 1:d0dfbce63a89 | 766 | |
| elmot | 1:d0dfbce63a89 | 767 | /* Set the Output Compare Polarity */ |
| elmot | 1:d0dfbce63a89 | 768 | MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity<< 4U); |
| elmot | 1:d0dfbce63a89 | 769 | |
| elmot | 1:d0dfbce63a89 | 770 | /* Set the Output State */ |
| elmot | 1:d0dfbce63a89 | 771 | MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); |
| elmot | 1:d0dfbce63a89 | 772 | |
| elmot | 1:d0dfbce63a89 | 773 | if(IS_TIM_BREAK_INSTANCE(TIMx)) |
| elmot | 1:d0dfbce63a89 | 774 | { |
| elmot | 1:d0dfbce63a89 | 775 | assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); |
| elmot | 1:d0dfbce63a89 | 776 | assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); |
| elmot | 1:d0dfbce63a89 | 777 | |
| elmot | 1:d0dfbce63a89 | 778 | /* Set the complementary output Polarity */ |
| elmot | 1:d0dfbce63a89 | 779 | MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); |
| elmot | 1:d0dfbce63a89 | 780 | |
| elmot | 1:d0dfbce63a89 | 781 | /* Set the complementary output State */ |
| elmot | 1:d0dfbce63a89 | 782 | MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); |
| elmot | 1:d0dfbce63a89 | 783 | |
| elmot | 1:d0dfbce63a89 | 784 | /* Set the Output Idle state */ |
| elmot | 1:d0dfbce63a89 | 785 | MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); |
| elmot | 1:d0dfbce63a89 | 786 | |
| elmot | 1:d0dfbce63a89 | 787 | /* Set the complementary output Idle state */ |
| elmot | 1:d0dfbce63a89 | 788 | MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); |
| elmot | 1:d0dfbce63a89 | 789 | } |
| elmot | 1:d0dfbce63a89 | 790 | |
| elmot | 1:d0dfbce63a89 | 791 | /* Write to TIMx CR2 */ |
| elmot | 1:d0dfbce63a89 | 792 | LL_TIM_WriteReg(TIMx, CR2, tmpcr2); |
| elmot | 1:d0dfbce63a89 | 793 | |
| elmot | 1:d0dfbce63a89 | 794 | /* Write to TIMx CCMR1 */ |
| elmot | 1:d0dfbce63a89 | 795 | LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); |
| elmot | 1:d0dfbce63a89 | 796 | |
| elmot | 1:d0dfbce63a89 | 797 | /* Set the Capture Compare Register value */ |
| elmot | 1:d0dfbce63a89 | 798 | LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); |
| elmot | 1:d0dfbce63a89 | 799 | |
| elmot | 1:d0dfbce63a89 | 800 | /* Write to TIMx CCER */ |
| elmot | 1:d0dfbce63a89 | 801 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
| elmot | 1:d0dfbce63a89 | 802 | |
| elmot | 1:d0dfbce63a89 | 803 | return SUCCESS; |
| elmot | 1:d0dfbce63a89 | 804 | } |
| elmot | 1:d0dfbce63a89 | 805 | |
| elmot | 1:d0dfbce63a89 | 806 | /** |
| elmot | 1:d0dfbce63a89 | 807 | * @brief Configure the TIMx output channel 3. |
| elmot | 1:d0dfbce63a89 | 808 | * @param TIMx Timer Instance |
| elmot | 1:d0dfbce63a89 | 809 | * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure |
| elmot | 1:d0dfbce63a89 | 810 | * @retval An ErrorStatus enumeration value: |
| elmot | 1:d0dfbce63a89 | 811 | * - SUCCESS: TIMx registers are de-initialized |
| elmot | 1:d0dfbce63a89 | 812 | * - ERROR: not applicable |
| elmot | 1:d0dfbce63a89 | 813 | */ |
| elmot | 1:d0dfbce63a89 | 814 | static ErrorStatus OC3Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct) |
| elmot | 1:d0dfbce63a89 | 815 | { |
| elmot | 1:d0dfbce63a89 | 816 | uint32_t tmpccmr2 = 0U; |
| elmot | 1:d0dfbce63a89 | 817 | uint32_t tmpccer = 0U; |
| elmot | 1:d0dfbce63a89 | 818 | uint32_t tmpcr2 = 0U; |
| elmot | 1:d0dfbce63a89 | 819 | |
| elmot | 1:d0dfbce63a89 | 820 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 821 | assert_param(IS_TIM_CC3_INSTANCE(TIMx)); |
| elmot | 1:d0dfbce63a89 | 822 | assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); |
| elmot | 1:d0dfbce63a89 | 823 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); |
| elmot | 1:d0dfbce63a89 | 824 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); |
| elmot | 1:d0dfbce63a89 | 825 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); |
| elmot | 1:d0dfbce63a89 | 826 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); |
| elmot | 1:d0dfbce63a89 | 827 | |
| elmot | 1:d0dfbce63a89 | 828 | /* Disable the Channel 3: Reset the CC3E Bit */ |
| elmot | 1:d0dfbce63a89 | 829 | CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); |
| elmot | 1:d0dfbce63a89 | 830 | |
| elmot | 1:d0dfbce63a89 | 831 | /* Get the TIMx CCER register value */ |
| elmot | 1:d0dfbce63a89 | 832 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
| elmot | 1:d0dfbce63a89 | 833 | |
| elmot | 1:d0dfbce63a89 | 834 | /* Get the TIMx CR2 register value */ |
| elmot | 1:d0dfbce63a89 | 835 | tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); |
| elmot | 1:d0dfbce63a89 | 836 | |
| elmot | 1:d0dfbce63a89 | 837 | /* Get the TIMx CCMR2 register value */ |
| elmot | 1:d0dfbce63a89 | 838 | tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); |
| elmot | 1:d0dfbce63a89 | 839 | |
| elmot | 1:d0dfbce63a89 | 840 | /* Reset Capture/Compare selection Bits */ |
| elmot | 1:d0dfbce63a89 | 841 | CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); |
| elmot | 1:d0dfbce63a89 | 842 | |
| elmot | 1:d0dfbce63a89 | 843 | /* Select the Output Compare Mode */ |
| elmot | 1:d0dfbce63a89 | 844 | MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); |
| elmot | 1:d0dfbce63a89 | 845 | |
| elmot | 1:d0dfbce63a89 | 846 | /* Set the Output Compare Polarity */ |
| elmot | 1:d0dfbce63a89 | 847 | MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); |
| elmot | 1:d0dfbce63a89 | 848 | |
| elmot | 1:d0dfbce63a89 | 849 | /* Set the Output State */ |
| elmot | 1:d0dfbce63a89 | 850 | MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); |
| elmot | 1:d0dfbce63a89 | 851 | |
| elmot | 1:d0dfbce63a89 | 852 | if(IS_TIM_BREAK_INSTANCE(TIMx)) |
| elmot | 1:d0dfbce63a89 | 853 | { |
| elmot | 1:d0dfbce63a89 | 854 | assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); |
| elmot | 1:d0dfbce63a89 | 855 | assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); |
| elmot | 1:d0dfbce63a89 | 856 | |
| elmot | 1:d0dfbce63a89 | 857 | /* Set the complementary output Polarity */ |
| elmot | 1:d0dfbce63a89 | 858 | MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); |
| elmot | 1:d0dfbce63a89 | 859 | |
| elmot | 1:d0dfbce63a89 | 860 | /* Set the complementary output State */ |
| elmot | 1:d0dfbce63a89 | 861 | MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); |
| elmot | 1:d0dfbce63a89 | 862 | |
| elmot | 1:d0dfbce63a89 | 863 | /* Set the Output Idle state */ |
| elmot | 1:d0dfbce63a89 | 864 | MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); |
| elmot | 1:d0dfbce63a89 | 865 | |
| elmot | 1:d0dfbce63a89 | 866 | /* Set the complementary output Idle state */ |
| elmot | 1:d0dfbce63a89 | 867 | MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); |
| elmot | 1:d0dfbce63a89 | 868 | } |
| elmot | 1:d0dfbce63a89 | 869 | |
| elmot | 1:d0dfbce63a89 | 870 | /* Write to TIMx CR2 */ |
| elmot | 1:d0dfbce63a89 | 871 | LL_TIM_WriteReg(TIMx, CR2, tmpcr2); |
| elmot | 1:d0dfbce63a89 | 872 | |
| elmot | 1:d0dfbce63a89 | 873 | /* Write to TIMx CCMR2 */ |
| elmot | 1:d0dfbce63a89 | 874 | LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); |
| elmot | 1:d0dfbce63a89 | 875 | |
| elmot | 1:d0dfbce63a89 | 876 | /* Set the Capture Compare Register value */ |
| elmot | 1:d0dfbce63a89 | 877 | LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); |
| elmot | 1:d0dfbce63a89 | 878 | |
| elmot | 1:d0dfbce63a89 | 879 | /* Write to TIMx CCER */ |
| elmot | 1:d0dfbce63a89 | 880 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
| elmot | 1:d0dfbce63a89 | 881 | |
| elmot | 1:d0dfbce63a89 | 882 | return SUCCESS; |
| elmot | 1:d0dfbce63a89 | 883 | } |
| elmot | 1:d0dfbce63a89 | 884 | |
| elmot | 1:d0dfbce63a89 | 885 | /** |
| elmot | 1:d0dfbce63a89 | 886 | * @brief Configure the TIMx output channel 4. |
| elmot | 1:d0dfbce63a89 | 887 | * @param TIMx Timer Instance |
| elmot | 1:d0dfbce63a89 | 888 | * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure |
| elmot | 1:d0dfbce63a89 | 889 | * @retval An ErrorStatus enumeration value: |
| elmot | 1:d0dfbce63a89 | 890 | * - SUCCESS: TIMx registers are de-initialized |
| elmot | 1:d0dfbce63a89 | 891 | * - ERROR: not applicable |
| elmot | 1:d0dfbce63a89 | 892 | */ |
| elmot | 1:d0dfbce63a89 | 893 | static ErrorStatus OC4Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct) |
| elmot | 1:d0dfbce63a89 | 894 | { |
| elmot | 1:d0dfbce63a89 | 895 | uint32_t tmpccmr2 = 0U; |
| elmot | 1:d0dfbce63a89 | 896 | uint32_t tmpccer = 0U; |
| elmot | 1:d0dfbce63a89 | 897 | uint32_t tmpcr2 = 0U; |
| elmot | 1:d0dfbce63a89 | 898 | |
| elmot | 1:d0dfbce63a89 | 899 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 900 | assert_param(IS_TIM_CC4_INSTANCE(TIMx)); |
| elmot | 1:d0dfbce63a89 | 901 | assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); |
| elmot | 1:d0dfbce63a89 | 902 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); |
| elmot | 1:d0dfbce63a89 | 903 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); |
| elmot | 1:d0dfbce63a89 | 904 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); |
| elmot | 1:d0dfbce63a89 | 905 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); |
| elmot | 1:d0dfbce63a89 | 906 | |
| elmot | 1:d0dfbce63a89 | 907 | /* Disable the Channel 4: Reset the CC4E Bit */ |
| elmot | 1:d0dfbce63a89 | 908 | CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); |
| elmot | 1:d0dfbce63a89 | 909 | |
| elmot | 1:d0dfbce63a89 | 910 | /* Get the TIMx CCER register value */ |
| elmot | 1:d0dfbce63a89 | 911 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
| elmot | 1:d0dfbce63a89 | 912 | |
| elmot | 1:d0dfbce63a89 | 913 | /* Get the TIMx CR2 register value */ |
| elmot | 1:d0dfbce63a89 | 914 | tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); |
| elmot | 1:d0dfbce63a89 | 915 | |
| elmot | 1:d0dfbce63a89 | 916 | /* Get the TIMx CCMR2 register value */ |
| elmot | 1:d0dfbce63a89 | 917 | tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); |
| elmot | 1:d0dfbce63a89 | 918 | |
| elmot | 1:d0dfbce63a89 | 919 | /* Reset Capture/Compare selection Bits */ |
| elmot | 1:d0dfbce63a89 | 920 | CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); |
| elmot | 1:d0dfbce63a89 | 921 | |
| elmot | 1:d0dfbce63a89 | 922 | /* Select the Output Compare Mode */ |
| elmot | 1:d0dfbce63a89 | 923 | MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); |
| elmot | 1:d0dfbce63a89 | 924 | |
| elmot | 1:d0dfbce63a89 | 925 | /* Set the Output Compare Polarity */ |
| elmot | 1:d0dfbce63a89 | 926 | MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); |
| elmot | 1:d0dfbce63a89 | 927 | |
| elmot | 1:d0dfbce63a89 | 928 | /* Set the Output State */ |
| elmot | 1:d0dfbce63a89 | 929 | MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); |
| elmot | 1:d0dfbce63a89 | 930 | |
| elmot | 1:d0dfbce63a89 | 931 | if(IS_TIM_BREAK_INSTANCE(TIMx)) |
| elmot | 1:d0dfbce63a89 | 932 | { |
| elmot | 1:d0dfbce63a89 | 933 | assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); |
| elmot | 1:d0dfbce63a89 | 934 | assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); |
| elmot | 1:d0dfbce63a89 | 935 | |
| elmot | 1:d0dfbce63a89 | 936 | /* Set the Output Idle state */ |
| elmot | 1:d0dfbce63a89 | 937 | MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); |
| elmot | 1:d0dfbce63a89 | 938 | } |
| elmot | 1:d0dfbce63a89 | 939 | |
| elmot | 1:d0dfbce63a89 | 940 | /* Write to TIMx CR2 */ |
| elmot | 1:d0dfbce63a89 | 941 | LL_TIM_WriteReg(TIMx, CR2, tmpcr2); |
| elmot | 1:d0dfbce63a89 | 942 | |
| elmot | 1:d0dfbce63a89 | 943 | /* Write to TIMx CCMR2 */ |
| elmot | 1:d0dfbce63a89 | 944 | LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); |
| elmot | 1:d0dfbce63a89 | 945 | |
| elmot | 1:d0dfbce63a89 | 946 | /* Set the Capture Compare Register value */ |
| elmot | 1:d0dfbce63a89 | 947 | LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); |
| elmot | 1:d0dfbce63a89 | 948 | |
| elmot | 1:d0dfbce63a89 | 949 | /* Write to TIMx CCER */ |
| elmot | 1:d0dfbce63a89 | 950 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
| elmot | 1:d0dfbce63a89 | 951 | |
| elmot | 1:d0dfbce63a89 | 952 | return SUCCESS; |
| elmot | 1:d0dfbce63a89 | 953 | } |
| elmot | 1:d0dfbce63a89 | 954 | |
| elmot | 1:d0dfbce63a89 | 955 | /** |
| elmot | 1:d0dfbce63a89 | 956 | * @brief Configure the TIMx output channel 5. |
| elmot | 1:d0dfbce63a89 | 957 | * @param TIMx Timer Instance |
| elmot | 1:d0dfbce63a89 | 958 | * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure |
| elmot | 1:d0dfbce63a89 | 959 | * @retval An ErrorStatus enumeration value: |
| elmot | 1:d0dfbce63a89 | 960 | * - SUCCESS: TIMx registers are de-initialized |
| elmot | 1:d0dfbce63a89 | 961 | * - ERROR: not applicable |
| elmot | 1:d0dfbce63a89 | 962 | */ |
| elmot | 1:d0dfbce63a89 | 963 | static ErrorStatus OC5Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct) |
| elmot | 1:d0dfbce63a89 | 964 | { |
| elmot | 1:d0dfbce63a89 | 965 | uint32_t tmpccmr3 = 0U; |
| elmot | 1:d0dfbce63a89 | 966 | uint32_t tmpccer = 0U; |
| elmot | 1:d0dfbce63a89 | 967 | |
| elmot | 1:d0dfbce63a89 | 968 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 969 | assert_param(IS_TIM_CC5_INSTANCE(TIMx)); |
| elmot | 1:d0dfbce63a89 | 970 | assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); |
| elmot | 1:d0dfbce63a89 | 971 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); |
| elmot | 1:d0dfbce63a89 | 972 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); |
| elmot | 1:d0dfbce63a89 | 973 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); |
| elmot | 1:d0dfbce63a89 | 974 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); |
| elmot | 1:d0dfbce63a89 | 975 | |
| elmot | 1:d0dfbce63a89 | 976 | /* Disable the Channel 5: Reset the CC5E Bit */ |
| elmot | 1:d0dfbce63a89 | 977 | CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); |
| elmot | 1:d0dfbce63a89 | 978 | |
| elmot | 1:d0dfbce63a89 | 979 | /* Get the TIMx CCER register value */ |
| elmot | 1:d0dfbce63a89 | 980 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
| elmot | 1:d0dfbce63a89 | 981 | |
| elmot | 1:d0dfbce63a89 | 982 | /* Get the TIMx CCMR3 register value */ |
| elmot | 1:d0dfbce63a89 | 983 | tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); |
| elmot | 1:d0dfbce63a89 | 984 | |
| elmot | 1:d0dfbce63a89 | 985 | /* Select the Output Compare Mode */ |
| elmot | 1:d0dfbce63a89 | 986 | MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode); |
| elmot | 1:d0dfbce63a89 | 987 | |
| elmot | 1:d0dfbce63a89 | 988 | /* Set the Output Compare Polarity */ |
| elmot | 1:d0dfbce63a89 | 989 | MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U); |
| elmot | 1:d0dfbce63a89 | 990 | |
| elmot | 1:d0dfbce63a89 | 991 | /* Set the Output State */ |
| elmot | 1:d0dfbce63a89 | 992 | MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U); |
| elmot | 1:d0dfbce63a89 | 993 | |
| elmot | 1:d0dfbce63a89 | 994 | if(IS_TIM_BREAK_INSTANCE(TIMx)) |
| elmot | 1:d0dfbce63a89 | 995 | { |
| elmot | 1:d0dfbce63a89 | 996 | assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); |
| elmot | 1:d0dfbce63a89 | 997 | assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); |
| elmot | 1:d0dfbce63a89 | 998 | |
| elmot | 1:d0dfbce63a89 | 999 | /* Set the Output Idle state */ |
| elmot | 1:d0dfbce63a89 | 1000 | MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U); |
| elmot | 1:d0dfbce63a89 | 1001 | |
| elmot | 1:d0dfbce63a89 | 1002 | } |
| elmot | 1:d0dfbce63a89 | 1003 | |
| elmot | 1:d0dfbce63a89 | 1004 | /* Write to TIMx CCMR3 */ |
| elmot | 1:d0dfbce63a89 | 1005 | LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); |
| elmot | 1:d0dfbce63a89 | 1006 | |
| elmot | 1:d0dfbce63a89 | 1007 | /* Set the Capture Compare Register value */ |
| elmot | 1:d0dfbce63a89 | 1008 | LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue); |
| elmot | 1:d0dfbce63a89 | 1009 | |
| elmot | 1:d0dfbce63a89 | 1010 | /* Write to TIMx CCER */ |
| elmot | 1:d0dfbce63a89 | 1011 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
| elmot | 1:d0dfbce63a89 | 1012 | |
| elmot | 1:d0dfbce63a89 | 1013 | return SUCCESS; |
| elmot | 1:d0dfbce63a89 | 1014 | } |
| elmot | 1:d0dfbce63a89 | 1015 | |
| elmot | 1:d0dfbce63a89 | 1016 | /** |
| elmot | 1:d0dfbce63a89 | 1017 | * @brief Configure the TIMx output channel 6. |
| elmot | 1:d0dfbce63a89 | 1018 | * @param TIMx Timer Instance |
| elmot | 1:d0dfbce63a89 | 1019 | * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure |
| elmot | 1:d0dfbce63a89 | 1020 | * @retval An ErrorStatus enumeration value: |
| elmot | 1:d0dfbce63a89 | 1021 | * - SUCCESS: TIMx registers are de-initialized |
| elmot | 1:d0dfbce63a89 | 1022 | * - ERROR: not applicable |
| elmot | 1:d0dfbce63a89 | 1023 | */ |
| elmot | 1:d0dfbce63a89 | 1024 | static ErrorStatus OC6Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct) |
| elmot | 1:d0dfbce63a89 | 1025 | { |
| elmot | 1:d0dfbce63a89 | 1026 | uint32_t tmpccmr3 = 0U; |
| elmot | 1:d0dfbce63a89 | 1027 | uint32_t tmpccer = 0U; |
| elmot | 1:d0dfbce63a89 | 1028 | |
| elmot | 1:d0dfbce63a89 | 1029 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 1030 | assert_param(IS_TIM_CC6_INSTANCE(TIMx)); |
| elmot | 1:d0dfbce63a89 | 1031 | assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); |
| elmot | 1:d0dfbce63a89 | 1032 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); |
| elmot | 1:d0dfbce63a89 | 1033 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); |
| elmot | 1:d0dfbce63a89 | 1034 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); |
| elmot | 1:d0dfbce63a89 | 1035 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); |
| elmot | 1:d0dfbce63a89 | 1036 | |
| elmot | 1:d0dfbce63a89 | 1037 | /* Disable the Channel 5: Reset the CC6E Bit */ |
| elmot | 1:d0dfbce63a89 | 1038 | CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); |
| elmot | 1:d0dfbce63a89 | 1039 | |
| elmot | 1:d0dfbce63a89 | 1040 | /* Get the TIMx CCER register value */ |
| elmot | 1:d0dfbce63a89 | 1041 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
| elmot | 1:d0dfbce63a89 | 1042 | |
| elmot | 1:d0dfbce63a89 | 1043 | /* Get the TIMx CCMR3 register value */ |
| elmot | 1:d0dfbce63a89 | 1044 | tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); |
| elmot | 1:d0dfbce63a89 | 1045 | |
| elmot | 1:d0dfbce63a89 | 1046 | /* Select the Output Compare Mode */ |
| elmot | 1:d0dfbce63a89 | 1047 | MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U); |
| elmot | 1:d0dfbce63a89 | 1048 | |
| elmot | 1:d0dfbce63a89 | 1049 | /* Set the Output Compare Polarity */ |
| elmot | 1:d0dfbce63a89 | 1050 | MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U); |
| elmot | 1:d0dfbce63a89 | 1051 | |
| elmot | 1:d0dfbce63a89 | 1052 | /* Set the Output State */ |
| elmot | 1:d0dfbce63a89 | 1053 | MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U); |
| elmot | 1:d0dfbce63a89 | 1054 | |
| elmot | 1:d0dfbce63a89 | 1055 | if(IS_TIM_BREAK_INSTANCE(TIMx)) |
| elmot | 1:d0dfbce63a89 | 1056 | { |
| elmot | 1:d0dfbce63a89 | 1057 | assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); |
| elmot | 1:d0dfbce63a89 | 1058 | assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); |
| elmot | 1:d0dfbce63a89 | 1059 | |
| elmot | 1:d0dfbce63a89 | 1060 | /* Set the Output Idle state */ |
| elmot | 1:d0dfbce63a89 | 1061 | MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U); |
| elmot | 1:d0dfbce63a89 | 1062 | } |
| elmot | 1:d0dfbce63a89 | 1063 | |
| elmot | 1:d0dfbce63a89 | 1064 | /* Write to TIMx CCMR3 */ |
| elmot | 1:d0dfbce63a89 | 1065 | LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); |
| elmot | 1:d0dfbce63a89 | 1066 | |
| elmot | 1:d0dfbce63a89 | 1067 | /* Set the Capture Compare Register value */ |
| elmot | 1:d0dfbce63a89 | 1068 | LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue); |
| elmot | 1:d0dfbce63a89 | 1069 | |
| elmot | 1:d0dfbce63a89 | 1070 | /* Write to TIMx CCER */ |
| elmot | 1:d0dfbce63a89 | 1071 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
| elmot | 1:d0dfbce63a89 | 1072 | |
| elmot | 1:d0dfbce63a89 | 1073 | return SUCCESS; |
| elmot | 1:d0dfbce63a89 | 1074 | } |
| elmot | 1:d0dfbce63a89 | 1075 | |
| elmot | 1:d0dfbce63a89 | 1076 | /** |
| elmot | 1:d0dfbce63a89 | 1077 | * @brief Configure the TIMx input channel 1. |
| elmot | 1:d0dfbce63a89 | 1078 | * @param TIMx Timer Instance |
| elmot | 1:d0dfbce63a89 | 1079 | * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure |
| elmot | 1:d0dfbce63a89 | 1080 | * @retval An ErrorStatus enumeration value: |
| elmot | 1:d0dfbce63a89 | 1081 | * - SUCCESS: TIMx registers are de-initialized |
| elmot | 1:d0dfbce63a89 | 1082 | * - ERROR: not applicable |
| elmot | 1:d0dfbce63a89 | 1083 | */ |
| elmot | 1:d0dfbce63a89 | 1084 | static ErrorStatus IC1Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct) |
| elmot | 1:d0dfbce63a89 | 1085 | { |
| elmot | 1:d0dfbce63a89 | 1086 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 1087 | assert_param(IS_TIM_CC1_INSTANCE(TIMx)); |
| elmot | 1:d0dfbce63a89 | 1088 | assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); |
| elmot | 1:d0dfbce63a89 | 1089 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); |
| elmot | 1:d0dfbce63a89 | 1090 | assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); |
| elmot | 1:d0dfbce63a89 | 1091 | assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); |
| elmot | 1:d0dfbce63a89 | 1092 | |
| elmot | 1:d0dfbce63a89 | 1093 | /* Disable the Channel 1: Reset the CC1E Bit */ |
| elmot | 1:d0dfbce63a89 | 1094 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; |
| elmot | 1:d0dfbce63a89 | 1095 | |
| elmot | 1:d0dfbce63a89 | 1096 | /* Select the Input and set the filter and the prescaler value */ |
| elmot | 1:d0dfbce63a89 | 1097 | MODIFY_REG(TIMx->CCMR1, |
| elmot | 1:d0dfbce63a89 | 1098 | (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), |
| elmot | 1:d0dfbce63a89 | 1099 | (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); |
| elmot | 1:d0dfbce63a89 | 1100 | |
| elmot | 1:d0dfbce63a89 | 1101 | /* Select the Polarity and set the CC1E Bit */ |
| elmot | 1:d0dfbce63a89 | 1102 | MODIFY_REG(TIMx->CCER, |
| elmot | 1:d0dfbce63a89 | 1103 | (TIM_CCER_CC1P | TIM_CCER_CC1NP), |
| elmot | 1:d0dfbce63a89 | 1104 | (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); |
| elmot | 1:d0dfbce63a89 | 1105 | |
| elmot | 1:d0dfbce63a89 | 1106 | return SUCCESS; |
| elmot | 1:d0dfbce63a89 | 1107 | } |
| elmot | 1:d0dfbce63a89 | 1108 | |
| elmot | 1:d0dfbce63a89 | 1109 | /** |
| elmot | 1:d0dfbce63a89 | 1110 | * @brief Configure the TIMx input channel 2. |
| elmot | 1:d0dfbce63a89 | 1111 | * @param TIMx Timer Instance |
| elmot | 1:d0dfbce63a89 | 1112 | * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure |
| elmot | 1:d0dfbce63a89 | 1113 | * @retval An ErrorStatus enumeration value: |
| elmot | 1:d0dfbce63a89 | 1114 | * - SUCCESS: TIMx registers are de-initialized |
| elmot | 1:d0dfbce63a89 | 1115 | * - ERROR: not applicable |
| elmot | 1:d0dfbce63a89 | 1116 | */ |
| elmot | 1:d0dfbce63a89 | 1117 | static ErrorStatus IC2Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct) |
| elmot | 1:d0dfbce63a89 | 1118 | { |
| elmot | 1:d0dfbce63a89 | 1119 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 1120 | assert_param(IS_TIM_CC2_INSTANCE(TIMx)); |
| elmot | 1:d0dfbce63a89 | 1121 | assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); |
| elmot | 1:d0dfbce63a89 | 1122 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); |
| elmot | 1:d0dfbce63a89 | 1123 | assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); |
| elmot | 1:d0dfbce63a89 | 1124 | assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); |
| elmot | 1:d0dfbce63a89 | 1125 | |
| elmot | 1:d0dfbce63a89 | 1126 | /* Disable the Channel 2: Reset the CC2E Bit */ |
| elmot | 1:d0dfbce63a89 | 1127 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; |
| elmot | 1:d0dfbce63a89 | 1128 | |
| elmot | 1:d0dfbce63a89 | 1129 | /* Select the Input and set the filter and the prescaler value */ |
| elmot | 1:d0dfbce63a89 | 1130 | MODIFY_REG(TIMx->CCMR1, |
| elmot | 1:d0dfbce63a89 | 1131 | (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), |
| elmot | 1:d0dfbce63a89 | 1132 | (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); |
| elmot | 1:d0dfbce63a89 | 1133 | |
| elmot | 1:d0dfbce63a89 | 1134 | /* Select the Polarity and set the CC2E Bit */ |
| elmot | 1:d0dfbce63a89 | 1135 | MODIFY_REG(TIMx->CCER, |
| elmot | 1:d0dfbce63a89 | 1136 | (TIM_CCER_CC2P | TIM_CCER_CC2NP), |
| elmot | 1:d0dfbce63a89 | 1137 | ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E) ); |
| elmot | 1:d0dfbce63a89 | 1138 | |
| elmot | 1:d0dfbce63a89 | 1139 | return SUCCESS; |
| elmot | 1:d0dfbce63a89 | 1140 | } |
| elmot | 1:d0dfbce63a89 | 1141 | |
| elmot | 1:d0dfbce63a89 | 1142 | /** |
| elmot | 1:d0dfbce63a89 | 1143 | * @brief Configure the TIMx input channel 3. |
| elmot | 1:d0dfbce63a89 | 1144 | * @param TIMx Timer Instance |
| elmot | 1:d0dfbce63a89 | 1145 | * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure |
| elmot | 1:d0dfbce63a89 | 1146 | * @retval An ErrorStatus enumeration value: |
| elmot | 1:d0dfbce63a89 | 1147 | * - SUCCESS: TIMx registers are de-initialized |
| elmot | 1:d0dfbce63a89 | 1148 | * - ERROR: not applicable |
| elmot | 1:d0dfbce63a89 | 1149 | */ |
| elmot | 1:d0dfbce63a89 | 1150 | static ErrorStatus IC3Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct) |
| elmot | 1:d0dfbce63a89 | 1151 | { |
| elmot | 1:d0dfbce63a89 | 1152 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 1153 | assert_param(IS_TIM_CC3_INSTANCE(TIMx)); |
| elmot | 1:d0dfbce63a89 | 1154 | assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); |
| elmot | 1:d0dfbce63a89 | 1155 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); |
| elmot | 1:d0dfbce63a89 | 1156 | assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); |
| elmot | 1:d0dfbce63a89 | 1157 | assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); |
| elmot | 1:d0dfbce63a89 | 1158 | |
| elmot | 1:d0dfbce63a89 | 1159 | /* Disable the Channel 3: Reset the CC3E Bit */ |
| elmot | 1:d0dfbce63a89 | 1160 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; |
| elmot | 1:d0dfbce63a89 | 1161 | |
| elmot | 1:d0dfbce63a89 | 1162 | /* Select the Input and set the filter and the prescaler value */ |
| elmot | 1:d0dfbce63a89 | 1163 | MODIFY_REG(TIMx->CCMR2, |
| elmot | 1:d0dfbce63a89 | 1164 | (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), |
| elmot | 1:d0dfbce63a89 | 1165 | (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); |
| elmot | 1:d0dfbce63a89 | 1166 | |
| elmot | 1:d0dfbce63a89 | 1167 | /* Select the Polarity and set the CC3E Bit */ |
| elmot | 1:d0dfbce63a89 | 1168 | MODIFY_REG(TIMx->CCER, |
| elmot | 1:d0dfbce63a89 | 1169 | (TIM_CCER_CC3P | TIM_CCER_CC3NP), |
| elmot | 1:d0dfbce63a89 | 1170 | ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E) ); |
| elmot | 1:d0dfbce63a89 | 1171 | |
| elmot | 1:d0dfbce63a89 | 1172 | return SUCCESS; |
| elmot | 1:d0dfbce63a89 | 1173 | } |
| elmot | 1:d0dfbce63a89 | 1174 | |
| elmot | 1:d0dfbce63a89 | 1175 | /** |
| elmot | 1:d0dfbce63a89 | 1176 | * @brief Configure the TIMx input channel 4. |
| elmot | 1:d0dfbce63a89 | 1177 | * @param TIMx Timer Instance |
| elmot | 1:d0dfbce63a89 | 1178 | * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure |
| elmot | 1:d0dfbce63a89 | 1179 | * @retval An ErrorStatus enumeration value: |
| elmot | 1:d0dfbce63a89 | 1180 | * - SUCCESS: TIMx registers are de-initialized |
| elmot | 1:d0dfbce63a89 | 1181 | * - ERROR: not applicable |
| elmot | 1:d0dfbce63a89 | 1182 | */ |
| elmot | 1:d0dfbce63a89 | 1183 | static ErrorStatus IC4Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct) |
| elmot | 1:d0dfbce63a89 | 1184 | { |
| elmot | 1:d0dfbce63a89 | 1185 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 1186 | assert_param(IS_TIM_CC4_INSTANCE(TIMx)); |
| elmot | 1:d0dfbce63a89 | 1187 | assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); |
| elmot | 1:d0dfbce63a89 | 1188 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); |
| elmot | 1:d0dfbce63a89 | 1189 | assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); |
| elmot | 1:d0dfbce63a89 | 1190 | assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); |
| elmot | 1:d0dfbce63a89 | 1191 | |
| elmot | 1:d0dfbce63a89 | 1192 | /* Disable the Channel 4: Reset the CC4E Bit */ |
| elmot | 1:d0dfbce63a89 | 1193 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; |
| elmot | 1:d0dfbce63a89 | 1194 | |
| elmot | 1:d0dfbce63a89 | 1195 | /* Select the Input and set the filter and the prescaler value */ |
| elmot | 1:d0dfbce63a89 | 1196 | MODIFY_REG(TIMx->CCMR2, |
| elmot | 1:d0dfbce63a89 | 1197 | (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), |
| elmot | 1:d0dfbce63a89 | 1198 | (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); |
| elmot | 1:d0dfbce63a89 | 1199 | |
| elmot | 1:d0dfbce63a89 | 1200 | /* Select the Polarity and set the CC2E Bit */ |
| elmot | 1:d0dfbce63a89 | 1201 | MODIFY_REG(TIMx->CCER, |
| elmot | 1:d0dfbce63a89 | 1202 | (TIM_CCER_CC4P | TIM_CCER_CC4NP), |
| elmot | 1:d0dfbce63a89 | 1203 | ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E) ); |
| elmot | 1:d0dfbce63a89 | 1204 | |
| elmot | 1:d0dfbce63a89 | 1205 | return SUCCESS; |
| elmot | 1:d0dfbce63a89 | 1206 | } |
| elmot | 1:d0dfbce63a89 | 1207 | |
| elmot | 1:d0dfbce63a89 | 1208 | |
| elmot | 1:d0dfbce63a89 | 1209 | /** |
| elmot | 1:d0dfbce63a89 | 1210 | * @} |
| elmot | 1:d0dfbce63a89 | 1211 | */ |
| elmot | 1:d0dfbce63a89 | 1212 | |
| elmot | 1:d0dfbce63a89 | 1213 | /** |
| elmot | 1:d0dfbce63a89 | 1214 | * @} |
| elmot | 1:d0dfbce63a89 | 1215 | */ |
| elmot | 1:d0dfbce63a89 | 1216 | |
| elmot | 1:d0dfbce63a89 | 1217 | #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */ |
| elmot | 1:d0dfbce63a89 | 1218 | |
| elmot | 1:d0dfbce63a89 | 1219 | /** |
| elmot | 1:d0dfbce63a89 | 1220 | * @} |
| elmot | 1:d0dfbce63a89 | 1221 | */ |
| elmot | 1:d0dfbce63a89 | 1222 | |
| elmot | 1:d0dfbce63a89 | 1223 | #endif /* USE_FULL_LL_DRIVER */ |
| elmot | 1:d0dfbce63a89 | 1224 | |
| elmot | 1:d0dfbce63a89 | 1225 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |