TOMB / MFRC522

RFID

MFRC522.cpp@0:43065f3f9951, 2015-12-04 (annotated)

Committer:
Gennanio
Date:
Fri Dec 04 09:31:53 2015 +0000
Revision:
0:43065f3f9951
MFRC522

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Gennanio 0:43065f3f9951 1 /*
Gennanio 0:43065f3f9951 2 * MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
Gennanio 0:43065f3f9951 3 * _Please_ see the comments in MFRC522.h - they give useful hints and background.
Gennanio 0:43065f3f9951 4 * Released into the public domain.
Gennanio 0:43065f3f9951 5 */
Gennanio 0:43065f3f9951 6
Gennanio 0:43065f3f9951 7 #include "MFRC522.h"
Gennanio 0:43065f3f9951 8
Gennanio 0:43065f3f9951 9 static const char* const _TypeNamePICC[] =
Gennanio 0:43065f3f9951 10 {
Gennanio 0:43065f3f9951 11 "Unknown type",
Gennanio 0:43065f3f9951 12 "PICC compliant with ISO/IEC 14443-4",
Gennanio 0:43065f3f9951 13 "PICC compliant with ISO/IEC 18092 (NFC)",
Gennanio 0:43065f3f9951 14 "MIFARE Mini, 320 bytes",
Gennanio 0:43065f3f9951 15 "MIFARE 1KB",
Gennanio 0:43065f3f9951 16 "MIFARE 4KB",
Gennanio 0:43065f3f9951 17 "MIFARE Ultralight or Ultralight C",
Gennanio 0:43065f3f9951 18 "MIFARE Plus",
Gennanio 0:43065f3f9951 19 "MIFARE TNP3XXX",
Gennanio 0:43065f3f9951 20
Gennanio 0:43065f3f9951 21 /* not complete UID */
Gennanio 0:43065f3f9951 22 "SAK indicates UID is not complete"
Gennanio 0:43065f3f9951 23 };
Gennanio 0:43065f3f9951 24
Gennanio 0:43065f3f9951 25 static const char* const _ErrorMessage[] =
Gennanio 0:43065f3f9951 26 {
Gennanio 0:43065f3f9951 27 "Unknown error",
Gennanio 0:43065f3f9951 28 "Success",
Gennanio 0:43065f3f9951 29 "Error in communication",
Gennanio 0:43065f3f9951 30 "Collision detected",
Gennanio 0:43065f3f9951 31 "Timeout in communication",
Gennanio 0:43065f3f9951 32 "A buffer is not big enough",
Gennanio 0:43065f3f9951 33 "Internal error in the code, should not happen",
Gennanio 0:43065f3f9951 34 "Invalid argument",
Gennanio 0:43065f3f9951 35 "The CRC_A does not match",
Gennanio 0:43065f3f9951 36 "A MIFARE PICC responded with NAK"
Gennanio 0:43065f3f9951 37 };
Gennanio 0:43065f3f9951 38
Gennanio 0:43065f3f9951 39 #define MFRC522_MaxPICCs (sizeof(_TypeNamePICC)/sizeof(_TypeNamePICC[0]))
Gennanio 0:43065f3f9951 40 #define MFRC522_MaxError (sizeof(_ErrorMessage)/sizeof(_ErrorMessage[0]))
Gennanio 0:43065f3f9951 41
Gennanio 0:43065f3f9951 42 /////////////////////////////////////////////////////////////////////////////////////
Gennanio 0:43065f3f9951 43 // Functions for setting up the driver
Gennanio 0:43065f3f9951 44 /////////////////////////////////////////////////////////////////////////////////////
Gennanio 0:43065f3f9951 45
Gennanio 0:43065f3f9951 46 /**
Gennanio 0:43065f3f9951 47 * Constructor.
Gennanio 0:43065f3f9951 48 * Prepares the output pins.
Gennanio 0:43065f3f9951 49 */
Gennanio 0:43065f3f9951 50 MFRC522::MFRC522(PinName mosi,
Gennanio 0:43065f3f9951 51 PinName miso,
Gennanio 0:43065f3f9951 52 PinName sclk,
Gennanio 0:43065f3f9951 53 PinName cs,
Gennanio 0:43065f3f9951 54 PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset)
Gennanio 0:43065f3f9951 55 {
Gennanio 0:43065f3f9951 56 /* Configure SPI bus */
Gennanio 0:43065f3f9951 57 m_SPI.format(8, 0);
Gennanio 0:43065f3f9951 58 m_SPI.frequency(8000000);
Gennanio 0:43065f3f9951 59
Gennanio 0:43065f3f9951 60 /* Release SPI-CS pin */
Gennanio 0:43065f3f9951 61 m_CS = 1;
Gennanio 0:43065f3f9951 62
Gennanio 0:43065f3f9951 63 /* Release RESET pin */
Gennanio 0:43065f3f9951 64 m_RESET = 1;
Gennanio 0:43065f3f9951 65 } // End constructor
Gennanio 0:43065f3f9951 66
Gennanio 0:43065f3f9951 67
Gennanio 0:43065f3f9951 68 /**
Gennanio 0:43065f3f9951 69 * Destructor.
Gennanio 0:43065f3f9951 70 */
Gennanio 0:43065f3f9951 71 MFRC522::~MFRC522()
Gennanio 0:43065f3f9951 72 {
Gennanio 0:43065f3f9951 73
Gennanio 0:43065f3f9951 74 }
Gennanio 0:43065f3f9951 75
Gennanio 0:43065f3f9951 76
Gennanio 0:43065f3f9951 77 /////////////////////////////////////////////////////////////////////////////////////
Gennanio 0:43065f3f9951 78 // Basic interface functions for communicating with the MFRC522
Gennanio 0:43065f3f9951 79 /////////////////////////////////////////////////////////////////////////////////////
Gennanio 0:43065f3f9951 80
Gennanio 0:43065f3f9951 81 /**
Gennanio 0:43065f3f9951 82 * Writes a byte to the specified register in the MFRC522 chip.
Gennanio 0:43065f3f9951 83 * The interface is described in the datasheet section 8.1.2.
Gennanio 0:43065f3f9951 84 */
Gennanio 0:43065f3f9951 85 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value)
Gennanio 0:43065f3f9951 86 {
Gennanio 0:43065f3f9951 87 m_CS = 0; /* Select SPI Chip MFRC522 */
Gennanio 0:43065f3f9951 88
Gennanio 0:43065f3f9951 89 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
Gennanio 0:43065f3f9951 90 (void) m_SPI.write(reg & 0x7E);
Gennanio 0:43065f3f9951 91 (void) m_SPI.write(value);
Gennanio 0:43065f3f9951 92
Gennanio 0:43065f3f9951 93 m_CS = 1; /* Release SPI Chip MFRC522 */
Gennanio 0:43065f3f9951 94 } // End PCD_WriteRegister()
Gennanio 0:43065f3f9951 95
Gennanio 0:43065f3f9951 96 /**
Gennanio 0:43065f3f9951 97 * Writes a number of bytes to the specified register in the MFRC522 chip.
Gennanio 0:43065f3f9951 98 * The interface is described in the datasheet section 8.1.2.
Gennanio 0:43065f3f9951 99 */
Gennanio 0:43065f3f9951 100 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values)
Gennanio 0:43065f3f9951 101 {
Gennanio 0:43065f3f9951 102 m_CS = 0; /* Select SPI Chip MFRC522 */
Gennanio 0:43065f3f9951 103
Gennanio 0:43065f3f9951 104 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
Gennanio 0:43065f3f9951 105 (void) m_SPI.write(reg & 0x7E);
Gennanio 0:43065f3f9951 106 for (uint8_t index = 0; index < count; index++)
Gennanio 0:43065f3f9951 107 {
Gennanio 0:43065f3f9951 108 (void) m_SPI.write(values[index]);
Gennanio 0:43065f3f9951 109 }
Gennanio 0:43065f3f9951 110
Gennanio 0:43065f3f9951 111 m_CS = 1; /* Release SPI Chip MFRC522 */
Gennanio 0:43065f3f9951 112 } // End PCD_WriteRegister()
Gennanio 0:43065f3f9951 113
Gennanio 0:43065f3f9951 114 /**
Gennanio 0:43065f3f9951 115 * Reads a byte from the specified register in the MFRC522 chip.
Gennanio 0:43065f3f9951 116 * The interface is described in the datasheet section 8.1.2.
Gennanio 0:43065f3f9951 117 */
Gennanio 0:43065f3f9951 118 uint8_t MFRC522::PCD_ReadRegister(uint8_t reg)
Gennanio 0:43065f3f9951 119 {
Gennanio 0:43065f3f9951 120 uint8_t value;
Gennanio 0:43065f3f9951 121 m_CS = 0; /* Select SPI Chip MFRC522 */
Gennanio 0:43065f3f9951 122
Gennanio 0:43065f3f9951 123 // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
Gennanio 0:43065f3f9951 124 (void) m_SPI.write(0x80 | reg);
Gennanio 0:43065f3f9951 125
Gennanio 0:43065f3f9951 126 // Read the value back. Send 0 to stop reading.
Gennanio 0:43065f3f9951 127 value = m_SPI.write(0);
Gennanio 0:43065f3f9951 128
Gennanio 0:43065f3f9951 129 m_CS = 1; /* Release SPI Chip MFRC522 */
Gennanio 0:43065f3f9951 130
Gennanio 0:43065f3f9951 131 return value;
Gennanio 0:43065f3f9951 132 } // End PCD_ReadRegister()
Gennanio 0:43065f3f9951 133
Gennanio 0:43065f3f9951 134 /**
Gennanio 0:43065f3f9951 135 * Reads a number of bytes from the specified register in the MFRC522 chip.
Gennanio 0:43065f3f9951 136 * The interface is described in the datasheet section 8.1.2.
Gennanio 0:43065f3f9951 137 */
Gennanio 0:43065f3f9951 138 void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign)
Gennanio 0:43065f3f9951 139 {
Gennanio 0:43065f3f9951 140 if (count == 0) { return; }
Gennanio 0:43065f3f9951 141
Gennanio 0:43065f3f9951 142 uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
Gennanio 0:43065f3f9951 143 uint8_t index = 0; // Index in values array.
Gennanio 0:43065f3f9951 144
Gennanio 0:43065f3f9951 145 m_CS = 0; /* Select SPI Chip MFRC522 */
Gennanio 0:43065f3f9951 146 count--; // One read is performed outside of the loop
Gennanio 0:43065f3f9951 147 (void) m_SPI.write(address); // Tell MFRC522 which address we want to read
Gennanio 0:43065f3f9951 148
Gennanio 0:43065f3f9951 149 while (index < count)
Gennanio 0:43065f3f9951 150 {
Gennanio 0:43065f3f9951 151 if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0]
Gennanio 0:43065f3f9951 152 {
Gennanio 0:43065f3f9951 153 // Create bit mask for bit positions rxAlign..7
Gennanio 0:43065f3f9951 154 uint8_t mask = 0;
Gennanio 0:43065f3f9951 155 for (uint8_t i = rxAlign; i <= 7; i++)
Gennanio 0:43065f3f9951 156 {
Gennanio 0:43065f3f9951 157 mask |= (1 << i);
Gennanio 0:43065f3f9951 158 }
Gennanio 0:43065f3f9951 159
Gennanio 0:43065f3f9951 160 // Read value and tell that we want to read the same address again.
Gennanio 0:43065f3f9951 161 uint8_t value = m_SPI.write(address);
Gennanio 0:43065f3f9951 162
Gennanio 0:43065f3f9951 163 // Apply mask to both current value of values[0] and the new data in value.
Gennanio 0:43065f3f9951 164 values[0] = (values[index] & ~mask) | (value & mask);
Gennanio 0:43065f3f9951 165 }
Gennanio 0:43065f3f9951 166 else
Gennanio 0:43065f3f9951 167 {
Gennanio 0:43065f3f9951 168 // Read value and tell that we want to read the same address again.
Gennanio 0:43065f3f9951 169 values[index] = m_SPI.write(address);
Gennanio 0:43065f3f9951 170 }
Gennanio 0:43065f3f9951 171
Gennanio 0:43065f3f9951 172 index++;
Gennanio 0:43065f3f9951 173 }
Gennanio 0:43065f3f9951 174
Gennanio 0:43065f3f9951 175 values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading.
Gennanio 0:43065f3f9951 176
Gennanio 0:43065f3f9951 177 m_CS = 1; /* Release SPI Chip MFRC522 */
Gennanio 0:43065f3f9951 178 } // End PCD_ReadRegister()
Gennanio 0:43065f3f9951 179
Gennanio 0:43065f3f9951 180 /**
Gennanio 0:43065f3f9951 181 * Sets the bits given in mask in register reg.
Gennanio 0:43065f3f9951 182 */
Gennanio 0:43065f3f9951 183 void MFRC522::PCD_SetRegisterBits(uint8_t reg, uint8_t mask)
Gennanio 0:43065f3f9951 184 {
Gennanio 0:43065f3f9951 185 uint8_t tmp = PCD_ReadRegister(reg);
Gennanio 0:43065f3f9951 186 PCD_WriteRegister(reg, tmp | mask); // set bit mask
Gennanio 0:43065f3f9951 187 } // End PCD_SetRegisterBitMask()
Gennanio 0:43065f3f9951 188
Gennanio 0:43065f3f9951 189 /**
Gennanio 0:43065f3f9951 190 * Clears the bits given in mask from register reg.
Gennanio 0:43065f3f9951 191 */
Gennanio 0:43065f3f9951 192 void MFRC522::PCD_ClrRegisterBits(uint8_t reg, uint8_t mask)
Gennanio 0:43065f3f9951 193 {
Gennanio 0:43065f3f9951 194 uint8_t tmp = PCD_ReadRegister(reg);
Gennanio 0:43065f3f9951 195 PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask
Gennanio 0:43065f3f9951 196 } // End PCD_ClearRegisterBitMask()
Gennanio 0:43065f3f9951 197
Gennanio 0:43065f3f9951 198
Gennanio 0:43065f3f9951 199 /**
Gennanio 0:43065f3f9951 200 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
Gennanio 0:43065f3f9951 201 */
Gennanio 0:43065f3f9951 202 uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result)
Gennanio 0:43065f3f9951 203 {
Gennanio 0:43065f3f9951 204 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
Gennanio 0:43065f3f9951 205 PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
Gennanio 0:43065f3f9951 206 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
Gennanio 0:43065f3f9951 207 PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO
Gennanio 0:43065f3f9951 208 PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation
Gennanio 0:43065f3f9951 209
Gennanio 0:43065f3f9951 210 // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73us.
Gennanio 0:43065f3f9951 211 uint16_t i = 5000;
Gennanio 0:43065f3f9951 212 uint8_t n;
Gennanio 0:43065f3f9951 213 while (1)
Gennanio 0:43065f3f9951 214 {
Gennanio 0:43065f3f9951 215 n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
Gennanio 0:43065f3f9951 216 if (n & 0x04)
Gennanio 0:43065f3f9951 217 {
Gennanio 0:43065f3f9951 218 // CRCIRq bit set - calculation done
Gennanio 0:43065f3f9951 219 break;
Gennanio 0:43065f3f9951 220 }
Gennanio 0:43065f3f9951 221
Gennanio 0:43065f3f9951 222 if (--i == 0)
Gennanio 0:43065f3f9951 223 {
Gennanio 0:43065f3f9951 224 // The emergency break. We will eventually terminate on this one after 89ms.
Gennanio 0:43065f3f9951 225 // Communication with the MFRC522 might be down.
Gennanio 0:43065f3f9951 226 return STATUS_TIMEOUT;
Gennanio 0:43065f3f9951 227 }
Gennanio 0:43065f3f9951 228 }
Gennanio 0:43065f3f9951 229
Gennanio 0:43065f3f9951 230 // Stop calculating CRC for new content in the FIFO.
Gennanio 0:43065f3f9951 231 PCD_WriteRegister(CommandReg, PCD_Idle);
Gennanio 0:43065f3f9951 232
Gennanio 0:43065f3f9951 233 // Transfer the result from the registers to the result buffer
Gennanio 0:43065f3f9951 234 result[0] = PCD_ReadRegister(CRCResultRegL);
Gennanio 0:43065f3f9951 235 result[1] = PCD_ReadRegister(CRCResultRegH);
Gennanio 0:43065f3f9951 236 return STATUS_OK;
Gennanio 0:43065f3f9951 237 } // End PCD_CalculateCRC()
Gennanio 0:43065f3f9951 238
Gennanio 0:43065f3f9951 239
Gennanio 0:43065f3f9951 240 /////////////////////////////////////////////////////////////////////////////////////
Gennanio 0:43065f3f9951 241 // Functions for manipulating the MFRC522
Gennanio 0:43065f3f9951 242 /////////////////////////////////////////////////////////////////////////////////////
Gennanio 0:43065f3f9951 243
Gennanio 0:43065f3f9951 244 /**
Gennanio 0:43065f3f9951 245 * Initializes the MFRC522 chip.
Gennanio 0:43065f3f9951 246 */
Gennanio 0:43065f3f9951 247 void MFRC522::PCD_Init()
Gennanio 0:43065f3f9951 248 {
Gennanio 0:43065f3f9951 249 /* Reset MFRC522 */
Gennanio 0:43065f3f9951 250 m_RESET = 0;
Gennanio 0:43065f3f9951 251 wait_ms(10);
Gennanio 0:43065f3f9951 252 m_RESET = 1;
Gennanio 0:43065f3f9951 253
Gennanio 0:43065f3f9951 254 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
Gennanio 0:43065f3f9951 255 wait_ms(50);
Gennanio 0:43065f3f9951 256
Gennanio 0:43065f3f9951 257 // When communicating with a PICC we need a timeout if something goes wrong.
Gennanio 0:43065f3f9951 258 // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
Gennanio 0:43065f3f9951 259 // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
Gennanio 0:43065f3f9951 260 PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
Gennanio 0:43065f3f9951 261 PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25us.
Gennanio 0:43065f3f9951 262 PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
Gennanio 0:43065f3f9951 263 PCD_WriteRegister(TReloadRegL, 0xE8);
Gennanio 0:43065f3f9951 264
Gennanio 0:43065f3f9951 265 PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
Gennanio 0:43065f3f9951 266 PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
Gennanio 0:43065f3f9951 267
Gennanio 0:43065f3f9951 268 PCD_WriteRegister(RFCfgReg, (0x07<<4)); // Set Rx Gain to max
Gennanio 0:43065f3f9951 269
Gennanio 0:43065f3f9951 270 PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
Gennanio 0:43065f3f9951 271 } // End PCD_Init()
Gennanio 0:43065f3f9951 272
Gennanio 0:43065f3f9951 273 /**
Gennanio 0:43065f3f9951 274 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
Gennanio 0:43065f3f9951 275 */
Gennanio 0:43065f3f9951 276 void MFRC522::PCD_Reset()
Gennanio 0:43065f3f9951 277 {
Gennanio 0:43065f3f9951 278 PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
Gennanio 0:43065f3f9951 279 // The datasheet does not mention how long the SoftRest command takes to complete.
Gennanio 0:43065f3f9951 280 // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
Gennanio 0:43065f3f9951 281 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
Gennanio 0:43065f3f9951 282 wait_ms(50);
Gennanio 0:43065f3f9951 283
Gennanio 0:43065f3f9951 284 // Wait for the PowerDown bit in CommandReg to be cleared
Gennanio 0:43065f3f9951 285 while (PCD_ReadRegister(CommandReg) & (1<<4))
Gennanio 0:43065f3f9951 286 {
Gennanio 0:43065f3f9951 287 // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry.
Gennanio 0:43065f3f9951 288 }
Gennanio 0:43065f3f9951 289 } // End PCD_Reset()
Gennanio 0:43065f3f9951 290
Gennanio 0:43065f3f9951 291 /**
Gennanio 0:43065f3f9951 292 * Turns the antenna on by enabling pins TX1 and TX2.
Gennanio 0:43065f3f9951 293 * After a reset these pins disabled.
Gennanio 0:43065f3f9951 294 */
Gennanio 0:43065f3f9951 295 void MFRC522::PCD_AntennaOn()
Gennanio 0:43065f3f9951 296 {
Gennanio 0:43065f3f9951 297 uint8_t value = PCD_ReadRegister(TxControlReg);
Gennanio 0:43065f3f9951 298 if ((value & 0x03) != 0x03)
Gennanio 0:43065f3f9951 299 {
Gennanio 0:43065f3f9951 300 PCD_WriteRegister(TxControlReg, value | 0x03);
Gennanio 0:43065f3f9951 301 }
Gennanio 0:43065f3f9951 302 } // End PCD_AntennaOn()
Gennanio 0:43065f3f9951 303
Gennanio 0:43065f3f9951 304 /////////////////////////////////////////////////////////////////////////////////////
Gennanio 0:43065f3f9951 305 // Functions for communicating with PICCs
Gennanio 0:43065f3f9951 306 /////////////////////////////////////////////////////////////////////////////////////
Gennanio 0:43065f3f9951 307
Gennanio 0:43065f3f9951 308 /**
Gennanio 0:43065f3f9951 309 * Executes the Transceive command.
Gennanio 0:43065f3f9951 310 * CRC validation can only be done if backData and backLen are specified.
Gennanio 0:43065f3f9951 311 */
Gennanio 0:43065f3f9951 312 uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData,
Gennanio 0:43065f3f9951 313 uint8_t sendLen,
Gennanio 0:43065f3f9951 314 uint8_t *backData,
Gennanio 0:43065f3f9951 315 uint8_t *backLen,
Gennanio 0:43065f3f9951 316 uint8_t *validBits,
Gennanio 0:43065f3f9951 317 uint8_t rxAlign,
Gennanio 0:43065f3f9951 318 bool checkCRC)
Gennanio 0:43065f3f9951 319 {
Gennanio 0:43065f3f9951 320 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
Gennanio 0:43065f3f9951 321 return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC);
Gennanio 0:43065f3f9951 322 } // End PCD_TransceiveData()
Gennanio 0:43065f3f9951 323
Gennanio 0:43065f3f9951 324 /**
Gennanio 0:43065f3f9951 325 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
Gennanio 0:43065f3f9951 326 * CRC validation can only be done if backData and backLen are specified.
Gennanio 0:43065f3f9951 327 */
Gennanio 0:43065f3f9951 328 uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command,
Gennanio 0:43065f3f9951 329 uint8_t waitIRq,
Gennanio 0:43065f3f9951 330 uint8_t *sendData,
Gennanio 0:43065f3f9951 331 uint8_t sendLen,
Gennanio 0:43065f3f9951 332 uint8_t *backData,
Gennanio 0:43065f3f9951 333 uint8_t *backLen,
Gennanio 0:43065f3f9951 334 uint8_t *validBits,
Gennanio 0:43065f3f9951 335 uint8_t rxAlign,
Gennanio 0:43065f3f9951 336 bool checkCRC)
Gennanio 0:43065f3f9951 337 {
Gennanio 0:43065f3f9951 338 uint8_t n, _validBits = 0;
Gennanio 0:43065f3f9951 339 uint32_t i;
Gennanio 0:43065f3f9951 340
Gennanio 0:43065f3f9951 341 // Prepare values for BitFramingReg
Gennanio 0:43065f3f9951 342 uint8_t txLastBits = validBits ? *validBits : 0;
Gennanio 0:43065f3f9951 343 uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
Gennanio 0:43065f3f9951 344
Gennanio 0:43065f3f9951 345 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
Gennanio 0:43065f3f9951 346 PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
Gennanio 0:43065f3f9951 347 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
Gennanio 0:43065f3f9951 348 PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO
Gennanio 0:43065f3f9951 349 PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments
Gennanio 0:43065f3f9951 350 PCD_WriteRegister(CommandReg, command); // Execute the command
Gennanio 0:43065f3f9951 351 if (command == PCD_Transceive)
Gennanio 0:43065f3f9951 352 {
Gennanio 0:43065f3f9951 353 PCD_SetRegisterBits(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
Gennanio 0:43065f3f9951 354 }
Gennanio 0:43065f3f9951 355
Gennanio 0:43065f3f9951 356 // Wait for the command to complete.
Gennanio 0:43065f3f9951 357 // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
Gennanio 0:43065f3f9951 358 // Each iteration of the do-while-loop takes 17.86us.
Gennanio 0:43065f3f9951 359 i = 2000;
Gennanio 0:43065f3f9951 360 while (1)
Gennanio 0:43065f3f9951 361 {
Gennanio 0:43065f3f9951 362 n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
Gennanio 0:43065f3f9951 363 if (n & waitIRq)
Gennanio 0:43065f3f9951 364 { // One of the interrupts that signal success has been set.
Gennanio 0:43065f3f9951 365 break;
Gennanio 0:43065f3f9951 366 }
Gennanio 0:43065f3f9951 367
Gennanio 0:43065f3f9951 368 if (n & 0x01)
Gennanio 0:43065f3f9951 369 { // Timer interrupt - nothing received in 25ms
Gennanio 0:43065f3f9951 370 return STATUS_TIMEOUT;
Gennanio 0:43065f3f9951 371 }
Gennanio 0:43065f3f9951 372
Gennanio 0:43065f3f9951 373 if (--i == 0)
Gennanio 0:43065f3f9951 374 { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down.
Gennanio 0:43065f3f9951 375 return STATUS_TIMEOUT;
Gennanio 0:43065f3f9951 376 }
Gennanio 0:43065f3f9951 377 }
Gennanio 0:43065f3f9951 378
Gennanio 0:43065f3f9951 379 // Stop now if any errors except collisions were detected.
Gennanio 0:43065f3f9951 380 uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
Gennanio 0:43065f3f9951 381 if (errorRegValue & 0x13)
Gennanio 0:43065f3f9951 382 { // BufferOvfl ParityErr ProtocolErr
Gennanio 0:43065f3f9951 383 return STATUS_ERROR;
Gennanio 0:43065f3f9951 384 }
Gennanio 0:43065f3f9951 385
Gennanio 0:43065f3f9951 386 // If the caller wants data back, get it from the MFRC522.
Gennanio 0:43065f3f9951 387 if (backData && backLen)
Gennanio 0:43065f3f9951 388 {
Gennanio 0:43065f3f9951 389 n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO
Gennanio 0:43065f3f9951 390 if (n > *backLen)
Gennanio 0:43065f3f9951 391 {
Gennanio 0:43065f3f9951 392 return STATUS_NO_ROOM;
Gennanio 0:43065f3f9951 393 }
Gennanio 0:43065f3f9951 394
Gennanio 0:43065f3f9951 395 *backLen = n; // Number of bytes returned
Gennanio 0:43065f3f9951 396 PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO
Gennanio 0:43065f3f9951 397 _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
Gennanio 0:43065f3f9951 398 if (validBits)
Gennanio 0:43065f3f9951 399 {
Gennanio 0:43065f3f9951 400 *validBits = _validBits;
Gennanio 0:43065f3f9951 401 }
Gennanio 0:43065f3f9951 402 }
Gennanio 0:43065f3f9951 403
Gennanio 0:43065f3f9951 404 // Tell about collisions
Gennanio 0:43065f3f9951 405 if (errorRegValue & 0x08)
Gennanio 0:43065f3f9951 406 { // CollErr
Gennanio 0:43065f3f9951 407 return STATUS_COLLISION;
Gennanio 0:43065f3f9951 408 }
Gennanio 0:43065f3f9951 409
Gennanio 0:43065f3f9951 410 // Perform CRC_A validation if requested.
Gennanio 0:43065f3f9951 411 if (backData && backLen && checkCRC)
Gennanio 0:43065f3f9951 412 {
Gennanio 0:43065f3f9951 413 // In this case a MIFARE Classic NAK is not OK.
Gennanio 0:43065f3f9951 414 if ((*backLen == 1) && (_validBits == 4))
Gennanio 0:43065f3f9951 415 {
Gennanio 0:43065f3f9951 416 return STATUS_MIFARE_NACK;
Gennanio 0:43065f3f9951 417 }
Gennanio 0:43065f3f9951 418
Gennanio 0:43065f3f9951 419 // We need at least the CRC_A value and all 8 bits of the last byte must be received.
Gennanio 0:43065f3f9951 420 if ((*backLen < 2) || (_validBits != 0))
Gennanio 0:43065f3f9951 421 {
Gennanio 0:43065f3f9951 422 return STATUS_CRC_WRONG;
Gennanio 0:43065f3f9951 423 }
Gennanio 0:43065f3f9951 424
Gennanio 0:43065f3f9951 425 // Verify CRC_A - do our own calculation and store the control in controlBuffer.
Gennanio 0:43065f3f9951 426 uint8_t controlBuffer[2];
Gennanio 0:43065f3f9951 427 n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]);
Gennanio 0:43065f3f9951 428 if (n != STATUS_OK)
Gennanio 0:43065f3f9951 429 {
Gennanio 0:43065f3f9951 430 return n;
Gennanio 0:43065f3f9951 431 }
Gennanio 0:43065f3f9951 432
Gennanio 0:43065f3f9951 433 if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1]))
Gennanio 0:43065f3f9951 434 {
Gennanio 0:43065f3f9951 435 return STATUS_CRC_WRONG;
Gennanio 0:43065f3f9951 436 }
Gennanio 0:43065f3f9951 437 }
Gennanio 0:43065f3f9951 438
Gennanio 0:43065f3f9951 439 return STATUS_OK;
Gennanio 0:43065f3f9951 440 } // End PCD_CommunicateWithPICC()
Gennanio 0:43065f3f9951 441
Gennanio 0:43065f3f9951 442 /*
Gennanio 0:43065f3f9951 443 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
Gennanio 0:43065f3f9951 444 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
Gennanio 0:43065f3f9951 445 */
Gennanio 0:43065f3f9951 446 uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize)
Gennanio 0:43065f3f9951 447 {
Gennanio 0:43065f3f9951 448 return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize);
Gennanio 0:43065f3f9951 449 } // End PICC_RequestA()
Gennanio 0:43065f3f9951 450
Gennanio 0:43065f3f9951 451 /**
Gennanio 0:43065f3f9951 452 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
Gennanio 0:43065f3f9951 453 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
Gennanio 0:43065f3f9951 454 */
Gennanio 0:43065f3f9951 455 uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize)
Gennanio 0:43065f3f9951 456 {
Gennanio 0:43065f3f9951 457 return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize);
Gennanio 0:43065f3f9951 458 } // End PICC_WakeupA()
Gennanio 0:43065f3f9951 459
Gennanio 0:43065f3f9951 460 /*
Gennanio 0:43065f3f9951 461 * Transmits REQA or WUPA commands.
Gennanio 0:43065f3f9951 462 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
Gennanio 0:43065f3f9951 463 */
Gennanio 0:43065f3f9951 464 uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize)
Gennanio 0:43065f3f9951 465 {
Gennanio 0:43065f3f9951 466 uint8_t validBits;
Gennanio 0:43065f3f9951 467 uint8_t status;
Gennanio 0:43065f3f9951 468
Gennanio 0:43065f3f9951 469 if (bufferATQA == NULL || *bufferSize < 2)
Gennanio 0:43065f3f9951 470 { // The ATQA response is 2 bytes long.
Gennanio 0:43065f3f9951 471 return STATUS_NO_ROOM;
Gennanio 0:43065f3f9951 472 }
Gennanio 0:43065f3f9951 473
Gennanio 0:43065f3f9951 474 // ValuesAfterColl=1 => Bits received after collision are cleared.
Gennanio 0:43065f3f9951 475 PCD_ClrRegisterBits(CollReg, 0x80);
Gennanio 0:43065f3f9951 476
Gennanio 0:43065f3f9951 477 // For REQA and WUPA we need the short frame format
Gennanio 0:43065f3f9951 478 // - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
Gennanio 0:43065f3f9951 479 validBits = 7;
Gennanio 0:43065f3f9951 480
Gennanio 0:43065f3f9951 481 status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits);
Gennanio 0:43065f3f9951 482 if (status != STATUS_OK)
Gennanio 0:43065f3f9951 483 {
Gennanio 0:43065f3f9951 484 return status;
Gennanio 0:43065f3f9951 485 }
Gennanio 0:43065f3f9951 486
Gennanio 0:43065f3f9951 487 if ((*bufferSize != 2) || (validBits != 0))
Gennanio 0:43065f3f9951 488 { // ATQA must be exactly 16 bits.
Gennanio 0:43065f3f9951 489 return STATUS_ERROR;
Gennanio 0:43065f3f9951 490 }
Gennanio 0:43065f3f9951 491
Gennanio 0:43065f3f9951 492 return STATUS_OK;
Gennanio 0:43065f3f9951 493 } // End PICC_REQA_or_WUPA()
Gennanio 0:43065f3f9951 494
Gennanio 0:43065f3f9951 495 /*
Gennanio 0:43065f3f9951 496 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
Gennanio 0:43065f3f9951 497 */
Gennanio 0:43065f3f9951 498 uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits)
Gennanio 0:43065f3f9951 499 {
Gennanio 0:43065f3f9951 500 bool uidComplete;
Gennanio 0:43065f3f9951 501 bool selectDone;
Gennanio 0:43065f3f9951 502 bool useCascadeTag;
Gennanio 0:43065f3f9951 503 uint8_t cascadeLevel = 1;
Gennanio 0:43065f3f9951 504 uint8_t result;
Gennanio 0:43065f3f9951 505 uint8_t count;
Gennanio 0:43065f3f9951 506 uint8_t index;
Gennanio 0:43065f3f9951 507 uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
Gennanio 0:43065f3f9951 508 uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
Gennanio 0:43065f3f9951 509 uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
Gennanio 0:43065f3f9951 510 uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
Gennanio 0:43065f3f9951 511 uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received.
Gennanio 0:43065f3f9951 512 uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
Gennanio 0:43065f3f9951 513 uint8_t *responseBuffer;
Gennanio 0:43065f3f9951 514 uint8_t responseLength;
Gennanio 0:43065f3f9951 515
Gennanio 0:43065f3f9951 516 // Description of buffer structure:
Gennanio 0:43065f3f9951 517 // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
Gennanio 0:43065f3f9951 518 // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
Gennanio 0:43065f3f9951 519 // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
Gennanio 0:43065f3f9951 520 // Byte 3: UID-data
Gennanio 0:43065f3f9951 521 // Byte 4: UID-data
Gennanio 0:43065f3f9951 522 // Byte 5: UID-data
Gennanio 0:43065f3f9951 523 // Byte 6: BCC Block Check Character - XOR of bytes 2-5
Gennanio 0:43065f3f9951 524 // Byte 7: CRC_A
Gennanio 0:43065f3f9951 525 // Byte 8: CRC_A
Gennanio 0:43065f3f9951 526 // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
Gennanio 0:43065f3f9951 527 //
Gennanio 0:43065f3f9951 528 // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
Gennanio 0:43065f3f9951 529 // UID size Cascade level Byte2 Byte3 Byte4 Byte5
Gennanio 0:43065f3f9951 530 // ======== ============= ===== ===== ===== =====
Gennanio 0:43065f3f9951 531 // 4 bytes 1 uid0 uid1 uid2 uid3
Gennanio 0:43065f3f9951 532 // 7 bytes 1 CT uid0 uid1 uid2
Gennanio 0:43065f3f9951 533 // 2 uid3 uid4 uid5 uid6
Gennanio 0:43065f3f9951 534 // 10 bytes 1 CT uid0 uid1 uid2
Gennanio 0:43065f3f9951 535 // 2 CT uid3 uid4 uid5
Gennanio 0:43065f3f9951 536 // 3 uid6 uid7 uid8 uid9
Gennanio 0:43065f3f9951 537
Gennanio 0:43065f3f9951 538 // Sanity checks
Gennanio 0:43065f3f9951 539 if (validBits > 80)
Gennanio 0:43065f3f9951 540 {
Gennanio 0:43065f3f9951 541 return STATUS_INVALID;
Gennanio 0:43065f3f9951 542 }
Gennanio 0:43065f3f9951 543
Gennanio 0:43065f3f9951 544 // Prepare MFRC522
Gennanio 0:43065f3f9951 545 // ValuesAfterColl=1 => Bits received after collision are cleared.
Gennanio 0:43065f3f9951 546 PCD_ClrRegisterBits(CollReg, 0x80);
Gennanio 0:43065f3f9951 547
Gennanio 0:43065f3f9951 548 // Repeat Cascade Level loop until we have a complete UID.
Gennanio 0:43065f3f9951 549 uidComplete = false;
Gennanio 0:43065f3f9951 550 while ( ! uidComplete)
Gennanio 0:43065f3f9951 551 {
Gennanio 0:43065f3f9951 552 // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
Gennanio 0:43065f3f9951 553 switch (cascadeLevel)
Gennanio 0:43065f3f9951 554 {
Gennanio 0:43065f3f9951 555 case 1:
Gennanio 0:43065f3f9951 556 buffer[0] = PICC_CMD_SEL_CL1;
Gennanio 0:43065f3f9951 557 uidIndex = 0;
Gennanio 0:43065f3f9951 558 useCascadeTag = validBits && (uid->size > 4); // When we know that the UID has more than 4 bytes
Gennanio 0:43065f3f9951 559 break;
Gennanio 0:43065f3f9951 560
Gennanio 0:43065f3f9951 561 case 2:
Gennanio 0:43065f3f9951 562 buffer[0] = PICC_CMD_SEL_CL2;
Gennanio 0:43065f3f9951 563 uidIndex = 3;
Gennanio 0:43065f3f9951 564 useCascadeTag = validBits && (uid->size > 7); // When we know that the UID has more than 7 bytes
Gennanio 0:43065f3f9951 565 break;
Gennanio 0:43065f3f9951 566
Gennanio 0:43065f3f9951 567 case 3:
Gennanio 0:43065f3f9951 568 buffer[0] = PICC_CMD_SEL_CL3;
Gennanio 0:43065f3f9951 569 uidIndex = 6;
Gennanio 0:43065f3f9951 570 useCascadeTag = false; // Never used in CL3.
Gennanio 0:43065f3f9951 571 break;
Gennanio 0:43065f3f9951 572
Gennanio 0:43065f3f9951 573 default:
Gennanio 0:43065f3f9951 574 return STATUS_INTERNAL_ERROR;
Gennanio 0:43065f3f9951 575 //break;
Gennanio 0:43065f3f9951 576 }
Gennanio 0:43065f3f9951 577
Gennanio 0:43065f3f9951 578 // How many UID bits are known in this Cascade Level?
Gennanio 0:43065f3f9951 579 if(validBits > (8 * uidIndex))
Gennanio 0:43065f3f9951 580 {
Gennanio 0:43065f3f9951 581 currentLevelKnownBits = validBits - (8 * uidIndex);
Gennanio 0:43065f3f9951 582 }
Gennanio 0:43065f3f9951 583 else
Gennanio 0:43065f3f9951 584 {
Gennanio 0:43065f3f9951 585 currentLevelKnownBits = 0;
Gennanio 0:43065f3f9951 586 }
Gennanio 0:43065f3f9951 587
Gennanio 0:43065f3f9951 588 // Copy the known bits from uid->uidByte[] to buffer[]
Gennanio 0:43065f3f9951 589 index = 2; // destination index in buffer[]
Gennanio 0:43065f3f9951 590 if (useCascadeTag)
Gennanio 0:43065f3f9951 591 {
Gennanio 0:43065f3f9951 592 buffer[index++] = PICC_CMD_CT;
Gennanio 0:43065f3f9951 593 }
Gennanio 0:43065f3f9951 594
Gennanio 0:43065f3f9951 595 uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
Gennanio 0:43065f3f9951 596 if (bytesToCopy)
Gennanio 0:43065f3f9951 597 {
Gennanio 0:43065f3f9951 598 // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
Gennanio 0:43065f3f9951 599 uint8_t maxBytes = useCascadeTag ? 3 : 4;
Gennanio 0:43065f3f9951 600 if (bytesToCopy > maxBytes)
Gennanio 0:43065f3f9951 601 {
Gennanio 0:43065f3f9951 602 bytesToCopy = maxBytes;
Gennanio 0:43065f3f9951 603 }
Gennanio 0:43065f3f9951 604
Gennanio 0:43065f3f9951 605 for (count = 0; count < bytesToCopy; count++)
Gennanio 0:43065f3f9951 606 {
Gennanio 0:43065f3f9951 607 buffer[index++] = uid->uidByte[uidIndex + count];
Gennanio 0:43065f3f9951 608 }
Gennanio 0:43065f3f9951 609 }
Gennanio 0:43065f3f9951 610
Gennanio 0:43065f3f9951 611 // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits
Gennanio 0:43065f3f9951 612 if (useCascadeTag)
Gennanio 0:43065f3f9951 613 {
Gennanio 0:43065f3f9951 614 currentLevelKnownBits += 8;
Gennanio 0:43065f3f9951 615 }
Gennanio 0:43065f3f9951 616
Gennanio 0:43065f3f9951 617 // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
Gennanio 0:43065f3f9951 618 selectDone = false;
Gennanio 0:43065f3f9951 619 while ( ! selectDone)
Gennanio 0:43065f3f9951 620 {
Gennanio 0:43065f3f9951 621 // Find out how many bits and bytes to send and receive.
Gennanio 0:43065f3f9951 622 if (currentLevelKnownBits >= 32)
Gennanio 0:43065f3f9951 623 { // All UID bits in this Cascade Level are known. This is a SELECT.
Gennanio 0:43065f3f9951 624 //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
Gennanio 0:43065f3f9951 625 buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
Gennanio 0:43065f3f9951 626
Gennanio 0:43065f3f9951 627 // Calulate BCC - Block Check Character
Gennanio 0:43065f3f9951 628 buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
Gennanio 0:43065f3f9951 629
Gennanio 0:43065f3f9951 630 // Calculate CRC_A
Gennanio 0:43065f3f9951 631 result = PCD_CalculateCRC(buffer, 7, &buffer[7]);
Gennanio 0:43065f3f9951 632 if (result != STATUS_OK)
Gennanio 0:43065f3f9951 633 {
Gennanio 0:43065f3f9951 634 return result;
Gennanio 0:43065f3f9951 635 }
Gennanio 0:43065f3f9951 636
Gennanio 0:43065f3f9951 637 txLastBits = 0; // 0 => All 8 bits are valid.
Gennanio 0:43065f3f9951 638 bufferUsed = 9;
Gennanio 0:43065f3f9951 639
Gennanio 0:43065f3f9951 640 // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
Gennanio 0:43065f3f9951 641 responseBuffer = &buffer[6];
Gennanio 0:43065f3f9951 642 responseLength = 3;
Gennanio 0:43065f3f9951 643 }
Gennanio 0:43065f3f9951 644 else
Gennanio 0:43065f3f9951 645 { // This is an ANTICOLLISION.
Gennanio 0:43065f3f9951 646 //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
Gennanio 0:43065f3f9951 647 txLastBits = currentLevelKnownBits % 8;
Gennanio 0:43065f3f9951 648 count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
Gennanio 0:43065f3f9951 649 index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
Gennanio 0:43065f3f9951 650 buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
Gennanio 0:43065f3f9951 651 bufferUsed = index + (txLastBits ? 1 : 0);
Gennanio 0:43065f3f9951 652
Gennanio 0:43065f3f9951 653 // Store response in the unused part of buffer
Gennanio 0:43065f3f9951 654 responseBuffer = &buffer[index];
Gennanio 0:43065f3f9951 655 responseLength = sizeof(buffer) - index;
Gennanio 0:43065f3f9951 656 }
Gennanio 0:43065f3f9951 657
Gennanio 0:43065f3f9951 658 // Set bit adjustments
Gennanio 0:43065f3f9951 659 rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read.
Gennanio 0:43065f3f9951 660 PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
Gennanio 0:43065f3f9951 661
Gennanio 0:43065f3f9951 662 // Transmit the buffer and receive the response.
Gennanio 0:43065f3f9951 663 result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign);
Gennanio 0:43065f3f9951 664 if (result == STATUS_COLLISION)
Gennanio 0:43065f3f9951 665 { // More than one PICC in the field => collision.
Gennanio 0:43065f3f9951 666 result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
Gennanio 0:43065f3f9951 667 if (result & 0x20)
Gennanio 0:43065f3f9951 668 { // CollPosNotValid
Gennanio 0:43065f3f9951 669 return STATUS_COLLISION; // Without a valid collision position we cannot continue
Gennanio 0:43065f3f9951 670 }
Gennanio 0:43065f3f9951 671
Gennanio 0:43065f3f9951 672 uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
Gennanio 0:43065f3f9951 673 if (collisionPos == 0)
Gennanio 0:43065f3f9951 674 {
Gennanio 0:43065f3f9951 675 collisionPos = 32;
Gennanio 0:43065f3f9951 676 }
Gennanio 0:43065f3f9951 677
Gennanio 0:43065f3f9951 678 if (collisionPos <= currentLevelKnownBits)
Gennanio 0:43065f3f9951 679 { // No progress - should not happen
Gennanio 0:43065f3f9951 680 return STATUS_INTERNAL_ERROR;
Gennanio 0:43065f3f9951 681 }
Gennanio 0:43065f3f9951 682
Gennanio 0:43065f3f9951 683 // Choose the PICC with the bit set.
Gennanio 0:43065f3f9951 684 currentLevelKnownBits = collisionPos;
Gennanio 0:43065f3f9951 685 count = (currentLevelKnownBits - 1) % 8; // The bit to modify
Gennanio 0:43065f3f9951 686 index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
Gennanio 0:43065f3f9951 687 buffer[index] |= (1 << count);
Gennanio 0:43065f3f9951 688 }
Gennanio 0:43065f3f9951 689 else if (result != STATUS_OK)
Gennanio 0:43065f3f9951 690 {
Gennanio 0:43065f3f9951 691 return result;
Gennanio 0:43065f3f9951 692 }
Gennanio 0:43065f3f9951 693 else
Gennanio 0:43065f3f9951 694 { // STATUS_OK
Gennanio 0:43065f3f9951 695 if (currentLevelKnownBits >= 32)
Gennanio 0:43065f3f9951 696 { // This was a SELECT.
Gennanio 0:43065f3f9951 697 selectDone = true; // No more anticollision
Gennanio 0:43065f3f9951 698 // We continue below outside the while.
Gennanio 0:43065f3f9951 699 }
Gennanio 0:43065f3f9951 700 else
Gennanio 0:43065f3f9951 701 { // This was an ANTICOLLISION.
Gennanio 0:43065f3f9951 702 // We now have all 32 bits of the UID in this Cascade Level
Gennanio 0:43065f3f9951 703 currentLevelKnownBits = 32;
Gennanio 0:43065f3f9951 704 // Run loop again to do the SELECT.
Gennanio 0:43065f3f9951 705 }
Gennanio 0:43065f3f9951 706 }
Gennanio 0:43065f3f9951 707 } // End of while ( ! selectDone)
Gennanio 0:43065f3f9951 708
Gennanio 0:43065f3f9951 709 // We do not check the CBB - it was constructed by us above.
Gennanio 0:43065f3f9951 710
Gennanio 0:43065f3f9951 711 // Copy the found UID bytes from buffer[] to uid->uidByte[]
Gennanio 0:43065f3f9951 712 index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
Gennanio 0:43065f3f9951 713 bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
Gennanio 0:43065f3f9951 714 for (count = 0; count < bytesToCopy; count++)
Gennanio 0:43065f3f9951 715 {
Gennanio 0:43065f3f9951 716 uid->uidByte[uidIndex + count] = buffer[index++];
Gennanio 0:43065f3f9951 717 }
Gennanio 0:43065f3f9951 718
Gennanio 0:43065f3f9951 719 // Check response SAK (Select Acknowledge)
Gennanio 0:43065f3f9951 720 if (responseLength != 3 || txLastBits != 0)
Gennanio 0:43065f3f9951 721 { // SAK must be exactly 24 bits (1 byte + CRC_A).
Gennanio 0:43065f3f9951 722 return STATUS_ERROR;
Gennanio 0:43065f3f9951 723 }
Gennanio 0:43065f3f9951 724
Gennanio 0:43065f3f9951 725 // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
Gennanio 0:43065f3f9951 726 result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]);
Gennanio 0:43065f3f9951 727 if (result != STATUS_OK)
Gennanio 0:43065f3f9951 728 {
Gennanio 0:43065f3f9951 729 return result;
Gennanio 0:43065f3f9951 730 }
Gennanio 0:43065f3f9951 731
Gennanio 0:43065f3f9951 732 if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
Gennanio 0:43065f3f9951 733 {
Gennanio 0:43065f3f9951 734 return STATUS_CRC_WRONG;
Gennanio 0:43065f3f9951 735 }
Gennanio 0:43065f3f9951 736
Gennanio 0:43065f3f9951 737 if (responseBuffer[0] & 0x04)
Gennanio 0:43065f3f9951 738 { // Cascade bit set - UID not complete yes
Gennanio 0:43065f3f9951 739 cascadeLevel++;
Gennanio 0:43065f3f9951 740 }
Gennanio 0:43065f3f9951 741 else
Gennanio 0:43065f3f9951 742 {
Gennanio 0:43065f3f9951 743 uidComplete = true;
Gennanio 0:43065f3f9951 744 uid->sak = responseBuffer[0];
Gennanio 0:43065f3f9951 745 }
Gennanio 0:43065f3f9951 746 } // End of while ( ! uidComplete)
Gennanio 0:43065f3f9951 747
Gennanio 0:43065f3f9951 748 // Set correct uid->size
Gennanio 0:43065f3f9951 749 uid->size = 3 * cascadeLevel + 1;
Gennanio 0:43065f3f9951 750
Gennanio 0:43065f3f9951 751 return STATUS_OK;
Gennanio 0:43065f3f9951 752 } // End PICC_Select()
Gennanio 0:43065f3f9951 753
Gennanio 0:43065f3f9951 754 /*
Gennanio 0:43065f3f9951 755 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
Gennanio 0:43065f3f9951 756 */
Gennanio 0:43065f3f9951 757 uint8_t MFRC522::PICC_HaltA()
Gennanio 0:43065f3f9951 758 {
Gennanio 0:43065f3f9951 759 uint8_t result;
Gennanio 0:43065f3f9951 760 uint8_t buffer[4];
Gennanio 0:43065f3f9951 761
Gennanio 0:43065f3f9951 762 // Build command buffer
Gennanio 0:43065f3f9951 763 buffer[0] = PICC_CMD_HLTA;
Gennanio 0:43065f3f9951 764 buffer[1] = 0;
Gennanio 0:43065f3f9951 765
Gennanio 0:43065f3f9951 766 // Calculate CRC_A
Gennanio 0:43065f3f9951 767 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
Gennanio 0:43065f3f9951 768 if (result == STATUS_OK)
Gennanio 0:43065f3f9951 769 {
Gennanio 0:43065f3f9951 770 // Send the command.
Gennanio 0:43065f3f9951 771 // The standard says:
Gennanio 0:43065f3f9951 772 // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
Gennanio 0:43065f3f9951 773 // HLTA command, this response shall be interpreted as 'not acknowledge'.
Gennanio 0:43065f3f9951 774 // We interpret that this way: Only STATUS_TIMEOUT is an success.
Gennanio 0:43065f3f9951 775 result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0);
Gennanio 0:43065f3f9951 776 if (result == STATUS_TIMEOUT)
Gennanio 0:43065f3f9951 777 {
Gennanio 0:43065f3f9951 778 result = STATUS_OK;
Gennanio 0:43065f3f9951 779 }
Gennanio 0:43065f3f9951 780 else if (result == STATUS_OK)
Gennanio 0:43065f3f9951 781 { // That is ironically NOT ok in this case ;-)
Gennanio 0:43065f3f9951 782 result = STATUS_ERROR;
Gennanio 0:43065f3f9951 783 }
Gennanio 0:43065f3f9951 784 }
Gennanio 0:43065f3f9951 785
Gennanio 0:43065f3f9951 786 return result;
Gennanio 0:43065f3f9951 787 } // End PICC_HaltA()
Gennanio 0:43065f3f9951 788
Gennanio 0:43065f3f9951 789
Gennanio 0:43065f3f9951 790 /////////////////////////////////////////////////////////////////////////////////////
Gennanio 0:43065f3f9951 791 // Functions for communicating with MIFARE PICCs
Gennanio 0:43065f3f9951 792 /////////////////////////////////////////////////////////////////////////////////////
Gennanio 0:43065f3f9951 793
Gennanio 0:43065f3f9951 794 /*
Gennanio 0:43065f3f9951 795 * Executes the MFRC522 MFAuthent command.
Gennanio 0:43065f3f9951 796 */
Gennanio 0:43065f3f9951 797 uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid)
Gennanio 0:43065f3f9951 798 {
Gennanio 0:43065f3f9951 799 uint8_t i, waitIRq = 0x10; // IdleIRq
Gennanio 0:43065f3f9951 800
Gennanio 0:43065f3f9951 801 // Build command buffer
Gennanio 0:43065f3f9951 802 uint8_t sendData[12];
Gennanio 0:43065f3f9951 803 sendData[0] = command;
Gennanio 0:43065f3f9951 804 sendData[1] = blockAddr;
Gennanio 0:43065f3f9951 805
Gennanio 0:43065f3f9951 806 for (i = 0; i < MF_KEY_SIZE; i++)
Gennanio 0:43065f3f9951 807 { // 6 key bytes
Gennanio 0:43065f3f9951 808 sendData[2+i] = key->keyByte[i];
Gennanio 0:43065f3f9951 809 }
Gennanio 0:43065f3f9951 810
Gennanio 0:43065f3f9951 811 for (i = 0; i < 4; i++)
Gennanio 0:43065f3f9951 812 { // The first 4 bytes of the UID
Gennanio 0:43065f3f9951 813 sendData[8+i] = uid->uidByte[i];
Gennanio 0:43065f3f9951 814 }
Gennanio 0:43065f3f9951 815
Gennanio 0:43065f3f9951 816 // Start the authentication.
Gennanio 0:43065f3f9951 817 return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData));
Gennanio 0:43065f3f9951 818 } // End PCD_Authenticate()
Gennanio 0:43065f3f9951 819
Gennanio 0:43065f3f9951 820 /*
Gennanio 0:43065f3f9951 821 * Used to exit the PCD from its authenticated state.
Gennanio 0:43065f3f9951 822 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
Gennanio 0:43065f3f9951 823 */
Gennanio 0:43065f3f9951 824 void MFRC522::PCD_StopCrypto1()
Gennanio 0:43065f3f9951 825 {
Gennanio 0:43065f3f9951 826 // Clear MFCrypto1On bit
Gennanio 0:43065f3f9951 827 PCD_ClrRegisterBits(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
Gennanio 0:43065f3f9951 828 } // End PCD_StopCrypto1()
Gennanio 0:43065f3f9951 829
Gennanio 0:43065f3f9951 830 /*
Gennanio 0:43065f3f9951 831 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
Gennanio 0:43065f3f9951 832 */
Gennanio 0:43065f3f9951 833 uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize)
Gennanio 0:43065f3f9951 834 {
Gennanio 0:43065f3f9951 835 uint8_t result = STATUS_NO_ROOM;
Gennanio 0:43065f3f9951 836
Gennanio 0:43065f3f9951 837 // Sanity check
Gennanio 0:43065f3f9951 838 if ((buffer == NULL) || (*bufferSize < 18))
Gennanio 0:43065f3f9951 839 {
Gennanio 0:43065f3f9951 840 return result;
Gennanio 0:43065f3f9951 841 }
Gennanio 0:43065f3f9951 842
Gennanio 0:43065f3f9951 843 // Build command buffer
Gennanio 0:43065f3f9951 844 buffer[0] = PICC_CMD_MF_READ;
Gennanio 0:43065f3f9951 845 buffer[1] = blockAddr;
Gennanio 0:43065f3f9951 846
Gennanio 0:43065f3f9951 847 // Calculate CRC_A
Gennanio 0:43065f3f9951 848 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
Gennanio 0:43065f3f9951 849 if (result != STATUS_OK)
Gennanio 0:43065f3f9951 850 {
Gennanio 0:43065f3f9951 851 return result;
Gennanio 0:43065f3f9951 852 }
Gennanio 0:43065f3f9951 853
Gennanio 0:43065f3f9951 854 // Transmit the buffer and receive the response, validate CRC_A.
Gennanio 0:43065f3f9951 855 return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true);
Gennanio 0:43065f3f9951 856 } // End MIFARE_Read()
Gennanio 0:43065f3f9951 857
Gennanio 0:43065f3f9951 858 /*
Gennanio 0:43065f3f9951 859 * Writes 16 bytes to the active PICC.
Gennanio 0:43065f3f9951 860 */
Gennanio 0:43065f3f9951 861 uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize)
Gennanio 0:43065f3f9951 862 {
Gennanio 0:43065f3f9951 863 uint8_t result;
Gennanio 0:43065f3f9951 864
Gennanio 0:43065f3f9951 865 // Sanity check
Gennanio 0:43065f3f9951 866 if (buffer == NULL || bufferSize < 16)
Gennanio 0:43065f3f9951 867 {
Gennanio 0:43065f3f9951 868 return STATUS_INVALID;
Gennanio 0:43065f3f9951 869 }
Gennanio 0:43065f3f9951 870
Gennanio 0:43065f3f9951 871 // Mifare Classic protocol requires two communications to perform a write.
Gennanio 0:43065f3f9951 872 // Step 1: Tell the PICC we want to write to block blockAddr.
Gennanio 0:43065f3f9951 873 uint8_t cmdBuffer[2];
Gennanio 0:43065f3f9951 874 cmdBuffer[0] = PICC_CMD_MF_WRITE;
Gennanio 0:43065f3f9951 875 cmdBuffer[1] = blockAddr;
Gennanio 0:43065f3f9951 876 // Adds CRC_A and checks that the response is MF_ACK.
Gennanio 0:43065f3f9951 877 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
Gennanio 0:43065f3f9951 878 if (result != STATUS_OK)
Gennanio 0:43065f3f9951 879 {
Gennanio 0:43065f3f9951 880 return result;
Gennanio 0:43065f3f9951 881 }
Gennanio 0:43065f3f9951 882
Gennanio 0:43065f3f9951 883 // Step 2: Transfer the data
Gennanio 0:43065f3f9951 884 // Adds CRC_A and checks that the response is MF_ACK.
Gennanio 0:43065f3f9951 885 result = PCD_MIFARE_Transceive(buffer, bufferSize);
Gennanio 0:43065f3f9951 886 if (result != STATUS_OK)
Gennanio 0:43065f3f9951 887 {
Gennanio 0:43065f3f9951 888 return result;
Gennanio 0:43065f3f9951 889 }
Gennanio 0:43065f3f9951 890
Gennanio 0:43065f3f9951 891 return STATUS_OK;
Gennanio 0:43065f3f9951 892 } // End MIFARE_Write()
Gennanio 0:43065f3f9951 893
Gennanio 0:43065f3f9951 894 /*
Gennanio 0:43065f3f9951 895 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
Gennanio 0:43065f3f9951 896 */
Gennanio 0:43065f3f9951 897 uint8_t MFRC522::MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize)
Gennanio 0:43065f3f9951 898 {
Gennanio 0:43065f3f9951 899 uint8_t result;
Gennanio 0:43065f3f9951 900
Gennanio 0:43065f3f9951 901 // Sanity check
Gennanio 0:43065f3f9951 902 if (buffer == NULL || bufferSize < 4)
Gennanio 0:43065f3f9951 903 {
Gennanio 0:43065f3f9951 904 return STATUS_INVALID;
Gennanio 0:43065f3f9951 905 }
Gennanio 0:43065f3f9951 906
Gennanio 0:43065f3f9951 907 // Build commmand buffer
Gennanio 0:43065f3f9951 908 uint8_t cmdBuffer[6];
Gennanio 0:43065f3f9951 909 cmdBuffer[0] = PICC_CMD_UL_WRITE;
Gennanio 0:43065f3f9951 910 cmdBuffer[1] = page;
Gennanio 0:43065f3f9951 911 memcpy(&cmdBuffer[2], buffer, 4);
Gennanio 0:43065f3f9951 912
Gennanio 0:43065f3f9951 913 // Perform the write
Gennanio 0:43065f3f9951 914 result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK.
Gennanio 0:43065f3f9951 915 if (result != STATUS_OK)
Gennanio 0:43065f3f9951 916 {
Gennanio 0:43065f3f9951 917 return result;
Gennanio 0:43065f3f9951 918 }
Gennanio 0:43065f3f9951 919
Gennanio 0:43065f3f9951 920 return STATUS_OK;
Gennanio 0:43065f3f9951 921 } // End MIFARE_Ultralight_Write()
Gennanio 0:43065f3f9951 922
Gennanio 0:43065f3f9951 923 /*
Gennanio 0:43065f3f9951 924 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
Gennanio 0:43065f3f9951 925 */
Gennanio 0:43065f3f9951 926 uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta)
Gennanio 0:43065f3f9951 927 {
Gennanio 0:43065f3f9951 928 return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta);
Gennanio 0:43065f3f9951 929 } // End MIFARE_Decrement()
Gennanio 0:43065f3f9951 930
Gennanio 0:43065f3f9951 931 /*
Gennanio 0:43065f3f9951 932 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
Gennanio 0:43065f3f9951 933 */
Gennanio 0:43065f3f9951 934 uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta)
Gennanio 0:43065f3f9951 935 {
Gennanio 0:43065f3f9951 936 return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta);
Gennanio 0:43065f3f9951 937 } // End MIFARE_Increment()
Gennanio 0:43065f3f9951 938
Gennanio 0:43065f3f9951 939 /**
Gennanio 0:43065f3f9951 940 * MIFARE Restore copies the value of the addressed block into a volatile memory.
Gennanio 0:43065f3f9951 941 */
Gennanio 0:43065f3f9951 942 uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr)
Gennanio 0:43065f3f9951 943 {
Gennanio 0:43065f3f9951 944 // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2.
Gennanio 0:43065f3f9951 945 // Doing only a single step does not work, so I chose to transfer 0L in step two.
Gennanio 0:43065f3f9951 946 return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L);
Gennanio 0:43065f3f9951 947 } // End MIFARE_Restore()
Gennanio 0:43065f3f9951 948
Gennanio 0:43065f3f9951 949 /*
Gennanio 0:43065f3f9951 950 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
Gennanio 0:43065f3f9951 951 */
Gennanio 0:43065f3f9951 952 uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data)
Gennanio 0:43065f3f9951 953 {
Gennanio 0:43065f3f9951 954 uint8_t result;
Gennanio 0:43065f3f9951 955 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
Gennanio 0:43065f3f9951 956
Gennanio 0:43065f3f9951 957 // Step 1: Tell the PICC the command and block address
Gennanio 0:43065f3f9951 958 cmdBuffer[0] = command;
Gennanio 0:43065f3f9951 959 cmdBuffer[1] = blockAddr;
Gennanio 0:43065f3f9951 960
Gennanio 0:43065f3f9951 961 // Adds CRC_A and checks that the response is MF_ACK.
Gennanio 0:43065f3f9951 962 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
Gennanio 0:43065f3f9951 963 if (result != STATUS_OK)
Gennanio 0:43065f3f9951 964 {
Gennanio 0:43065f3f9951 965 return result;
Gennanio 0:43065f3f9951 966 }
Gennanio 0:43065f3f9951 967
Gennanio 0:43065f3f9951 968 // Step 2: Transfer the data
Gennanio 0:43065f3f9951 969 // Adds CRC_A and accept timeout as success.
Gennanio 0:43065f3f9951 970 result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true);
Gennanio 0:43065f3f9951 971 if (result != STATUS_OK)
Gennanio 0:43065f3f9951 972 {
Gennanio 0:43065f3f9951 973 return result;
Gennanio 0:43065f3f9951 974 }
Gennanio 0:43065f3f9951 975
Gennanio 0:43065f3f9951 976 return STATUS_OK;
Gennanio 0:43065f3f9951 977 } // End MIFARE_TwoStepHelper()
Gennanio 0:43065f3f9951 978
Gennanio 0:43065f3f9951 979 /*
Gennanio 0:43065f3f9951 980 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
Gennanio 0:43065f3f9951 981 */
Gennanio 0:43065f3f9951 982 uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr)
Gennanio 0:43065f3f9951 983 {
Gennanio 0:43065f3f9951 984 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
Gennanio 0:43065f3f9951 985
Gennanio 0:43065f3f9951 986 // Tell the PICC we want to transfer the result into block blockAddr.
Gennanio 0:43065f3f9951 987 cmdBuffer[0] = PICC_CMD_MF_TRANSFER;
Gennanio 0:43065f3f9951 988 cmdBuffer[1] = blockAddr;
Gennanio 0:43065f3f9951 989
Gennanio 0:43065f3f9951 990 // Adds CRC_A and checks that the response is MF_ACK.
Gennanio 0:43065f3f9951 991 return PCD_MIFARE_Transceive(cmdBuffer, 2);
Gennanio 0:43065f3f9951 992 } // End MIFARE_Transfer()
Gennanio 0:43065f3f9951 993
Gennanio 0:43065f3f9951 994
Gennanio 0:43065f3f9951 995 /////////////////////////////////////////////////////////////////////////////////////
Gennanio 0:43065f3f9951 996 // Support functions
Gennanio 0:43065f3f9951 997 /////////////////////////////////////////////////////////////////////////////////////
Gennanio 0:43065f3f9951 998
Gennanio 0:43065f3f9951 999 /*
Gennanio 0:43065f3f9951 1000 * Wrapper for MIFARE protocol communication.
Gennanio 0:43065f3f9951 1001 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
Gennanio 0:43065f3f9951 1002 */
Gennanio 0:43065f3f9951 1003 uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout)
Gennanio 0:43065f3f9951 1004 {
Gennanio 0:43065f3f9951 1005 uint8_t result;
Gennanio 0:43065f3f9951 1006 uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A.
Gennanio 0:43065f3f9951 1007
Gennanio 0:43065f3f9951 1008 // Sanity check
Gennanio 0:43065f3f9951 1009 if (sendData == NULL || sendLen > 16)
Gennanio 0:43065f3f9951 1010 {
Gennanio 0:43065f3f9951 1011 return STATUS_INVALID;
Gennanio 0:43065f3f9951 1012 }
Gennanio 0:43065f3f9951 1013
Gennanio 0:43065f3f9951 1014 // Copy sendData[] to cmdBuffer[] and add CRC_A
Gennanio 0:43065f3f9951 1015 memcpy(cmdBuffer, sendData, sendLen);
Gennanio 0:43065f3f9951 1016 result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]);
Gennanio 0:43065f3f9951 1017 if (result != STATUS_OK)
Gennanio 0:43065f3f9951 1018 {
Gennanio 0:43065f3f9951 1019 return result;
Gennanio 0:43065f3f9951 1020 }
Gennanio 0:43065f3f9951 1021
Gennanio 0:43065f3f9951 1022 sendLen += 2;
Gennanio 0:43065f3f9951 1023
Gennanio 0:43065f3f9951 1024 // Transceive the data, store the reply in cmdBuffer[]
Gennanio 0:43065f3f9951 1025 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
Gennanio 0:43065f3f9951 1026 uint8_t cmdBufferSize = sizeof(cmdBuffer);
Gennanio 0:43065f3f9951 1027 uint8_t validBits = 0;
Gennanio 0:43065f3f9951 1028 result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits);
Gennanio 0:43065f3f9951 1029 if (acceptTimeout && result == STATUS_TIMEOUT)
Gennanio 0:43065f3f9951 1030 {
Gennanio 0:43065f3f9951 1031 return STATUS_OK;
Gennanio 0:43065f3f9951 1032 }
Gennanio 0:43065f3f9951 1033
Gennanio 0:43065f3f9951 1034 if (result != STATUS_OK)
Gennanio 0:43065f3f9951 1035 {
Gennanio 0:43065f3f9951 1036 return result;
Gennanio 0:43065f3f9951 1037 }
Gennanio 0:43065f3f9951 1038
Gennanio 0:43065f3f9951 1039 // The PICC must reply with a 4 bit ACK
Gennanio 0:43065f3f9951 1040 if (cmdBufferSize != 1 || validBits != 4)
Gennanio 0:43065f3f9951 1041 {
Gennanio 0:43065f3f9951 1042 return STATUS_ERROR;
Gennanio 0:43065f3f9951 1043 }
Gennanio 0:43065f3f9951 1044
Gennanio 0:43065f3f9951 1045 if (cmdBuffer[0] != MF_ACK)
Gennanio 0:43065f3f9951 1046 {
Gennanio 0:43065f3f9951 1047 return STATUS_MIFARE_NACK;
Gennanio 0:43065f3f9951 1048 }
Gennanio 0:43065f3f9951 1049
Gennanio 0:43065f3f9951 1050 return STATUS_OK;
Gennanio 0:43065f3f9951 1051 } // End PCD_MIFARE_Transceive()
Gennanio 0:43065f3f9951 1052
Gennanio 0:43065f3f9951 1053
Gennanio 0:43065f3f9951 1054 /*
Gennanio 0:43065f3f9951 1055 * Translates the SAK (Select Acknowledge) to a PICC type.
Gennanio 0:43065f3f9951 1056 */
Gennanio 0:43065f3f9951 1057 uint8_t MFRC522::PICC_GetType(uint8_t sak)
Gennanio 0:43065f3f9951 1058 {
Gennanio 0:43065f3f9951 1059 uint8_t retType = PICC_TYPE_UNKNOWN;
Gennanio 0:43065f3f9951 1060
Gennanio 0:43065f3f9951 1061 if (sak & 0x04)
Gennanio 0:43065f3f9951 1062 { // UID not complete
Gennanio 0:43065f3f9951 1063 retType = PICC_TYPE_NOT_COMPLETE;
Gennanio 0:43065f3f9951 1064 }
Gennanio 0:43065f3f9951 1065 else
Gennanio 0:43065f3f9951 1066 {
Gennanio 0:43065f3f9951 1067 switch (sak)
Gennanio 0:43065f3f9951 1068 {
Gennanio 0:43065f3f9951 1069 case 0x09: retType = PICC_TYPE_MIFARE_MINI; break;
Gennanio 0:43065f3f9951 1070 case 0x08: retType = PICC_TYPE_MIFARE_1K; break;
Gennanio 0:43065f3f9951 1071 case 0x18: retType = PICC_TYPE_MIFARE_4K; break;
Gennanio 0:43065f3f9951 1072 case 0x00: retType = PICC_TYPE_MIFARE_UL; break;
Gennanio 0:43065f3f9951 1073 case 0x10:
Gennanio 0:43065f3f9951 1074 case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break;
Gennanio 0:43065f3f9951 1075 case 0x01: retType = PICC_TYPE_TNP3XXX; break;
Gennanio 0:43065f3f9951 1076 default:
Gennanio 0:43065f3f9951 1077 if (sak & 0x20)
Gennanio 0:43065f3f9951 1078 {
Gennanio 0:43065f3f9951 1079 retType = PICC_TYPE_ISO_14443_4;
Gennanio 0:43065f3f9951 1080 }
Gennanio 0:43065f3f9951 1081 else if (sak & 0x40)
Gennanio 0:43065f3f9951 1082 {
Gennanio 0:43065f3f9951 1083 retType = PICC_TYPE_ISO_18092;
Gennanio 0:43065f3f9951 1084 }
Gennanio 0:43065f3f9951 1085 break;
Gennanio 0:43065f3f9951 1086 }
Gennanio 0:43065f3f9951 1087 }
Gennanio 0:43065f3f9951 1088
Gennanio 0:43065f3f9951 1089 return (retType);
Gennanio 0:43065f3f9951 1090 } // End PICC_GetType()
Gennanio 0:43065f3f9951 1091
Gennanio 0:43065f3f9951 1092 /*
Gennanio 0:43065f3f9951 1093 * Returns a string pointer to the PICC type name.
Gennanio 0:43065f3f9951 1094 */
Gennanio 0:43065f3f9951 1095 char* MFRC522::PICC_GetTypeName(uint8_t piccType)
Gennanio 0:43065f3f9951 1096 {
Gennanio 0:43065f3f9951 1097 if(piccType == PICC_TYPE_NOT_COMPLETE)
Gennanio 0:43065f3f9951 1098 {
Gennanio 0:43065f3f9951 1099 piccType = MFRC522_MaxPICCs - 1;
Gennanio 0:43065f3f9951 1100 }
Gennanio 0:43065f3f9951 1101
Gennanio 0:43065f3f9951 1102 return((char *) _TypeNamePICC[piccType]);
Gennanio 0:43065f3f9951 1103 } // End PICC_GetTypeName()
Gennanio 0:43065f3f9951 1104
Gennanio 0:43065f3f9951 1105 /*
Gennanio 0:43065f3f9951 1106 * Returns a string pointer to a status code name.
Gennanio 0:43065f3f9951 1107 */
Gennanio 0:43065f3f9951 1108 char* MFRC522::GetStatusCodeName(uint8_t code)
Gennanio 0:43065f3f9951 1109 {
Gennanio 0:43065f3f9951 1110 return((char *) _ErrorMessage[code]);
Gennanio 0:43065f3f9951 1111 } // End GetStatusCodeName()
Gennanio 0:43065f3f9951 1112
Gennanio 0:43065f3f9951 1113 /*
Gennanio 0:43065f3f9951 1114 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
Gennanio 0:43065f3f9951 1115 */
Gennanio 0:43065f3f9951 1116 void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer,
Gennanio 0:43065f3f9951 1117 uint8_t g0,
Gennanio 0:43065f3f9951 1118 uint8_t g1,
Gennanio 0:43065f3f9951 1119 uint8_t g2,
Gennanio 0:43065f3f9951 1120 uint8_t g3)
Gennanio 0:43065f3f9951 1121 {
Gennanio 0:43065f3f9951 1122 uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2);
Gennanio 0:43065f3f9951 1123 uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1);
Gennanio 0:43065f3f9951 1124 uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0);
Gennanio 0:43065f3f9951 1125
Gennanio 0:43065f3f9951 1126 accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF);
Gennanio 0:43065f3f9951 1127 accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF);
Gennanio 0:43065f3f9951 1128 accessBitBuffer[2] = c3 << 4 | c2;
Gennanio 0:43065f3f9951 1129 } // End MIFARE_SetAccessBits()
Gennanio 0:43065f3f9951 1130
Gennanio 0:43065f3f9951 1131 /////////////////////////////////////////////////////////////////////////////////////
Gennanio 0:43065f3f9951 1132 // Convenience functions - does not add extra functionality
Gennanio 0:43065f3f9951 1133 /////////////////////////////////////////////////////////////////////////////////////
Gennanio 0:43065f3f9951 1134
Gennanio 0:43065f3f9951 1135 /*
Gennanio 0:43065f3f9951 1136 * Returns true if a PICC responds to PICC_CMD_REQA.
Gennanio 0:43065f3f9951 1137 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
Gennanio 0:43065f3f9951 1138 */
Gennanio 0:43065f3f9951 1139 bool MFRC522::PICC_IsNewCardPresent(void)
Gennanio 0:43065f3f9951 1140 {
Gennanio 0:43065f3f9951 1141 uint8_t bufferATQA[2];
Gennanio 0:43065f3f9951 1142 uint8_t bufferSize = sizeof(bufferATQA);
Gennanio 0:43065f3f9951 1143 uint8_t result = PICC_RequestA(bufferATQA, &bufferSize);
Gennanio 0:43065f3f9951 1144 return ((result == STATUS_OK) || (result == STATUS_COLLISION));
Gennanio 0:43065f3f9951 1145 } // End PICC_IsNewCardPresent()
Gennanio 0:43065f3f9951 1146
Gennanio 0:43065f3f9951 1147 /*
Gennanio 0:43065f3f9951 1148 * Simple wrapper around PICC_Select.
Gennanio 0:43065f3f9951 1149 */
Gennanio 0:43065f3f9951 1150 bool MFRC522::PICC_ReadCardSerial(void)
Gennanio 0:43065f3f9951 1151 {
Gennanio 0:43065f3f9951 1152 uint8_t result = PICC_Select(&uid);
Gennanio 0:43065f3f9951 1153 return (result == STATUS_OK);
Gennanio 0:43065f3f9951 1154 } // End PICC_ReadCardSerial()