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Components/L6474/L6474_def.h@36:8a192295a94b, 2017-04-29 (annotated)

Committer:
d3dfantasy99
Date:
Sat Apr 29 08:16:25 2017 +0000
Revision:
36:8a192295a94b
Parent:
35:974ca699c792 
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davide.aliprandi@st.com 33:8daea0279301 1 /**
davide.aliprandi@st.com 33:8daea0279301 2 ******************************************************************************
davide.aliprandi@st.com 33:8daea0279301 3 * @file L6474_def.h
davide.aliprandi@st.com 33:8daea0279301 4 * @author IPC Rennes
davide.aliprandi@st.com 33:8daea0279301 5 * @version V1.5.0
davide.aliprandi@st.com 33:8daea0279301 6 * @date November 12, 2014
davide.aliprandi@st.com 33:8daea0279301 7 * @brief Header for L6474 driver (fully integrated microstepping motor driver)
davide.aliprandi@st.com 33:8daea0279301 8 * @note (C) COPYRIGHT 2014 STMicroelectronics
davide.aliprandi@st.com 33:8daea0279301 9 ******************************************************************************
davide.aliprandi@st.com 33:8daea0279301 10 * @attention
davide.aliprandi@st.com 33:8daea0279301 11 *
davide.aliprandi@st.com 33:8daea0279301 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
davide.aliprandi@st.com 33:8daea0279301 13 *
davide.aliprandi@st.com 33:8daea0279301 14 * Redistribution and use in source and binary forms, with or without modification,
davide.aliprandi@st.com 33:8daea0279301 15 * are permitted provided that the following conditions are met:
davide.aliprandi@st.com 33:8daea0279301 16 * 1. Redistributions of source code must retain the above copyright notice,
davide.aliprandi@st.com 33:8daea0279301 17 * this list of conditions and the following disclaimer.
davide.aliprandi@st.com 33:8daea0279301 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
davide.aliprandi@st.com 33:8daea0279301 19 * this list of conditions and the following disclaimer in the documentation
davide.aliprandi@st.com 33:8daea0279301 20 * and/or other materials provided with the distribution.
davide.aliprandi@st.com 33:8daea0279301 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
davide.aliprandi@st.com 33:8daea0279301 22 * may be used to endorse or promote products derived from this software
davide.aliprandi@st.com 33:8daea0279301 23 * without specific prior written permission.
davide.aliprandi@st.com 33:8daea0279301 24 *
davide.aliprandi@st.com 33:8daea0279301 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
davide.aliprandi@st.com 33:8daea0279301 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
davide.aliprandi@st.com 33:8daea0279301 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
davide.aliprandi@st.com 33:8daea0279301 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
davide.aliprandi@st.com 33:8daea0279301 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
davide.aliprandi@st.com 33:8daea0279301 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
davide.aliprandi@st.com 33:8daea0279301 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
davide.aliprandi@st.com 33:8daea0279301 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
davide.aliprandi@st.com 33:8daea0279301 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
davide.aliprandi@st.com 33:8daea0279301 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
davide.aliprandi@st.com 33:8daea0279301 35 *
davide.aliprandi@st.com 33:8daea0279301 36 ******************************************************************************
davide.aliprandi@st.com 33:8daea0279301 37 */
davide.aliprandi@st.com 33:8daea0279301 38
davide.aliprandi@st.com 33:8daea0279301 39
davide.aliprandi@st.com 33:8daea0279301 40 /* Define to prevent recursive inclusion -------------------------------------*/
davide.aliprandi@st.com 33:8daea0279301 41
davide.aliprandi@st.com 33:8daea0279301 42 #ifndef __L6474_H
davide.aliprandi@st.com 33:8daea0279301 43 #define __L6474_H
davide.aliprandi@st.com 33:8daea0279301 44
davide.aliprandi@st.com 33:8daea0279301 45 #ifdef __cplusplus
davide.aliprandi@st.com 33:8daea0279301 46 extern "C" {
davide.aliprandi@st.com 33:8daea0279301 47 #endif
davide.aliprandi@st.com 33:8daea0279301 48
davide.aliprandi@st.com 33:8daea0279301 49
davide.aliprandi@st.com 33:8daea0279301 50 /* Includes ------------------------------------------------------------------*/
davide.aliprandi@st.com 33:8daea0279301 51
davide.aliprandi@st.com 33:8daea0279301 52 #include "L6474_config.h"
davide.aliprandi@st.com 33:8daea0279301 53 #include "../Common/motor_def.h"
davide.aliprandi@st.com 33:8daea0279301 54
davide.aliprandi@st.com 33:8daea0279301 55
davide.aliprandi@st.com 33:8daea0279301 56 /* Definitions ---------------------------------------------------------------*/
davide.aliprandi@st.com 33:8daea0279301 57
davide.aliprandi@st.com 33:8daea0279301 58 /** @addtogroup BSP
davide.aliprandi@st.com 33:8daea0279301 59 * @{
davide.aliprandi@st.com 33:8daea0279301 60 */
davide.aliprandi@st.com 33:8daea0279301 61
davide.aliprandi@st.com 33:8daea0279301 62 /** @addtogroup Components
davide.aliprandi@st.com 33:8daea0279301 63 * @{
davide.aliprandi@st.com 33:8daea0279301 64 */
davide.aliprandi@st.com 33:8daea0279301 65
davide.aliprandi@st.com 33:8daea0279301 66 /** @addtogroup L6474
davide.aliprandi@st.com 33:8daea0279301 67 * @{
davide.aliprandi@st.com 33:8daea0279301 68 */
davide.aliprandi@st.com 33:8daea0279301 69
davide.aliprandi@st.com 33:8daea0279301 70 /** @defgroup L6474_Exported_Defines L6474_Exported_Defines
davide.aliprandi@st.com 33:8daea0279301 71 * @{
davide.aliprandi@st.com 33:8daea0279301 72 */
davide.aliprandi@st.com 33:8daea0279301 73
davide.aliprandi@st.com 33:8daea0279301 74 /// Current FW version
davide.aliprandi@st.com 33:8daea0279301 75 #define L6474_FW_VERSION (5)
davide.aliprandi@st.com 33:8daea0279301 76
davide.aliprandi@st.com 33:8daea0279301 77 /// L6474 max number of bytes of command & arguments to set a parameter
davide.aliprandi@st.com 33:8daea0279301 78 #define L6474_CMD_ARG_MAX_NB_BYTES (4)
davide.aliprandi@st.com 33:8daea0279301 79
davide.aliprandi@st.com 33:8daea0279301 80 /// L6474 command + argument bytes number for GET_STATUS command
davide.aliprandi@st.com 33:8daea0279301 81 #define L6474_CMD_ARG_NB_BYTES_GET_STATUS (1)
davide.aliprandi@st.com 33:8daea0279301 82
davide.aliprandi@st.com 33:8daea0279301 83 /// L6474 response bytes number
davide.aliprandi@st.com 33:8daea0279301 84 #define L6474_RSP_NB_BYTES_GET_STATUS (2)
davide.aliprandi@st.com 33:8daea0279301 85
davide.aliprandi@st.com 33:8daea0279301 86 /// L6474 value mask for ABS_POS register
davide.aliprandi@st.com 33:8daea0279301 87 #define L6474_ABS_POS_VALUE_MASK ((uint32_t) 0x003FFFFF)
davide.aliprandi@st.com 33:8daea0279301 88
davide.aliprandi@st.com 33:8daea0279301 89 /// L6474 sign bit mask for ABS_POS register
davide.aliprandi@st.com 33:8daea0279301 90 #define L6474_ABS_POS_SIGN_BIT_MASK ((uint32_t) 0x00200000)
davide.aliprandi@st.com 33:8daea0279301 91
davide.aliprandi@st.com 33:8daea0279301 92
davide.aliprandi@st.com 33:8daea0279301 93 /* Types ---------------------------------------------------------------------*/
davide.aliprandi@st.com 33:8daea0279301 94
davide.aliprandi@st.com 33:8daea0279301 95 /** @defgroup L6474_Exported_Types
davide.aliprandi@st.com 33:8daea0279301 96 * @{
davide.aliprandi@st.com 33:8daea0279301 97 */
davide.aliprandi@st.com 33:8daea0279301 98
davide.aliprandi@st.com 33:8daea0279301 99 /** @defgroup L6474_Fast_Decay_Time_Options
davide.aliprandi@st.com 33:8daea0279301 100 * @{
davide.aliprandi@st.com 33:8daea0279301 101 */
davide.aliprandi@st.com 33:8daea0279301 102 ///TOFF_FAST values for T_FAST register
davide.aliprandi@st.com 33:8daea0279301 103 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 104 L6474_TOFF_FAST_2us = ((uint8_t) 0x00 << 4),
davide.aliprandi@st.com 33:8daea0279301 105 L6474_TOFF_FAST_4us = ((uint8_t) 0x01 << 4),
davide.aliprandi@st.com 33:8daea0279301 106 L6474_TOFF_FAST_6us = ((uint8_t) 0x02 << 4),
davide.aliprandi@st.com 33:8daea0279301 107 L6474_TOFF_FAST_8us = ((uint8_t) 0x03 << 4),
davide.aliprandi@st.com 33:8daea0279301 108 L6474_TOFF_FAST_10us = ((uint8_t) 0x04 << 4),
davide.aliprandi@st.com 33:8daea0279301 109 L6474_TOFF_FAST_12us = ((uint8_t) 0x05 << 4),
davide.aliprandi@st.com 33:8daea0279301 110 L6474_TOFF_FAST_14us = ((uint8_t) 0x06 << 4),
davide.aliprandi@st.com 33:8daea0279301 111 L6474_TOFF_FAST_16us = ((uint8_t) 0x07 << 4),
davide.aliprandi@st.com 33:8daea0279301 112 L6474_TOFF_FAST_18us = ((uint8_t) 0x08 << 4),
davide.aliprandi@st.com 33:8daea0279301 113 L6474_TOFF_FAST_20us = ((uint8_t) 0x09 << 4),
davide.aliprandi@st.com 33:8daea0279301 114 L6474_TOFF_FAST_22us = ((uint8_t) 0x0A << 4),
davide.aliprandi@st.com 33:8daea0279301 115 L6474_TOFF_FAST_24us = ((uint8_t) 0x0B << 4),
davide.aliprandi@st.com 33:8daea0279301 116 L6474_TOFF_FAST_26us = ((uint8_t) 0x0C << 4),
davide.aliprandi@st.com 33:8daea0279301 117 L6474_TOFF_FAST_28us = ((uint8_t) 0x0D << 4),
davide.aliprandi@st.com 33:8daea0279301 118 L6474_TOFF_FAST_30us = ((uint8_t) 0x0E << 4),
davide.aliprandi@st.com 33:8daea0279301 119 L6474_TOFF_FAST_32us = ((uint8_t) 0x0F << 4)
davide.aliprandi@st.com 33:8daea0279301 120 } L6474_TOFF_FAST_t;
davide.aliprandi@st.com 33:8daea0279301 121 /**
davide.aliprandi@st.com 33:8daea0279301 122 * @}
davide.aliprandi@st.com 33:8daea0279301 123 */
davide.aliprandi@st.com 33:8daea0279301 124
davide.aliprandi@st.com 33:8daea0279301 125 /** @defgroup L6474_Fall_Step_Time_Options
davide.aliprandi@st.com 33:8daea0279301 126 * @{
davide.aliprandi@st.com 33:8daea0279301 127 */
davide.aliprandi@st.com 33:8daea0279301 128 ///FAST_STEP values for T_FAST register
davide.aliprandi@st.com 33:8daea0279301 129 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 130 L6474_FAST_STEP_2us = ((uint8_t) 0x00),
davide.aliprandi@st.com 33:8daea0279301 131 L6474_FAST_STEP_4us = ((uint8_t) 0x01),
davide.aliprandi@st.com 33:8daea0279301 132 L6474_FAST_STEP_6us = ((uint8_t) 0x02),
davide.aliprandi@st.com 33:8daea0279301 133 L6474_FAST_STEP_8us = ((uint8_t) 0x03),
davide.aliprandi@st.com 33:8daea0279301 134 L6474_FAST_STEP_10us = ((uint8_t) 0x04),
davide.aliprandi@st.com 33:8daea0279301 135 L6474_FAST_STEP_12us = ((uint8_t) 0x05),
davide.aliprandi@st.com 33:8daea0279301 136 L6474_FAST_STEP_14us = ((uint8_t) 0x06),
davide.aliprandi@st.com 33:8daea0279301 137 L6474_FAST_STEP_16us = ((uint8_t) 0x07),
davide.aliprandi@st.com 33:8daea0279301 138 L6474_FAST_STEP_18us = ((uint8_t) 0x08),
davide.aliprandi@st.com 33:8daea0279301 139 L6474_FAST_STEP_20us = ((uint8_t) 0x09),
davide.aliprandi@st.com 33:8daea0279301 140 L6474_FAST_STEP_22us = ((uint8_t) 0x0A),
davide.aliprandi@st.com 33:8daea0279301 141 L6474_FAST_STEP_24us = ((uint8_t) 0x0B),
davide.aliprandi@st.com 33:8daea0279301 142 L6474_FAST_STEP_26us = ((uint8_t) 0x0C),
davide.aliprandi@st.com 33:8daea0279301 143 L6474_FAST_STEP_28us = ((uint8_t) 0x0D),
davide.aliprandi@st.com 33:8daea0279301 144 L6474_FAST_STEP_30us = ((uint8_t) 0x0E),
davide.aliprandi@st.com 33:8daea0279301 145 L6474_FAST_STEP_32us = ((uint8_t) 0x0F)
davide.aliprandi@st.com 33:8daea0279301 146 } L6474_FAST_STEP_t;
davide.aliprandi@st.com 33:8daea0279301 147 /**
davide.aliprandi@st.com 33:8daea0279301 148 * @}
davide.aliprandi@st.com 33:8daea0279301 149 */
davide.aliprandi@st.com 33:8daea0279301 150
davide.aliprandi@st.com 33:8daea0279301 151 /** @defgroup L6474_Overcurrent_Threshold_options
davide.aliprandi@st.com 33:8daea0279301 152 * @{
davide.aliprandi@st.com 33:8daea0279301 153 */
davide.aliprandi@st.com 33:8daea0279301 154 ///OCD_TH register
davide.aliprandi@st.com 33:8daea0279301 155 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 156 L6474_OCD_TH_375mA = ((uint8_t) 0x00),
davide.aliprandi@st.com 33:8daea0279301 157 L6474_OCD_TH_750mA = ((uint8_t) 0x01),
davide.aliprandi@st.com 33:8daea0279301 158 L6474_OCD_TH_1125mA = ((uint8_t) 0x02),
davide.aliprandi@st.com 33:8daea0279301 159 L6474_OCD_TH_1500mA = ((uint8_t) 0x03),
davide.aliprandi@st.com 33:8daea0279301 160 L6474_OCD_TH_1875mA = ((uint8_t) 0x04),
davide.aliprandi@st.com 33:8daea0279301 161 L6474_OCD_TH_2250mA = ((uint8_t) 0x05),
davide.aliprandi@st.com 33:8daea0279301 162 L6474_OCD_TH_2625mA = ((uint8_t) 0x06),
davide.aliprandi@st.com 33:8daea0279301 163 L6474_OCD_TH_3000mA = ((uint8_t) 0x07),
davide.aliprandi@st.com 33:8daea0279301 164 L6474_OCD_TH_3375mA = ((uint8_t) 0x08),
davide.aliprandi@st.com 33:8daea0279301 165 L6474_OCD_TH_3750mA = ((uint8_t) 0x09),
davide.aliprandi@st.com 33:8daea0279301 166 L6474_OCD_TH_4125mA = ((uint8_t) 0x0A),
davide.aliprandi@st.com 33:8daea0279301 167 L6474_OCD_TH_4500mA = ((uint8_t) 0x0B),
davide.aliprandi@st.com 33:8daea0279301 168 L6474_OCD_TH_4875mA = ((uint8_t) 0x0C),
davide.aliprandi@st.com 33:8daea0279301 169 L6474_OCD_TH_5250mA = ((uint8_t) 0x0D),
davide.aliprandi@st.com 33:8daea0279301 170 L6474_OCD_TH_5625mA = ((uint8_t) 0x0E),
davide.aliprandi@st.com 33:8daea0279301 171 L6474_OCD_TH_6000mA = ((uint8_t) 0x0F)
davide.aliprandi@st.com 33:8daea0279301 172 } L6474_OCD_TH_t;
davide.aliprandi@st.com 33:8daea0279301 173 /**
davide.aliprandi@st.com 33:8daea0279301 174 * @}
davide.aliprandi@st.com 33:8daea0279301 175 */
davide.aliprandi@st.com 33:8daea0279301 176
davide.aliprandi@st.com 33:8daea0279301 177 /** @defgroup L6474_STEP_MODE_Register_Masks
davide.aliprandi@st.com 33:8daea0279301 178 * @{
davide.aliprandi@st.com 33:8daea0279301 179 */
davide.aliprandi@st.com 33:8daea0279301 180 ///STEP_MODE register
davide.aliprandi@st.com 33:8daea0279301 181 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 182 L6474_STEP_MODE_STEP_SEL = ((uint8_t) 0x07),
davide.aliprandi@st.com 33:8daea0279301 183 L6474_STEP_MODE_SYNC_SEL = ((uint8_t) 0x70)
davide.aliprandi@st.com 33:8daea0279301 184 } L6474_STEP_MODE_Masks_t;
davide.aliprandi@st.com 33:8daea0279301 185 /**
davide.aliprandi@st.com 33:8daea0279301 186 * @}
davide.aliprandi@st.com 33:8daea0279301 187 */
davide.aliprandi@st.com 33:8daea0279301 188
davide.aliprandi@st.com 33:8daea0279301 189 /** @defgroup L6474_STEP_SEL_Options_For_STEP_MODE_Register
davide.aliprandi@st.com 33:8daea0279301 190 * @{
davide.aliprandi@st.com 33:8daea0279301 191 */
davide.aliprandi@st.com 33:8daea0279301 192 ///STEP_SEL field of STEP_MODE register
davide.aliprandi@st.com 33:8daea0279301 193 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 194 L6474_STEP_SEL_1 = ((uint8_t) 0x08), //full step
davide.aliprandi@st.com 33:8daea0279301 195 L6474_STEP_SEL_1_2 = ((uint8_t) 0x09), //half step
davide.aliprandi@st.com 33:8daea0279301 196 L6474_STEP_SEL_1_4 = ((uint8_t) 0x0A), //1/4 microstep
davide.aliprandi@st.com 33:8daea0279301 197 L6474_STEP_SEL_1_8 = ((uint8_t) 0x0B), //1/8 microstep
davide.aliprandi@st.com 33:8daea0279301 198 L6474_STEP_SEL_1_16 = ((uint8_t) 0x0C) //1/16 microstep
davide.aliprandi@st.com 33:8daea0279301 199 } L6474_STEP_SEL_t;
davide.aliprandi@st.com 33:8daea0279301 200 /**
davide.aliprandi@st.com 33:8daea0279301 201 * @}
davide.aliprandi@st.com 33:8daea0279301 202 */
davide.aliprandi@st.com 33:8daea0279301 203
davide.aliprandi@st.com 33:8daea0279301 204 /** @defgroup L6474_SYNC_SEL_Options_For_STEP_MODE_Register
davide.aliprandi@st.com 33:8daea0279301 205 * @{
davide.aliprandi@st.com 33:8daea0279301 206 */
davide.aliprandi@st.com 33:8daea0279301 207 ///SYNC_SEL field of STEP_MODE register
davide.aliprandi@st.com 33:8daea0279301 208 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 209 L6474_SYNC_SEL_1_2 = ((uint8_t) 0x80),
davide.aliprandi@st.com 33:8daea0279301 210 L6474_SYNC_SEL_1 = ((uint8_t) 0x90),
davide.aliprandi@st.com 33:8daea0279301 211 L6474_SYNC_SEL_2 = ((uint8_t) 0xA0),
davide.aliprandi@st.com 33:8daea0279301 212 L6474_SYNC_SEL_4 = ((uint8_t) 0xB0),
davide.aliprandi@st.com 33:8daea0279301 213 L6474_SYNC_SEL_8 = ((uint8_t) 0xC0),
davide.aliprandi@st.com 33:8daea0279301 214 L6474_SYNC_SEL_UNUSED = ((uint8_t) 0xD0)
davide.aliprandi@st.com 33:8daea0279301 215 } L6474_SYNC_SEL_t;
davide.aliprandi@st.com 33:8daea0279301 216 /**
davide.aliprandi@st.com 33:8daea0279301 217 * @}
davide.aliprandi@st.com 33:8daea0279301 218 */
davide.aliprandi@st.com 33:8daea0279301 219
davide.aliprandi@st.com 33:8daea0279301 220 /** @defgroup L6474_ALARM_EN_Register_Options
davide.aliprandi@st.com 33:8daea0279301 221 * @{
davide.aliprandi@st.com 33:8daea0279301 222 */
davide.aliprandi@st.com 33:8daea0279301 223 ///ALARM_EN register
davide.aliprandi@st.com 33:8daea0279301 224 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 225 L6474_ALARM_EN_OVERCURRENT = ((uint8_t) 0x01),
davide.aliprandi@st.com 33:8daea0279301 226 L6474_ALARM_EN_THERMAL_SHUTDOWN = ((uint8_t) 0x02),
davide.aliprandi@st.com 33:8daea0279301 227 L6474_ALARM_EN_THERMAL_WARNING = ((uint8_t) 0x04),
davide.aliprandi@st.com 33:8daea0279301 228 L6474_ALARM_EN_UNDERVOLTAGE = ((uint8_t) 0x08),
davide.aliprandi@st.com 33:8daea0279301 229 L6474_ALARM_EN_SW_TURN_ON = ((uint8_t) 0x40),
davide.aliprandi@st.com 33:8daea0279301 230 L6474_ALARM_EN_WRONG_NPERF_CMD = ((uint8_t) 0x80)
davide.aliprandi@st.com 33:8daea0279301 231 } L6474_ALARM_EN_t;
davide.aliprandi@st.com 33:8daea0279301 232 /**
davide.aliprandi@st.com 33:8daea0279301 233 * @}
davide.aliprandi@st.com 33:8daea0279301 234 */
davide.aliprandi@st.com 33:8daea0279301 235
davide.aliprandi@st.com 33:8daea0279301 236 /** @defgroup L6474_CONFIG_Register_Masks
davide.aliprandi@st.com 33:8daea0279301 237 * @{
davide.aliprandi@st.com 33:8daea0279301 238 */
davide.aliprandi@st.com 33:8daea0279301 239 ///CONFIG register
davide.aliprandi@st.com 33:8daea0279301 240 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 241 L6474_CONFIG_OSC_SEL = ((uint16_t) 0x0007),
davide.aliprandi@st.com 33:8daea0279301 242 L6474_CONFIG_EXT_CLK = ((uint16_t) 0x0008),
davide.aliprandi@st.com 33:8daea0279301 243 L6474_CONFIG_EN_TQREG = ((uint16_t) 0x0020),
davide.aliprandi@st.com 33:8daea0279301 244 L6474_CONFIG_OC_SD = ((uint16_t) 0x0080),
davide.aliprandi@st.com 33:8daea0279301 245 L6474_CONFIG_POW_SR = ((uint16_t) 0x0300),
davide.aliprandi@st.com 33:8daea0279301 246 L6474_CONFIG_TOFF = ((uint16_t) 0x7C00)
davide.aliprandi@st.com 33:8daea0279301 247 } L6474_CONFIG_Masks_t;
davide.aliprandi@st.com 33:8daea0279301 248 /**
davide.aliprandi@st.com 33:8daea0279301 249 * @}
davide.aliprandi@st.com 33:8daea0279301 250 */
davide.aliprandi@st.com 33:8daea0279301 251
davide.aliprandi@st.com 33:8daea0279301 252 /** @defgroup L6474_Clock_Source_Options_For_CONFIG_Register
davide.aliprandi@st.com 33:8daea0279301 253 * @{
davide.aliprandi@st.com 33:8daea0279301 254 */
davide.aliprandi@st.com 33:8daea0279301 255 ///Clock source option for CONFIG register
davide.aliprandi@st.com 33:8daea0279301 256 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 257 L6474_CONFIG_INT_16MHZ = ((uint16_t) 0x0000),
davide.aliprandi@st.com 33:8daea0279301 258 L6474_CONFIG_INT_16MHZ_OSCOUT_2MHZ = ((uint16_t) 0x0008),
davide.aliprandi@st.com 33:8daea0279301 259 L6474_CONFIG_INT_16MHZ_OSCOUT_4MHZ = ((uint16_t) 0x0009),
davide.aliprandi@st.com 33:8daea0279301 260 L6474_CONFIG_INT_16MHZ_OSCOUT_8MHZ = ((uint16_t) 0x000A),
davide.aliprandi@st.com 33:8daea0279301 261 L6474_CONFIG_INT_16MHZ_OSCOUT_16MHZ = ((uint16_t) 0x000B),
davide.aliprandi@st.com 33:8daea0279301 262 L6474_CONFIG_EXT_8MHZ_XTAL_DRIVE = ((uint16_t) 0x0004),
davide.aliprandi@st.com 33:8daea0279301 263 L6474_CONFIG_EXT_16MHZ_XTAL_DRIVE = ((uint16_t) 0x0005),
davide.aliprandi@st.com 33:8daea0279301 264 L6474_CONFIG_EXT_24MHZ_XTAL_DRIVE = ((uint16_t) 0x0006),
davide.aliprandi@st.com 33:8daea0279301 265 L6474_CONFIG_EXT_32MHZ_XTAL_DRIVE = ((uint16_t) 0x0007),
davide.aliprandi@st.com 33:8daea0279301 266 L6474_CONFIG_EXT_8MHZ_OSCOUT_INVERT = ((uint16_t) 0x000C),
davide.aliprandi@st.com 33:8daea0279301 267 L6474_CONFIG_EXT_16MHZ_OSCOUT_INVERT = ((uint16_t) 0x000D),
davide.aliprandi@st.com 33:8daea0279301 268 L6474_CONFIG_EXT_24MHZ_OSCOUT_INVERT = ((uint16_t) 0x000E),
davide.aliprandi@st.com 33:8daea0279301 269 L6474_CONFIG_EXT_32MHZ_OSCOUT_INVERT = ((uint16_t) 0x000F)
davide.aliprandi@st.com 33:8daea0279301 270 } L6474_CONFIG_OSC_MGMT_t;
davide.aliprandi@st.com 33:8daea0279301 271 /**
davide.aliprandi@st.com 33:8daea0279301 272 * @}
davide.aliprandi@st.com 33:8daea0279301 273 */
davide.aliprandi@st.com 33:8daea0279301 274
davide.aliprandi@st.com 33:8daea0279301 275 /** @defgroup L6474_External_Torque_Regulation_Options_For_CONFIG_Register
davide.aliprandi@st.com 33:8daea0279301 276 * @{
davide.aliprandi@st.com 33:8daea0279301 277 */
davide.aliprandi@st.com 33:8daea0279301 278 ///External Torque regulation options for CONFIG register
davide.aliprandi@st.com 33:8daea0279301 279 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 280 L6474_CONFIG_EN_TQREG_TVAL_USED = ((uint16_t) 0x0000),
davide.aliprandi@st.com 33:8daea0279301 281 L6474_CONFIG_EN_TQREG_ADC_OUT = ((uint16_t) 0x0020)
davide.aliprandi@st.com 33:8daea0279301 282 } L6474_CONFIG_EN_TQREG_t;
davide.aliprandi@st.com 33:8daea0279301 283 /**
davide.aliprandi@st.com 33:8daea0279301 284 * @}
davide.aliprandi@st.com 33:8daea0279301 285 */
davide.aliprandi@st.com 33:8daea0279301 286
davide.aliprandi@st.com 33:8daea0279301 287 /** @defgroup L6474_Over_Current_Shutdown_Options_For_CONFIG_Register
davide.aliprandi@st.com 33:8daea0279301 288 * @{
davide.aliprandi@st.com 33:8daea0279301 289 */
davide.aliprandi@st.com 33:8daea0279301 290 ///Over Current Shutdown options for CONFIG register
davide.aliprandi@st.com 33:8daea0279301 291 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 292 L6474_CONFIG_OC_SD_DISABLE = ((uint16_t) 0x0000),
davide.aliprandi@st.com 33:8daea0279301 293 L6474_CONFIG_OC_SD_ENABLE = ((uint16_t) 0x0080)
davide.aliprandi@st.com 33:8daea0279301 294 } L6474_CONFIG_OC_SD_t;
davide.aliprandi@st.com 33:8daea0279301 295 /**
davide.aliprandi@st.com 33:8daea0279301 296 * @}
davide.aliprandi@st.com 33:8daea0279301 297 */
davide.aliprandi@st.com 33:8daea0279301 298
davide.aliprandi@st.com 33:8daea0279301 299 /** @defgroup L6474_Power_Bridge_Output_Slew_Rate_Options
davide.aliprandi@st.com 33:8daea0279301 300 * @{
davide.aliprandi@st.com 33:8daea0279301 301 */
davide.aliprandi@st.com 33:8daea0279301 302 /// POW_SR values for CONFIG register
davide.aliprandi@st.com 33:8daea0279301 303 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 304 L6474_CONFIG_SR_320V_us =((uint16_t)0x0000),
davide.aliprandi@st.com 33:8daea0279301 305 L6474_CONFIG_SR_075V_us =((uint16_t)0x0100),
davide.aliprandi@st.com 33:8daea0279301 306 L6474_CONFIG_SR_110V_us =((uint16_t)0x0200),
davide.aliprandi@st.com 33:8daea0279301 307 L6474_CONFIG_SR_260V_us =((uint16_t)0x0300)
davide.aliprandi@st.com 33:8daea0279301 308 } L6474_CONFIG_POW_SR_t;
davide.aliprandi@st.com 33:8daea0279301 309 /**
davide.aliprandi@st.com 33:8daea0279301 310 * @}
davide.aliprandi@st.com 33:8daea0279301 311 */
davide.aliprandi@st.com 33:8daea0279301 312
davide.aliprandi@st.com 33:8daea0279301 313 /** @defgroup L6474_Off_Time_Options
davide.aliprandi@st.com 33:8daea0279301 314 * @{
davide.aliprandi@st.com 33:8daea0279301 315 */
davide.aliprandi@st.com 33:8daea0279301 316 /// TOFF values for CONFIG register
davide.aliprandi@st.com 33:8daea0279301 317 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 318 L6474_CONFIG_TOFF_004us = (((uint16_t) 0x01) << 10),
davide.aliprandi@st.com 33:8daea0279301 319 L6474_CONFIG_TOFF_008us = (((uint16_t) 0x02) << 10),
davide.aliprandi@st.com 33:8daea0279301 320 L6474_CONFIG_TOFF_012us = (((uint16_t) 0x03) << 10),
davide.aliprandi@st.com 33:8daea0279301 321 L6474_CONFIG_TOFF_016us = (((uint16_t) 0x04) << 10),
davide.aliprandi@st.com 33:8daea0279301 322 L6474_CONFIG_TOFF_020us = (((uint16_t) 0x05) << 10),
davide.aliprandi@st.com 33:8daea0279301 323 L6474_CONFIG_TOFF_024us = (((uint16_t) 0x06) << 10),
davide.aliprandi@st.com 33:8daea0279301 324 L6474_CONFIG_TOFF_028us = (((uint16_t) 0x07) << 10),
davide.aliprandi@st.com 33:8daea0279301 325 L6474_CONFIG_TOFF_032us = (((uint16_t) 0x08) << 10),
davide.aliprandi@st.com 33:8daea0279301 326 L6474_CONFIG_TOFF_036us = (((uint16_t) 0x09) << 10),
davide.aliprandi@st.com 33:8daea0279301 327 L6474_CONFIG_TOFF_040us = (((uint16_t) 0x0A) << 10),
davide.aliprandi@st.com 33:8daea0279301 328 L6474_CONFIG_TOFF_044us = (((uint16_t) 0x0B) << 10),
davide.aliprandi@st.com 33:8daea0279301 329 L6474_CONFIG_TOFF_048us = (((uint16_t) 0x0C) << 10),
davide.aliprandi@st.com 33:8daea0279301 330 L6474_CONFIG_TOFF_052us = (((uint16_t) 0x0D) << 10),
davide.aliprandi@st.com 33:8daea0279301 331 L6474_CONFIG_TOFF_056us = (((uint16_t) 0x0E) << 10),
davide.aliprandi@st.com 33:8daea0279301 332 L6474_CONFIG_TOFF_060us = (((uint16_t) 0x0F) << 10),
davide.aliprandi@st.com 33:8daea0279301 333 L6474_CONFIG_TOFF_064us = (((uint16_t) 0x10) << 10),
davide.aliprandi@st.com 33:8daea0279301 334 L6474_CONFIG_TOFF_068us = (((uint16_t) 0x11) << 10),
davide.aliprandi@st.com 33:8daea0279301 335 L6474_CONFIG_TOFF_072us = (((uint16_t) 0x12) << 10),
davide.aliprandi@st.com 33:8daea0279301 336 L6474_CONFIG_TOFF_076us = (((uint16_t) 0x13) << 10),
davide.aliprandi@st.com 33:8daea0279301 337 L6474_CONFIG_TOFF_080us = (((uint16_t) 0x14) << 10),
davide.aliprandi@st.com 33:8daea0279301 338 L6474_CONFIG_TOFF_084us = (((uint16_t) 0x15) << 10),
davide.aliprandi@st.com 33:8daea0279301 339 L6474_CONFIG_TOFF_088us = (((uint16_t) 0x16) << 10),
davide.aliprandi@st.com 33:8daea0279301 340 L6474_CONFIG_TOFF_092us = (((uint16_t) 0x17) << 10),
davide.aliprandi@st.com 33:8daea0279301 341 L6474_CONFIG_TOFF_096us = (((uint16_t) 0x18) << 10),
davide.aliprandi@st.com 33:8daea0279301 342 L6474_CONFIG_TOFF_100us = (((uint16_t) 0x19) << 10),
davide.aliprandi@st.com 33:8daea0279301 343 L6474_CONFIG_TOFF_104us = (((uint16_t) 0x1A) << 10),
davide.aliprandi@st.com 33:8daea0279301 344 L6474_CONFIG_TOFF_108us = (((uint16_t) 0x1B) << 10),
davide.aliprandi@st.com 33:8daea0279301 345 L6474_CONFIG_TOFF_112us = (((uint16_t) 0x1C) << 10),
davide.aliprandi@st.com 33:8daea0279301 346 L6474_CONFIG_TOFF_116us = (((uint16_t) 0x1D) << 10),
davide.aliprandi@st.com 33:8daea0279301 347 L6474_CONFIG_TOFF_120us = (((uint16_t) 0x1E) << 10),
davide.aliprandi@st.com 33:8daea0279301 348 L6474_CONFIG_TOFF_124us = (((uint16_t) 0x1F) << 10)
davide.aliprandi@st.com 33:8daea0279301 349 } L6474_CONFIG_TOFF_t;
davide.aliprandi@st.com 33:8daea0279301 350 /**
davide.aliprandi@st.com 33:8daea0279301 351 * @}
davide.aliprandi@st.com 33:8daea0279301 352 */
davide.aliprandi@st.com 33:8daea0279301 353
davide.aliprandi@st.com 33:8daea0279301 354 /** @defgroup L6474_STATUS_Register_Bit_Masks
davide.aliprandi@st.com 33:8daea0279301 355 * @{
davide.aliprandi@st.com 33:8daea0279301 356 */
davide.aliprandi@st.com 33:8daea0279301 357 ///STATUS Register Bit Masks
davide.aliprandi@st.com 33:8daea0279301 358 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 359 L6474_STATUS_HIZ = (((uint16_t) 0x0001)),
davide.aliprandi@st.com 33:8daea0279301 360 L6474_STATUS_DIR = (((uint16_t) 0x0010)),
davide.aliprandi@st.com 33:8daea0279301 361 L6474_STATUS_NOTPERF_CMD = (((uint16_t) 0x0080)),
davide.aliprandi@st.com 33:8daea0279301 362 L6474_STATUS_WRONG_CMD = (((uint16_t) 0x0100)),
davide.aliprandi@st.com 33:8daea0279301 363 L6474_STATUS_UVLO = (((uint16_t) 0x0200)),
davide.aliprandi@st.com 33:8daea0279301 364 L6474_STATUS_TH_WRN = (((uint16_t) 0x0400)),
davide.aliprandi@st.com 33:8daea0279301 365 L6474_STATUS_TH_SD = (((uint16_t) 0x0800)),
davide.aliprandi@st.com 33:8daea0279301 366 L6474_STATUS_OCD = (((uint16_t) 0x1000))
davide.aliprandi@st.com 33:8daea0279301 367 } L6474_STATUS_Masks_t;
davide.aliprandi@st.com 33:8daea0279301 368 /**
davide.aliprandi@st.com 33:8daea0279301 369 * @}
davide.aliprandi@st.com 33:8daea0279301 370 */
davide.aliprandi@st.com 33:8daea0279301 371
davide.aliprandi@st.com 33:8daea0279301 372 /** @defgroup L6474_Direction_Field_Of_STATUS_Register
davide.aliprandi@st.com 33:8daea0279301 373 * @{
davide.aliprandi@st.com 33:8daea0279301 374 */
davide.aliprandi@st.com 33:8daea0279301 375 ///Diretion field of STATUS register
davide.aliprandi@st.com 33:8daea0279301 376 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 377 L6474_STATUS_DIR_FORWARD = (((uint16_t) 0x0001) << 4),
davide.aliprandi@st.com 33:8daea0279301 378 L6474_STATUS_DIR_REVERSE = (((uint16_t) 0x0000) << 4)
davide.aliprandi@st.com 33:8daea0279301 379 } L6474_STATUS_DIR_t;
davide.aliprandi@st.com 33:8daea0279301 380 /**
davide.aliprandi@st.com 33:8daea0279301 381 * @}
davide.aliprandi@st.com 33:8daea0279301 382 */
davide.aliprandi@st.com 33:8daea0279301 383
davide.aliprandi@st.com 33:8daea0279301 384 /** @defgroup L6474_Internal_Register_Addresses
davide.aliprandi@st.com 33:8daea0279301 385 * @{
davide.aliprandi@st.com 33:8daea0279301 386 */
davide.aliprandi@st.com 33:8daea0279301 387 /// Internal L6474 register addresses
davide.aliprandi@st.com 33:8daea0279301 388 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 389 L6474_ABS_POS = ((uint8_t) 0x01),
davide.aliprandi@st.com 33:8daea0279301 390 L6474_EL_POS = ((uint8_t) 0x02),
davide.aliprandi@st.com 33:8daea0279301 391 L6474_MARK = ((uint8_t) 0x03),
davide.aliprandi@st.com 33:8daea0279301 392 L6474_RESERVED_REG01 = ((uint8_t) 0x04),
davide.aliprandi@st.com 33:8daea0279301 393 L6474_RESERVED_REG02 = ((uint8_t) 0x05),
davide.aliprandi@st.com 33:8daea0279301 394 L6474_RESERVED_REG03 = ((uint8_t) 0x06),
davide.aliprandi@st.com 33:8daea0279301 395 L6474_RESERVED_REG04 = ((uint8_t) 0x07),
davide.aliprandi@st.com 33:8daea0279301 396 L6474_RESERVED_REG05 = ((uint8_t) 0x08),
davide.aliprandi@st.com 33:8daea0279301 397 L6474_RESERVED_REG06 = ((uint8_t) 0x15),
davide.aliprandi@st.com 33:8daea0279301 398 L6474_TVAL = ((uint8_t) 0x09),
davide.aliprandi@st.com 33:8daea0279301 399 L6474_RESERVED_REG07 = ((uint8_t) 0x0A),
davide.aliprandi@st.com 33:8daea0279301 400 L6474_RESERVED_REG08 = ((uint8_t) 0x0B),
davide.aliprandi@st.com 33:8daea0279301 401 L6474_RESERVED_REG09 = ((uint8_t) 0x0C),
davide.aliprandi@st.com 33:8daea0279301 402 L6474_RESERVED_REG10 = ((uint8_t) 0x0D),
davide.aliprandi@st.com 33:8daea0279301 403 L6474_T_FAST = ((uint8_t) 0x0E),
davide.aliprandi@st.com 33:8daea0279301 404 L6474_TON_MIN = ((uint8_t) 0x0F),
davide.aliprandi@st.com 33:8daea0279301 405 L6474_TOFF_MIN = ((uint8_t) 0x10),
davide.aliprandi@st.com 33:8daea0279301 406 L6474_RESERVED_REG11 = ((uint8_t) 0x11),
davide.aliprandi@st.com 33:8daea0279301 407 L6474_ADC_OUT = ((uint8_t) 0x12),
davide.aliprandi@st.com 33:8daea0279301 408 L6474_OCD_TH = ((uint8_t) 0x13),
davide.aliprandi@st.com 33:8daea0279301 409 L6474_RESERVED_REG12 = ((uint8_t) 0x14),
davide.aliprandi@st.com 33:8daea0279301 410 L6474_STEP_MODE = ((uint8_t) 0x16),
davide.aliprandi@st.com 33:8daea0279301 411 L6474_ALARM_EN = ((uint8_t) 0x17),
davide.aliprandi@st.com 33:8daea0279301 412 L6474_CONFIG = ((uint8_t) 0x18),
davide.aliprandi@st.com 33:8daea0279301 413 L6474_STATUS = ((uint8_t) 0x19),
davide.aliprandi@st.com 33:8daea0279301 414 L6474_RESERVED_REG13 = ((uint8_t) 0x1A),
davide.aliprandi@st.com 33:8daea0279301 415 L6474_RESERVED_REG14 = ((uint8_t) 0x1B),
davide.aliprandi@st.com 33:8daea0279301 416 L6474_INEXISTENT_REG = ((uint8_t) 0x1F)
davide.aliprandi@st.com 33:8daea0279301 417 } L6474_Registers_t;
davide.aliprandi@st.com 33:8daea0279301 418 /**
davide.aliprandi@st.com 33:8daea0279301 419 * @}
davide.aliprandi@st.com 33:8daea0279301 420 */
davide.aliprandi@st.com 33:8daea0279301 421
davide.aliprandi@st.com 33:8daea0279301 422 /** @defgroup L6474_Command_Set
davide.aliprandi@st.com 33:8daea0279301 423 * @{
davide.aliprandi@st.com 33:8daea0279301 424 */
davide.aliprandi@st.com 33:8daea0279301 425 /// L6474 command set
davide.aliprandi@st.com 33:8daea0279301 426 typedef enum {
davide.aliprandi@st.com 33:8daea0279301 427 L6474_NOP = ((uint8_t) 0x00),
davide.aliprandi@st.com 33:8daea0279301 428 L6474_SET_PARAM = ((uint8_t) 0x00),
davide.aliprandi@st.com 33:8daea0279301 429 L6474_GET_PARAM = ((uint8_t) 0x20),
davide.aliprandi@st.com 33:8daea0279301 430 L6474_ENABLE = ((uint8_t) 0xB8),
davide.aliprandi@st.com 33:8daea0279301 431 L6474_DISABLE = ((uint8_t) 0xA8),
davide.aliprandi@st.com 33:8daea0279301 432 L6474_GET_STATUS = ((uint8_t) 0xD0),
davide.aliprandi@st.com 33:8daea0279301 433 L6474_RESERVED_CMD1 = ((uint8_t) 0xEB),
davide.aliprandi@st.com 33:8daea0279301 434 L6474_RESERVED_CMD2 = ((uint8_t) 0xF8)
davide.aliprandi@st.com 33:8daea0279301 435 } L6474_Commands_t;
davide.aliprandi@st.com 33:8daea0279301 436
davide.aliprandi@st.com 33:8daea0279301 437 /**
davide.aliprandi@st.com 33:8daea0279301 438 * @brief L6474 driver initialization structure definition.
davide.aliprandi@st.com 33:8daea0279301 439 */
davide.aliprandi@st.com 33:8daea0279301 440 /* ACTION --------------------------------------------------------------------*
davide.aliprandi@st.com 33:8daea0279301 441 * Declare here the component's initialization structure, if any, one *
davide.aliprandi@st.com 33:8daea0279301 442 * variable per line without initialization. *
davide.aliprandi@st.com 33:8daea0279301 443 * *
davide.aliprandi@st.com 33:8daea0279301 444 * Example: *
davide.aliprandi@st.com 33:8daea0279301 445 * typedef struct *
davide.aliprandi@st.com 33:8daea0279301 446 * { *
davide.aliprandi@st.com 33:8daea0279301 447 * int frequency; *
davide.aliprandi@st.com 33:8daea0279301 448 * int update_mode; *
davide.aliprandi@st.com 33:8daea0279301 449 * } COMPONENT_Init_t; *
davide.aliprandi@st.com 33:8daea0279301 450 *----------------------------------------------------------------------------*/
davide.aliprandi@st.com 33:8daea0279301 451 typedef struct
davide.aliprandi@st.com 33:8daea0279301 452 {
davide.aliprandi@st.com 33:8daea0279301 453 /* Acceleration rate in pps^2. Range: (0..+inf). */
davide.aliprandi@st.com 33:8daea0279301 454 int acceleration_pps_2;
davide.aliprandi@st.com 33:8daea0279301 455
davide.aliprandi@st.com 33:8daea0279301 456 /* Deceleration rate in pps^2. Range: (0..+inf). */
davide.aliprandi@st.com 33:8daea0279301 457 int deceleration_pps_2;
davide.aliprandi@st.com 33:8daea0279301 458
davide.aliprandi@st.com 33:8daea0279301 459 /* Maximum speed in pps. Range: (30..10000]. */
davide.aliprandi@st.com 33:8daea0279301 460 int maximum_speed_pps;
davide.aliprandi@st.com 33:8daea0279301 461
davide.aliprandi@st.com 33:8daea0279301 462 /* Minimum speed in pps. Range: [30..10000). */
davide.aliprandi@st.com 33:8daea0279301 463 int minimum_speed_pps;
davide.aliprandi@st.com 33:8daea0279301 464
davide.aliprandi@st.com 33:8daea0279301 465 /* Torque regulation current in mA. Range: 31.25mA to 4000mA. */
davide.aliprandi@st.com 33:8daea0279301 466 float torque_regulation_current_mA;
davide.aliprandi@st.com 33:8daea0279301 467
davide.aliprandi@st.com 33:8daea0279301 468 /* Overcurrent threshold (OCD_TH register). */
davide.aliprandi@st.com 33:8daea0279301 469 L6474_OCD_TH_t overcurrent_threshold;
davide.aliprandi@st.com 33:8daea0279301 470
davide.aliprandi@st.com 33:8daea0279301 471 /* Overcurrent shutwdown (OC_SD field of CONFIG register). */
davide.aliprandi@st.com 33:8daea0279301 472 L6474_CONFIG_OC_SD_t overcurrent_shutwdown;
davide.aliprandi@st.com 33:8daea0279301 473
davide.aliprandi@st.com 33:8daea0279301 474 /* Torque regulation method (EN_TQREG field of CONFIG register). */
davide.aliprandi@st.com 33:8daea0279301 475 L6474_CONFIG_EN_TQREG_t torque_regulation_method;
davide.aliprandi@st.com 33:8daea0279301 476
davide.aliprandi@st.com 33:8daea0279301 477 /* Step selection (STEP_SEL field of STEP_MODE register). */
davide.aliprandi@st.com 33:8daea0279301 478 L6474_STEP_SEL_t step_selection;
davide.aliprandi@st.com 33:8daea0279301 479
davide.aliprandi@st.com 33:8daea0279301 480 /* Sync selection (SYNC_SEL field of STEP_MODE register). */
davide.aliprandi@st.com 33:8daea0279301 481 L6474_SYNC_SEL_t sync_selection;
davide.aliprandi@st.com 33:8daea0279301 482
davide.aliprandi@st.com 33:8daea0279301 483 /* Fall time value (T_FAST field of T_FAST register). Range: 2us to 32us. */
davide.aliprandi@st.com 33:8daea0279301 484 L6474_FAST_STEP_t fall_time;
davide.aliprandi@st.com 33:8daea0279301 485
davide.aliprandi@st.com 33:8daea0279301 486 /* Maximum fast decay time (T_OFF field of T_FAST register). Range: 2us to 32us. */
davide.aliprandi@st.com 33:8daea0279301 487 L6474_TOFF_FAST_t maximum_fast_decay_time;
davide.aliprandi@st.com 33:8daea0279301 488
davide.aliprandi@st.com 33:8daea0279301 489 /* Minimum ON time in us (TON_MIN register). Range: 0.5us to 64us. */
davide.aliprandi@st.com 33:8daea0279301 490 float minimum_ON_time_us;
davide.aliprandi@st.com 33:8daea0279301 491
davide.aliprandi@st.com 33:8daea0279301 492 /* Minimum OFF time in us (TOFF_MIN register). Range: 0.5us to 64us. */
davide.aliprandi@st.com 33:8daea0279301 493 float minimum_OFF_time_us;
davide.aliprandi@st.com 33:8daea0279301 494
davide.aliprandi@st.com 33:8daea0279301 495 /* Target Swicthing Period (field TOFF of CONFIG register). */
davide.aliprandi@st.com 33:8daea0279301 496 L6474_CONFIG_TOFF_t target_swicthing_period;
davide.aliprandi@st.com 33:8daea0279301 497
davide.aliprandi@st.com 33:8daea0279301 498 /* Slew rate (POW_SR field of CONFIG register). */
davide.aliprandi@st.com 33:8daea0279301 499 L6474_CONFIG_POW_SR_t slew_rate;
davide.aliprandi@st.com 33:8daea0279301 500
davide.aliprandi@st.com 33:8daea0279301 501 /* Clock setting (OSC_CLK_SEL field of CONFIG register). */
davide.aliprandi@st.com 33:8daea0279301 502 L6474_CONFIG_OSC_MGMT_t clock;
davide.aliprandi@st.com 33:8daea0279301 503
davide.aliprandi@st.com 33:8daea0279301 504 /* Alarm (ALARM_EN register). */
davide.aliprandi@st.com 33:8daea0279301 505 int alarm;
davide.aliprandi@st.com 33:8daea0279301 506 } L6474_init_t;
davide.aliprandi@st.com 33:8daea0279301 507
davide.aliprandi@st.com 33:8daea0279301 508 /**
davide.aliprandi@st.com 33:8daea0279301 509 * @brief L6474 driver data structure definition.
davide.aliprandi@st.com 33:8daea0279301 510 */
davide.aliprandi@st.com 33:8daea0279301 511 /* ACTION --------------------------------------------------------------------*
davide.aliprandi@st.com 33:8daea0279301 512 * Declare here the structure of component's data, if any, one variable per *
davide.aliprandi@st.com 33:8daea0279301 513 * line without initialization. *
davide.aliprandi@st.com 33:8daea0279301 514 * *
davide.aliprandi@st.com 33:8daea0279301 515 * Example: *
davide.aliprandi@st.com 33:8daea0279301 516 * typedef struct *
davide.aliprandi@st.com 33:8daea0279301 517 * { *
davide.aliprandi@st.com 33:8daea0279301 518 * int T0_out; *
davide.aliprandi@st.com 33:8daea0279301 519 * int T1_out; *
davide.aliprandi@st.com 33:8daea0279301 520 * float T0_degC; *
davide.aliprandi@st.com 33:8daea0279301 521 * float T1_degC; *
davide.aliprandi@st.com 33:8daea0279301 522 * } COMPONENT_Data_t; *
davide.aliprandi@st.com 33:8daea0279301 523 *----------------------------------------------------------------------------*/
davide.aliprandi@st.com 33:8daea0279301 524 typedef struct
davide.aliprandi@st.com 33:8daea0279301 525 {
davide.aliprandi@st.com 33:8daea0279301 526 /// Function pointer to flag interrupt call back
davide.aliprandi@st.com 33:8daea0279301 527 void (*flagInterruptCallback)(void);
davide.aliprandi@st.com 33:8daea0279301 528 /// Function pointer to error handler call back
davide.aliprandi@st.com 33:8daea0279301 529 void (*errorHandlerCallback)(uint16_t error);
davide.aliprandi@st.com 33:8daea0279301 530 bool spiPreemtionByIsr; // = FALSE;
davide.aliprandi@st.com 33:8daea0279301 531 bool isrFlag; // = FALSE;
davide.aliprandi@st.com 33:8daea0279301 532 /// L6474 Device Paramaters structure
davide.aliprandi@st.com 33:8daea0279301 533 deviceParams_t devicePrm; //[MAX_NUMBER_OF_DEVICES];
davide.aliprandi@st.com 33:8daea0279301 534 uint8_t number_of_devices;
davide.aliprandi@st.com 33:8daea0279301 535 uint8_t device_instance;
davide.aliprandi@st.com 33:8daea0279301 536 uint8_t spiTxBursts[L6474_CMD_ARG_MAX_NB_BYTES][MAX_NUMBER_OF_DEVICES];
davide.aliprandi@st.com 33:8daea0279301 537 uint8_t spiRxBursts[L6474_CMD_ARG_MAX_NB_BYTES][MAX_NUMBER_OF_DEVICES];
davide.aliprandi@st.com 33:8daea0279301 538 } L6474_Data_t;
davide.aliprandi@st.com 33:8daea0279301 539
davide.aliprandi@st.com 33:8daea0279301 540
davide.aliprandi@st.com 33:8daea0279301 541 /* Functions -----------------------------------------------------------------*/
davide.aliprandi@st.com 33:8daea0279301 542
davide.aliprandi@st.com 33:8daea0279301 543 /** @addtogroup BSP
davide.aliprandi@st.com 33:8daea0279301 544 * @{
davide.aliprandi@st.com 33:8daea0279301 545 */
davide.aliprandi@st.com 33:8daea0279301 546
davide.aliprandi@st.com 33:8daea0279301 547 /** @addtogroup Components
davide.aliprandi@st.com 33:8daea0279301 548 * @{
davide.aliprandi@st.com 33:8daea0279301 549 */
davide.aliprandi@st.com 33:8daea0279301 550
davide.aliprandi@st.com 33:8daea0279301 551 /** @addtogroup L6474
davide.aliprandi@st.com 33:8daea0279301 552 * @{
davide.aliprandi@st.com 33:8daea0279301 553 */
davide.aliprandi@st.com 33:8daea0279301 554
davide.aliprandi@st.com 33:8daea0279301 555 /** @defgroup L6474_Imported_Functions L6474_Imported_Functions
davide.aliprandi@st.com 33:8daea0279301 556 * @{
davide.aliprandi@st.com 33:8daea0279301 557 */
davide.aliprandi@st.com 33:8daea0279301 558
davide.aliprandi@st.com 33:8daea0279301 559 /* ACTION --------------------------------------------------------------------*
davide.aliprandi@st.com 33:8daea0279301 560 * Declare here extern platform-dependent APIs you might need (e.g.: I/O and *
davide.aliprandi@st.com 33:8daea0279301 561 * interrupt related functions), and implement them in a glue-logic file on *
davide.aliprandi@st.com 33:8daea0279301 562 * the target environment, for example within the "x_nucleo_board.c" file. *
davide.aliprandi@st.com 33:8daea0279301 563 * E.g.: *
davide.aliprandi@st.com 33:8daea0279301 564 * extern status_t COMPONENT_IO_Init (void *handle); *
davide.aliprandi@st.com 33:8daea0279301 565 * extern status_t COMPONENT_IO_Read (handle, buf, regadd, bytes); *
davide.aliprandi@st.com 33:8daea0279301 566 * extern status_t COMPONENT_IO_Write(handle, buf, regadd, bytes); *
davide.aliprandi@st.com 33:8daea0279301 567 * extern void COMPONENT_IO_ITConfig(void); *
davide.aliprandi@st.com 33:8daea0279301 568 *----------------------------------------------------------------------------*/
davide.aliprandi@st.com 33:8daea0279301 569 ///Delay of the requested number of milliseconds
davide.aliprandi@st.com 33:8daea0279301 570 extern void L6474_Delay(void *handle, uint32_t delay);
davide.aliprandi@st.com 33:8daea0279301 571 ///Enable Irq
davide.aliprandi@st.com 33:8daea0279301 572 extern void L6474_EnableIrq(void *handle);
davide.aliprandi@st.com 33:8daea0279301 573 ///Disable Irq
davide.aliprandi@st.com 33:8daea0279301 574 extern void L6474_DisableIrq(void *handle);
davide.aliprandi@st.com 33:8daea0279301 575 ///Set PWM1 frequency and start it
davide.aliprandi@st.com 33:8daea0279301 576 extern void L6474_Pwm1SetFreq(void *handle, uint16_t newFreq);
davide.aliprandi@st.com 33:8daea0279301 577 ///Set PWM2 frequency and start it
davide.aliprandi@st.com 33:8daea0279301 578 extern void L6474_Pwm2SetFreq(void *handle, uint16_t newFreq);
davide.aliprandi@st.com 33:8daea0279301 579 ///Set PWM3 frequency and start it
davide.aliprandi@st.com 33:8daea0279301 580 extern void L6474_Pwm3SetFreq(void *handle, uint16_t newFreq);
davide.aliprandi@st.com 33:8daea0279301 581 ///Init the PWM
davide.aliprandi@st.com 33:8daea0279301 582 extern void L6474_PwmInit(void *handle);
davide.aliprandi@st.com 33:8daea0279301 583 ///Stop the PWM
davide.aliprandi@st.com 33:8daea0279301 584 extern void L6474_PwmStop(void *handle);
davide.aliprandi@st.com 33:8daea0279301 585 ///Reset the L6474 reset pin
davide.aliprandi@st.com 33:8daea0279301 586 extern void L6474_ReleaseReset(void *handle);
davide.aliprandi@st.com 33:8daea0279301 587 ///Set the L6474 reset pin
davide.aliprandi@st.com 33:8daea0279301 588 extern void L6474_Reset(void *handle);
davide.aliprandi@st.com 33:8daea0279301 589 ///Set direction GPIO
davide.aliprandi@st.com 33:8daea0279301 590 extern void L6474_SetDirectionGpio(void *handle, uint8_t gpioState);
davide.aliprandi@st.com 33:8daea0279301 591 ///Write bytes to the L6474s via SPI
davide.aliprandi@st.com 33:8daea0279301 592 extern uint8_t L6474_SpiWriteBytes(void *handle, uint8_t *pByteToTransmit, uint8_t *pReceivedByte);
davide.aliprandi@st.com 33:8daea0279301 593
davide.aliprandi@st.com 33:8daea0279301 594 #ifdef __cplusplus
davide.aliprandi@st.com 33:8daea0279301 595 }
davide.aliprandi@st.com 33:8daea0279301 596 #endif
davide.aliprandi@st.com 33:8daea0279301 597
davide.aliprandi@st.com 33:8daea0279301 598 #endif /* #ifndef __L6474_H */
davide.aliprandi@st.com 33:8daea0279301 599
davide.aliprandi@st.com 33:8daea0279301 600 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/