TECHSTEP / Mbed 2 deprecated Nucleo_display_ssd1963

SSD1963 Initial code & test fill screen.

Dependencies:   mbed

SSD1963/SSD1963.cpp@0:2714fcd95190, 2014-04-18 (annotated)

Committer:
techstep
Date:
Fri Apr 18 04:16:35 2014 +0000
Revision:
0:2714fcd95190
ST Nucleo F401RE; 7" TFT LCD 800x480 [SSD1963]; Test TFT Init.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
techstep 0:2714fcd95190 1 /*****************************************************************************
techstep 0:2714fcd95190 2 * Project : 7" TFT LCD 800x480 [AT070TN92]
techstep 0:2714fcd95190 3 * Compiler : mbed Online
techstep 0:2714fcd95190 4 * Type : Libraries
techstep 0:2714fcd95190 5 * Comment : Support mbed ST Nucleo Board.
techstep 0:2714fcd95190 6 * : Support Chip = SSD1963
techstep 0:2714fcd95190 7 * File : SSD1963.c
techstep 0:2714fcd95190 8 *
techstep 0:2714fcd95190 9 * Author : Mr.Thongchai Artsamart [Bird Techstep]
techstep 0:2714fcd95190 10 * E-Mail : t.artsamart@gmail.com
techstep 0:2714fcd95190 11 * : tbird_th@hotmail.com
techstep 0:2714fcd95190 12 * Start Date : 20/03/2014 [dd/mm/yyyy]
techstep 0:2714fcd95190 13 * Version Date : 20/03/2014 [dd/mm/yyyy]
techstep 0:2714fcd95190 14 * Licensed under a Creative Commons Attribution-ShareAlike 3.0 License.
techstep 0:2714fcd95190 15 *****************************************************************************
techstep 0:2714fcd95190 16 * Remark : Thank you -. no1wudi [CooCox]
techstep 0:2714fcd95190 17 * -.
techstep 0:2714fcd95190 18 *****************************************************************************/
techstep 0:2714fcd95190 19 #include "mbed.h"
techstep 0:2714fcd95190 20 #include "SSD1963.h"
techstep 0:2714fcd95190 21 //#include "tFontLCD.c"
techstep 0:2714fcd95190 22 //#include "stm32f4xx.h"
techstep 0:2714fcd95190 23
techstep 0:2714fcd95190 24 /*
techstep 0:2714fcd95190 25 #define HDP 799 // [ 799][ 799] Horizontal Display Period
techstep 0:2714fcd95190 26 #define HT 928 // [ 928][1000] Horizontal Total
techstep 0:2714fcd95190 27 #define HPS 46 // [ 46][ 51] LLINE Pulse Start Position
techstep 0:2714fcd95190 28 #define LPS 15 // [ 15][ 3] Horizontal Display Period Start Position
techstep 0:2714fcd95190 29 #define HPW 48 // [ 48][ 8] LLINE Pulse Width
techstep 0:2714fcd95190 30 #define VDP 479 // [ 479][ 479] Vertical Display Period
techstep 0:2714fcd95190 31 #define VT 525 // [ 525][ 530] Vertical Total
techstep 0:2714fcd95190 32 #define VPS 16 // [ 16][ 24] LFRAME Pulse Start Position
techstep 0:2714fcd95190 33 #define FPS 8 // [ 8][ 23] Vertical Display Period Start Position
techstep 0:2714fcd95190 34 #define VPW 16 // [ 16][ 3] LFRAME Pulse Width
techstep 0:2714fcd95190 35 */
techstep 0:2714fcd95190 36
techstep 0:2714fcd95190 37 SSD1963::SSD1963() {
techstep 0:2714fcd95190 38 init();
techstep 0:2714fcd95190 39 }
techstep 0:2714fcd95190 40 /*
techstep 0:2714fcd95190 41 uint16_t SSD1963::width(void) {
techstep 0:2714fcd95190 42 return _width;
techstep 0:2714fcd95190 43 }
techstep 0:2714fcd95190 44 uint16_t SSD1963::height(void) {
techstep 0:2714fcd95190 45 return _height;
techstep 0:2714fcd95190 46 }
techstep 0:2714fcd95190 47 */
techstep 0:2714fcd95190 48 void SSD1963::init(void) {
techstep 0:2714fcd95190 49
techstep 0:2714fcd95190 50 /* GPIOC Periph clock enable */
techstep 0:2714fcd95190 51 //RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN); // For F401RE
techstep 0:2714fcd95190 52 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;
techstep 0:2714fcd95190 53 //RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
techstep 0:2714fcd95190 54 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;
techstep 0:2714fcd95190 55 //RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;
techstep 0:2714fcd95190 56
techstep 0:2714fcd95190 57 /* Configure PC[0..7] in input/output mode */
techstep 0:2714fcd95190 58 GPIOC->MODER |= (GPIO_MODER_MODER0_0 | GPIO_MODER_MODER1_0 | GPIO_MODER_MODER2_0 | GPIO_MODER_MODER3_0 |
techstep 0:2714fcd95190 59 GPIO_MODER_MODER4_0 | GPIO_MODER_MODER5_0 | GPIO_MODER_MODER6_0 | GPIO_MODER_MODER7_0);
techstep 0:2714fcd95190 60 /* Configure PA[8..15] in input/output mode */
techstep 0:2714fcd95190 61 GPIOC->MODER |= (GPIO_MODER_MODER8_0 | GPIO_MODER_MODER9_0 | GPIO_MODER_MODER10_0 | GPIO_MODER_MODER11_0 |
techstep 0:2714fcd95190 62 GPIO_MODER_MODER12_0 | GPIO_MODER_MODER13_0 | GPIO_MODER_MODER14_0 | GPIO_MODER_MODER15_0);
techstep 0:2714fcd95190 63 /* Configure PB[0:1:2:6:7] in input/output mode */
techstep 0:2714fcd95190 64 GPIOB->MODER |= (GPIO_MODER_MODER0_0 | GPIO_MODER_MODER1_0 | GPIO_MODER_MODER2_0 |
techstep 0:2714fcd95190 65 GPIO_MODER_MODER6_0 | GPIO_MODER_MODER7_0);
techstep 0:2714fcd95190 66
techstep 0:2714fcd95190 67 // Ensure push pull mode selected--default
techstep 0:2714fcd95190 68 GPIOC->OTYPER &= ~(GPIO_OTYPER_OT_0 | GPIO_OTYPER_OT_1 | GPIO_OTYPER_OT_2 | GPIO_OTYPER_OT_3 |
techstep 0:2714fcd95190 69 GPIO_OTYPER_OT_4 | GPIO_OTYPER_OT_5 | GPIO_OTYPER_OT_6 | GPIO_OTYPER_OT_7);
techstep 0:2714fcd95190 70 GPIOC->OTYPER &= ~(GPIO_OTYPER_OT_8 | GPIO_OTYPER_OT_9 | GPIO_OTYPER_OT_10 | GPIO_OTYPER_OT_11 |
techstep 0:2714fcd95190 71 GPIO_OTYPER_OT_12 | GPIO_OTYPER_OT_13 | GPIO_OTYPER_OT_14 | GPIO_OTYPER_OT_15);
techstep 0:2714fcd95190 72 GPIOB->OTYPER &= ~(GPIO_OTYPER_OT_0 | GPIO_OTYPER_OT_1 | GPIO_OTYPER_OT_2 |
techstep 0:2714fcd95190 73 GPIO_OTYPER_OT_6 | GPIO_OTYPER_OT_7);
techstep 0:2714fcd95190 74
techstep 0:2714fcd95190 75 //Ensure maximum speed setting (even though it is unnecessary)
techstep 0:2714fcd95190 76 GPIOC->OSPEEDR |= (GPIO_OSPEEDER_OSPEEDR0 | GPIO_OSPEEDER_OSPEEDR1 | GPIO_OSPEEDER_OSPEEDR2 | GPIO_OSPEEDER_OSPEEDR3 |
techstep 0:2714fcd95190 77 GPIO_OSPEEDER_OSPEEDR4 | GPIO_OSPEEDER_OSPEEDR5 | GPIO_OSPEEDER_OSPEEDR6 | GPIO_OSPEEDER_OSPEEDR7);
techstep 0:2714fcd95190 78 GPIOC->OSPEEDR |= (GPIO_OSPEEDER_OSPEEDR8 | GPIO_OSPEEDER_OSPEEDR9 | GPIO_OSPEEDER_OSPEEDR10 | GPIO_OSPEEDER_OSPEEDR11 |
techstep 0:2714fcd95190 79 GPIO_OSPEEDER_OSPEEDR12 | GPIO_OSPEEDER_OSPEEDR13 | GPIO_OSPEEDER_OSPEEDR14 | GPIO_OSPEEDER_OSPEEDR15);
techstep 0:2714fcd95190 80 GPIOB->OSPEEDR |= (GPIO_OSPEEDER_OSPEEDR0 | GPIO_OSPEEDER_OSPEEDR1 | GPIO_OSPEEDER_OSPEEDR2 |
techstep 0:2714fcd95190 81 GPIO_OSPEEDER_OSPEEDR6 | GPIO_OSPEEDER_OSPEEDR7);
techstep 0:2714fcd95190 82
techstep 0:2714fcd95190 83 //Ensure all pull up pull down resistors are disabled
techstep 0:2714fcd95190 84 //GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR0 | GPIO_PUPDR_PUPDR1 | GPIO_PUPDR_PUPDR2 | GPIO_PUPDR_PUPDR3 |
techstep 0:2714fcd95190 85 // GPIO_PUPDR_PUPDR4 | GPIO_PUPDR_PUPDR5 | GPIO_PUPDR_PUPDR6 | GPIO_PUPDR_PUPDR7);
techstep 0:2714fcd95190 86 // Pull UP
techstep 0:2714fcd95190 87 //GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR0_0 | GPIO_PUPDR_PUPDR1_0 | GPIO_PUPDR_PUPDR2_0 | GPIO_PUPDR_PUPDR3_0 |
techstep 0:2714fcd95190 88 // GPIO_PUPDR_PUPDR4_0 | GPIO_PUPDR_PUPDR5_0 | GPIO_PUPDR_PUPDR6_0 | GPIO_PUPDR_PUPDR7_0);
techstep 0:2714fcd95190 89 // Pull Down
techstep 0:2714fcd95190 90 GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR0_1 | GPIO_PUPDR_PUPDR1_1 | GPIO_PUPDR_PUPDR2_1 | GPIO_PUPDR_PUPDR3_1 |
techstep 0:2714fcd95190 91 GPIO_PUPDR_PUPDR4_1 | GPIO_PUPDR_PUPDR5_1 | GPIO_PUPDR_PUPDR6_1 | GPIO_PUPDR_PUPDR7_1);
techstep 0:2714fcd95190 92
techstep 0:2714fcd95190 93 //GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR8 | GPIO_PUPDR_PUPDR9 | GPIO_PUPDR_PUPDR10 | GPIO_PUPDR_PUPDR11 |
techstep 0:2714fcd95190 94 // GPIO_PUPDR_PUPDR12 | GPIO_PUPDR_PUPDR13 | GPIO_PUPDR_PUPDR14 | GPIO_PUPDR_PUPDR15);
techstep 0:2714fcd95190 95 GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR8_1 | GPIO_PUPDR_PUPDR9_1 | GPIO_PUPDR_PUPDR10_1 | GPIO_PUPDR_PUPDR11_1 |
techstep 0:2714fcd95190 96 GPIO_PUPDR_PUPDR12_1 | GPIO_PUPDR_PUPDR13_1 | GPIO_PUPDR_PUPDR14_1 | GPIO_PUPDR_PUPDR15_1);
techstep 0:2714fcd95190 97 GPIOB->PUPDR &= ~(GPIO_PUPDR_PUPDR0 | GPIO_PUPDR_PUPDR1 | GPIO_PUPDR_PUPDR2 |
techstep 0:2714fcd95190 98 GPIO_PUPDR_PUPDR6 | GPIO_PUPDR_PUPDR7);
techstep 0:2714fcd95190 99
techstep 0:2714fcd95190 100 wait_ms(100);
techstep 0:2714fcd95190 101 //rotation = 0;
techstep 0:2714fcd95190 102 //cursor_y = cursor_x = 0;
techstep 0:2714fcd95190 103 //textsize = 1;
techstep 0:2714fcd95190 104 //textcolor = 0xFFFF;
techstep 0:2714fcd95190 105 //_width = TFTWIDTH;
techstep 0:2714fcd95190 106 //_height = TFTHEIGHT;
techstep 0:2714fcd95190 107 //wrap = true;
techstep 0:2714fcd95190 108 }
techstep 0:2714fcd95190 109
techstep 0:2714fcd95190 110 void SSD1963::writeData(uint16_t data) {
techstep 0:2714fcd95190 111 CS_LOW; RS_HIGH; RD_HIGH; WR_HIGH;
techstep 0:2714fcd95190 112 //GPIOA->ODR = (data&0xFF00);
techstep 0:2714fcd95190 113 //GPIOC->ODR = (data&0x00FF);
techstep 0:2714fcd95190 114 GPIOC->ODR = (data&0xFFFF);
techstep 0:2714fcd95190 115 WR_STROBE;
techstep 0:2714fcd95190 116 CS_HIGH;
techstep 0:2714fcd95190 117 }
techstep 0:2714fcd95190 118
techstep 0:2714fcd95190 119 void SSD1963::writeCommand(uint16_t cmd) {
techstep 0:2714fcd95190 120 CS_LOW; RS_LOW; RD_HIGH; WR_HIGH;
techstep 0:2714fcd95190 121 //GPIOA->ODR = (cmd&0xFF00);
techstep 0:2714fcd95190 122 //GPIOC->ODR = (cmd&0x00FF);
techstep 0:2714fcd95190 123 GPIOC->ODR = (cmd&0xFFFF);
techstep 0:2714fcd95190 124 WR_STROBE;
techstep 0:2714fcd95190 125 RS_HIGH;
techstep 0:2714fcd95190 126 CS_HIGH;
techstep 0:2714fcd95190 127 }
techstep 0:2714fcd95190 128
techstep 0:2714fcd95190 129 uint16_t SSD1963::readData(void) {
techstep 0:2714fcd95190 130 uint16_t data = 0x0000;
techstep 0:2714fcd95190 131 CS_LOW; RS_HIGH; RD_LOW; WR_HIGH;
techstep 0:2714fcd95190 132 wait_us(10);
techstep 0:2714fcd95190 133 //data = (GPIOA->IDR&0xFF00 | GPIOC->IDR&0x00FF);
techstep 0:2714fcd95190 134 data = (GPIOC->IDR&0xFFFF);
techstep 0:2714fcd95190 135 RD_HIGH;
techstep 0:2714fcd95190 136 CS_HIGH;
techstep 0:2714fcd95190 137 return data;
techstep 0:2714fcd95190 138 }
techstep 0:2714fcd95190 139
techstep 0:2714fcd95190 140 void SSD1963::writeRegister(uint16_t addr, uint16_t data) {
techstep 0:2714fcd95190 141 writeCommand(addr);
techstep 0:2714fcd95190 142 writeData(data);
techstep 0:2714fcd95190 143 }
techstep 0:2714fcd95190 144
techstep 0:2714fcd95190 145 void SSD1963::reset(void) {
techstep 0:2714fcd95190 146 //CS_LOW;
techstep 0:2714fcd95190 147 RST_HIGH; wait_ms(2);
techstep 0:2714fcd95190 148 RST_LOW; wait_ms(2);
techstep 0:2714fcd95190 149 RST_HIGH; wait_ms(4);
techstep 0:2714fcd95190 150
techstep 0:2714fcd95190 151 CS_HIGH;
techstep 0:2714fcd95190 152 RS_HIGH;
techstep 0:2714fcd95190 153 RD_HIGH;
techstep 0:2714fcd95190 154 WR_HIGH;
techstep 0:2714fcd95190 155 }
techstep 0:2714fcd95190 156
techstep 0:2714fcd95190 157 void SSD1963::begin() {
techstep 0:2714fcd95190 158
techstep 0:2714fcd95190 159 reset();
techstep 0:2714fcd95190 160 wait_ms(10);
techstep 0:2714fcd95190 161 // Set PLL MN -------------------------------------------------------------
techstep 0:2714fcd95190 162 // @Parameters : 3
techstep 0:2714fcd95190 163 writeCommand(0xE2);
techstep 0:2714fcd95190 164 writeData(0x23); // N[7:0] : Multiplier (N) of PLL. (POR = 00101101) b00100011
techstep 0:2714fcd95190 165 writeData(0x02); // M[3:0] : Divider (M) of PLL. (POR = 0011)
techstep 0:2714fcd95190 166 writeData(0x04); // C[2] : Effectuate MN value (POR = 100) - Effectuate the multiplier and divider value
techstep 0:2714fcd95190 167 //writeData(0x54);
techstep 0:2714fcd95190 168
techstep 0:2714fcd95190 169 // Set PLL
techstep 0:2714fcd95190 170 // @Parameters : 1
techstep 0:2714fcd95190 171 writeCommand(0xE0);
techstep 0:2714fcd95190 172 writeData(0x01); // Use reference clock as system clock & Enable PLL
techstep 0:2714fcd95190 173 wait_us(100); // Wait 100us to let the PLL stable
techstep 0:2714fcd95190 174 writeCommand(0xE0); // Set PLL
techstep 0:2714fcd95190 175 writeData(0x03); // Use PLL output as system clock & Enable PLL
techstep 0:2714fcd95190 176 wait_us(100);
techstep 0:2714fcd95190 177
techstep 0:2714fcd95190 178 // Software Reset ---------------------------------------------------------
techstep 0:2714fcd95190 179 writeCommand(0x01);
techstep 0:2714fcd95190 180 wait_us(100);
techstep 0:2714fcd95190 181
techstep 0:2714fcd95190 182 // Set LSHIFT Frequency ---------------------------------------------------
techstep 0:2714fcd95190 183 // @Parameters : 3
techstep 0:2714fcd95190 184 writeCommand(0xE6); // Set LSHIFT Frequency
techstep 0:2714fcd95190 185 writeData(0x03); // LCDC_FPR[19:16] : The highest 4 bits for the pixel clock frequency settings
techstep 0:2714fcd95190 186 writeData(0xFF); // LCDC_FPR[15:8] : The higher byte for the pixel clock frequency settings
techstep 0:2714fcd95190 187 writeData(0xFF); // LCDC_FPR[7:0] : The low byte for the pixel clock frequency settings
techstep 0:2714fcd95190 188
techstep 0:2714fcd95190 189 // Set LCD Mode
techstep 0:2714fcd95190 190 // @Parameters : 7
techstep 0:2714fcd95190 191 writeCommand(0xB0);
techstep 0:2714fcd95190 192 /*
techstep 0:2714fcd95190 193 writeData(0x00); // A[5..0] TFT
techstep 0:2714fcd95190 194 //writeData(0x10);
techstep 0:2714fcd95190 195 writeData(0x00); // B[7..5] : Hsync+Vsync +DE mode & TFT mode
techstep 0:2714fcd95190 196 //writeData(0x80);
techstep 0:2714fcd95190 197 writeData((HDP>>8)&0xFF); // HPS[10:8] : Set the horizontal panel size (POR = 010)
techstep 0:2714fcd95190 198 writeData(HDP&0xFF); // HPS[7:0] : Set the horizontal panel size (POR = 01111111)
techstep 0:2714fcd95190 199 writeData((VDP>>8)&0xFF); // VPS[10:8] : Set the vertical panel size (POR = 001)
techstep 0:2714fcd95190 200 writeData(VDP&0xFF); // VPS[7:0] : Set the vertical panel size (POR = 11011111)
techstep 0:2714fcd95190 201 writeData(0x00); // G[5..0] : Even line RGB sequence & Odd line RGB sequence
techstep 0:2714fcd95190 202 */
techstep 0:2714fcd95190 203 writeData(0x10); // set 18-bit for 7" panel TY700TFT800480
techstep 0:2714fcd95190 204 writeData(0x80); // set TTL mode
techstep 0:2714fcd95190 205 writeData((DISP_HOR_RESOLUTION-1)>>8); //Set panel size
techstep 0:2714fcd95190 206 writeData(DISP_HOR_RESOLUTION-1);
techstep 0:2714fcd95190 207 writeData((DISP_VER_RESOLUTION-1)>>8);
techstep 0:2714fcd95190 208 writeData(DISP_VER_RESOLUTION-1);
techstep 0:2714fcd95190 209 writeData(0x00);
techstep 0:2714fcd95190 210
techstep 0:2714fcd95190 211
techstep 0:2714fcd95190 212 // Set Horizontal Period --------------------------------------------------
techstep 0:2714fcd95190 213 // @Parameters : 8
techstep 0:2714fcd95190 214 writeCommand(0xB4);
techstep 0:2714fcd95190 215 /*
techstep 0:2714fcd95190 216 writeData((HT>>8)&0xFF); // HT[10:8] : High byte of horizontal total period (display + non-display) in pixel clock
techstep 0:2714fcd95190 217 writeData(HT&0xFF); // HT[7:0] : Low byte of the horizontal total period (display + non-display) in pixel clock
techstep 0:2714fcd95190 218 writeData((HPS>>8)&0xFF); // HPS[10:8] : High byte of the non-display period between the start of the horizontal sync (LLINE) signal
techstep 0:2714fcd95190 219 writeData(HPS&0xFF); // HPS[7:0] : Low byte of the non-display period between the start of the horizontal sync (LLINE) signal
techstep 0:2714fcd95190 220 writeData(HPW&0xFF); // HPW[6:0] : Set the horizontal sync pulse width (LLINE) in pixel clock
techstep 0:2714fcd95190 221 writeData((LPS>>8)&0xFF); // LPS[10:8] : Set the horizontal sync pulse (LLINE) start location in pixel clock
techstep 0:2714fcd95190 222 writeData(LPS&0xFF); // LPS[7:0] : Set the horizontal sync pulse width (LLINE) in start.
techstep 0:2714fcd95190 223 writeData(0x00); // LPSPP[1:0] : Set the horizontal sync pulse subpixel start position
techstep 0:2714fcd95190 224 */
techstep 0:2714fcd95190 225 #define HT (DISP_HOR_RESOLUTION+DISP_HOR_PULSE_WIDTH+DISP_HOR_BACK_PORCH+DISP_HOR_FRONT_PORCH)
techstep 0:2714fcd95190 226 writeData((HT-1)>>8);
techstep 0:2714fcd95190 227 writeData(HT-1);
techstep 0:2714fcd95190 228 #define HPS (DISP_HOR_PULSE_WIDTH+DISP_HOR_BACK_PORCH)
techstep 0:2714fcd95190 229 writeData((HPS-1)>>8);
techstep 0:2714fcd95190 230 writeData(HPS-1);
techstep 0:2714fcd95190 231 writeData(DISP_HOR_PULSE_WIDTH-1);
techstep 0:2714fcd95190 232 writeData(0x00);
techstep 0:2714fcd95190 233 writeData(0x00);
techstep 0:2714fcd95190 234 writeData(0x00);
techstep 0:2714fcd95190 235
techstep 0:2714fcd95190 236 // Set Vertical Period ----------------------------------------------------
techstep 0:2714fcd95190 237 // @Parameters : 7
techstep 0:2714fcd95190 238 writeCommand(0xB6);
techstep 0:2714fcd95190 239 /*
techstep 0:2714fcd95190 240 writeData((VT>>8)&0xFF); // VT[10:8] : High byte of the vertical total (display + non-display) period in lines
techstep 0:2714fcd95190 241 writeData(VT&0xFF); // VT[7:0] : Low byte of the vertical total (display + non-display) period in lines
techstep 0:2714fcd95190 242 writeData((VPS>>8)&0xFF); // VPS[10:8] : High byte the non-display period in lines between the start of the frame and the first display data in line
techstep 0:2714fcd95190 243 writeData(VPS&0xFF); // VPS[7:0] : The non-display period in lines between the start of the frame and the first display data in line
techstep 0:2714fcd95190 244 writeData(VPW&0xFF); // VPW[6:0] : Set the vertical sync pulse width (LFRAME) in lines
techstep 0:2714fcd95190 245 writeData((FPS>>8)&0xFF); // FPS[10:8] : High byte of the vertical sync pulse (LFRAME) start location in lines
techstep 0:2714fcd95190 246 writeData(FPS&0xFF); // FPS[7:0] : Low byte of the vertical sync pulse (LFRAME) start location in lines
techstep 0:2714fcd95190 247 */
techstep 0:2714fcd95190 248 #define VT (DISP_VER_PULSE_WIDTH+DISP_VER_BACK_PORCH+DISP_VER_FRONT_PORCH+DISP_VER_RESOLUTION)
techstep 0:2714fcd95190 249 writeData((VT-1)>>8);
techstep 0:2714fcd95190 250 writeData(VT-1);
techstep 0:2714fcd95190 251 #define VSP (DISP_VER_PULSE_WIDTH+DISP_VER_BACK_PORCH)
techstep 0:2714fcd95190 252 writeData((VSP-1)>>8);
techstep 0:2714fcd95190 253 writeData(VSP-1);
techstep 0:2714fcd95190 254 writeData(DISP_VER_PULSE_WIDTH-1);
techstep 0:2714fcd95190 255 writeData(0x00);
techstep 0:2714fcd95190 256 writeData(0x00);
techstep 0:2714fcd95190 257
techstep 0:2714fcd95190 258 // Set GPIO Value ---------------------------------------------------------
techstep 0:2714fcd95190 259 // @Parameters : 1
techstep 0:2714fcd95190 260 writeCommand(0xBA);
techstep 0:2714fcd95190 261 writeData(0x05); // A[3..0] : GPIO[2:0] Output 1
techstep 0:2714fcd95190 262
techstep 0:2714fcd95190 263 // Set GPIO Configuration
techstep 0:2714fcd95190 264 // @Parameters : 2
techstep 0:2714fcd95190 265 writeCommand(0xB8);
techstep 0:2714fcd95190 266 writeData(0x07); // A[7..0] : GPIO3 = Input, GPIO[2:0] = Output
techstep 0:2714fcd95190 267 writeData(0x01); // B[0] : GPIO0 Normal
techstep 0:2714fcd95190 268
techstep 0:2714fcd95190 269 //Set pixel format, i.e. the bpp
techstep 0:2714fcd95190 270 writeCommand(0x3A);
techstep 0:2714fcd95190 271 writeData(0x55); // set 16bpp
techstep 0:2714fcd95190 272
techstep 0:2714fcd95190 273 // Set Address Mode -------------------------------------------------------
techstep 0:2714fcd95190 274 // @Parameters : 1
techstep 0:2714fcd95190 275 //writeCommand(0x36); // Set Rotation
techstep 0:2714fcd95190 276 //writeData(0x00); // A[7..0] : Set the read order from host processor to frame buffer by A[7:5] and A[3] and
techstep 0:2714fcd95190 277 // from frame buffer to the display panel by A[2:0] and A[4].
techstep 0:2714fcd95190 278 // A[7] : Page address order
techstep 0:2714fcd95190 279 // Set Pixel Data Interface -----------------------------------------------
techstep 0:2714fcd95190 280 // @Parameters : 1
techstep 0:2714fcd95190 281 writeCommand(0xF0); // A[2:0] : Pixel Data Interface Format
techstep 0:2714fcd95190 282 writeData(0x03); // 16-bit (565 format)
techstep 0:2714fcd95190 283 wait_us(100);
techstep 0:2714fcd95190 284
techstep 0:2714fcd95190 285 // enter_partial_mode
techstep 0:2714fcd95190 286 //writeCommand(0x12); // Part of the display area is used for image display
techstep 0:2714fcd95190 287 // set_display_on
techstep 0:2714fcd95190 288 writeCommand(0x29); // Show the image on the display device
techstep 0:2714fcd95190 289
techstep 0:2714fcd95190 290 //writeCommand(0x2C);
techstep 0:2714fcd95190 291 }
techstep 0:2714fcd95190 292
techstep 0:2714fcd95190 293 void SSD1963::fillScreen(uint16_t color){
techstep 0:2714fcd95190 294
techstep 0:2714fcd95190 295 uint16_t start_x = 0;
techstep 0:2714fcd95190 296 uint16_t end_x = 799;
techstep 0:2714fcd95190 297 uint16_t start_y = 0;
techstep 0:2714fcd95190 298 uint16_t end_y = 479;
techstep 0:2714fcd95190 299
techstep 0:2714fcd95190 300 writeCommand(0x2A);
techstep 0:2714fcd95190 301 //nCS_LOW;
techstep 0:2714fcd95190 302 writeData(start_x>>8);
techstep 0:2714fcd95190 303 writeData(start_x);
techstep 0:2714fcd95190 304 writeData(end_x>>8);
techstep 0:2714fcd95190 305 writeData(end_x);
techstep 0:2714fcd95190 306 //nCS_HIGH;
techstep 0:2714fcd95190 307 writeCommand(0x2B);
techstep 0:2714fcd95190 308 //nCS_LOW;
techstep 0:2714fcd95190 309 writeData(start_y>>8);
techstep 0:2714fcd95190 310 writeData(start_y);
techstep 0:2714fcd95190 311 writeData(end_y>>8);
techstep 0:2714fcd95190 312 writeData(end_y);
techstep 0:2714fcd95190 313 //nCS_HIGH;
techstep 0:2714fcd95190 314
techstep 0:2714fcd95190 315 writeCommand(0x2C);
techstep 0:2714fcd95190 316
techstep 0:2714fcd95190 317 uint16_t i,j;
techstep 0:2714fcd95190 318 for(i=0;i<800;i++){
techstep 0:2714fcd95190 319 for (j=0;j<480;j++){
techstep 0:2714fcd95190 320 writeData(color);
techstep 0:2714fcd95190 321 }
techstep 0:2714fcd95190 322 }
techstep 0:2714fcd95190 323 }
techstep 0:2714fcd95190 324
techstep 0:2714fcd95190 325 // - Color RGB R5 G6 B5 -------------------------------------------------------
techstep 0:2714fcd95190 326 uint16_t SSD1963::Color565(uint8_t r, uint8_t g, uint8_t b) {
techstep 0:2714fcd95190 327 uint16_t c;
techstep 0:2714fcd95190 328 c = r >> 3;
techstep 0:2714fcd95190 329 c <<= 6;
techstep 0:2714fcd95190 330 c |= g >> 2;
techstep 0:2714fcd95190 331 c <<= 5;
techstep 0:2714fcd95190 332 c |= b >> 3;
techstep 0:2714fcd95190 333 return c;
techstep 0:2714fcd95190 334 }
techstep 0:2714fcd95190 335