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Dependents:   SPI_slave_frdm

Fork of mbed-src by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/spi_api.c@251:de9a1e4ffd79, 2014-07-08 (annotated)

Committer:
mbed_official
Date:
Tue Jul 08 14:15:07 2014 +0100
Revision:
251:de9a1e4ffd79
Parent:
250:a49055e7a707
Child:
265:9632ea190e16
Synchronized with git revision b0ac1e3485a9aa1cb98d1ca68df9d1cdbcd6ce63



Full URL: https://github.com/mbedmicro/mbed/commit/b0ac1e3485a9aa1cb98d1ca68df9d1cdbcd6ce63/



Revert "error.h -> mbed_error.h"

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /* mbed Microcontroller Library
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2013 ARM Limited
mbed_official 146:f64d43ff0c18 3 *
mbed_official 146:f64d43ff0c18 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 146:f64d43ff0c18 5 * you may not use this file except in compliance with the License.
mbed_official 146:f64d43ff0c18 6 * You may obtain a copy of the License at
mbed_official 146:f64d43ff0c18 7 *
mbed_official 146:f64d43ff0c18 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 146:f64d43ff0c18 9 *
mbed_official 146:f64d43ff0c18 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 146:f64d43ff0c18 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 146:f64d43ff0c18 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 146:f64d43ff0c18 13 * See the License for the specific language governing permissions and
mbed_official 146:f64d43ff0c18 14 * limitations under the License.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 227:7bd0639b8911 16 #include <math.h>
mbed_official 227:7bd0639b8911 17 #include "mbed_assert.h"
mbed_official 146:f64d43ff0c18 18
mbed_official 227:7bd0639b8911 19 #include "spi_api.h"
mbed_official 146:f64d43ff0c18 20 #include "cmsis.h"
mbed_official 146:f64d43ff0c18 21 #include "pinmap.h"
mbed_official 251:de9a1e4ffd79 22 #include "error.h"
mbed_official 146:f64d43ff0c18 23 #include "fsl_clock_manager.h"
mbed_official 146:f64d43ff0c18 24 #include "fsl_dspi_hal.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 static const PinMap PinMap_SPI_SCLK[] = {
mbed_official 146:f64d43ff0c18 27 {PTD1 , SPI_0, 2},
mbed_official 146:f64d43ff0c18 28 {PTE2 , SPI_1, 2},
mbed_official 146:f64d43ff0c18 29 {PTA15, SPI_0, 2},
mbed_official 146:f64d43ff0c18 30 {PTB11, SPI_1, 2},
mbed_official 146:f64d43ff0c18 31 {PTB21, SPI_2, 2},
mbed_official 146:f64d43ff0c18 32 {PTC5 , SPI_0, 2},
mbed_official 146:f64d43ff0c18 33 {PTD5 , SPI_1, 7},
mbed_official 146:f64d43ff0c18 34 {NC , NC , 0}
mbed_official 146:f64d43ff0c18 35 };
mbed_official 146:f64d43ff0c18 36
mbed_official 146:f64d43ff0c18 37 static const PinMap PinMap_SPI_MOSI[] = {
mbed_official 146:f64d43ff0c18 38 {PTD2 , SPI_0, 2},
mbed_official 146:f64d43ff0c18 39 {PTE1 , SPI_1, 2},
mbed_official 146:f64d43ff0c18 40 {PTE3 , SPI_1, 7},
mbed_official 146:f64d43ff0c18 41 {PTA16, SPI_0, 2},
mbed_official 146:f64d43ff0c18 42 {PTB16, SPI_1, 2},
mbed_official 146:f64d43ff0c18 43 {PTB22, SPI_2, 2},
mbed_official 146:f64d43ff0c18 44 {PTC6 , SPI_0, 2},
mbed_official 158:3121b9889f7b 45 {PTD6 , SPI_1, 7},
mbed_official 146:f64d43ff0c18 46 {NC , NC , 0}
mbed_official 146:f64d43ff0c18 47 };
mbed_official 146:f64d43ff0c18 48
mbed_official 146:f64d43ff0c18 49 static const PinMap PinMap_SPI_MISO[] = {
mbed_official 146:f64d43ff0c18 50 {PTD3 , SPI_0, 2},
mbed_official 146:f64d43ff0c18 51 {PTE1 , SPI_1, 7},
mbed_official 146:f64d43ff0c18 52 {PTE3 , SPI_1, 2},
mbed_official 146:f64d43ff0c18 53 {PTA17, SPI_0, 2},
mbed_official 146:f64d43ff0c18 54 {PTB17, SPI_1, 2},
mbed_official 146:f64d43ff0c18 55 {PTB23, SPI_2, 2},
mbed_official 146:f64d43ff0c18 56 {PTC7 , SPI_0, 2},
mbed_official 146:f64d43ff0c18 57 {PTD7 , SPI_1, 7},
mbed_official 146:f64d43ff0c18 58 {NC , NC , 0}
mbed_official 146:f64d43ff0c18 59 };
mbed_official 146:f64d43ff0c18 60
mbed_official 146:f64d43ff0c18 61 static const PinMap PinMap_SPI_SSEL[] = {
mbed_official 146:f64d43ff0c18 62 {PTD0 , SPI_0, 2},
mbed_official 146:f64d43ff0c18 63 {PTE4 , SPI_1, 2},
mbed_official 146:f64d43ff0c18 64 {PTA14, SPI_0, 2},
mbed_official 146:f64d43ff0c18 65 {PTB10, SPI_1, 2},
mbed_official 146:f64d43ff0c18 66 {PTB20, SPI_2, 2},
mbed_official 146:f64d43ff0c18 67 {PTC4 , SPI_0, 2},
mbed_official 146:f64d43ff0c18 68 {PTD4 , SPI_1, 7},
mbed_official 146:f64d43ff0c18 69 {NC , NC , 0}
mbed_official 146:f64d43ff0c18 70 };
mbed_official 146:f64d43ff0c18 71
mbed_official 146:f64d43ff0c18 72 static void spi_set_delays(uint32_t instance) {
mbed_official 146:f64d43ff0c18 73 dspi_delay_settings_config_t delay_config;
mbed_official 146:f64d43ff0c18 74 delay_config.pcsToSck = 1; /*!< PCS to SCK delay (CSSCK): initialize the scalar
mbed_official 146:f64d43ff0c18 75 * value to '1' to provide the master with a little
mbed_official 146:f64d43ff0c18 76 * more data-in read setup time.
mbed_official 146:f64d43ff0c18 77 */
mbed_official 146:f64d43ff0c18 78 delay_config.pcsToSckPre = 0; /*!< PCS to SCK delay prescalar (PCSSCK) */
mbed_official 146:f64d43ff0c18 79 delay_config.afterSckPre = 0; /*!< After SCK delay prescalar (PASC)*/
mbed_official 146:f64d43ff0c18 80 delay_config.afterSck = 0; /*!< After SCK delay scalar (ASC)*/
mbed_official 146:f64d43ff0c18 81 delay_config.afterTransferPre = 0; /*!< Delay after transfer prescalar (PDT)*/
mbed_official 146:f64d43ff0c18 82 delay_config.afterTransfer = 0;
mbed_official 146:f64d43ff0c18 83 dspi_hal_configure_delays(instance, kDspiCtar0, &delay_config);
mbed_official 146:f64d43ff0c18 84 }
mbed_official 146:f64d43ff0c18 85
mbed_official 146:f64d43ff0c18 86 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
mbed_official 146:f64d43ff0c18 87 // determine the SPI to use
mbed_official 146:f64d43ff0c18 88 uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
mbed_official 146:f64d43ff0c18 89 uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
mbed_official 146:f64d43ff0c18 90 uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
mbed_official 146:f64d43ff0c18 91 uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
mbed_official 146:f64d43ff0c18 92 uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
mbed_official 146:f64d43ff0c18 93 uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
mbed_official 146:f64d43ff0c18 94
mbed_official 146:f64d43ff0c18 95 obj->instance = pinmap_merge(spi_data, spi_cntl);
mbed_official 227:7bd0639b8911 96 MBED_ASSERT((int)obj->instance != NC);
mbed_official 146:f64d43ff0c18 97
mbed_official 146:f64d43ff0c18 98 // enable power and clocking
mbed_official 146:f64d43ff0c18 99 clock_manager_set_gate(kClockModuleSPI, obj->instance, true);
mbed_official 146:f64d43ff0c18 100
mbed_official 146:f64d43ff0c18 101 dspi_hal_disable(obj->instance);
mbed_official 146:f64d43ff0c18 102 // set default format and frequency
mbed_official 146:f64d43ff0c18 103 if (ssel == NC) {
mbed_official 146:f64d43ff0c18 104 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
mbed_official 146:f64d43ff0c18 105 } else {
mbed_official 146:f64d43ff0c18 106 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
mbed_official 146:f64d43ff0c18 107 }
mbed_official 146:f64d43ff0c18 108 spi_set_delays(obj->instance);
mbed_official 146:f64d43ff0c18 109 spi_frequency(obj, 1000000);
mbed_official 146:f64d43ff0c18 110
mbed_official 146:f64d43ff0c18 111 dspi_hal_enable(obj->instance);
mbed_official 146:f64d43ff0c18 112 dspi_hal_start_transfer(obj->instance);
mbed_official 146:f64d43ff0c18 113
mbed_official 146:f64d43ff0c18 114 // pin out the spi pins
mbed_official 146:f64d43ff0c18 115 pinmap_pinout(mosi, PinMap_SPI_MOSI);
mbed_official 146:f64d43ff0c18 116 pinmap_pinout(miso, PinMap_SPI_MISO);
mbed_official 146:f64d43ff0c18 117 pinmap_pinout(sclk, PinMap_SPI_SCLK);
mbed_official 146:f64d43ff0c18 118 if (ssel != NC) {
mbed_official 146:f64d43ff0c18 119 pinmap_pinout(ssel, PinMap_SPI_SSEL);
mbed_official 146:f64d43ff0c18 120 }
mbed_official 146:f64d43ff0c18 121 }
mbed_official 146:f64d43ff0c18 122
mbed_official 146:f64d43ff0c18 123 void spi_free(spi_t *obj) {
mbed_official 146:f64d43ff0c18 124 // [TODO]
mbed_official 146:f64d43ff0c18 125 }
mbed_official 146:f64d43ff0c18 126 void spi_format(spi_t *obj, int bits, int mode, int slave) {
mbed_official 146:f64d43ff0c18 127 dspi_data_format_config_t config = {0};
mbed_official 146:f64d43ff0c18 128 config.bitsPerFrame = (uint32_t)bits;
mbed_official 146:f64d43ff0c18 129 config.clkPolarity = (mode & 0x2) ? kDspiClockPolarity_ActiveLow : kDspiClockPolarity_ActiveHigh;
mbed_official 146:f64d43ff0c18 130 config.clkPhase = (mode & 0x1) ? kDspiClockPhase_SecondEdge : kDspiClockPhase_FirstEdge;
mbed_official 146:f64d43ff0c18 131 config.direction = kDspiMsbFirst;
mbed_official 146:f64d43ff0c18 132 dspi_status_t result = dspi_hal_configure_data_format(obj->instance, kDspiCtar0, &config);
mbed_official 146:f64d43ff0c18 133 if (result != kStatus_DSPI_Success) {
mbed_official 146:f64d43ff0c18 134 error("Failed to configure SPI data format");
mbed_official 146:f64d43ff0c18 135 }
mbed_official 146:f64d43ff0c18 136
mbed_official 146:f64d43ff0c18 137 if (slave) {
mbed_official 146:f64d43ff0c18 138 dspi_hal_set_master_slave(obj->instance, kDspiSlave);
mbed_official 146:f64d43ff0c18 139 } else {
mbed_official 146:f64d43ff0c18 140 dspi_hal_set_master_slave(obj->instance, kDspiMaster);
mbed_official 146:f64d43ff0c18 141 }
mbed_official 146:f64d43ff0c18 142 }
mbed_official 146:f64d43ff0c18 143
mbed_official 146:f64d43ff0c18 144 void spi_frequency(spi_t *obj, int hz) {
mbed_official 146:f64d43ff0c18 145 uint32_t busClock;
mbed_official 146:f64d43ff0c18 146 clock_manager_get_frequency(kBusClock, &busClock);
mbed_official 146:f64d43ff0c18 147 dspi_hal_set_baud(obj->instance, kDspiCtar0, (uint32_t)hz, busClock);
mbed_official 146:f64d43ff0c18 148 }
mbed_official 146:f64d43ff0c18 149
mbed_official 146:f64d43ff0c18 150 static inline int spi_writeable(spi_t * obj) {
mbed_official 146:f64d43ff0c18 151 return dspi_hal_get_status_flag(obj->instance, kDspiTxFifoFillRequest);
mbed_official 146:f64d43ff0c18 152 }
mbed_official 146:f64d43ff0c18 153
mbed_official 146:f64d43ff0c18 154 static inline int spi_readable(spi_t * obj) {
mbed_official 146:f64d43ff0c18 155 return dspi_hal_get_status_flag(obj->instance, kDspiRxFifoDrainRequest);
mbed_official 146:f64d43ff0c18 156 }
mbed_official 146:f64d43ff0c18 157
mbed_official 146:f64d43ff0c18 158 int spi_master_write(spi_t *obj, int value) {
mbed_official 146:f64d43ff0c18 159 // wait tx buffer empty
mbed_official 146:f64d43ff0c18 160 while(!spi_writeable(obj));
mbed_official 146:f64d43ff0c18 161 dspi_command_config_t command = {0};
mbed_official 146:f64d43ff0c18 162 command.isEndOfQueue = true;
mbed_official 146:f64d43ff0c18 163 command.isChipSelectContinuous = 0;
mbed_official 146:f64d43ff0c18 164 dspi_hal_write_data_master_mode(obj->instance, &command, (uint16_t)value);
mbed_official 146:f64d43ff0c18 165 dspi_hal_clear_status_flag(obj->instance, kDspiTxFifoFillRequest);
mbed_official 146:f64d43ff0c18 166
mbed_official 146:f64d43ff0c18 167 // wait rx buffer full
mbed_official 146:f64d43ff0c18 168 while (!spi_readable(obj));
mbed_official 146:f64d43ff0c18 169 dspi_hal_clear_status_flag(obj->instance, kDspiRxFifoDrainRequest);
mbed_official 146:f64d43ff0c18 170 return dspi_hal_read_data(obj->instance) & 0xff;
mbed_official 146:f64d43ff0c18 171 }
mbed_official 146:f64d43ff0c18 172
mbed_official 146:f64d43ff0c18 173 int spi_slave_receive(spi_t *obj) {
mbed_official 146:f64d43ff0c18 174 return spi_readable(obj);
mbed_official 146:f64d43ff0c18 175 }
mbed_official 146:f64d43ff0c18 176
mbed_official 146:f64d43ff0c18 177 int spi_slave_read(spi_t *obj) {
mbed_official 146:f64d43ff0c18 178 return dspi_hal_read_data(obj->instance);
mbed_official 146:f64d43ff0c18 179 }
mbed_official 146:f64d43ff0c18 180
mbed_official 146:f64d43ff0c18 181 void spi_slave_write(spi_t *obj, int value) {
mbed_official 146:f64d43ff0c18 182 while (!spi_writeable(obj));
mbed_official 146:f64d43ff0c18 183 dspi_hal_write_data_slave_mode(obj->instance, (uint32_t)value);
mbed_official 146:f64d43ff0c18 184 }