Šolski center Kranj / Mbed 2 deprecated 005-pwm

This program demonstrates the usage of the PWM. Program sets PWM0 chanel 1 and outputs it to the pin P1.2 where we get a PWM signal with a constant working cycle.

Dependencies:   mbed

LPC4088-pwm.h@0:c1305ab902af, 2015-05-02 (annotated)

Committer:
71GA
Date:
Sat May 02 17:29:12 2015 +0000
Revision:
0:c1305ab902af
First commit of this program.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
71GA 0:c1305ab902af 1 //definicije registrov za periferijo PWM
71GA 0:c1305ab902af 2
71GA 0:c1305ab902af 3 //PWM0
71GA 0:c1305ab902af 4 #define IR (*((volatile unsigned int *) 0x40014000))
71GA 0:c1305ab902af 5 #define TCR (*((volatile unsigned int *) 0x40014004))
71GA 0:c1305ab902af 6 #define TC (*((volatile unsigned int *) 0x40014008))
71GA 0:c1305ab902af 7 #define PR (*((volatile unsigned int *) 0x4001400C))
71GA 0:c1305ab902af 8 #define PC (*((volatile unsigned int *) 0x40014010))
71GA 0:c1305ab902af 9
71GA 0:c1305ab902af 10 #define MCR (*((volatile unsigned int *) 0x40014014))
71GA 0:c1305ab902af 11 #define MR0 (*((volatile unsigned int *) 0x40014018))
71GA 0:c1305ab902af 12 #define MR1 (*((volatile unsigned int *) 0x4001401C))
71GA 0:c1305ab902af 13 #define MR2 (*((volatile unsigned int *) 0x40014020))
71GA 0:c1305ab902af 14 #define MR3 (*((volatile unsigned int *) 0x40014024))
71GA 0:c1305ab902af 15 #define MR4 (*((volatile unsigned int *) 0x40014040))
71GA 0:c1305ab902af 16 #define MR5 (*((volatile unsigned int *) 0x40014044))
71GA 0:c1305ab902af 17 #define MR6 (*((volatile unsigned int *) 0x40014048))
71GA 0:c1305ab902af 18
71GA 0:c1305ab902af 19 #define CCR (*((volatile unsigned int *) 0x40014028))
71GA 0:c1305ab902af 20 #define CR0 (*((volatile unsigned int *) 0x4001402C))
71GA 0:c1305ab902af 21 #define CR1 (*((volatile unsigned int *) 0x40014030))
71GA 0:c1305ab902af 22
71GA 0:c1305ab902af 23 #define PCR (*((volatile unsigned int *) 0x4001404C))
71GA 0:c1305ab902af 24 #define LER (*((volatile unsigned int *) 0x40014050))
71GA 0:c1305ab902af 25 #define CTCR (*((volatile unsigned int *) 0x40014070))
71GA 0:c1305ab902af 26
71GA 0:c1305ab902af 27 /*
71GA 0:c1305ab902af 28 //PWM1
71GA 0:c1305ab902af 29 #define IR (*((volatile unsigned int *) 0x40018000))
71GA 0:c1305ab902af 30 #define TCR (*((volatile unsigned int *) 0x40018004))
71GA 0:c1305ab902af 31 #define TC (*((volatile unsigned int *) 0x40018008))
71GA 0:c1305ab902af 32 #define PR (*((volatile unsigned int *) 0x4001800C))
71GA 0:c1305ab902af 33 #define PC (*((volatile unsigned int *) 0x40018010))
71GA 0:c1305ab902af 34
71GA 0:c1305ab902af 35 #define MCR (*((volatile unsigned int *) 0x40018014))
71GA 0:c1305ab902af 36 #define MR0 (*((volatile unsigned int *) 0x40018018))
71GA 0:c1305ab902af 37 #define MR1 (*((volatile unsigned int *) 0x4001801C))
71GA 0:c1305ab902af 38 #define MR2 (*((volatile unsigned int *) 0x40018020))
71GA 0:c1305ab902af 39 #define MR3 (*((volatile unsigned int *) 0x40018024))
71GA 0:c1305ab902af 40 #define MR4 (*((volatile unsigned int *) 0x40018040))
71GA 0:c1305ab902af 41 #define MR5 (*((volatile unsigned int *) 0x40018044))
71GA 0:c1305ab902af 42 #define MR6 (*((volatile unsigned int *) 0x40018048))
71GA 0:c1305ab902af 43
71GA 0:c1305ab902af 44 #define CCR (*((volatile unsigned int *) 0x40018028))
71GA 0:c1305ab902af 45 #define CR0 (*((volatile unsigned int *) 0x4001802C))
71GA 0:c1305ab902af 46 #define CR1 (*((volatile unsigned int *) 0x40018030))
71GA 0:c1305ab902af 47
71GA 0:c1305ab902af 48 #define PCR (*((volatile unsigned int *) 0x4001804C))
71GA 0:c1305ab902af 49 #define LER (*((volatile unsigned int *) 0x40018050))
71GA 0:c1305ab902af 50 #define CTCR (*((volatile unsigned int *) 0x40018070))
71GA 0:c1305ab902af 51 */