Šolski center Kranj / Mbed 2 deprecated 005-pwm

This program demonstrates the usage of the PWM. Program sets PWM0 chanel 1 and outputs it to the pin P1.2 where we get a PWM signal with a constant working cycle.

Dependencies:   mbed

main.c@0:c1305ab902af, 2015-05-02 (annotated)

Committer:
71GA
Date:
Sat May 02 17:29:12 2015 +0000
Revision:
0:c1305ab902af
First commit of this program.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
71GA 0:c1305ab902af 1 #include "LPC4088-ioconfig.h"
71GA 0:c1305ab902af 2 #include "LPC4088-system.h"
71GA 0:c1305ab902af 3 #include "LPC4088-pwm.h"
71GA 0:c1305ab902af 4
71GA 0:c1305ab902af 5 int main(){
71GA 0:c1305ab902af 6
71GA 0:c1305ab902af 7 //omogocimo PWM0, ki ob zagonu ni prizgan
71GA 0:c1305ab902af 8 PCONP = PCONP | (0x1<<5);
71GA 0:c1305ab902af 9
71GA 0:c1305ab902af 10 //resetiranje PWM0
71GA 0:c1305ab902af 11 //RSTCON0 = RSTCON0 | (0x1<<5);
71GA 0:c1305ab902af 12
71GA 0:c1305ab902af 13 //nastavitev pina P1.2 kot izhoda PWM0_1 - v headerju zakomentiramo timer PWM1
71GA 0:c1305ab902af 14 IOCON_P1_2 = IOCON_P1_2 & !(0x67F);
71GA 0:c1305ab902af 15 IOCON_P1_2 = IOCON_P1_2 | 0x3;
71GA 0:c1305ab902af 16
71GA 0:c1305ab902af 17 //nastavitev pina P1.18 kot izhoda PWM1_1 - v headerju zakomentiramo timer PWM0
71GA 0:c1305ab902af 18 //IOCON_P1_18 = IOCON_P1_18 & !(0x67F);
71GA 0:c1305ab902af 19 //IOCON_P1_18 = IOCON_P1_18 | 0b010;
71GA 0:c1305ab902af 20
71GA 0:c1305ab902af 21 //pocistimo interrupte za PWM0
71GA 0:c1305ab902af 22 IR = IR | 0x73F;
71GA 0:c1305ab902af 23
71GA 0:c1305ab902af 24 //nastavimo "individual use"
71GA 0:c1305ab902af 25 TCR = TCR & !(1<<4);
71GA 0:c1305ab902af 26
71GA 0:c1305ab902af 27 //nastavimo "Timer mode"
71GA 0:c1305ab902af 28 CTCR = CTCR & !(0x3);
71GA 0:c1305ab902af 29
71GA 0:c1305ab902af 30 //omogočimo PWMx_1 kanal (izhod)
71GA 0:c1305ab902af 31 PCR = PCR | (1<<9);
71GA 0:c1305ab902af 32
71GA 0:c1305ab902af 33 //nastavimo match register R0 tako, da ob TC == MR0 resetira
71GA 0:c1305ab902af 34 //celotni PWM0. Uporabili bomo kanal PWM0_1 in tega setamo in
71GA 0:c1305ab902af 35 //resetamo z MR0 in MR1 (UM, tabela 556). 1
71GA 0:c1305ab902af 36 MCR = MCR | (1<<1);
71GA 0:c1305ab902af 37 MR0 = 0x7FFFF;
71GA 0:c1305ab902af 38 MR1 = 0x0FFFF;
71GA 0:c1305ab902af 39
71GA 0:c1305ab902af 40 //ko so vrednosti vpisane v MR0 in MR1, obe vrednosti omogočimo (istočasno)
71GA 0:c1305ab902af 41 LER = LER | 0x3;
71GA 0:c1305ab902af 42
71GA 0:c1305ab902af 43 //nastavimo "timer mode" in ne "PWM mode" (ne deluje)
71GA 0:c1305ab902af 44 //POZOR! Mora biti za nastavitvijo MR0/MR1
71GA 0:c1305ab902af 45 TCR = TCR & !(1<<3);
71GA 0:c1305ab902af 46
71GA 0:c1305ab902af 47 //vklopimo PWM0 - mora biti za nastavitvijo MR0/MR1
71GA 0:c1305ab902af 48 //POZOR! Mora biti za nastavitvijo MR0/MR1
71GA 0:c1305ab902af 49 TCR = TCR | (1<<0);
71GA 0:c1305ab902af 50
71GA 0:c1305ab902af 51 while(1);
71GA 0:c1305ab902af 52
71GA 0:c1305ab902af 53 }