Šolski center Kranj / Mbed 2 deprecated 005-pwm

This program demonstrates the usage of the PWM. Program sets PWM0 chanel 1 and outputs it to the pin P1.2 where we get a PWM signal with a constant working cycle.

Dependencies:   mbed

LPC4088-timer.h@0:c1305ab902af, 2015-05-02 (annotated)

Committer:
71GA
Date:
Sat May 02 17:29:12 2015 +0000
Revision:
0:c1305ab902af
First commit of this program.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
71GA 0:c1305ab902af 1 //definicije registrov za periferijo TIMER
71GA 0:c1305ab902af 2
71GA 0:c1305ab902af 3 //timer 0
71GA 0:c1305ab902af 4 /*
71GA 0:c1305ab902af 5 #define IR (*((volatile unsigned int *) 0x40004000))
71GA 0:c1305ab902af 6 #define TCR (*((volatile unsigned int *) 0x40004004))
71GA 0:c1305ab902af 7 #define TC (*((volatile unsigned int *) 0x40004008))
71GA 0:c1305ab902af 8 #define PR (*((volatile unsigned int *) 0x4000400C))
71GA 0:c1305ab902af 9 #define PC (*((volatile unsigned int *) 0x40004010))
71GA 0:c1305ab902af 10 #define MCR (*((volatile unsigned int *) 0x40004014))
71GA 0:c1305ab902af 11 #define MR0 (*((volatile unsigned int *) 0x40004018))
71GA 0:c1305ab902af 12 #define MR1 (*((volatile unsigned int *) 0x4000401C))
71GA 0:c1305ab902af 13 #define MR2 (*((volatile unsigned int *) 0x40004020))
71GA 0:c1305ab902af 14 #define MR3 (*((volatile unsigned int *) 0x40004024))
71GA 0:c1305ab902af 15 #define CCR (*((volatile unsigned int *) 0x40004028))
71GA 0:c1305ab902af 16 #define CR0 (*((volatile unsigned int *) 0x4000402C))
71GA 0:c1305ab902af 17 #define CR1 (*((volatile unsigned int *) 0x40004030))
71GA 0:c1305ab902af 18 #define EMR (*((volatile unsigned int *) 0x4000403C))
71GA 0:c1305ab902af 19 #define CTCR (*((volatile unsigned int *) 0x40004070))
71GA 0:c1305ab902af 20 */
71GA 0:c1305ab902af 21
71GA 0:c1305ab902af 22 //timer 1
71GA 0:c1305ab902af 23 /*
71GA 0:c1305ab902af 24 #define IR (*((volatile unsigned int *) 0x40008000))
71GA 0:c1305ab902af 25 #define TCR (*((volatile unsigned int *) 0x40008004))
71GA 0:c1305ab902af 26 #define TC (*((volatile unsigned int *) 0x40008008))
71GA 0:c1305ab902af 27 #define PR (*((volatile unsigned int *) 0x4000800C))
71GA 0:c1305ab902af 28 #define PC (*((volatile unsigned int *) 0x40008010))
71GA 0:c1305ab902af 29 #define MCR (*((volatile unsigned int *) 0x40008014))
71GA 0:c1305ab902af 30 #define MR0 (*((volatile unsigned int *) 0x40008018))
71GA 0:c1305ab902af 31 #define MR1 (*((volatile unsigned int *) 0x4000801C))
71GA 0:c1305ab902af 32 #define MR2 (*((volatile unsigned int *) 0x40008020))
71GA 0:c1305ab902af 33 #define MR3 (*((volatile unsigned int *) 0x40008024))
71GA 0:c1305ab902af 34 #define CCR (*((volatile unsigned int *) 0x40008028))
71GA 0:c1305ab902af 35 #define CR0 (*((volatile unsigned int *) 0x4000802C))
71GA 0:c1305ab902af 36 #define CR1 (*((volatile unsigned int *) 0x40008030))
71GA 0:c1305ab902af 37 #define EMR (*((volatile unsigned int *) 0x4000803C))
71GA 0:c1305ab902af 38 #define CTCR (*((volatile unsigned int *) 0x40008070))
71GA 0:c1305ab902af 39 */
71GA 0:c1305ab902af 40
71GA 0:c1305ab902af 41 //timer 2
71GA 0:c1305ab902af 42 #define IR (*((volatile unsigned int *) 0x40090000))
71GA 0:c1305ab902af 43 #define TCR (*((volatile unsigned int *) 0x40090004))
71GA 0:c1305ab902af 44 #define TC (*((volatile unsigned int *) 0x40090008))
71GA 0:c1305ab902af 45 #define PR (*((volatile unsigned int *) 0x4009000C))
71GA 0:c1305ab902af 46 #define PC (*((volatile unsigned int *) 0x40090010))
71GA 0:c1305ab902af 47 #define MCR (*((volatile unsigned int *) 0x40090014))
71GA 0:c1305ab902af 48 #define MR0 (*((volatile unsigned int *) 0x40090018))
71GA 0:c1305ab902af 49 #define MR1 (*((volatile unsigned int *) 0x4009001C))
71GA 0:c1305ab902af 50 #define MR2 (*((volatile unsigned int *) 0x40090020))
71GA 0:c1305ab902af 51 #define MR3 (*((volatile unsigned int *) 0x40090024))
71GA 0:c1305ab902af 52 #define CCR (*((volatile unsigned int *) 0x40090028))
71GA 0:c1305ab902af 53 #define CR0 (*((volatile unsigned int *) 0x4009002C))
71GA 0:c1305ab902af 54 #define CR1 (*((volatile unsigned int *) 0x40090030))
71GA 0:c1305ab902af 55 #define EMR (*((volatile unsigned int *) 0x4009003C))
71GA 0:c1305ab902af 56 #define CTCR (*((volatile unsigned int *) 0x40090070))
71GA 0:c1305ab902af 57
71GA 0:c1305ab902af 58
71GA 0:c1305ab902af 59 //timer 3
71GA 0:c1305ab902af 60 /*
71GA 0:c1305ab902af 61 #define IR (*((volatile unsigned int *) 0x40094000))
71GA 0:c1305ab902af 62 #define TCR (*((volatile unsigned int *) 0x40094004))
71GA 0:c1305ab902af 63 #define TC (*((volatile unsigned int *) 0x40094008))
71GA 0:c1305ab902af 64 #define PR (*((volatile unsigned int *) 0x4009400C))
71GA 0:c1305ab902af 65 #define PC (*((volatile unsigned int *) 0x40094010))
71GA 0:c1305ab902af 66 #define MCR (*((volatile unsigned int *) 0x40094014))
71GA 0:c1305ab902af 67 #define MR0 (*((volatile unsigned int *) 0x40094018))
71GA 0:c1305ab902af 68 #define MR1 (*((volatile unsigned int *) 0x4009401C))
71GA 0:c1305ab902af 69 #define MR2 (*((volatile unsigned int *) 0x40094020))
71GA 0:c1305ab902af 70 #define MR3 (*((volatile unsigned int *) 0x40094024))
71GA 0:c1305ab902af 71 #define CCR (*((volatile unsigned int *) 0x40094028))
71GA 0:c1305ab902af 72 #define CR0 (*((volatile unsigned int *) 0x4009402C))
71GA 0:c1305ab902af 73 #define CR1 (*((volatile unsigned int *) 0x40094030))
71GA 0:c1305ab902af 74 #define EMR (*((volatile unsigned int *) 0x4009403C))
71GA 0:c1305ab902af 75 #define CTCR (*((volatile unsigned int *) 0x40094070))
71GA 0:c1305ab902af 76 */