Skovbrynet / Mbed 2 deprecated TankCounter

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mbed-rtos/rtx/rt_HAL_CM.h@0:ecaf3e593122, 2016-02-29 (annotated)

Committer:
Tuxitheone
Date:
Mon Feb 29 18:59:15 2016 +0000
Revision:
0:ecaf3e593122
TankCounter

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Tuxitheone 0:ecaf3e593122 1 /*----------------------------------------------------------------------------
Tuxitheone 0:ecaf3e593122 2 * RL-ARM - RTX
Tuxitheone 0:ecaf3e593122 3 *----------------------------------------------------------------------------
Tuxitheone 0:ecaf3e593122 4 * Name: RT_HAL_CM.H
Tuxitheone 0:ecaf3e593122 5 * Purpose: Hardware Abstraction Layer for Cortex-M definitions
Tuxitheone 0:ecaf3e593122 6 * Rev.: V4.60
Tuxitheone 0:ecaf3e593122 7 *----------------------------------------------------------------------------
Tuxitheone 0:ecaf3e593122 8 *
Tuxitheone 0:ecaf3e593122 9 * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
Tuxitheone 0:ecaf3e593122 10 * All rights reserved.
Tuxitheone 0:ecaf3e593122 11 * Redistribution and use in source and binary forms, with or without
Tuxitheone 0:ecaf3e593122 12 * modification, are permitted provided that the following conditions are met:
Tuxitheone 0:ecaf3e593122 13 * - Redistributions of source code must retain the above copyright
Tuxitheone 0:ecaf3e593122 14 * notice, this list of conditions and the following disclaimer.
Tuxitheone 0:ecaf3e593122 15 * - Redistributions in binary form must reproduce the above copyright
Tuxitheone 0:ecaf3e593122 16 * notice, this list of conditions and the following disclaimer in the
Tuxitheone 0:ecaf3e593122 17 * documentation and/or other materials provided with the distribution.
Tuxitheone 0:ecaf3e593122 18 * - Neither the name of ARM nor the names of its contributors may be used
Tuxitheone 0:ecaf3e593122 19 * to endorse or promote products derived from this software without
Tuxitheone 0:ecaf3e593122 20 * specific prior written permission.
Tuxitheone 0:ecaf3e593122 21 *
Tuxitheone 0:ecaf3e593122 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Tuxitheone 0:ecaf3e593122 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Tuxitheone 0:ecaf3e593122 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Tuxitheone 0:ecaf3e593122 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Tuxitheone 0:ecaf3e593122 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Tuxitheone 0:ecaf3e593122 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Tuxitheone 0:ecaf3e593122 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Tuxitheone 0:ecaf3e593122 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Tuxitheone 0:ecaf3e593122 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Tuxitheone 0:ecaf3e593122 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Tuxitheone 0:ecaf3e593122 32 * POSSIBILITY OF SUCH DAMAGE.
Tuxitheone 0:ecaf3e593122 33 *---------------------------------------------------------------------------*/
Tuxitheone 0:ecaf3e593122 34
Tuxitheone 0:ecaf3e593122 35 /* Definitions */
Tuxitheone 0:ecaf3e593122 36 #define INITIAL_xPSR 0x01000000
Tuxitheone 0:ecaf3e593122 37 #define DEMCR_TRCENA 0x01000000
Tuxitheone 0:ecaf3e593122 38 #define ITM_ITMENA 0x00000001
Tuxitheone 0:ecaf3e593122 39 #define MAGIC_WORD 0xE25A2EA5
Tuxitheone 0:ecaf3e593122 40
Tuxitheone 0:ecaf3e593122 41 #if defined (__CC_ARM) /* ARM Compiler */
Tuxitheone 0:ecaf3e593122 42
Tuxitheone 0:ecaf3e593122 43 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS)
Tuxitheone 0:ecaf3e593122 44 #define __USE_EXCLUSIVE_ACCESS
Tuxitheone 0:ecaf3e593122 45 #else
Tuxitheone 0:ecaf3e593122 46 #undef __USE_EXCLUSIVE_ACCESS
Tuxitheone 0:ecaf3e593122 47 #endif
Tuxitheone 0:ecaf3e593122 48
Tuxitheone 0:ecaf3e593122 49 #elif defined (__GNUC__) /* GNU Compiler */
Tuxitheone 0:ecaf3e593122 50
Tuxitheone 0:ecaf3e593122 51 #undef __USE_EXCLUSIVE_ACCESS
Tuxitheone 0:ecaf3e593122 52
Tuxitheone 0:ecaf3e593122 53 #if defined (__CORTEX_M0) || defined (__CORTEX_M0PLUS)
Tuxitheone 0:ecaf3e593122 54 #define __TARGET_ARCH_6S_M 1
Tuxitheone 0:ecaf3e593122 55 #else
Tuxitheone 0:ecaf3e593122 56 #define __TARGET_ARCH_6S_M 0
Tuxitheone 0:ecaf3e593122 57 #endif
Tuxitheone 0:ecaf3e593122 58
Tuxitheone 0:ecaf3e593122 59 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Tuxitheone 0:ecaf3e593122 60 #define __TARGET_FPU_VFP 1
Tuxitheone 0:ecaf3e593122 61 #else
Tuxitheone 0:ecaf3e593122 62 #define __TARGET_FPU_VFP 0
Tuxitheone 0:ecaf3e593122 63 #endif
Tuxitheone 0:ecaf3e593122 64
Tuxitheone 0:ecaf3e593122 65 #define __inline inline
Tuxitheone 0:ecaf3e593122 66 #define __weak __attribute__((weak))
Tuxitheone 0:ecaf3e593122 67
Tuxitheone 0:ecaf3e593122 68 #ifndef __CMSIS_GENERIC
Tuxitheone 0:ecaf3e593122 69
Tuxitheone 0:ecaf3e593122 70 __attribute__((always_inline)) static inline void __enable_irq(void)
Tuxitheone 0:ecaf3e593122 71 {
Tuxitheone 0:ecaf3e593122 72 __asm volatile ("cpsie i");
Tuxitheone 0:ecaf3e593122 73 }
Tuxitheone 0:ecaf3e593122 74
Tuxitheone 0:ecaf3e593122 75 __attribute__((always_inline)) static inline U32 __disable_irq(void)
Tuxitheone 0:ecaf3e593122 76 {
Tuxitheone 0:ecaf3e593122 77 U32 result;
Tuxitheone 0:ecaf3e593122 78
Tuxitheone 0:ecaf3e593122 79 __asm volatile ("mrs %0, primask" : "=r" (result));
Tuxitheone 0:ecaf3e593122 80 __asm volatile ("cpsid i");
Tuxitheone 0:ecaf3e593122 81 return(result & 1);
Tuxitheone 0:ecaf3e593122 82 }
Tuxitheone 0:ecaf3e593122 83
Tuxitheone 0:ecaf3e593122 84 #endif
Tuxitheone 0:ecaf3e593122 85
Tuxitheone 0:ecaf3e593122 86 __attribute__(( always_inline)) static inline U8 __clz(U32 value)
Tuxitheone 0:ecaf3e593122 87 {
Tuxitheone 0:ecaf3e593122 88 U8 result;
Tuxitheone 0:ecaf3e593122 89
Tuxitheone 0:ecaf3e593122 90 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
Tuxitheone 0:ecaf3e593122 91 return(result);
Tuxitheone 0:ecaf3e593122 92 }
Tuxitheone 0:ecaf3e593122 93
Tuxitheone 0:ecaf3e593122 94 #elif defined (__ICCARM__) /* IAR Compiler */
Tuxitheone 0:ecaf3e593122 95
Tuxitheone 0:ecaf3e593122 96 #undef __USE_EXCLUSIVE_ACCESS
Tuxitheone 0:ecaf3e593122 97
Tuxitheone 0:ecaf3e593122 98 #if (__CORE__ == __ARM6M__)
Tuxitheone 0:ecaf3e593122 99 #define __TARGET_ARCH_6S_M 1
Tuxitheone 0:ecaf3e593122 100 #else
Tuxitheone 0:ecaf3e593122 101 #define __TARGET_ARCH_6S_M 0
Tuxitheone 0:ecaf3e593122 102 #endif
Tuxitheone 0:ecaf3e593122 103
Tuxitheone 0:ecaf3e593122 104 #if defined __ARMVFP__
Tuxitheone 0:ecaf3e593122 105 #define __TARGET_FPU_VFP 1
Tuxitheone 0:ecaf3e593122 106 #else
Tuxitheone 0:ecaf3e593122 107 #define __TARGET_FPU_VFP 0
Tuxitheone 0:ecaf3e593122 108 #endif
Tuxitheone 0:ecaf3e593122 109
Tuxitheone 0:ecaf3e593122 110 #define __inline inline
Tuxitheone 0:ecaf3e593122 111
Tuxitheone 0:ecaf3e593122 112 #ifndef __CMSIS_GENERIC
Tuxitheone 0:ecaf3e593122 113
Tuxitheone 0:ecaf3e593122 114 static inline void __enable_irq(void)
Tuxitheone 0:ecaf3e593122 115 {
Tuxitheone 0:ecaf3e593122 116 __asm volatile ("cpsie i");
Tuxitheone 0:ecaf3e593122 117 }
Tuxitheone 0:ecaf3e593122 118
Tuxitheone 0:ecaf3e593122 119 static inline U32 __disable_irq(void)
Tuxitheone 0:ecaf3e593122 120 {
Tuxitheone 0:ecaf3e593122 121 U32 result;
Tuxitheone 0:ecaf3e593122 122
Tuxitheone 0:ecaf3e593122 123 __asm volatile ("mrs %0, primask" : "=r" (result));
Tuxitheone 0:ecaf3e593122 124 __asm volatile ("cpsid i");
Tuxitheone 0:ecaf3e593122 125 return(result & 1);
Tuxitheone 0:ecaf3e593122 126 }
Tuxitheone 0:ecaf3e593122 127
Tuxitheone 0:ecaf3e593122 128 #endif
Tuxitheone 0:ecaf3e593122 129
Tuxitheone 0:ecaf3e593122 130 static inline U8 __clz(U32 value)
Tuxitheone 0:ecaf3e593122 131 {
Tuxitheone 0:ecaf3e593122 132 U8 result;
Tuxitheone 0:ecaf3e593122 133
Tuxitheone 0:ecaf3e593122 134 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
Tuxitheone 0:ecaf3e593122 135 return(result);
Tuxitheone 0:ecaf3e593122 136 }
Tuxitheone 0:ecaf3e593122 137
Tuxitheone 0:ecaf3e593122 138 #endif
Tuxitheone 0:ecaf3e593122 139
Tuxitheone 0:ecaf3e593122 140 /* NVIC registers */
Tuxitheone 0:ecaf3e593122 141 #define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010))
Tuxitheone 0:ecaf3e593122 142 #define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014))
Tuxitheone 0:ecaf3e593122 143 #define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
Tuxitheone 0:ecaf3e593122 144 #define NVIC_ISER ((volatile U32 *)0xE000E100)
Tuxitheone 0:ecaf3e593122 145 #define NVIC_ICER ((volatile U32 *)0xE000E180)
Tuxitheone 0:ecaf3e593122 146 #if (__TARGET_ARCH_6S_M)
Tuxitheone 0:ecaf3e593122 147 #define NVIC_IP ((volatile U32 *)0xE000E400)
Tuxitheone 0:ecaf3e593122 148 #else
Tuxitheone 0:ecaf3e593122 149 #define NVIC_IP ((volatile U8 *)0xE000E400)
Tuxitheone 0:ecaf3e593122 150 #endif
Tuxitheone 0:ecaf3e593122 151 #define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04))
Tuxitheone 0:ecaf3e593122 152 #define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C))
Tuxitheone 0:ecaf3e593122 153 #define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C))
Tuxitheone 0:ecaf3e593122 154 #define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20))
Tuxitheone 0:ecaf3e593122 155
Tuxitheone 0:ecaf3e593122 156 #define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28)
Tuxitheone 0:ecaf3e593122 157 #define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
Tuxitheone 0:ecaf3e593122 158 #define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25
Tuxitheone 0:ecaf3e593122 159 #define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26
Tuxitheone 0:ecaf3e593122 160 #define OS_LOCK() NVIC_ST_CTRL = 0x0005
Tuxitheone 0:ecaf3e593122 161 #define OS_UNLOCK() NVIC_ST_CTRL = 0x0007
Tuxitheone 0:ecaf3e593122 162
Tuxitheone 0:ecaf3e593122 163 #define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1)
Tuxitheone 0:ecaf3e593122 164 #define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27
Tuxitheone 0:ecaf3e593122 165 #define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28
Tuxitheone 0:ecaf3e593122 166 #if (__TARGET_ARCH_6S_M)
Tuxitheone 0:ecaf3e593122 167 #define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
Tuxitheone 0:ecaf3e593122 168 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
Tuxitheone 0:ecaf3e593122 169 #else
Tuxitheone 0:ecaf3e593122 170 #define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \
Tuxitheone 0:ecaf3e593122 171 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
Tuxitheone 0:ecaf3e593122 172 #endif
Tuxitheone 0:ecaf3e593122 173 #define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F)
Tuxitheone 0:ecaf3e593122 174 #define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F)
Tuxitheone 0:ecaf3e593122 175
Tuxitheone 0:ecaf3e593122 176 /* Core Debug registers */
Tuxitheone 0:ecaf3e593122 177 #define DEMCR (*((volatile U32 *)0xE000EDFC))
Tuxitheone 0:ecaf3e593122 178
Tuxitheone 0:ecaf3e593122 179 /* ITM registers */
Tuxitheone 0:ecaf3e593122 180 #define ITM_CONTROL (*((volatile U32 *)0xE0000E80))
Tuxitheone 0:ecaf3e593122 181 #define ITM_ENABLE (*((volatile U32 *)0xE0000E00))
Tuxitheone 0:ecaf3e593122 182 #define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078))
Tuxitheone 0:ecaf3e593122 183 #define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C))
Tuxitheone 0:ecaf3e593122 184 #define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C))
Tuxitheone 0:ecaf3e593122 185 #define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C))
Tuxitheone 0:ecaf3e593122 186
Tuxitheone 0:ecaf3e593122 187 /* Variables */
Tuxitheone 0:ecaf3e593122 188 extern BIT dbg_msg;
Tuxitheone 0:ecaf3e593122 189
Tuxitheone 0:ecaf3e593122 190 /* Functions */
Tuxitheone 0:ecaf3e593122 191 #ifdef __USE_EXCLUSIVE_ACCESS
Tuxitheone 0:ecaf3e593122 192 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
Tuxitheone 0:ecaf3e593122 193 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
Tuxitheone 0:ecaf3e593122 194 #else
Tuxitheone 0:ecaf3e593122 195 #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
Tuxitheone 0:ecaf3e593122 196 #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
Tuxitheone 0:ecaf3e593122 197 #endif
Tuxitheone 0:ecaf3e593122 198
Tuxitheone 0:ecaf3e593122 199 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
Tuxitheone 0:ecaf3e593122 200 U32 cnt,c2;
Tuxitheone 0:ecaf3e593122 201 #ifdef __USE_EXCLUSIVE_ACCESS
Tuxitheone 0:ecaf3e593122 202 do {
Tuxitheone 0:ecaf3e593122 203 if ((cnt = __ldrex(count)) == size) {
Tuxitheone 0:ecaf3e593122 204 __clrex();
Tuxitheone 0:ecaf3e593122 205 return (cnt); }
Tuxitheone 0:ecaf3e593122 206 } while (__strex(cnt+1, count));
Tuxitheone 0:ecaf3e593122 207 do {
Tuxitheone 0:ecaf3e593122 208 c2 = (cnt = __ldrex(first)) + 1;
Tuxitheone 0:ecaf3e593122 209 if (c2 == size) c2 = 0;
Tuxitheone 0:ecaf3e593122 210 } while (__strex(c2, first));
Tuxitheone 0:ecaf3e593122 211 #else
Tuxitheone 0:ecaf3e593122 212 __disable_irq();
Tuxitheone 0:ecaf3e593122 213 if ((cnt = *count) < size) {
Tuxitheone 0:ecaf3e593122 214 *count = cnt+1;
Tuxitheone 0:ecaf3e593122 215 c2 = (cnt = *first) + 1;
Tuxitheone 0:ecaf3e593122 216 if (c2 == size) c2 = 0;
Tuxitheone 0:ecaf3e593122 217 *first = c2;
Tuxitheone 0:ecaf3e593122 218 }
Tuxitheone 0:ecaf3e593122 219 __enable_irq ();
Tuxitheone 0:ecaf3e593122 220 #endif
Tuxitheone 0:ecaf3e593122 221 return (cnt);
Tuxitheone 0:ecaf3e593122 222 }
Tuxitheone 0:ecaf3e593122 223
Tuxitheone 0:ecaf3e593122 224 __inline static void rt_systick_init (void) {
Tuxitheone 0:ecaf3e593122 225 NVIC_ST_RELOAD = os_trv;
Tuxitheone 0:ecaf3e593122 226 NVIC_ST_CURRENT = 0;
Tuxitheone 0:ecaf3e593122 227 NVIC_ST_CTRL = 0x0007;
Tuxitheone 0:ecaf3e593122 228 NVIC_SYS_PRI3 |= 0xFF000000;
Tuxitheone 0:ecaf3e593122 229 }
Tuxitheone 0:ecaf3e593122 230
Tuxitheone 0:ecaf3e593122 231 __inline static void rt_svc_init (void) {
Tuxitheone 0:ecaf3e593122 232 #if !(__TARGET_ARCH_6S_M)
Tuxitheone 0:ecaf3e593122 233 int sh,prigroup;
Tuxitheone 0:ecaf3e593122 234 #endif
Tuxitheone 0:ecaf3e593122 235 NVIC_SYS_PRI3 |= 0x00FF0000;
Tuxitheone 0:ecaf3e593122 236 #if (__TARGET_ARCH_6S_M)
Tuxitheone 0:ecaf3e593122 237 NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
Tuxitheone 0:ecaf3e593122 238 #else
Tuxitheone 0:ecaf3e593122 239 sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
Tuxitheone 0:ecaf3e593122 240 prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
Tuxitheone 0:ecaf3e593122 241 if (prigroup >= sh) {
Tuxitheone 0:ecaf3e593122 242 sh = prigroup + 1;
Tuxitheone 0:ecaf3e593122 243 }
Tuxitheone 0:ecaf3e593122 244 NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
Tuxitheone 0:ecaf3e593122 245 #endif
Tuxitheone 0:ecaf3e593122 246 }
Tuxitheone 0:ecaf3e593122 247
Tuxitheone 0:ecaf3e593122 248 extern void rt_set_PSP (U32 stack);
Tuxitheone 0:ecaf3e593122 249 extern U32 rt_get_PSP (void);
Tuxitheone 0:ecaf3e593122 250 extern void os_set_env (void);
Tuxitheone 0:ecaf3e593122 251 extern void *_alloc_box (void *box_mem);
Tuxitheone 0:ecaf3e593122 252 extern int _free_box (void *box_mem, void *box);
Tuxitheone 0:ecaf3e593122 253
Tuxitheone 0:ecaf3e593122 254 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
Tuxitheone 0:ecaf3e593122 255 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
Tuxitheone 0:ecaf3e593122 256 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
Tuxitheone 0:ecaf3e593122 257
Tuxitheone 0:ecaf3e593122 258 extern void dbg_init (void);
Tuxitheone 0:ecaf3e593122 259 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
Tuxitheone 0:ecaf3e593122 260 extern void dbg_task_switch (U32 task_id);
Tuxitheone 0:ecaf3e593122 261
Tuxitheone 0:ecaf3e593122 262 #ifdef DBG_MSG
Tuxitheone 0:ecaf3e593122 263 #define DBG_INIT() dbg_init()
Tuxitheone 0:ecaf3e593122 264 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
Tuxitheone 0:ecaf3e593122 265 #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk != os_tsk.run)) \
Tuxitheone 0:ecaf3e593122 266 dbg_task_switch(task_id)
Tuxitheone 0:ecaf3e593122 267 #else
Tuxitheone 0:ecaf3e593122 268 #define DBG_INIT()
Tuxitheone 0:ecaf3e593122 269 #define DBG_TASK_NOTIFY(p_tcb,create)
Tuxitheone 0:ecaf3e593122 270 #define DBG_TASK_SWITCH(task_id)
Tuxitheone 0:ecaf3e593122 271 #endif
Tuxitheone 0:ecaf3e593122 272
Tuxitheone 0:ecaf3e593122 273 /*----------------------------------------------------------------------------
Tuxitheone 0:ecaf3e593122 274 * end of file
Tuxitheone 0:ecaf3e593122 275 *---------------------------------------------------------------------------*/
Tuxitheone 0:ecaf3e593122 276