Skovbrynet / Mbed 2 deprecated TankCounter

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Dependencies:   EthernetInterface NTPClient SDFileSystem TextLCD WebSocketClient mbed-rtos mbed Socket lwip-eth lwip-sys lwip FATFileSystem

EthernetInterface/lwip-eth/arch/lpc17xx_emac.h@0:ecaf3e593122, 2016-02-29 (annotated)

Committer:
Tuxitheone
Date:
Mon Feb 29 18:59:15 2016 +0000
Revision:
0:ecaf3e593122
TankCounter

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Tuxitheone 0:ecaf3e593122 1 /**********************************************************************
Tuxitheone 0:ecaf3e593122 2 * $Id$ lpc17xx_emac.h 2010-05-21
Tuxitheone 0:ecaf3e593122 3 *//**
Tuxitheone 0:ecaf3e593122 4 * @file lpc17xx_emac.h
Tuxitheone 0:ecaf3e593122 5 * @brief Contains all macro definitions and function prototypes
Tuxitheone 0:ecaf3e593122 6 * support for Ethernet MAC firmware library on LPC17xx
Tuxitheone 0:ecaf3e593122 7 * @version 2.0
Tuxitheone 0:ecaf3e593122 8 * @date 21. May. 2010
Tuxitheone 0:ecaf3e593122 9 * @author NXP MCU SW Application Team
Tuxitheone 0:ecaf3e593122 10 *
Tuxitheone 0:ecaf3e593122 11 * Copyright(C) 2010, NXP Semiconductor
Tuxitheone 0:ecaf3e593122 12 * All rights reserved.
Tuxitheone 0:ecaf3e593122 13 *
Tuxitheone 0:ecaf3e593122 14 ***********************************************************************
Tuxitheone 0:ecaf3e593122 15 * Software that is described herein is for illustrative purposes only
Tuxitheone 0:ecaf3e593122 16 * which provides customers with programming information regarding the
Tuxitheone 0:ecaf3e593122 17 * products. This software is supplied "AS IS" without any warranties.
Tuxitheone 0:ecaf3e593122 18 * NXP Semiconductors assumes no responsibility or liability for the
Tuxitheone 0:ecaf3e593122 19 * use of the software, conveys no license or title under any patent,
Tuxitheone 0:ecaf3e593122 20 * copyright, or mask work right to the product. NXP Semiconductors
Tuxitheone 0:ecaf3e593122 21 * reserves the right to make changes in the software without
Tuxitheone 0:ecaf3e593122 22 * notification. NXP Semiconductors also make no representation or
Tuxitheone 0:ecaf3e593122 23 * warranty that such application will be suitable for the specified
Tuxitheone 0:ecaf3e593122 24 * use without further testing or modification.
Tuxitheone 0:ecaf3e593122 25 **********************************************************************/
Tuxitheone 0:ecaf3e593122 26
Tuxitheone 0:ecaf3e593122 27 /* Peripheral group ----------------------------------------------------------- */
Tuxitheone 0:ecaf3e593122 28 /** @defgroup EMAC EMAC (Ethernet Media Access Controller)
Tuxitheone 0:ecaf3e593122 29 * @ingroup LPC1700CMSIS_FwLib_Drivers
Tuxitheone 0:ecaf3e593122 30 * @{
Tuxitheone 0:ecaf3e593122 31 */
Tuxitheone 0:ecaf3e593122 32
Tuxitheone 0:ecaf3e593122 33 #ifndef LPC17XX_EMAC_H_
Tuxitheone 0:ecaf3e593122 34 #define LPC17XX_EMAC_H_
Tuxitheone 0:ecaf3e593122 35
Tuxitheone 0:ecaf3e593122 36 /* Includes ------------------------------------------------------------------- */
Tuxitheone 0:ecaf3e593122 37 #include "LPC17xx.h"
Tuxitheone 0:ecaf3e593122 38
Tuxitheone 0:ecaf3e593122 39 #ifdef __cplusplus
Tuxitheone 0:ecaf3e593122 40 extern "C"
Tuxitheone 0:ecaf3e593122 41 {
Tuxitheone 0:ecaf3e593122 42 #endif
Tuxitheone 0:ecaf3e593122 43
Tuxitheone 0:ecaf3e593122 44 #define MCB_LPC_1768
Tuxitheone 0:ecaf3e593122 45 //#define IAR_LPC_1768
Tuxitheone 0:ecaf3e593122 46
Tuxitheone 0:ecaf3e593122 47 /* Public Macros -------------------------------------------------------------- */
Tuxitheone 0:ecaf3e593122 48 /** @defgroup EMAC_Public_Macros EMAC Public Macros
Tuxitheone 0:ecaf3e593122 49 * @{
Tuxitheone 0:ecaf3e593122 50 */
Tuxitheone 0:ecaf3e593122 51
Tuxitheone 0:ecaf3e593122 52
Tuxitheone 0:ecaf3e593122 53 /* EMAC PHY status type definitions */
Tuxitheone 0:ecaf3e593122 54 #define EMAC_PHY_STAT_LINK (0) /**< Link Status */
Tuxitheone 0:ecaf3e593122 55 #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
Tuxitheone 0:ecaf3e593122 56 #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
Tuxitheone 0:ecaf3e593122 57
Tuxitheone 0:ecaf3e593122 58 /* EMAC PHY device Speed definitions */
Tuxitheone 0:ecaf3e593122 59 #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
Tuxitheone 0:ecaf3e593122 60 #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
Tuxitheone 0:ecaf3e593122 61 #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
Tuxitheone 0:ecaf3e593122 62 #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
Tuxitheone 0:ecaf3e593122 63 #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
Tuxitheone 0:ecaf3e593122 64
Tuxitheone 0:ecaf3e593122 65 /**
Tuxitheone 0:ecaf3e593122 66 * @}
Tuxitheone 0:ecaf3e593122 67 */
Tuxitheone 0:ecaf3e593122 68 /* Private Macros ------------------------------------------------------------- */
Tuxitheone 0:ecaf3e593122 69 /** @defgroup EMAC_Private_Macros EMAC Private Macros
Tuxitheone 0:ecaf3e593122 70 * @{
Tuxitheone 0:ecaf3e593122 71 */
Tuxitheone 0:ecaf3e593122 72
Tuxitheone 0:ecaf3e593122 73
Tuxitheone 0:ecaf3e593122 74 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */
Tuxitheone 0:ecaf3e593122 75 #define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
Tuxitheone 0:ecaf3e593122 76 #define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
Tuxitheone 0:ecaf3e593122 77 #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
Tuxitheone 0:ecaf3e593122 78 #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
Tuxitheone 0:ecaf3e593122 79
Tuxitheone 0:ecaf3e593122 80 /* --------------------- BIT DEFINITIONS -------------------------------------- */
Tuxitheone 0:ecaf3e593122 81 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 82 * Macro defines for MAC Configuration Register 1
Tuxitheone 0:ecaf3e593122 83 **********************************************************************/
Tuxitheone 0:ecaf3e593122 84 #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
Tuxitheone 0:ecaf3e593122 85 #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
Tuxitheone 0:ecaf3e593122 86 #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
Tuxitheone 0:ecaf3e593122 87 #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
Tuxitheone 0:ecaf3e593122 88 #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
Tuxitheone 0:ecaf3e593122 89 #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
Tuxitheone 0:ecaf3e593122 90 #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
Tuxitheone 0:ecaf3e593122 91 #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
Tuxitheone 0:ecaf3e593122 92 #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
Tuxitheone 0:ecaf3e593122 93 #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
Tuxitheone 0:ecaf3e593122 94 #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
Tuxitheone 0:ecaf3e593122 95
Tuxitheone 0:ecaf3e593122 96 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 97 * Macro defines for MAC Configuration Register 2
Tuxitheone 0:ecaf3e593122 98 **********************************************************************/
Tuxitheone 0:ecaf3e593122 99 #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
Tuxitheone 0:ecaf3e593122 100 #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
Tuxitheone 0:ecaf3e593122 101 #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
Tuxitheone 0:ecaf3e593122 102 #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
Tuxitheone 0:ecaf3e593122 103 #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
Tuxitheone 0:ecaf3e593122 104 #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
Tuxitheone 0:ecaf3e593122 105 #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
Tuxitheone 0:ecaf3e593122 106 #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
Tuxitheone 0:ecaf3e593122 107 #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
Tuxitheone 0:ecaf3e593122 108 #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
Tuxitheone 0:ecaf3e593122 109 #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
Tuxitheone 0:ecaf3e593122 110 #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
Tuxitheone 0:ecaf3e593122 111 #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
Tuxitheone 0:ecaf3e593122 112
Tuxitheone 0:ecaf3e593122 113 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 114 * Macro defines for Back-to-Back Inter-Packet-Gap Register
Tuxitheone 0:ecaf3e593122 115 **********************************************************************/
Tuxitheone 0:ecaf3e593122 116 /** Programmable field representing the nibble time offset of the minimum possible period
Tuxitheone 0:ecaf3e593122 117 * between the end of any transmitted packet to the beginning of the next */
Tuxitheone 0:ecaf3e593122 118 #define EMAC_IPGT_BBIPG(n) (n&0x7F)
Tuxitheone 0:ecaf3e593122 119 /** Recommended value for Full Duplex of Programmable field representing the nibble time
Tuxitheone 0:ecaf3e593122 120 * offset of the minimum possible period between the end of any transmitted packet to the
Tuxitheone 0:ecaf3e593122 121 * beginning of the next */
Tuxitheone 0:ecaf3e593122 122 #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
Tuxitheone 0:ecaf3e593122 123 /** Recommended value for Half Duplex of Programmable field representing the nibble time
Tuxitheone 0:ecaf3e593122 124 * offset of the minimum possible period between the end of any transmitted packet to the
Tuxitheone 0:ecaf3e593122 125 * beginning of the next */
Tuxitheone 0:ecaf3e593122 126 #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
Tuxitheone 0:ecaf3e593122 127
Tuxitheone 0:ecaf3e593122 128 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 129 * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
Tuxitheone 0:ecaf3e593122 130 **********************************************************************/
Tuxitheone 0:ecaf3e593122 131 /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
Tuxitheone 0:ecaf3e593122 132 #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
Tuxitheone 0:ecaf3e593122 133 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
Tuxitheone 0:ecaf3e593122 134 #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
Tuxitheone 0:ecaf3e593122 135 /** Programmable field representing the optional carrierSense window referenced in
Tuxitheone 0:ecaf3e593122 136 * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
Tuxitheone 0:ecaf3e593122 137 #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
Tuxitheone 0:ecaf3e593122 138 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
Tuxitheone 0:ecaf3e593122 139 #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
Tuxitheone 0:ecaf3e593122 140
Tuxitheone 0:ecaf3e593122 141 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 142 * Macro defines for Collision Window/Retry Register
Tuxitheone 0:ecaf3e593122 143 **********************************************************************/
Tuxitheone 0:ecaf3e593122 144 /** Programmable field specifying the number of retransmission attempts following a collision before
Tuxitheone 0:ecaf3e593122 145 * aborting the packet due to excessive collisions */
Tuxitheone 0:ecaf3e593122 146 #define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
Tuxitheone 0:ecaf3e593122 147 /** Programmable field representing the slot time or collision window during which collisions occur
Tuxitheone 0:ecaf3e593122 148 * in properly configured networks */
Tuxitheone 0:ecaf3e593122 149 #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
Tuxitheone 0:ecaf3e593122 150 /** Default value for Collision Window / Retry register */
Tuxitheone 0:ecaf3e593122 151 #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
Tuxitheone 0:ecaf3e593122 152
Tuxitheone 0:ecaf3e593122 153 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 154 * Macro defines for Maximum Frame Register
Tuxitheone 0:ecaf3e593122 155 **********************************************************************/
Tuxitheone 0:ecaf3e593122 156 /** Represents a maximum receive frame of 1536 octets */
Tuxitheone 0:ecaf3e593122 157 #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
Tuxitheone 0:ecaf3e593122 158
Tuxitheone 0:ecaf3e593122 159 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 160 * Macro defines for PHY Support Register
Tuxitheone 0:ecaf3e593122 161 **********************************************************************/
Tuxitheone 0:ecaf3e593122 162 #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
Tuxitheone 0:ecaf3e593122 163 #define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
Tuxitheone 0:ecaf3e593122 164
Tuxitheone 0:ecaf3e593122 165 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 166 * Macro defines for Test Register
Tuxitheone 0:ecaf3e593122 167 **********************************************************************/
Tuxitheone 0:ecaf3e593122 168 #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
Tuxitheone 0:ecaf3e593122 169 #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
Tuxitheone 0:ecaf3e593122 170 #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
Tuxitheone 0:ecaf3e593122 171
Tuxitheone 0:ecaf3e593122 172 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 173 * Macro defines for MII Management Configuration Register
Tuxitheone 0:ecaf3e593122 174 **********************************************************************/
Tuxitheone 0:ecaf3e593122 175 #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
Tuxitheone 0:ecaf3e593122 176 #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
Tuxitheone 0:ecaf3e593122 177 #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
Tuxitheone 0:ecaf3e593122 178 #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
Tuxitheone 0:ecaf3e593122 179 #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
Tuxitheone 0:ecaf3e593122 180
Tuxitheone 0:ecaf3e593122 181 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 182 * Macro defines for MII Management Command Register
Tuxitheone 0:ecaf3e593122 183 **********************************************************************/
Tuxitheone 0:ecaf3e593122 184 #define EMAC_MCMD_READ 0x00000001 /**< MII Read */
Tuxitheone 0:ecaf3e593122 185 #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
Tuxitheone 0:ecaf3e593122 186
Tuxitheone 0:ecaf3e593122 187 #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
Tuxitheone 0:ecaf3e593122 188 #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
Tuxitheone 0:ecaf3e593122 189
Tuxitheone 0:ecaf3e593122 190 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 191 * Macro defines for MII Management Address Register
Tuxitheone 0:ecaf3e593122 192 **********************************************************************/
Tuxitheone 0:ecaf3e593122 193 #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
Tuxitheone 0:ecaf3e593122 194 #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
Tuxitheone 0:ecaf3e593122 195
Tuxitheone 0:ecaf3e593122 196 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 197 * Macro defines for MII Management Write Data Register
Tuxitheone 0:ecaf3e593122 198 **********************************************************************/
Tuxitheone 0:ecaf3e593122 199 #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
Tuxitheone 0:ecaf3e593122 200
Tuxitheone 0:ecaf3e593122 201 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 202 * Macro defines for MII Management Read Data Register
Tuxitheone 0:ecaf3e593122 203 **********************************************************************/
Tuxitheone 0:ecaf3e593122 204 #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
Tuxitheone 0:ecaf3e593122 205
Tuxitheone 0:ecaf3e593122 206 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 207 * Macro defines for MII Management Indicators Register
Tuxitheone 0:ecaf3e593122 208 **********************************************************************/
Tuxitheone 0:ecaf3e593122 209 #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
Tuxitheone 0:ecaf3e593122 210 #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
Tuxitheone 0:ecaf3e593122 211 #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
Tuxitheone 0:ecaf3e593122 212 #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
Tuxitheone 0:ecaf3e593122 213
Tuxitheone 0:ecaf3e593122 214 /* Station Address 0 Register */
Tuxitheone 0:ecaf3e593122 215 /* Station Address 1 Register */
Tuxitheone 0:ecaf3e593122 216 /* Station Address 2 Register */
Tuxitheone 0:ecaf3e593122 217
Tuxitheone 0:ecaf3e593122 218
Tuxitheone 0:ecaf3e593122 219 /* Control register definitions --------------------------------------------------------------------------- */
Tuxitheone 0:ecaf3e593122 220 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 221 * Macro defines for Command Register
Tuxitheone 0:ecaf3e593122 222 **********************************************************************/
Tuxitheone 0:ecaf3e593122 223 #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
Tuxitheone 0:ecaf3e593122 224 #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
Tuxitheone 0:ecaf3e593122 225 #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
Tuxitheone 0:ecaf3e593122 226 #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
Tuxitheone 0:ecaf3e593122 227 #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
Tuxitheone 0:ecaf3e593122 228 #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
Tuxitheone 0:ecaf3e593122 229 #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
Tuxitheone 0:ecaf3e593122 230 #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
Tuxitheone 0:ecaf3e593122 231 #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
Tuxitheone 0:ecaf3e593122 232 #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
Tuxitheone 0:ecaf3e593122 233
Tuxitheone 0:ecaf3e593122 234 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 235 * Macro defines for Status Register
Tuxitheone 0:ecaf3e593122 236 **********************************************************************/
Tuxitheone 0:ecaf3e593122 237 #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
Tuxitheone 0:ecaf3e593122 238 #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
Tuxitheone 0:ecaf3e593122 239
Tuxitheone 0:ecaf3e593122 240 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 241 * Macro defines for Transmit Status Vector 0 Register
Tuxitheone 0:ecaf3e593122 242 **********************************************************************/
Tuxitheone 0:ecaf3e593122 243 #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
Tuxitheone 0:ecaf3e593122 244 #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
Tuxitheone 0:ecaf3e593122 245 #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
Tuxitheone 0:ecaf3e593122 246 #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
Tuxitheone 0:ecaf3e593122 247 #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
Tuxitheone 0:ecaf3e593122 248 #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
Tuxitheone 0:ecaf3e593122 249 #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
Tuxitheone 0:ecaf3e593122 250 #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
Tuxitheone 0:ecaf3e593122 251 #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
Tuxitheone 0:ecaf3e593122 252 #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
Tuxitheone 0:ecaf3e593122 253 #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
Tuxitheone 0:ecaf3e593122 254 #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
Tuxitheone 0:ecaf3e593122 255 #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
Tuxitheone 0:ecaf3e593122 256 #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
Tuxitheone 0:ecaf3e593122 257 #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
Tuxitheone 0:ecaf3e593122 258 #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
Tuxitheone 0:ecaf3e593122 259 #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
Tuxitheone 0:ecaf3e593122 260
Tuxitheone 0:ecaf3e593122 261 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 262 * Macro defines for Transmit Status Vector 1 Register
Tuxitheone 0:ecaf3e593122 263 **********************************************************************/
Tuxitheone 0:ecaf3e593122 264 #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
Tuxitheone 0:ecaf3e593122 265 #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
Tuxitheone 0:ecaf3e593122 266
Tuxitheone 0:ecaf3e593122 267 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 268 * Macro defines for Receive Status Vector Register
Tuxitheone 0:ecaf3e593122 269 **********************************************************************/
Tuxitheone 0:ecaf3e593122 270 #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
Tuxitheone 0:ecaf3e593122 271 #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
Tuxitheone 0:ecaf3e593122 272 #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
Tuxitheone 0:ecaf3e593122 273 #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
Tuxitheone 0:ecaf3e593122 274 #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
Tuxitheone 0:ecaf3e593122 275 #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
Tuxitheone 0:ecaf3e593122 276 #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
Tuxitheone 0:ecaf3e593122 277 #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
Tuxitheone 0:ecaf3e593122 278 #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
Tuxitheone 0:ecaf3e593122 279 #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
Tuxitheone 0:ecaf3e593122 280 #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
Tuxitheone 0:ecaf3e593122 281 #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
Tuxitheone 0:ecaf3e593122 282 #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
Tuxitheone 0:ecaf3e593122 283 #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
Tuxitheone 0:ecaf3e593122 284 #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
Tuxitheone 0:ecaf3e593122 285 #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
Tuxitheone 0:ecaf3e593122 286
Tuxitheone 0:ecaf3e593122 287 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 288 * Macro defines for Flow Control Counter Register
Tuxitheone 0:ecaf3e593122 289 **********************************************************************/
Tuxitheone 0:ecaf3e593122 290 #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
Tuxitheone 0:ecaf3e593122 291 #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
Tuxitheone 0:ecaf3e593122 292
Tuxitheone 0:ecaf3e593122 293 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 294 * Macro defines for Flow Control Status Register
Tuxitheone 0:ecaf3e593122 295 **********************************************************************/
Tuxitheone 0:ecaf3e593122 296 #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
Tuxitheone 0:ecaf3e593122 297
Tuxitheone 0:ecaf3e593122 298
Tuxitheone 0:ecaf3e593122 299 /* Receive filter register definitions -------------------------------------------------------- */
Tuxitheone 0:ecaf3e593122 300 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 301 * Macro defines for Receive Filter Control Register
Tuxitheone 0:ecaf3e593122 302 **********************************************************************/
Tuxitheone 0:ecaf3e593122 303 #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
Tuxitheone 0:ecaf3e593122 304 #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
Tuxitheone 0:ecaf3e593122 305 #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
Tuxitheone 0:ecaf3e593122 306 #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
Tuxitheone 0:ecaf3e593122 307 #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
Tuxitheone 0:ecaf3e593122 308 #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
Tuxitheone 0:ecaf3e593122 309 #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
Tuxitheone 0:ecaf3e593122 310 #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
Tuxitheone 0:ecaf3e593122 311
Tuxitheone 0:ecaf3e593122 312 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 313 * Macro defines for Receive Filter WoL Status/Clear Registers
Tuxitheone 0:ecaf3e593122 314 **********************************************************************/
Tuxitheone 0:ecaf3e593122 315 #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
Tuxitheone 0:ecaf3e593122 316 #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
Tuxitheone 0:ecaf3e593122 317 #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
Tuxitheone 0:ecaf3e593122 318 #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
Tuxitheone 0:ecaf3e593122 319 #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
Tuxitheone 0:ecaf3e593122 320 #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
Tuxitheone 0:ecaf3e593122 321 #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
Tuxitheone 0:ecaf3e593122 322 #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
Tuxitheone 0:ecaf3e593122 323 #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
Tuxitheone 0:ecaf3e593122 324
Tuxitheone 0:ecaf3e593122 325
Tuxitheone 0:ecaf3e593122 326 /* Module control register definitions ---------------------------------------------------- */
Tuxitheone 0:ecaf3e593122 327 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 328 * Macro defines for Interrupt Status/Enable/Clear/Set Registers
Tuxitheone 0:ecaf3e593122 329 **********************************************************************/
Tuxitheone 0:ecaf3e593122 330 #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
Tuxitheone 0:ecaf3e593122 331 #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
Tuxitheone 0:ecaf3e593122 332 #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
Tuxitheone 0:ecaf3e593122 333 #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
Tuxitheone 0:ecaf3e593122 334 #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
Tuxitheone 0:ecaf3e593122 335 #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
Tuxitheone 0:ecaf3e593122 336 #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
Tuxitheone 0:ecaf3e593122 337 #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
Tuxitheone 0:ecaf3e593122 338 #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
Tuxitheone 0:ecaf3e593122 339 #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
Tuxitheone 0:ecaf3e593122 340
Tuxitheone 0:ecaf3e593122 341 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 342 * Macro defines for Power Down Register
Tuxitheone 0:ecaf3e593122 343 **********************************************************************/
Tuxitheone 0:ecaf3e593122 344 #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
Tuxitheone 0:ecaf3e593122 345
Tuxitheone 0:ecaf3e593122 346 /* Descriptor and status formats ---------------------------------------------------- */
Tuxitheone 0:ecaf3e593122 347 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 348 * Macro defines for RX Descriptor Control Word
Tuxitheone 0:ecaf3e593122 349 **********************************************************************/
Tuxitheone 0:ecaf3e593122 350 #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
Tuxitheone 0:ecaf3e593122 351 #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
Tuxitheone 0:ecaf3e593122 352
Tuxitheone 0:ecaf3e593122 353 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 354 * Macro defines for RX Status Hash CRC Word
Tuxitheone 0:ecaf3e593122 355 **********************************************************************/
Tuxitheone 0:ecaf3e593122 356 #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
Tuxitheone 0:ecaf3e593122 357 #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
Tuxitheone 0:ecaf3e593122 358
Tuxitheone 0:ecaf3e593122 359 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 360 * Macro defines for RX Status Information Word
Tuxitheone 0:ecaf3e593122 361 **********************************************************************/
Tuxitheone 0:ecaf3e593122 362 #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
Tuxitheone 0:ecaf3e593122 363 #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
Tuxitheone 0:ecaf3e593122 364 #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
Tuxitheone 0:ecaf3e593122 365 #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
Tuxitheone 0:ecaf3e593122 366 #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
Tuxitheone 0:ecaf3e593122 367 #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
Tuxitheone 0:ecaf3e593122 368 #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
Tuxitheone 0:ecaf3e593122 369 #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
Tuxitheone 0:ecaf3e593122 370 #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
Tuxitheone 0:ecaf3e593122 371 #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
Tuxitheone 0:ecaf3e593122 372 #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
Tuxitheone 0:ecaf3e593122 373 #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
Tuxitheone 0:ecaf3e593122 374 #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
Tuxitheone 0:ecaf3e593122 375 #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
Tuxitheone 0:ecaf3e593122 376 #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
Tuxitheone 0:ecaf3e593122 377 #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
Tuxitheone 0:ecaf3e593122 378 EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
Tuxitheone 0:ecaf3e593122 379
Tuxitheone 0:ecaf3e593122 380 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 381 * Macro defines for TX Descriptor Control Word
Tuxitheone 0:ecaf3e593122 382 **********************************************************************/
Tuxitheone 0:ecaf3e593122 383 #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
Tuxitheone 0:ecaf3e593122 384 #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
Tuxitheone 0:ecaf3e593122 385 #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
Tuxitheone 0:ecaf3e593122 386 #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
Tuxitheone 0:ecaf3e593122 387 #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
Tuxitheone 0:ecaf3e593122 388 #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
Tuxitheone 0:ecaf3e593122 389 #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
Tuxitheone 0:ecaf3e593122 390
Tuxitheone 0:ecaf3e593122 391 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 392 * Macro defines for TX Status Information Word
Tuxitheone 0:ecaf3e593122 393 **********************************************************************/
Tuxitheone 0:ecaf3e593122 394 #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
Tuxitheone 0:ecaf3e593122 395 #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
Tuxitheone 0:ecaf3e593122 396 #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
Tuxitheone 0:ecaf3e593122 397 #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
Tuxitheone 0:ecaf3e593122 398 #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
Tuxitheone 0:ecaf3e593122 399 #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
Tuxitheone 0:ecaf3e593122 400 #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
Tuxitheone 0:ecaf3e593122 401 #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
Tuxitheone 0:ecaf3e593122 402
Tuxitheone 0:ecaf3e593122 403 #ifdef MCB_LPC_1768
Tuxitheone 0:ecaf3e593122 404 /* DP83848C PHY definition ------------------------------------------------------------ */
Tuxitheone 0:ecaf3e593122 405
Tuxitheone 0:ecaf3e593122 406 /** PHY device reset time out definition */
Tuxitheone 0:ecaf3e593122 407 #define EMAC_PHY_RESP_TOUT 0x100000UL
Tuxitheone 0:ecaf3e593122 408
Tuxitheone 0:ecaf3e593122 409 /* ENET Device Revision ID */
Tuxitheone 0:ecaf3e593122 410 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
Tuxitheone 0:ecaf3e593122 411
Tuxitheone 0:ecaf3e593122 412 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 413 * Macro defines for DP83848C PHY Registers
Tuxitheone 0:ecaf3e593122 414 **********************************************************************/
Tuxitheone 0:ecaf3e593122 415 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
Tuxitheone 0:ecaf3e593122 416 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
Tuxitheone 0:ecaf3e593122 417 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
Tuxitheone 0:ecaf3e593122 418 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
Tuxitheone 0:ecaf3e593122 419 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
Tuxitheone 0:ecaf3e593122 420 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
Tuxitheone 0:ecaf3e593122 421 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
Tuxitheone 0:ecaf3e593122 422 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
Tuxitheone 0:ecaf3e593122 423 #define EMAC_PHY_REG_LPNPA 0x08
Tuxitheone 0:ecaf3e593122 424
Tuxitheone 0:ecaf3e593122 425 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 426 * Macro defines for PHY Extended Registers
Tuxitheone 0:ecaf3e593122 427 **********************************************************************/
Tuxitheone 0:ecaf3e593122 428 #define EMAC_PHY_REG_STS 0x10 /**< Status Register */
Tuxitheone 0:ecaf3e593122 429 #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
Tuxitheone 0:ecaf3e593122 430 #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
Tuxitheone 0:ecaf3e593122 431 #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
Tuxitheone 0:ecaf3e593122 432 #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
Tuxitheone 0:ecaf3e593122 433 #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
Tuxitheone 0:ecaf3e593122 434 #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
Tuxitheone 0:ecaf3e593122 435 #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
Tuxitheone 0:ecaf3e593122 436 #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
Tuxitheone 0:ecaf3e593122 437 #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
Tuxitheone 0:ecaf3e593122 438 #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
Tuxitheone 0:ecaf3e593122 439 #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
Tuxitheone 0:ecaf3e593122 440
Tuxitheone 0:ecaf3e593122 441 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 442 * Macro defines for PHY Basic Mode Control Register
Tuxitheone 0:ecaf3e593122 443 **********************************************************************/
Tuxitheone 0:ecaf3e593122 444 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
Tuxitheone 0:ecaf3e593122 445 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
Tuxitheone 0:ecaf3e593122 446 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
Tuxitheone 0:ecaf3e593122 447 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
Tuxitheone 0:ecaf3e593122 448 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
Tuxitheone 0:ecaf3e593122 449 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
Tuxitheone 0:ecaf3e593122 450 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
Tuxitheone 0:ecaf3e593122 451 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
Tuxitheone 0:ecaf3e593122 452
Tuxitheone 0:ecaf3e593122 453 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 454 * Macro defines for PHY Basic Mode Status Status Register
Tuxitheone 0:ecaf3e593122 455 **********************************************************************/
Tuxitheone 0:ecaf3e593122 456 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
Tuxitheone 0:ecaf3e593122 457 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
Tuxitheone 0:ecaf3e593122 458 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
Tuxitheone 0:ecaf3e593122 459 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
Tuxitheone 0:ecaf3e593122 460 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
Tuxitheone 0:ecaf3e593122 461 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
Tuxitheone 0:ecaf3e593122 462 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
Tuxitheone 0:ecaf3e593122 463 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
Tuxitheone 0:ecaf3e593122 464 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
Tuxitheone 0:ecaf3e593122 465 #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
Tuxitheone 0:ecaf3e593122 466
Tuxitheone 0:ecaf3e593122 467 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 468 * Macro defines for PHY Status Register
Tuxitheone 0:ecaf3e593122 469 **********************************************************************/
Tuxitheone 0:ecaf3e593122 470 #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
Tuxitheone 0:ecaf3e593122 471 #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
Tuxitheone 0:ecaf3e593122 472 #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
Tuxitheone 0:ecaf3e593122 473 #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
Tuxitheone 0:ecaf3e593122 474 #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
Tuxitheone 0:ecaf3e593122 475 #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
Tuxitheone 0:ecaf3e593122 476 #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
Tuxitheone 0:ecaf3e593122 477
Tuxitheone 0:ecaf3e593122 478 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
Tuxitheone 0:ecaf3e593122 479 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
Tuxitheone 0:ecaf3e593122 480 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
Tuxitheone 0:ecaf3e593122 481 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
Tuxitheone 0:ecaf3e593122 482 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
Tuxitheone 0:ecaf3e593122 483
Tuxitheone 0:ecaf3e593122 484 #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
Tuxitheone 0:ecaf3e593122 485 #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
Tuxitheone 0:ecaf3e593122 486
Tuxitheone 0:ecaf3e593122 487 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
Tuxitheone 0:ecaf3e593122 488 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
Tuxitheone 0:ecaf3e593122 489 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
Tuxitheone 0:ecaf3e593122 490
Tuxitheone 0:ecaf3e593122 491 #elif defined(IAR_LPC_1768)
Tuxitheone 0:ecaf3e593122 492 /* KSZ8721BL PHY definition ------------------------------------------------------------ */
Tuxitheone 0:ecaf3e593122 493 /** PHY device reset time out definition */
Tuxitheone 0:ecaf3e593122 494 #define EMAC_PHY_RESP_TOUT 0x100000UL
Tuxitheone 0:ecaf3e593122 495
Tuxitheone 0:ecaf3e593122 496 /* ENET Device Revision ID */
Tuxitheone 0:ecaf3e593122 497 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
Tuxitheone 0:ecaf3e593122 498
Tuxitheone 0:ecaf3e593122 499 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 500 * Macro defines for KSZ8721BL PHY Registers
Tuxitheone 0:ecaf3e593122 501 **********************************************************************/
Tuxitheone 0:ecaf3e593122 502 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
Tuxitheone 0:ecaf3e593122 503 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
Tuxitheone 0:ecaf3e593122 504 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
Tuxitheone 0:ecaf3e593122 505 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
Tuxitheone 0:ecaf3e593122 506 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
Tuxitheone 0:ecaf3e593122 507 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
Tuxitheone 0:ecaf3e593122 508 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
Tuxitheone 0:ecaf3e593122 509 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
Tuxitheone 0:ecaf3e593122 510 #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
Tuxitheone 0:ecaf3e593122 511 #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
Tuxitheone 0:ecaf3e593122 512 #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
Tuxitheone 0:ecaf3e593122 513 #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
Tuxitheone 0:ecaf3e593122 514
Tuxitheone 0:ecaf3e593122 515 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 516 * Macro defines for PHY Basic Mode Control Register
Tuxitheone 0:ecaf3e593122 517 **********************************************************************/
Tuxitheone 0:ecaf3e593122 518 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
Tuxitheone 0:ecaf3e593122 519 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
Tuxitheone 0:ecaf3e593122 520 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
Tuxitheone 0:ecaf3e593122 521 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
Tuxitheone 0:ecaf3e593122 522 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
Tuxitheone 0:ecaf3e593122 523 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
Tuxitheone 0:ecaf3e593122 524 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
Tuxitheone 0:ecaf3e593122 525 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
Tuxitheone 0:ecaf3e593122 526 #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
Tuxitheone 0:ecaf3e593122 527 #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
Tuxitheone 0:ecaf3e593122 528
Tuxitheone 0:ecaf3e593122 529 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 530 * Macro defines for PHY Basic Mode Status Register
Tuxitheone 0:ecaf3e593122 531 **********************************************************************/
Tuxitheone 0:ecaf3e593122 532 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
Tuxitheone 0:ecaf3e593122 533 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
Tuxitheone 0:ecaf3e593122 534 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
Tuxitheone 0:ecaf3e593122 535 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
Tuxitheone 0:ecaf3e593122 536 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
Tuxitheone 0:ecaf3e593122 537 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
Tuxitheone 0:ecaf3e593122 538 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
Tuxitheone 0:ecaf3e593122 539 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
Tuxitheone 0:ecaf3e593122 540 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
Tuxitheone 0:ecaf3e593122 541 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
Tuxitheone 0:ecaf3e593122 542 #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
Tuxitheone 0:ecaf3e593122 543 #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
Tuxitheone 0:ecaf3e593122 544
Tuxitheone 0:ecaf3e593122 545 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 546 * Macro defines for PHY Identifier
Tuxitheone 0:ecaf3e593122 547 **********************************************************************/
Tuxitheone 0:ecaf3e593122 548 /* PHY Identifier 1 bitmap definitions */
Tuxitheone 0:ecaf3e593122 549 #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
Tuxitheone 0:ecaf3e593122 550
Tuxitheone 0:ecaf3e593122 551 /* PHY Identifier 2 bitmap definitions */
Tuxitheone 0:ecaf3e593122 552 #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
Tuxitheone 0:ecaf3e593122 553
Tuxitheone 0:ecaf3e593122 554 /*********************************************************************//**
Tuxitheone 0:ecaf3e593122 555 * Macro defines for Auto-Negotiation Advertisement
Tuxitheone 0:ecaf3e593122 556 **********************************************************************/
Tuxitheone 0:ecaf3e593122 557 #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
Tuxitheone 0:ecaf3e593122 558 #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
Tuxitheone 0:ecaf3e593122 559 #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
Tuxitheone 0:ecaf3e593122 560 #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
Tuxitheone 0:ecaf3e593122 561 #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
Tuxitheone 0:ecaf3e593122 562 #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
Tuxitheone 0:ecaf3e593122 563 #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
Tuxitheone 0:ecaf3e593122 564 #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
Tuxitheone 0:ecaf3e593122 565 #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
Tuxitheone 0:ecaf3e593122 566
Tuxitheone 0:ecaf3e593122 567 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
Tuxitheone 0:ecaf3e593122 568 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
Tuxitheone 0:ecaf3e593122 569 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
Tuxitheone 0:ecaf3e593122 570 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
Tuxitheone 0:ecaf3e593122 571 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
Tuxitheone 0:ecaf3e593122 572
Tuxitheone 0:ecaf3e593122 573 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
Tuxitheone 0:ecaf3e593122 574 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
Tuxitheone 0:ecaf3e593122 575
Tuxitheone 0:ecaf3e593122 576 #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
Tuxitheone 0:ecaf3e593122 577 #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
Tuxitheone 0:ecaf3e593122 578 #endif
Tuxitheone 0:ecaf3e593122 579
Tuxitheone 0:ecaf3e593122 580 /**
Tuxitheone 0:ecaf3e593122 581 * @}
Tuxitheone 0:ecaf3e593122 582 */
Tuxitheone 0:ecaf3e593122 583
Tuxitheone 0:ecaf3e593122 584
Tuxitheone 0:ecaf3e593122 585 /* Public Types --------------------------------------------------------------- */
Tuxitheone 0:ecaf3e593122 586 /** @defgroup EMAC_Public_Types EMAC Public Types
Tuxitheone 0:ecaf3e593122 587 * @{
Tuxitheone 0:ecaf3e593122 588 */
Tuxitheone 0:ecaf3e593122 589
Tuxitheone 0:ecaf3e593122 590 /* Descriptor and status formats ---------------------------------------------- */
Tuxitheone 0:ecaf3e593122 591
Tuxitheone 0:ecaf3e593122 592 /**
Tuxitheone 0:ecaf3e593122 593 * @brief RX Descriptor structure type definition
Tuxitheone 0:ecaf3e593122 594 */
Tuxitheone 0:ecaf3e593122 595 typedef struct {
Tuxitheone 0:ecaf3e593122 596 uint32_t Packet; /**< Receive Packet Descriptor */
Tuxitheone 0:ecaf3e593122 597 uint32_t Ctrl; /**< Receive Control Descriptor */
Tuxitheone 0:ecaf3e593122 598 } RX_Desc;
Tuxitheone 0:ecaf3e593122 599
Tuxitheone 0:ecaf3e593122 600 /**
Tuxitheone 0:ecaf3e593122 601 * @brief RX Status structure type definition
Tuxitheone 0:ecaf3e593122 602 */
Tuxitheone 0:ecaf3e593122 603 typedef struct {
Tuxitheone 0:ecaf3e593122 604 uint32_t Info; /**< Receive Information Status */
Tuxitheone 0:ecaf3e593122 605 uint32_t HashCRC; /**< Receive Hash CRC Status */
Tuxitheone 0:ecaf3e593122 606 } RX_Stat;
Tuxitheone 0:ecaf3e593122 607
Tuxitheone 0:ecaf3e593122 608 /**
Tuxitheone 0:ecaf3e593122 609 * @brief TX Descriptor structure type definition
Tuxitheone 0:ecaf3e593122 610 */
Tuxitheone 0:ecaf3e593122 611 typedef struct {
Tuxitheone 0:ecaf3e593122 612 uint32_t Packet; /**< Transmit Packet Descriptor */
Tuxitheone 0:ecaf3e593122 613 uint32_t Ctrl; /**< Transmit Control Descriptor */
Tuxitheone 0:ecaf3e593122 614 } TX_Desc;
Tuxitheone 0:ecaf3e593122 615
Tuxitheone 0:ecaf3e593122 616 /**
Tuxitheone 0:ecaf3e593122 617 * @brief TX Status structure type definition
Tuxitheone 0:ecaf3e593122 618 */
Tuxitheone 0:ecaf3e593122 619 typedef struct {
Tuxitheone 0:ecaf3e593122 620 uint32_t Info; /**< Transmit Information Status */
Tuxitheone 0:ecaf3e593122 621 } TX_Stat;
Tuxitheone 0:ecaf3e593122 622
Tuxitheone 0:ecaf3e593122 623
Tuxitheone 0:ecaf3e593122 624 /**
Tuxitheone 0:ecaf3e593122 625 * @brief TX Data Buffer structure definition
Tuxitheone 0:ecaf3e593122 626 */
Tuxitheone 0:ecaf3e593122 627 typedef struct {
Tuxitheone 0:ecaf3e593122 628 uint32_t ulDataLen; /**< Data length */
Tuxitheone 0:ecaf3e593122 629 uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
Tuxitheone 0:ecaf3e593122 630 } EMAC_PACKETBUF_Type;
Tuxitheone 0:ecaf3e593122 631
Tuxitheone 0:ecaf3e593122 632 /**
Tuxitheone 0:ecaf3e593122 633 * @brief EMAC configuration structure definition
Tuxitheone 0:ecaf3e593122 634 */
Tuxitheone 0:ecaf3e593122 635 typedef struct {
Tuxitheone 0:ecaf3e593122 636 uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
Tuxitheone 0:ecaf3e593122 637 - EMAC_MODE_AUTO
Tuxitheone 0:ecaf3e593122 638 - EMAC_MODE_10M_FULL
Tuxitheone 0:ecaf3e593122 639 - EMAC_MODE_10M_HALF
Tuxitheone 0:ecaf3e593122 640 - EMAC_MODE_100M_FULL
Tuxitheone 0:ecaf3e593122 641 - EMAC_MODE_100M_HALF
Tuxitheone 0:ecaf3e593122 642 */
Tuxitheone 0:ecaf3e593122 643 uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
Tuxitheone 0:ecaf3e593122 644 of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
Tuxitheone 0:ecaf3e593122 645 */
Tuxitheone 0:ecaf3e593122 646 } EMAC_CFG_Type;
Tuxitheone 0:ecaf3e593122 647
Tuxitheone 0:ecaf3e593122 648 /** Ethernet block power/clock control bit*/
Tuxitheone 0:ecaf3e593122 649 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
Tuxitheone 0:ecaf3e593122 650
Tuxitheone 0:ecaf3e593122 651 #ifdef __cplusplus
Tuxitheone 0:ecaf3e593122 652 }
Tuxitheone 0:ecaf3e593122 653 #endif
Tuxitheone 0:ecaf3e593122 654
Tuxitheone 0:ecaf3e593122 655 #endif /* LPC17XX_EMAC_H_ */
Tuxitheone 0:ecaf3e593122 656
Tuxitheone 0:ecaf3e593122 657 /**
Tuxitheone 0:ecaf3e593122 658 * @}
Tuxitheone 0:ecaf3e593122 659 */
Tuxitheone 0:ecaf3e593122 660
Tuxitheone 0:ecaf3e593122 661 /* --------------------------------- End Of File ------------------------------ */