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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.c@180:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
180:96ed750bd169
Parent:
156:95d6b41a828b 
mbed-dev libray. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 156:95d6b41a828b 2 ******************************************************************************
<> 156:95d6b41a828b 3 * @file stm32f0xx_ll_utils.c
<> 156:95d6b41a828b 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @brief UTILS LL module driver.
<> 156:95d6b41a828b 6 ******************************************************************************
<> 156:95d6b41a828b 7 * @attention
<> 156:95d6b41a828b 8 *
<> 156:95d6b41a828b 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 156:95d6b41a828b 10 *
<> 156:95d6b41a828b 11 * Redistribution and use in source and binary forms, with or without modification,
<> 156:95d6b41a828b 12 * are permitted provided that the following conditions are met:
<> 156:95d6b41a828b 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 156:95d6b41a828b 14 * this list of conditions and the following disclaimer.
<> 156:95d6b41a828b 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 156:95d6b41a828b 16 * this list of conditions and the following disclaimer in the documentation
<> 156:95d6b41a828b 17 * and/or other materials provided with the distribution.
<> 156:95d6b41a828b 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 156:95d6b41a828b 19 * may be used to endorse or promote products derived from this software
<> 156:95d6b41a828b 20 * without specific prior written permission.
<> 156:95d6b41a828b 21 *
<> 156:95d6b41a828b 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 156:95d6b41a828b 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 156:95d6b41a828b 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 156:95d6b41a828b 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 156:95d6b41a828b 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 156:95d6b41a828b 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 156:95d6b41a828b 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 156:95d6b41a828b 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 156:95d6b41a828b 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 156:95d6b41a828b 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 156:95d6b41a828b 32 *
<> 156:95d6b41a828b 33 ******************************************************************************
<> 156:95d6b41a828b 34 */
<> 156:95d6b41a828b 35 /* Includes ------------------------------------------------------------------*/
<> 156:95d6b41a828b 36 #include "stm32f0xx_ll_rcc.h"
<> 156:95d6b41a828b 37 #include "stm32f0xx_ll_utils.h"
<> 156:95d6b41a828b 38 #include "stm32f0xx_ll_system.h"
<> 156:95d6b41a828b 39 #ifdef USE_FULL_ASSERT
<> 156:95d6b41a828b 40 #include "stm32_assert.h"
<> 156:95d6b41a828b 41 #else
<> 156:95d6b41a828b 42 #define assert_param(expr) ((void)0U)
<> 156:95d6b41a828b 43 #endif
<> 156:95d6b41a828b 44
<> 156:95d6b41a828b 45 /** @addtogroup STM32F0xx_LL_Driver
<> 156:95d6b41a828b 46 * @{
<> 156:95d6b41a828b 47 */
<> 156:95d6b41a828b 48
<> 156:95d6b41a828b 49 /** @addtogroup UTILS_LL
<> 156:95d6b41a828b 50 * @{
<> 156:95d6b41a828b 51 */
<> 156:95d6b41a828b 52
<> 156:95d6b41a828b 53 /* Private types -------------------------------------------------------------*/
<> 156:95d6b41a828b 54 /* Private variables ---------------------------------------------------------*/
<> 156:95d6b41a828b 55 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 56 /** @addtogroup UTILS_LL_Private_Constants
<> 156:95d6b41a828b 57 * @{
<> 156:95d6b41a828b 58 */
<> 156:95d6b41a828b 59
<> 156:95d6b41a828b 60 /* Defines used for PLL range */
Anna Bridge 180:96ed750bd169 61 #define UTILS_PLL_OUTPUT_MIN 16000000U /*!< Frequency min for PLL output, in Hz */
Anna Bridge 180:96ed750bd169 62 #define UTILS_PLL_OUTPUT_MAX 48000000U /*!< Frequency max for PLL output, in Hz */
<> 156:95d6b41a828b 63
<> 156:95d6b41a828b 64 /* Defines used for HSE range */
Anna Bridge 180:96ed750bd169 65 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
Anna Bridge 180:96ed750bd169 66 #define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */
<> 156:95d6b41a828b 67
<> 156:95d6b41a828b 68 /* Defines used for FLASH latency according to SYSCLK Frequency */
Anna Bridge 180:96ed750bd169 69 #define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */
<> 156:95d6b41a828b 70 /**
<> 156:95d6b41a828b 71 * @}
<> 156:95d6b41a828b 72 */
<> 156:95d6b41a828b 73 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 74 /** @addtogroup UTILS_LL_Private_Macros
<> 156:95d6b41a828b 75 * @{
<> 156:95d6b41a828b 76 */
<> 156:95d6b41a828b 77 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
<> 156:95d6b41a828b 78 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
<> 156:95d6b41a828b 79 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
<> 156:95d6b41a828b 80 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
<> 156:95d6b41a828b 81 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
<> 156:95d6b41a828b 82 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
<> 156:95d6b41a828b 83 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
<> 156:95d6b41a828b 84 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
<> 156:95d6b41a828b 85 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
<> 156:95d6b41a828b 86
<> 156:95d6b41a828b 87 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
<> 156:95d6b41a828b 88 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
<> 156:95d6b41a828b 89 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
<> 156:95d6b41a828b 90 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
<> 156:95d6b41a828b 91 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
<> 156:95d6b41a828b 92
<> 156:95d6b41a828b 93 #define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
<> 156:95d6b41a828b 94 || ((__VALUE__) == LL_RCC_PLL_MUL_3) \
<> 156:95d6b41a828b 95 || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
<> 156:95d6b41a828b 96 || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
<> 156:95d6b41a828b 97 || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
<> 156:95d6b41a828b 98 || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
<> 156:95d6b41a828b 99 || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
<> 156:95d6b41a828b 100 || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
<> 156:95d6b41a828b 101 || ((__VALUE__) == LL_RCC_PLL_MUL_10) \
<> 156:95d6b41a828b 102 || ((__VALUE__) == LL_RCC_PLL_MUL_11) \
<> 156:95d6b41a828b 103 || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
<> 156:95d6b41a828b 104 || ((__VALUE__) == LL_RCC_PLL_MUL_13) \
<> 156:95d6b41a828b 105 || ((__VALUE__) == LL_RCC_PLL_MUL_14) \
<> 156:95d6b41a828b 106 || ((__VALUE__) == LL_RCC_PLL_MUL_15) \
<> 156:95d6b41a828b 107 || ((__VALUE__) == LL_RCC_PLL_MUL_16))
<> 156:95d6b41a828b 108
<> 156:95d6b41a828b 109 #define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \
<> 156:95d6b41a828b 110 ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \
<> 156:95d6b41a828b 111 ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
<> 156:95d6b41a828b 112 ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \
<> 156:95d6b41a828b 113 ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \
<> 156:95d6b41a828b 114 ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \
<> 156:95d6b41a828b 115 ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \
<> 156:95d6b41a828b 116 ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
<> 156:95d6b41a828b 117
<> 156:95d6b41a828b 118 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((UTILS_PLL_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX))
<> 156:95d6b41a828b 119
<> 156:95d6b41a828b 120
<> 156:95d6b41a828b 121 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
<> 156:95d6b41a828b 122 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
<> 156:95d6b41a828b 123
<> 156:95d6b41a828b 124 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
<> 156:95d6b41a828b 125 /**
<> 156:95d6b41a828b 126 * @}
<> 156:95d6b41a828b 127 */
<> 156:95d6b41a828b 128 /* Private function prototypes -----------------------------------------------*/
<> 156:95d6b41a828b 129 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
<> 156:95d6b41a828b 130 * @{
<> 156:95d6b41a828b 131 */
<> 156:95d6b41a828b 132 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
<> 156:95d6b41a828b 133 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
Anna Bridge 180:96ed750bd169 134 #if defined(FLASH_ACR_LATENCY)
<> 156:95d6b41a828b 135 static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
Anna Bridge 180:96ed750bd169 136 #endif /* FLASH_ACR_LATENCY */
<> 156:95d6b41a828b 137 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
<> 156:95d6b41a828b 138 static ErrorStatus UTILS_PLL_IsBusy(void);
<> 156:95d6b41a828b 139 /**
<> 156:95d6b41a828b 140 * @}
<> 156:95d6b41a828b 141 */
<> 156:95d6b41a828b 142
<> 156:95d6b41a828b 143 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 144 /** @addtogroup UTILS_LL_Exported_Functions
<> 156:95d6b41a828b 145 * @{
<> 156:95d6b41a828b 146 */
<> 156:95d6b41a828b 147
<> 156:95d6b41a828b 148 /** @addtogroup UTILS_LL_EF_DELAY
<> 156:95d6b41a828b 149 * @{
<> 156:95d6b41a828b 150 */
<> 156:95d6b41a828b 151
<> 156:95d6b41a828b 152 /**
<> 156:95d6b41a828b 153 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
<> 156:95d6b41a828b 154 * @note When a RTOS is used, it is recommended to avoid changing the Systick
<> 156:95d6b41a828b 155 * configuration by calling this function, for a delay use rather osDelay RTOS service.
<> 156:95d6b41a828b 156 * @param HCLKFrequency HCLK frequency in Hz
<> 156:95d6b41a828b 157 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
<> 156:95d6b41a828b 158 * @retval None
<> 156:95d6b41a828b 159 */
<> 156:95d6b41a828b 160 void LL_Init1msTick(uint32_t HCLKFrequency)
<> 156:95d6b41a828b 161 {
<> 156:95d6b41a828b 162 /* Use frequency provided in argument */
<> 156:95d6b41a828b 163 LL_InitTick(HCLKFrequency, 1000U);
<> 156:95d6b41a828b 164 }
<> 156:95d6b41a828b 165
<> 156:95d6b41a828b 166 /**
<> 156:95d6b41a828b 167 * @brief This function provides accurate delay (in milliseconds) based
<> 156:95d6b41a828b 168 * on SysTick counter flag
<> 156:95d6b41a828b 169 * @note When a RTOS is used, it is recommended to avoid using blocking delay
<> 156:95d6b41a828b 170 * and use rather osDelay service.
<> 156:95d6b41a828b 171 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
<> 156:95d6b41a828b 172 * will configure Systick to 1ms
<> 156:95d6b41a828b 173 * @param Delay specifies the delay time length, in milliseconds.
<> 156:95d6b41a828b 174 * @retval None
<> 156:95d6b41a828b 175 */
<> 156:95d6b41a828b 176 void LL_mDelay(uint32_t Delay)
<> 156:95d6b41a828b 177 {
<> 156:95d6b41a828b 178 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
<> 156:95d6b41a828b 179 /* Add this code to indicate that local variable is not used */
<> 156:95d6b41a828b 180 ((void)tmp);
<> 156:95d6b41a828b 181
<> 156:95d6b41a828b 182 /* Add a period to guaranty minimum wait */
<> 156:95d6b41a828b 183 if (Delay < LL_MAX_DELAY)
<> 156:95d6b41a828b 184 {
<> 156:95d6b41a828b 185 Delay++;
<> 156:95d6b41a828b 186 }
<> 156:95d6b41a828b 187
<> 156:95d6b41a828b 188 while (Delay)
<> 156:95d6b41a828b 189 {
<> 156:95d6b41a828b 190 if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
<> 156:95d6b41a828b 191 {
<> 156:95d6b41a828b 192 Delay--;
<> 156:95d6b41a828b 193 }
<> 156:95d6b41a828b 194 }
<> 156:95d6b41a828b 195 }
<> 156:95d6b41a828b 196
<> 156:95d6b41a828b 197 /**
<> 156:95d6b41a828b 198 * @}
<> 156:95d6b41a828b 199 */
<> 156:95d6b41a828b 200
<> 156:95d6b41a828b 201 /** @addtogroup UTILS_EF_SYSTEM
<> 156:95d6b41a828b 202 * @brief System Configuration functions
<> 156:95d6b41a828b 203 *
<> 156:95d6b41a828b 204 @verbatim
<> 156:95d6b41a828b 205 ===============================================================================
<> 156:95d6b41a828b 206 ##### System Configuration functions #####
<> 156:95d6b41a828b 207 ===============================================================================
<> 156:95d6b41a828b 208 [..]
<> 156:95d6b41a828b 209 System, AHB and APB buses clocks configuration
<> 156:95d6b41a828b 210
<> 156:95d6b41a828b 211 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 48000000 Hz.
<> 156:95d6b41a828b 212 @endverbatim
<> 156:95d6b41a828b 213 @internal
<> 156:95d6b41a828b 214 Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
<> 156:95d6b41a828b 215 (++) +-----------------------------------------------+
<> 156:95d6b41a828b 216 (++) | Latency | SYSCLK clock frequency (MHz) |
<> 156:95d6b41a828b 217 (++) |---------------|-------------------------------|
<> 156:95d6b41a828b 218 (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
<> 156:95d6b41a828b 219 (++) |---------------|-------------------------------|
<> 156:95d6b41a828b 220 (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
<> 156:95d6b41a828b 221 (++) +-----------------------------------------------+
<> 156:95d6b41a828b 222 @endinternal
<> 156:95d6b41a828b 223 * @{
<> 156:95d6b41a828b 224 */
<> 156:95d6b41a828b 225
<> 156:95d6b41a828b 226 /**
<> 156:95d6b41a828b 227 * @brief This function sets directly SystemCoreClock CMSIS variable.
<> 156:95d6b41a828b 228 * @note Variable can be calculated also through SystemCoreClockUpdate function.
<> 156:95d6b41a828b 229 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
<> 156:95d6b41a828b 230 * @retval None
<> 156:95d6b41a828b 231 */
<> 156:95d6b41a828b 232 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
<> 156:95d6b41a828b 233 {
<> 156:95d6b41a828b 234 /* HCLK clock frequency */
<> 156:95d6b41a828b 235 SystemCoreClock = HCLKFrequency;
<> 156:95d6b41a828b 236 }
<> 156:95d6b41a828b 237
<> 156:95d6b41a828b 238 /**
<> 156:95d6b41a828b 239 * @brief This function configures system clock with HSI as clock source of the PLL
<> 156:95d6b41a828b 240 * @note The application need to ensure that PLL is disabled.
<> 156:95d6b41a828b 241 * @note Function is based on the following formula:
<> 156:95d6b41a828b 242 * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
<> 156:95d6b41a828b 243 * - PREDIV: Set to 2 for few devices
<> 156:95d6b41a828b 244 * - PLLMUL: The application software must set correctly the PLL multiplication factor to
<> 156:95d6b41a828b 245 * be in the range 16-48MHz
<> 156:95d6b41a828b 246 * @note FLASH latency can be modified through this function.
<> 156:95d6b41a828b 247 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<> 156:95d6b41a828b 248 * the configuration information for the PLL.
<> 156:95d6b41a828b 249 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<> 156:95d6b41a828b 250 * the configuration information for the BUS prescalers.
<> 156:95d6b41a828b 251 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 252 * - SUCCESS: Max frequency configuration done
<> 156:95d6b41a828b 253 * - ERROR: Max frequency configuration not done
<> 156:95d6b41a828b 254 */
<> 156:95d6b41a828b 255 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
<> 156:95d6b41a828b 256 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
<> 156:95d6b41a828b 257 {
<> 156:95d6b41a828b 258 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 259 uint32_t pllfreq = 0U;
<> 156:95d6b41a828b 260
<> 156:95d6b41a828b 261 /* Check if one of the PLL is enabled */
<> 156:95d6b41a828b 262 if (UTILS_PLL_IsBusy() == SUCCESS)
<> 156:95d6b41a828b 263 {
<> 156:95d6b41a828b 264 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<> 156:95d6b41a828b 265 /* Check PREDIV value */
<> 156:95d6b41a828b 266 assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
<> 156:95d6b41a828b 267 #else
<> 156:95d6b41a828b 268 /* Force PREDIV value to 2 */
<> 156:95d6b41a828b 269 UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
<> 156:95d6b41a828b 270 #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
<> 156:95d6b41a828b 271 /* Calculate the new PLL output frequency */
<> 156:95d6b41a828b 272 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
<> 156:95d6b41a828b 273
<> 156:95d6b41a828b 274 /* Enable HSI if not enabled */
<> 156:95d6b41a828b 275 if (LL_RCC_HSI_IsReady() != 1U)
<> 156:95d6b41a828b 276 {
<> 156:95d6b41a828b 277 LL_RCC_HSI_Enable();
<> 156:95d6b41a828b 278 while (LL_RCC_HSI_IsReady() != 1U)
<> 156:95d6b41a828b 279 {
<> 156:95d6b41a828b 280 /* Wait for HSI ready */
<> 156:95d6b41a828b 281 }
<> 156:95d6b41a828b 282 }
<> 156:95d6b41a828b 283
<> 156:95d6b41a828b 284 /* Configure PLL */
<> 156:95d6b41a828b 285 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<> 156:95d6b41a828b 286 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
<> 156:95d6b41a828b 287 #else
<> 156:95d6b41a828b 288 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
<> 156:95d6b41a828b 289 #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
<> 156:95d6b41a828b 290
<> 156:95d6b41a828b 291 /* Enable PLL and switch system clock to PLL */
<> 156:95d6b41a828b 292 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
<> 156:95d6b41a828b 293 }
<> 156:95d6b41a828b 294 else
<> 156:95d6b41a828b 295 {
<> 156:95d6b41a828b 296 /* Current PLL configuration cannot be modified */
<> 156:95d6b41a828b 297 status = ERROR;
<> 156:95d6b41a828b 298 }
<> 156:95d6b41a828b 299
<> 156:95d6b41a828b 300 return status;
<> 156:95d6b41a828b 301 }
<> 156:95d6b41a828b 302
<> 156:95d6b41a828b 303 #if defined(RCC_CFGR_SW_HSI48)
<> 156:95d6b41a828b 304 /**
<> 156:95d6b41a828b 305 * @brief This function configures system clock with HSI48 as clock source of the PLL
<> 156:95d6b41a828b 306 * @note The application need to ensure that PLL is disabled.
<> 156:95d6b41a828b 307 * @note Function is based on the following formula:
<> 156:95d6b41a828b 308 * - PLL output frequency = ((HSI48 frequency / PREDIV) * PLLMUL)
<> 156:95d6b41a828b 309 * - PLLMUL: The application software must set correctly the PLL multiplication factor to
<> 156:95d6b41a828b 310 * be in the range 16-48MHz
<> 156:95d6b41a828b 311 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<> 156:95d6b41a828b 312 * the configuration information for the PLL.
<> 156:95d6b41a828b 313 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<> 156:95d6b41a828b 314 * the configuration information for the BUS prescalers.
<> 156:95d6b41a828b 315 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 316 * - SUCCESS: Max frequency configuration done
<> 156:95d6b41a828b 317 * - ERROR: Max frequency configuration not done
<> 156:95d6b41a828b 318 */
<> 156:95d6b41a828b 319 ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
<> 156:95d6b41a828b 320 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
<> 156:95d6b41a828b 321 {
<> 156:95d6b41a828b 322 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 323 uint32_t pllfreq = 0U;
<> 156:95d6b41a828b 324
<> 156:95d6b41a828b 325 /* Check if one of the PLL is enabled */
<> 156:95d6b41a828b 326 if (UTILS_PLL_IsBusy() == SUCCESS)
<> 156:95d6b41a828b 327 {
<> 156:95d6b41a828b 328 /* Check PREDIV value */
<> 156:95d6b41a828b 329 assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
<> 156:95d6b41a828b 330
<> 156:95d6b41a828b 331 /* Calculate the new PLL output frequency */
<> 156:95d6b41a828b 332 pllfreq = UTILS_GetPLLOutputFrequency(HSI48_VALUE, UTILS_PLLInitStruct);
<> 156:95d6b41a828b 333
<> 156:95d6b41a828b 334 /* Enable HSI48 if not enabled */
<> 156:95d6b41a828b 335 if (LL_RCC_HSI48_IsReady() != 1U)
<> 156:95d6b41a828b 336 {
<> 156:95d6b41a828b 337 LL_RCC_HSI48_Enable();
<> 156:95d6b41a828b 338 while (LL_RCC_HSI48_IsReady() != 1U)
<> 156:95d6b41a828b 339 {
<> 156:95d6b41a828b 340 /* Wait for HSI48 ready */
<> 156:95d6b41a828b 341 }
<> 156:95d6b41a828b 342 }
<> 156:95d6b41a828b 343
<> 156:95d6b41a828b 344 /* Configure PLL */
<> 156:95d6b41a828b 345 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI48, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
<> 156:95d6b41a828b 346
<> 156:95d6b41a828b 347 /* Enable PLL and switch system clock to PLL */
<> 156:95d6b41a828b 348 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
<> 156:95d6b41a828b 349 }
<> 156:95d6b41a828b 350 else
<> 156:95d6b41a828b 351 {
<> 156:95d6b41a828b 352 /* Current PLL configuration cannot be modified */
<> 156:95d6b41a828b 353 status = ERROR;
<> 156:95d6b41a828b 354 }
<> 156:95d6b41a828b 355
<> 156:95d6b41a828b 356 return status;
<> 156:95d6b41a828b 357 }
<> 156:95d6b41a828b 358
<> 156:95d6b41a828b 359 #endif /*RCC_CFGR_SW_HSI48*/
<> 156:95d6b41a828b 360 /**
<> 156:95d6b41a828b 361 * @brief This function configures system clock with HSE as clock source of the PLL
<> 156:95d6b41a828b 362 * @note The application need to ensure that PLL is disabled.
<> 156:95d6b41a828b 363 * @note Function is based on the following formula:
<> 156:95d6b41a828b 364 * - PLL output frequency = ((HSE frequency / PREDIV) * PLLMUL)
<> 156:95d6b41a828b 365 * - PLLMUL: The application software must set correctly the PLL multiplication factor to
<> 156:95d6b41a828b 366 * be in the range 16-48MHz
<> 156:95d6b41a828b 367 * @note FLASH latency can be modified through this function.
<> 156:95d6b41a828b 368 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 32000000
<> 156:95d6b41a828b 369 * @param HSEBypass This parameter can be one of the following values:
<> 156:95d6b41a828b 370 * @arg @ref LL_UTILS_HSEBYPASS_ON
<> 156:95d6b41a828b 371 * @arg @ref LL_UTILS_HSEBYPASS_OFF
<> 156:95d6b41a828b 372 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<> 156:95d6b41a828b 373 * the configuration information for the PLL.
<> 156:95d6b41a828b 374 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<> 156:95d6b41a828b 375 * the configuration information for the BUS prescalers.
<> 156:95d6b41a828b 376 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 377 * - SUCCESS: Max frequency configuration done
<> 156:95d6b41a828b 378 * - ERROR: Max frequency configuration not done
<> 156:95d6b41a828b 379 */
<> 156:95d6b41a828b 380 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
<> 156:95d6b41a828b 381 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
<> 156:95d6b41a828b 382 {
<> 156:95d6b41a828b 383 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 384 uint32_t pllfreq = 0U;
<> 156:95d6b41a828b 385
<> 156:95d6b41a828b 386 /* Check the parameters */
<> 156:95d6b41a828b 387 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
<> 156:95d6b41a828b 388 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
<> 156:95d6b41a828b 389
<> 156:95d6b41a828b 390 /* Check if one of the PLL is enabled */
<> 156:95d6b41a828b 391 if (UTILS_PLL_IsBusy() == SUCCESS)
<> 156:95d6b41a828b 392 {
<> 156:95d6b41a828b 393 /* Check PREDIV value */
<> 156:95d6b41a828b 394 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<> 156:95d6b41a828b 395 assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
<> 156:95d6b41a828b 396 #else
<> 156:95d6b41a828b 397 assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
<> 156:95d6b41a828b 398 #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
<> 156:95d6b41a828b 399
<> 156:95d6b41a828b 400 /* Calculate the new PLL output frequency */
<> 156:95d6b41a828b 401 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
<> 156:95d6b41a828b 402
<> 156:95d6b41a828b 403 /* Enable HSE if not enabled */
<> 156:95d6b41a828b 404 if (LL_RCC_HSE_IsReady() != 1U)
<> 156:95d6b41a828b 405 {
<> 156:95d6b41a828b 406 /* Check if need to enable HSE bypass feature or not */
<> 156:95d6b41a828b 407 if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
<> 156:95d6b41a828b 408 {
<> 156:95d6b41a828b 409 LL_RCC_HSE_EnableBypass();
<> 156:95d6b41a828b 410 }
<> 156:95d6b41a828b 411 else
<> 156:95d6b41a828b 412 {
<> 156:95d6b41a828b 413 LL_RCC_HSE_DisableBypass();
<> 156:95d6b41a828b 414 }
<> 156:95d6b41a828b 415
<> 156:95d6b41a828b 416 /* Enable HSE */
<> 156:95d6b41a828b 417 LL_RCC_HSE_Enable();
<> 156:95d6b41a828b 418 while (LL_RCC_HSE_IsReady() != 1U)
<> 156:95d6b41a828b 419 {
<> 156:95d6b41a828b 420 /* Wait for HSE ready */
<> 156:95d6b41a828b 421 }
<> 156:95d6b41a828b 422 }
<> 156:95d6b41a828b 423
<> 156:95d6b41a828b 424 /* Configure PLL */
<> 156:95d6b41a828b 425 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<> 156:95d6b41a828b 426 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
<> 156:95d6b41a828b 427 #else
Anna Bridge 180:96ed750bd169 428 LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
<> 156:95d6b41a828b 429 #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
<> 156:95d6b41a828b 430
<> 156:95d6b41a828b 431 /* Enable PLL and switch system clock to PLL */
<> 156:95d6b41a828b 432 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
<> 156:95d6b41a828b 433 }
<> 156:95d6b41a828b 434 else
<> 156:95d6b41a828b 435 {
<> 156:95d6b41a828b 436 /* Current PLL configuration cannot be modified */
<> 156:95d6b41a828b 437 status = ERROR;
<> 156:95d6b41a828b 438 }
<> 156:95d6b41a828b 439
<> 156:95d6b41a828b 440 return status;
<> 156:95d6b41a828b 441 }
<> 156:95d6b41a828b 442
<> 156:95d6b41a828b 443 /**
<> 156:95d6b41a828b 444 * @}
<> 156:95d6b41a828b 445 */
<> 156:95d6b41a828b 446
<> 156:95d6b41a828b 447 /**
<> 156:95d6b41a828b 448 * @}
<> 156:95d6b41a828b 449 */
<> 156:95d6b41a828b 450
<> 156:95d6b41a828b 451 /** @addtogroup UTILS_LL_Private_Functions
<> 156:95d6b41a828b 452 * @{
<> 156:95d6b41a828b 453 */
<> 156:95d6b41a828b 454 /**
<> 156:95d6b41a828b 455 * @brief Update number of Flash wait states in line with new frequency and current
<> 156:95d6b41a828b 456 voltage range.
<> 156:95d6b41a828b 457 * @param Frequency SYSCLK frequency
<> 156:95d6b41a828b 458 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 459 * - SUCCESS: Latency has been modified
<> 156:95d6b41a828b 460 * - ERROR: Latency cannot be modified
<> 156:95d6b41a828b 461 */
Anna Bridge 180:96ed750bd169 462 #if defined(FLASH_ACR_LATENCY)
<> 156:95d6b41a828b 463 static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
<> 156:95d6b41a828b 464 {
<> 156:95d6b41a828b 465 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 466
<> 156:95d6b41a828b 467 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
<> 156:95d6b41a828b 468
<> 156:95d6b41a828b 469 /* Frequency cannot be equal to 0 */
<> 156:95d6b41a828b 470 if (Frequency == 0U)
<> 156:95d6b41a828b 471 {
<> 156:95d6b41a828b 472 status = ERROR;
<> 156:95d6b41a828b 473 }
<> 156:95d6b41a828b 474 else
<> 156:95d6b41a828b 475 {
<> 156:95d6b41a828b 476 if (Frequency > UTILS_LATENCY1_FREQ)
<> 156:95d6b41a828b 477 {
<> 156:95d6b41a828b 478 /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
<> 156:95d6b41a828b 479 latency = LL_FLASH_LATENCY_1;
<> 156:95d6b41a828b 480 }
<> 156:95d6b41a828b 481 /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
<> 156:95d6b41a828b 482
<> 156:95d6b41a828b 483 LL_FLASH_SetLatency(latency);
<> 156:95d6b41a828b 484
<> 156:95d6b41a828b 485 /* Check that the new number of wait states is taken into account to access the Flash
<> 156:95d6b41a828b 486 memory by reading the FLASH_ACR register */
<> 156:95d6b41a828b 487 if (LL_FLASH_GetLatency() != latency)
<> 156:95d6b41a828b 488 {
<> 156:95d6b41a828b 489 status = ERROR;
<> 156:95d6b41a828b 490 }
<> 156:95d6b41a828b 491 }
<> 156:95d6b41a828b 492 return status;
<> 156:95d6b41a828b 493 }
Anna Bridge 180:96ed750bd169 494 #endif /* FLASH_ACR_LATENCY */
<> 156:95d6b41a828b 495
<> 156:95d6b41a828b 496 /**
<> 156:95d6b41a828b 497 * @brief Function to check that PLL can be modified
<> 156:95d6b41a828b 498 * @param PLL_InputFrequency PLL input frequency (in Hz)
<> 156:95d6b41a828b 499 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<> 156:95d6b41a828b 500 * the configuration information for the PLL.
<> 156:95d6b41a828b 501 * @retval PLL output frequency (in Hz)
<> 156:95d6b41a828b 502 */
<> 156:95d6b41a828b 503 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
<> 156:95d6b41a828b 504 {
<> 156:95d6b41a828b 505 uint32_t pllfreq = 0U;
<> 156:95d6b41a828b 506
<> 156:95d6b41a828b 507 /* Check the parameters */
<> 156:95d6b41a828b 508 assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
<> 156:95d6b41a828b 509
<> 156:95d6b41a828b 510 /* Check different PLL parameters according to RM */
<> 156:95d6b41a828b 511 /* The application software must set correctly the PLL multiplication factor to
<> 156:95d6b41a828b 512 be in the range 16-48MHz */
<> 156:95d6b41a828b 513 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<> 156:95d6b41a828b 514 pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
<> 156:95d6b41a828b 515 #else
<> 156:95d6b41a828b 516 pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
<> 156:95d6b41a828b 517 #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
<> 156:95d6b41a828b 518 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
<> 156:95d6b41a828b 519
<> 156:95d6b41a828b 520 return pllfreq;
<> 156:95d6b41a828b 521 }
<> 156:95d6b41a828b 522
<> 156:95d6b41a828b 523 /**
<> 156:95d6b41a828b 524 * @brief Function to check that PLL can be modified
<> 156:95d6b41a828b 525 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 526 * - SUCCESS: PLL modification can be done
<> 156:95d6b41a828b 527 * - ERROR: PLL is busy
<> 156:95d6b41a828b 528 */
<> 156:95d6b41a828b 529 static ErrorStatus UTILS_PLL_IsBusy(void)
<> 156:95d6b41a828b 530 {
<> 156:95d6b41a828b 531 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 532
<> 156:95d6b41a828b 533 /* Check if PLL is busy*/
<> 156:95d6b41a828b 534 if (LL_RCC_PLL_IsReady() != 0U)
<> 156:95d6b41a828b 535 {
<> 156:95d6b41a828b 536 /* PLL configuration cannot be modified */
<> 156:95d6b41a828b 537 status = ERROR;
<> 156:95d6b41a828b 538 }
<> 156:95d6b41a828b 539
<> 156:95d6b41a828b 540 return status;
<> 156:95d6b41a828b 541 }
<> 156:95d6b41a828b 542
<> 156:95d6b41a828b 543 /**
<> 156:95d6b41a828b 544 * @brief Function to enable PLL and switch system clock to PLL
<> 156:95d6b41a828b 545 * @param SYSCLK_Frequency SYSCLK frequency
<> 156:95d6b41a828b 546 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<> 156:95d6b41a828b 547 * the configuration information for the BUS prescalers.
<> 156:95d6b41a828b 548 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 549 * - SUCCESS: No problem to switch system to PLL
<> 156:95d6b41a828b 550 * - ERROR: Problem to switch system to PLL
<> 156:95d6b41a828b 551 */
<> 156:95d6b41a828b 552 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
<> 156:95d6b41a828b 553 {
<> 156:95d6b41a828b 554 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 555 uint32_t sysclk_frequency_current = 0U;
<> 156:95d6b41a828b 556
<> 156:95d6b41a828b 557 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
<> 156:95d6b41a828b 558 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
<> 156:95d6b41a828b 559
<> 156:95d6b41a828b 560 /* Calculate current SYSCLK frequency */
Anna Bridge 180:96ed750bd169 561 sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]);
<> 156:95d6b41a828b 562
<> 156:95d6b41a828b 563 /* Increasing the number of wait states because of higher CPU frequency */
<> 156:95d6b41a828b 564 if (sysclk_frequency_current < SYSCLK_Frequency)
<> 156:95d6b41a828b 565 {
<> 156:95d6b41a828b 566 /* Set FLASH latency to highest latency */
<> 156:95d6b41a828b 567 status = UTILS_SetFlashLatency(SYSCLK_Frequency);
<> 156:95d6b41a828b 568 }
<> 156:95d6b41a828b 569
<> 156:95d6b41a828b 570 /* Update system clock configuration */
<> 156:95d6b41a828b 571 if (status == SUCCESS)
<> 156:95d6b41a828b 572 {
<> 156:95d6b41a828b 573 /* Enable PLL */
<> 156:95d6b41a828b 574 LL_RCC_PLL_Enable();
<> 156:95d6b41a828b 575 while (LL_RCC_PLL_IsReady() != 1U)
<> 156:95d6b41a828b 576 {
<> 156:95d6b41a828b 577 /* Wait for PLL ready */
<> 156:95d6b41a828b 578 }
<> 156:95d6b41a828b 579
<> 156:95d6b41a828b 580 /* Sysclk activation on the main PLL */
<> 156:95d6b41a828b 581 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
<> 156:95d6b41a828b 582 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
<> 156:95d6b41a828b 583 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
<> 156:95d6b41a828b 584 {
<> 156:95d6b41a828b 585 /* Wait for system clock switch to PLL */
<> 156:95d6b41a828b 586 }
<> 156:95d6b41a828b 587
<> 156:95d6b41a828b 588 /* Set APB1 & APB2 prescaler*/
<> 156:95d6b41a828b 589 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
<> 156:95d6b41a828b 590 }
<> 156:95d6b41a828b 591
<> 156:95d6b41a828b 592 /* Decreasing the number of wait states because of lower CPU frequency */
<> 156:95d6b41a828b 593 if (sysclk_frequency_current > SYSCLK_Frequency)
<> 156:95d6b41a828b 594 {
<> 156:95d6b41a828b 595 /* Set FLASH latency to lowest latency */
<> 156:95d6b41a828b 596 status = UTILS_SetFlashLatency(SYSCLK_Frequency);
<> 156:95d6b41a828b 597 }
<> 156:95d6b41a828b 598
<> 156:95d6b41a828b 599 /* Update SystemCoreClock variable */
<> 156:95d6b41a828b 600 if (status == SUCCESS)
<> 156:95d6b41a828b 601 {
<> 156:95d6b41a828b 602 LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
<> 156:95d6b41a828b 603 }
<> 156:95d6b41a828b 604
<> 156:95d6b41a828b 605 return status;
<> 156:95d6b41a828b 606 }
<> 156:95d6b41a828b 607
<> 156:95d6b41a828b 608 /**
<> 156:95d6b41a828b 609 * @}
<> 156:95d6b41a828b 610 */
<> 156:95d6b41a828b 611
<> 156:95d6b41a828b 612 /**
<> 156:95d6b41a828b 613 * @}
<> 156:95d6b41a828b 614 */
<> 156:95d6b41a828b 615
<> 156:95d6b41a828b 616 /**
<> 156:95d6b41a828b 617 * @}
<> 156:95d6b41a828b 618 */
<> 156:95d6b41a828b 619
<> 156:95d6b41a828b 620 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/