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lwip-eth/arch/TARGET_STM/stm32f4_emac.c@0:d7bd7384a37c, 2016-12-07 (annotated)

Committer:
grzemich
Date:
Wed Dec 07 23:47:50 2016 +0000
Revision:
0:d7bd7384a37c
dgd

Who changed what in which revision?

UserRevisionLine numberNew contents of line
grzemich 0:d7bd7384a37c 1
grzemich 0:d7bd7384a37c 2 #include "stm32f4xx_hal.h"
grzemich 0:d7bd7384a37c 3 #include "lwip/opt.h"
grzemich 0:d7bd7384a37c 4
grzemich 0:d7bd7384a37c 5 #include "lwip/timers.h"
grzemich 0:d7bd7384a37c 6 #include "netif/etharp.h"
grzemich 0:d7bd7384a37c 7 #include "lwip/tcpip.h"
grzemich 0:d7bd7384a37c 8 #include <string.h>
grzemich 0:d7bd7384a37c 9 #include "cmsis_os.h"
grzemich 0:d7bd7384a37c 10 #include "mbed_interface.h"
grzemich 0:d7bd7384a37c 11
grzemich 0:d7bd7384a37c 12 /** @defgroup lwipstm32f4xx_emac_DRIVER stm32f4 EMAC driver for LWIP
grzemich 0:d7bd7384a37c 13 * @ingroup lwip_emac
grzemich 0:d7bd7384a37c 14 *
grzemich 0:d7bd7384a37c 15 * @{
grzemich 0:d7bd7384a37c 16 */
grzemich 0:d7bd7384a37c 17
grzemich 0:d7bd7384a37c 18 #define RECV_TASK_PRI (osPriorityHigh)
grzemich 0:d7bd7384a37c 19 #define PHY_TASK_PRI (osPriorityLow)
grzemich 0:d7bd7384a37c 20 #define PHY_TASK_WAIT (200)
grzemich 0:d7bd7384a37c 21
grzemich 0:d7bd7384a37c 22
grzemich 0:d7bd7384a37c 23 #if defined (__ICCARM__) /*!< IAR Compiler */
grzemich 0:d7bd7384a37c 24 #pragma data_alignment=4
grzemich 0:d7bd7384a37c 25 #endif
grzemich 0:d7bd7384a37c 26 __ALIGN_BEGIN ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB] __ALIGN_END; /* Ethernet Rx MA Descriptor */
grzemich 0:d7bd7384a37c 27
grzemich 0:d7bd7384a37c 28 #if defined (__ICCARM__) /*!< IAR Compiler */
grzemich 0:d7bd7384a37c 29 #pragma data_alignment=4
grzemich 0:d7bd7384a37c 30 #endif
grzemich 0:d7bd7384a37c 31 __ALIGN_BEGIN ETH_DMADescTypeDef DMATxDscrTab[ETH_TXBUFNB] __ALIGN_END; /* Ethernet Tx DMA Descriptor */
grzemich 0:d7bd7384a37c 32
grzemich 0:d7bd7384a37c 33 #if defined (__ICCARM__) /*!< IAR Compiler */
grzemich 0:d7bd7384a37c 34 #pragma data_alignment=4
grzemich 0:d7bd7384a37c 35 #endif
grzemich 0:d7bd7384a37c 36 __ALIGN_BEGIN uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __ALIGN_END; /* Ethernet Receive Buffer */
grzemich 0:d7bd7384a37c 37
grzemich 0:d7bd7384a37c 38 #if defined (__ICCARM__) /*!< IAR Compiler */
grzemich 0:d7bd7384a37c 39 #pragma data_alignment=4
grzemich 0:d7bd7384a37c 40 #endif
grzemich 0:d7bd7384a37c 41 __ALIGN_BEGIN uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __ALIGN_END; /* Ethernet Transmit Buffer */
grzemich 0:d7bd7384a37c 42
grzemich 0:d7bd7384a37c 43
grzemich 0:d7bd7384a37c 44 ETH_HandleTypeDef heth;
grzemich 0:d7bd7384a37c 45
grzemich 0:d7bd7384a37c 46 static sys_sem_t rx_ready_sem; /* receive ready semaphore */
grzemich 0:d7bd7384a37c 47 static sys_mutex_t tx_lock_mutex;
grzemich 0:d7bd7384a37c 48
grzemich 0:d7bd7384a37c 49 /* function */
grzemich 0:d7bd7384a37c 50 static void stm32f4_rx_task(void *arg);
grzemich 0:d7bd7384a37c 51 static void stm32f4_phy_task(void *arg);
grzemich 0:d7bd7384a37c 52 static err_t stm32f4_etharp_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr);
grzemich 0:d7bd7384a37c 53 static err_t stm32f4_low_level_output(struct netif *netif, struct pbuf *p);
grzemich 0:d7bd7384a37c 54
grzemich 0:d7bd7384a37c 55 /**
grzemich 0:d7bd7384a37c 56 * Override HAL Eth Init function
grzemich 0:d7bd7384a37c 57 */
grzemich 0:d7bd7384a37c 58 void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
grzemich 0:d7bd7384a37c 59 {
grzemich 0:d7bd7384a37c 60 GPIO_InitTypeDef GPIO_InitStruct;
grzemich 0:d7bd7384a37c 61 if (heth->Instance == ETH) {
grzemich 0:d7bd7384a37c 62 /* Peripheral clock enable */
grzemich 0:d7bd7384a37c 63 __ETH_CLK_ENABLE();
grzemich 0:d7bd7384a37c 64
grzemich 0:d7bd7384a37c 65 __GPIOA_CLK_ENABLE();
grzemich 0:d7bd7384a37c 66 __GPIOB_CLK_ENABLE();
grzemich 0:d7bd7384a37c 67 __GPIOC_CLK_ENABLE();
grzemich 0:d7bd7384a37c 68
grzemich 0:d7bd7384a37c 69 /**ETH GPIO Configuration
grzemich 0:d7bd7384a37c 70 PC1 ------> ETH_MDC
grzemich 0:d7bd7384a37c 71 PA1 ------> ETH_REF_CLK
grzemich 0:d7bd7384a37c 72 PA2 ------> ETH_MDIO
grzemich 0:d7bd7384a37c 73 PA7 ------> ETH_CRS_DV
grzemich 0:d7bd7384a37c 74 PC4 ------> ETH_RXD0
grzemich 0:d7bd7384a37c 75 PC5 ------> ETH_RXD1
grzemich 0:d7bd7384a37c 76 PB11 ------> ETH_TX_EN
grzemich 0:d7bd7384a37c 77 PB12 ------> ETH_TXD0
grzemich 0:d7bd7384a37c 78 PB13 ------> ETH_TXD1
grzemich 0:d7bd7384a37c 79 */
grzemich 0:d7bd7384a37c 80 GPIO_InitStruct.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
grzemich 0:d7bd7384a37c 81 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
grzemich 0:d7bd7384a37c 82 GPIO_InitStruct.Pull = GPIO_NOPULL;
grzemich 0:d7bd7384a37c 83 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
grzemich 0:d7bd7384a37c 84 GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
grzemich 0:d7bd7384a37c 85 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
grzemich 0:d7bd7384a37c 86
grzemich 0:d7bd7384a37c 87 GPIO_InitStruct.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
grzemich 0:d7bd7384a37c 88 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
grzemich 0:d7bd7384a37c 89 GPIO_InitStruct.Pull = GPIO_NOPULL;
grzemich 0:d7bd7384a37c 90 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
grzemich 0:d7bd7384a37c 91 GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
grzemich 0:d7bd7384a37c 92 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
grzemich 0:d7bd7384a37c 93
grzemich 0:d7bd7384a37c 94 GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;
grzemich 0:d7bd7384a37c 95 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
grzemich 0:d7bd7384a37c 96 GPIO_InitStruct.Pull = GPIO_NOPULL;
grzemich 0:d7bd7384a37c 97 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
grzemich 0:d7bd7384a37c 98 GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
grzemich 0:d7bd7384a37c 99 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
grzemich 0:d7bd7384a37c 100
grzemich 0:d7bd7384a37c 101 /* Peripheral interrupt init*/
grzemich 0:d7bd7384a37c 102 /* Sets the priority grouping field */
grzemich 0:d7bd7384a37c 103 HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
grzemich 0:d7bd7384a37c 104 HAL_NVIC_SetPriority(ETH_IRQn, 0, 0);
grzemich 0:d7bd7384a37c 105 HAL_NVIC_EnableIRQ(ETH_IRQn);
grzemich 0:d7bd7384a37c 106 }
grzemich 0:d7bd7384a37c 107 }
grzemich 0:d7bd7384a37c 108
grzemich 0:d7bd7384a37c 109 /**
grzemich 0:d7bd7384a37c 110 * Override HAL Eth DeInit function
grzemich 0:d7bd7384a37c 111 */
grzemich 0:d7bd7384a37c 112 void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
grzemich 0:d7bd7384a37c 113 {
grzemich 0:d7bd7384a37c 114 if (heth->Instance == ETH) {
grzemich 0:d7bd7384a37c 115 /* Peripheral clock disable */
grzemich 0:d7bd7384a37c 116 __ETH_CLK_DISABLE();
grzemich 0:d7bd7384a37c 117
grzemich 0:d7bd7384a37c 118 /**ETH GPIO Configuration
grzemich 0:d7bd7384a37c 119 PC1 ------> ETH_MDC
grzemich 0:d7bd7384a37c 120 PA1 ------> ETH_REF_CLK
grzemich 0:d7bd7384a37c 121 PA2 ------> ETH_MDIO
grzemich 0:d7bd7384a37c 122 PA7 ------> ETH_CRS_DV
grzemich 0:d7bd7384a37c 123 PC4 ------> ETH_RXD0
grzemich 0:d7bd7384a37c 124 PC5 ------> ETH_RXD1
grzemich 0:d7bd7384a37c 125 PB11 ------> ETH_TX_EN
grzemich 0:d7bd7384a37c 126 PB12 ------> ETH_TXD0
grzemich 0:d7bd7384a37c 127 PB13 ------> ETH_TXD1
grzemich 0:d7bd7384a37c 128 */
grzemich 0:d7bd7384a37c 129 HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
grzemich 0:d7bd7384a37c 130
grzemich 0:d7bd7384a37c 131 HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
grzemich 0:d7bd7384a37c 132
grzemich 0:d7bd7384a37c 133 HAL_GPIO_DeInit(GPIOB, GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13);
grzemich 0:d7bd7384a37c 134
grzemich 0:d7bd7384a37c 135 /* Peripheral interrupt Deinit*/
grzemich 0:d7bd7384a37c 136 HAL_NVIC_DisableIRQ(ETH_IRQn);
grzemich 0:d7bd7384a37c 137 }
grzemich 0:d7bd7384a37c 138 }
grzemich 0:d7bd7384a37c 139
grzemich 0:d7bd7384a37c 140 /**
grzemich 0:d7bd7384a37c 141 * Ethernet Rx Transfer completed callback
grzemich 0:d7bd7384a37c 142 *
grzemich 0:d7bd7384a37c 143 * @param heth: ETH handle
grzemich 0:d7bd7384a37c 144 * @retval None
grzemich 0:d7bd7384a37c 145 */
grzemich 0:d7bd7384a37c 146 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
grzemich 0:d7bd7384a37c 147 {
grzemich 0:d7bd7384a37c 148
grzemich 0:d7bd7384a37c 149 sys_sem_signal(&rx_ready_sem);
grzemich 0:d7bd7384a37c 150 }
grzemich 0:d7bd7384a37c 151
grzemich 0:d7bd7384a37c 152
grzemich 0:d7bd7384a37c 153 /**
grzemich 0:d7bd7384a37c 154 * Ethernet IRQ Handler
grzemich 0:d7bd7384a37c 155 *
grzemich 0:d7bd7384a37c 156 * @param None
grzemich 0:d7bd7384a37c 157 * @retval None
grzemich 0:d7bd7384a37c 158 */
grzemich 0:d7bd7384a37c 159 void ETH_IRQHandler(void)
grzemich 0:d7bd7384a37c 160 {
grzemich 0:d7bd7384a37c 161 HAL_ETH_IRQHandler(&heth);
grzemich 0:d7bd7384a37c 162 }
grzemich 0:d7bd7384a37c 163
grzemich 0:d7bd7384a37c 164
grzemich 0:d7bd7384a37c 165
grzemich 0:d7bd7384a37c 166 /**
grzemich 0:d7bd7384a37c 167 * In this function, the hardware should be initialized.
grzemich 0:d7bd7384a37c 168 * Called from eth_arch_enetif_init().
grzemich 0:d7bd7384a37c 169 *
grzemich 0:d7bd7384a37c 170 * @param netif the already initialized lwip network interface structure
grzemich 0:d7bd7384a37c 171 * for this ethernetif
grzemich 0:d7bd7384a37c 172 */
grzemich 0:d7bd7384a37c 173 static void stm32f4_low_level_init(struct netif *netif)
grzemich 0:d7bd7384a37c 174 {
grzemich 0:d7bd7384a37c 175 uint32_t regvalue = 0;
grzemich 0:d7bd7384a37c 176 HAL_StatusTypeDef hal_eth_init_status;
grzemich 0:d7bd7384a37c 177
grzemich 0:d7bd7384a37c 178 /* Init ETH */
grzemich 0:d7bd7384a37c 179 uint8_t MACAddr[6];
grzemich 0:d7bd7384a37c 180 heth.Instance = ETH;
grzemich 0:d7bd7384a37c 181 heth.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
grzemich 0:d7bd7384a37c 182 heth.Init.Speed = ETH_SPEED_10M;
grzemich 0:d7bd7384a37c 183 heth.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
grzemich 0:d7bd7384a37c 184 heth.Init.PhyAddress = 1;
grzemich 0:d7bd7384a37c 185 #if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
grzemich 0:d7bd7384a37c 186 MACAddr[0] = MBED_MAC_ADDR_0;
grzemich 0:d7bd7384a37c 187 MACAddr[1] = MBED_MAC_ADDR_1;
grzemich 0:d7bd7384a37c 188 MACAddr[2] = MBED_MAC_ADDR_2;
grzemich 0:d7bd7384a37c 189 MACAddr[3] = MBED_MAC_ADDR_3;
grzemich 0:d7bd7384a37c 190 MACAddr[4] = MBED_MAC_ADDR_4;
grzemich 0:d7bd7384a37c 191 MACAddr[5] = MBED_MAC_ADDR_5;
grzemich 0:d7bd7384a37c 192 #else
grzemich 0:d7bd7384a37c 193 mbed_mac_address((char *)MACAddr);
grzemich 0:d7bd7384a37c 194 #endif
grzemich 0:d7bd7384a37c 195 heth.Init.MACAddr = &MACAddr[0];
grzemich 0:d7bd7384a37c 196 heth.Init.RxMode = ETH_RXINTERRUPT_MODE;
grzemich 0:d7bd7384a37c 197 heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
grzemich 0:d7bd7384a37c 198 heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
grzemich 0:d7bd7384a37c 199 hal_eth_init_status = HAL_ETH_Init(&heth);
grzemich 0:d7bd7384a37c 200
grzemich 0:d7bd7384a37c 201 if (hal_eth_init_status == HAL_OK) {
grzemich 0:d7bd7384a37c 202 /* Set netif link flag */
grzemich 0:d7bd7384a37c 203 netif->flags |= NETIF_FLAG_LINK_UP;
grzemich 0:d7bd7384a37c 204 }
grzemich 0:d7bd7384a37c 205
grzemich 0:d7bd7384a37c 206 /* Initialize Tx Descriptors list: Chain Mode */
grzemich 0:d7bd7384a37c 207 HAL_ETH_DMATxDescListInit(&heth, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
grzemich 0:d7bd7384a37c 208
grzemich 0:d7bd7384a37c 209 /* Initialize Rx Descriptors list: Chain Mode */
grzemich 0:d7bd7384a37c 210 HAL_ETH_DMARxDescListInit(&heth, DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
grzemich 0:d7bd7384a37c 211
grzemich 0:d7bd7384a37c 212 #if LWIP_ARP || LWIP_ETHERNET
grzemich 0:d7bd7384a37c 213 /* set MAC hardware address length */
grzemich 0:d7bd7384a37c 214 netif->hwaddr_len = ETHARP_HWADDR_LEN;
grzemich 0:d7bd7384a37c 215
grzemich 0:d7bd7384a37c 216 /* set MAC hardware address */
grzemich 0:d7bd7384a37c 217 netif->hwaddr[0] = heth.Init.MACAddr[0];
grzemich 0:d7bd7384a37c 218 netif->hwaddr[1] = heth.Init.MACAddr[1];
grzemich 0:d7bd7384a37c 219 netif->hwaddr[2] = heth.Init.MACAddr[2];
grzemich 0:d7bd7384a37c 220 netif->hwaddr[3] = heth.Init.MACAddr[3];
grzemich 0:d7bd7384a37c 221 netif->hwaddr[4] = heth.Init.MACAddr[4];
grzemich 0:d7bd7384a37c 222 netif->hwaddr[5] = heth.Init.MACAddr[5];
grzemich 0:d7bd7384a37c 223
grzemich 0:d7bd7384a37c 224 /* maximum transfer unit */
grzemich 0:d7bd7384a37c 225 netif->mtu = 1500;
grzemich 0:d7bd7384a37c 226
grzemich 0:d7bd7384a37c 227 /* device capabilities */
grzemich 0:d7bd7384a37c 228 /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
grzemich 0:d7bd7384a37c 229 netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
grzemich 0:d7bd7384a37c 230
grzemich 0:d7bd7384a37c 231 /* Enable MAC and DMA transmission and reception */
grzemich 0:d7bd7384a37c 232 HAL_ETH_Start(&heth);
grzemich 0:d7bd7384a37c 233
grzemich 0:d7bd7384a37c 234 /**** Configure PHY to generate an interrupt when Eth Link state changes ****/
grzemich 0:d7bd7384a37c 235 /* Read Register Configuration */
grzemich 0:d7bd7384a37c 236 HAL_ETH_ReadPHYRegister(&heth, PHY_MICR, &regvalue);
grzemich 0:d7bd7384a37c 237
grzemich 0:d7bd7384a37c 238 regvalue |= (PHY_MICR_INT_EN | PHY_MICR_INT_OE);
grzemich 0:d7bd7384a37c 239
grzemich 0:d7bd7384a37c 240 /* Enable Interrupts */
grzemich 0:d7bd7384a37c 241 HAL_ETH_WritePHYRegister(&heth, PHY_MICR, regvalue);
grzemich 0:d7bd7384a37c 242
grzemich 0:d7bd7384a37c 243 /* Read Register Configuration */
grzemich 0:d7bd7384a37c 244 HAL_ETH_ReadPHYRegister(&heth, PHY_MISR, &regvalue);
grzemich 0:d7bd7384a37c 245
grzemich 0:d7bd7384a37c 246 regvalue |= PHY_MISR_LINK_INT_EN;
grzemich 0:d7bd7384a37c 247
grzemich 0:d7bd7384a37c 248 /* Enable Interrupt on change of link status */
grzemich 0:d7bd7384a37c 249 HAL_ETH_WritePHYRegister(&heth, PHY_MISR, regvalue);
grzemich 0:d7bd7384a37c 250 #endif
grzemich 0:d7bd7384a37c 251 }
grzemich 0:d7bd7384a37c 252
grzemich 0:d7bd7384a37c 253 /**
grzemich 0:d7bd7384a37c 254 * This function should do the actual transmission of the packet. The packet is
grzemich 0:d7bd7384a37c 255 * contained in the pbuf that is passed to the function. This pbuf
grzemich 0:d7bd7384a37c 256 * might be chained.
grzemich 0:d7bd7384a37c 257 *
grzemich 0:d7bd7384a37c 258 * @param netif the lwip network interface structure for this ethernetif
grzemich 0:d7bd7384a37c 259 * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
grzemich 0:d7bd7384a37c 260 * @return ERR_OK if the packet could be sent
grzemich 0:d7bd7384a37c 261 * an err_t value if the packet couldn't be sent
grzemich 0:d7bd7384a37c 262 *
grzemich 0:d7bd7384a37c 263 * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
grzemich 0:d7bd7384a37c 264 * strange results. You might consider waiting for space in the DMA queue
grzemich 0:d7bd7384a37c 265 * to become availale since the stack doesn't retry to send a packet
grzemich 0:d7bd7384a37c 266 * dropped because of memory failure (except for the TCP timers).
grzemich 0:d7bd7384a37c 267 */
grzemich 0:d7bd7384a37c 268
grzemich 0:d7bd7384a37c 269 static err_t stm32f4_low_level_output(struct netif *netif, struct pbuf *p)
grzemich 0:d7bd7384a37c 270 {
grzemich 0:d7bd7384a37c 271 err_t errval;
grzemich 0:d7bd7384a37c 272 struct pbuf *q;
grzemich 0:d7bd7384a37c 273 uint8_t *buffer = (uint8_t*)(heth.TxDesc->Buffer1Addr);
grzemich 0:d7bd7384a37c 274 __IO ETH_DMADescTypeDef *DmaTxDesc;
grzemich 0:d7bd7384a37c 275 uint32_t framelength = 0;
grzemich 0:d7bd7384a37c 276 uint32_t bufferoffset = 0;
grzemich 0:d7bd7384a37c 277 uint32_t byteslefttocopy = 0;
grzemich 0:d7bd7384a37c 278 uint32_t payloadoffset = 0;
grzemich 0:d7bd7384a37c 279 DmaTxDesc = heth.TxDesc;
grzemich 0:d7bd7384a37c 280 bufferoffset = 0;
grzemich 0:d7bd7384a37c 281
grzemich 0:d7bd7384a37c 282
grzemich 0:d7bd7384a37c 283 sys_mutex_lock(&tx_lock_mutex);
grzemich 0:d7bd7384a37c 284
grzemich 0:d7bd7384a37c 285 /* copy frame from pbufs to driver buffers */
grzemich 0:d7bd7384a37c 286 for (q = p; q != NULL; q = q->next) {
grzemich 0:d7bd7384a37c 287 /* Is this buffer available? If not, goto error */
grzemich 0:d7bd7384a37c 288 if ((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET) {
grzemich 0:d7bd7384a37c 289 errval = ERR_USE;
grzemich 0:d7bd7384a37c 290 goto error;
grzemich 0:d7bd7384a37c 291 }
grzemich 0:d7bd7384a37c 292
grzemich 0:d7bd7384a37c 293 /* Get bytes in current lwIP buffer */
grzemich 0:d7bd7384a37c 294 byteslefttocopy = q->len;
grzemich 0:d7bd7384a37c 295 payloadoffset = 0;
grzemich 0:d7bd7384a37c 296
grzemich 0:d7bd7384a37c 297 /* Check if the length of data to copy is bigger than Tx buffer size*/
grzemich 0:d7bd7384a37c 298 while ((byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE) {
grzemich 0:d7bd7384a37c 299 /* Copy data to Tx buffer*/
grzemich 0:d7bd7384a37c 300 memcpy((uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset));
grzemich 0:d7bd7384a37c 301
grzemich 0:d7bd7384a37c 302 /* Point to next descriptor */
grzemich 0:d7bd7384a37c 303 DmaTxDesc = (ETH_DMADescTypeDef*)(DmaTxDesc->Buffer2NextDescAddr);
grzemich 0:d7bd7384a37c 304
grzemich 0:d7bd7384a37c 305 /* Check if the buffer is available */
grzemich 0:d7bd7384a37c 306 if ((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET) {
grzemich 0:d7bd7384a37c 307 errval = ERR_USE;
grzemich 0:d7bd7384a37c 308 goto error;
grzemich 0:d7bd7384a37c 309 }
grzemich 0:d7bd7384a37c 310
grzemich 0:d7bd7384a37c 311 buffer = (uint8_t*)(DmaTxDesc->Buffer1Addr);
grzemich 0:d7bd7384a37c 312
grzemich 0:d7bd7384a37c 313 byteslefttocopy = byteslefttocopy - (ETH_TX_BUF_SIZE - bufferoffset);
grzemich 0:d7bd7384a37c 314 payloadoffset = payloadoffset + (ETH_TX_BUF_SIZE - bufferoffset);
grzemich 0:d7bd7384a37c 315 framelength = framelength + (ETH_TX_BUF_SIZE - bufferoffset);
grzemich 0:d7bd7384a37c 316 bufferoffset = 0;
grzemich 0:d7bd7384a37c 317 }
grzemich 0:d7bd7384a37c 318
grzemich 0:d7bd7384a37c 319 /* Copy the remaining bytes */
grzemich 0:d7bd7384a37c 320 memcpy((uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), byteslefttocopy);
grzemich 0:d7bd7384a37c 321 bufferoffset = bufferoffset + byteslefttocopy;
grzemich 0:d7bd7384a37c 322 framelength = framelength + byteslefttocopy;
grzemich 0:d7bd7384a37c 323 }
grzemich 0:d7bd7384a37c 324
grzemich 0:d7bd7384a37c 325 /* Prepare transmit descriptors to give to DMA */
grzemich 0:d7bd7384a37c 326 HAL_ETH_TransmitFrame(&heth, framelength);
grzemich 0:d7bd7384a37c 327
grzemich 0:d7bd7384a37c 328 errval = ERR_OK;
grzemich 0:d7bd7384a37c 329
grzemich 0:d7bd7384a37c 330 error:
grzemich 0:d7bd7384a37c 331
grzemich 0:d7bd7384a37c 332 /* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */
grzemich 0:d7bd7384a37c 333 if ((heth.Instance->DMASR & ETH_DMASR_TUS) != (uint32_t)RESET) {
grzemich 0:d7bd7384a37c 334 /* Clear TUS ETHERNET DMA flag */
grzemich 0:d7bd7384a37c 335 heth.Instance->DMASR = ETH_DMASR_TUS;
grzemich 0:d7bd7384a37c 336
grzemich 0:d7bd7384a37c 337 /* Resume DMA transmission*/
grzemich 0:d7bd7384a37c 338 heth.Instance->DMATPDR = 0;
grzemich 0:d7bd7384a37c 339 }
grzemich 0:d7bd7384a37c 340
grzemich 0:d7bd7384a37c 341 sys_mutex_unlock(&tx_lock_mutex);
grzemich 0:d7bd7384a37c 342
grzemich 0:d7bd7384a37c 343 return errval;
grzemich 0:d7bd7384a37c 344 }
grzemich 0:d7bd7384a37c 345
grzemich 0:d7bd7384a37c 346
grzemich 0:d7bd7384a37c 347 /**
grzemich 0:d7bd7384a37c 348 * Should allocate a pbuf and transfer the bytes of the incoming
grzemich 0:d7bd7384a37c 349 * packet from the interface into the pbuf.
grzemich 0:d7bd7384a37c 350 *
grzemich 0:d7bd7384a37c 351 * @param netif the lwip network interface structure for this ethernetif
grzemich 0:d7bd7384a37c 352 * @return a pbuf filled with the received packet (including MAC header)
grzemich 0:d7bd7384a37c 353 * NULL on memory error
grzemich 0:d7bd7384a37c 354 */
grzemich 0:d7bd7384a37c 355 static struct pbuf * stm32f4_low_level_input(struct netif *netif)
grzemich 0:d7bd7384a37c 356 {
grzemich 0:d7bd7384a37c 357 struct pbuf *p = NULL;
grzemich 0:d7bd7384a37c 358 struct pbuf *q;
grzemich 0:d7bd7384a37c 359 uint16_t len = 0;
grzemich 0:d7bd7384a37c 360 uint8_t *buffer;
grzemich 0:d7bd7384a37c 361 __IO ETH_DMADescTypeDef *dmarxdesc;
grzemich 0:d7bd7384a37c 362 uint32_t bufferoffset = 0;
grzemich 0:d7bd7384a37c 363 uint32_t payloadoffset = 0;
grzemich 0:d7bd7384a37c 364 uint32_t byteslefttocopy = 0;
grzemich 0:d7bd7384a37c 365 uint32_t i = 0;
grzemich 0:d7bd7384a37c 366
grzemich 0:d7bd7384a37c 367
grzemich 0:d7bd7384a37c 368 /* get received frame */
grzemich 0:d7bd7384a37c 369 if (HAL_ETH_GetReceivedFrame(&heth) != HAL_OK)
grzemich 0:d7bd7384a37c 370 return NULL;
grzemich 0:d7bd7384a37c 371
grzemich 0:d7bd7384a37c 372 /* Obtain the size of the packet and put it into the "len" variable. */
grzemich 0:d7bd7384a37c 373 len = heth.RxFrameInfos.length;
grzemich 0:d7bd7384a37c 374 buffer = (uint8_t*)heth.RxFrameInfos.buffer;
grzemich 0:d7bd7384a37c 375
grzemich 0:d7bd7384a37c 376 if (len > 0) {
grzemich 0:d7bd7384a37c 377 /* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
grzemich 0:d7bd7384a37c 378 p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
grzemich 0:d7bd7384a37c 379 }
grzemich 0:d7bd7384a37c 380
grzemich 0:d7bd7384a37c 381 if (p != NULL) {
grzemich 0:d7bd7384a37c 382 dmarxdesc = heth.RxFrameInfos.FSRxDesc;
grzemich 0:d7bd7384a37c 383 bufferoffset = 0;
grzemich 0:d7bd7384a37c 384 for (q = p; q != NULL; q = q->next) {
grzemich 0:d7bd7384a37c 385 byteslefttocopy = q->len;
grzemich 0:d7bd7384a37c 386 payloadoffset = 0;
grzemich 0:d7bd7384a37c 387
grzemich 0:d7bd7384a37c 388 /* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
grzemich 0:d7bd7384a37c 389 while ((byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE) {
grzemich 0:d7bd7384a37c 390 /* Copy data to pbuf */
grzemich 0:d7bd7384a37c 391 memcpy((uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
grzemich 0:d7bd7384a37c 392
grzemich 0:d7bd7384a37c 393 /* Point to next descriptor */
grzemich 0:d7bd7384a37c 394 dmarxdesc = (ETH_DMADescTypeDef*)(dmarxdesc->Buffer2NextDescAddr);
grzemich 0:d7bd7384a37c 395 buffer = (uint8_t*)(dmarxdesc->Buffer1Addr);
grzemich 0:d7bd7384a37c 396
grzemich 0:d7bd7384a37c 397 byteslefttocopy = byteslefttocopy - (ETH_RX_BUF_SIZE - bufferoffset);
grzemich 0:d7bd7384a37c 398 payloadoffset = payloadoffset + (ETH_RX_BUF_SIZE - bufferoffset);
grzemich 0:d7bd7384a37c 399 bufferoffset = 0;
grzemich 0:d7bd7384a37c 400 }
grzemich 0:d7bd7384a37c 401 /* Copy remaining data in pbuf */
grzemich 0:d7bd7384a37c 402 memcpy((uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), byteslefttocopy);
grzemich 0:d7bd7384a37c 403 bufferoffset = bufferoffset + byteslefttocopy;
grzemich 0:d7bd7384a37c 404 }
grzemich 0:d7bd7384a37c 405
grzemich 0:d7bd7384a37c 406 /* Release descriptors to DMA */
grzemich 0:d7bd7384a37c 407 /* Point to first descriptor */
grzemich 0:d7bd7384a37c 408 dmarxdesc = heth.RxFrameInfos.FSRxDesc;
grzemich 0:d7bd7384a37c 409 /* Set Own bit in Rx descriptors: gives the buffers back to DMA */
grzemich 0:d7bd7384a37c 410 for (i = 0; i < heth.RxFrameInfos.SegCount; i++) {
grzemich 0:d7bd7384a37c 411 dmarxdesc->Status |= ETH_DMARXDESC_OWN;
grzemich 0:d7bd7384a37c 412 dmarxdesc = (ETH_DMADescTypeDef*)(dmarxdesc->Buffer2NextDescAddr);
grzemich 0:d7bd7384a37c 413 }
grzemich 0:d7bd7384a37c 414
grzemich 0:d7bd7384a37c 415 /* Clear Segment_Count */
grzemich 0:d7bd7384a37c 416 heth.RxFrameInfos.SegCount = 0;
grzemich 0:d7bd7384a37c 417 }
grzemich 0:d7bd7384a37c 418
grzemich 0:d7bd7384a37c 419 /* When Rx Buffer unavailable flag is set: clear it and resume reception */
grzemich 0:d7bd7384a37c 420 if ((heth.Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) {
grzemich 0:d7bd7384a37c 421 /* Clear RBUS ETHERNET DMA flag */
grzemich 0:d7bd7384a37c 422 heth.Instance->DMASR = ETH_DMASR_RBUS;
grzemich 0:d7bd7384a37c 423 /* Resume DMA reception */
grzemich 0:d7bd7384a37c 424 heth.Instance->DMARPDR = 0;
grzemich 0:d7bd7384a37c 425 }
grzemich 0:d7bd7384a37c 426 return p;
grzemich 0:d7bd7384a37c 427 }
grzemich 0:d7bd7384a37c 428
grzemich 0:d7bd7384a37c 429 /**
grzemich 0:d7bd7384a37c 430 * This task receives input data
grzemich 0:d7bd7384a37c 431 *
grzemich 0:d7bd7384a37c 432 * \param[in] netif the lwip network interface structure
grzemich 0:d7bd7384a37c 433 */
grzemich 0:d7bd7384a37c 434 static void stm32f4_rx_task(void *arg)
grzemich 0:d7bd7384a37c 435 {
grzemich 0:d7bd7384a37c 436 struct netif *netif = (struct netif*)arg;
grzemich 0:d7bd7384a37c 437 struct pbuf *p;
grzemich 0:d7bd7384a37c 438
grzemich 0:d7bd7384a37c 439 while (1) {
grzemich 0:d7bd7384a37c 440 sys_arch_sem_wait(&rx_ready_sem, 0);
grzemich 0:d7bd7384a37c 441 p = stm32f4_low_level_input(netif);
grzemich 0:d7bd7384a37c 442 if (p != NULL) {
grzemich 0:d7bd7384a37c 443 if (netif->input(p, netif) != ERR_OK) {
grzemich 0:d7bd7384a37c 444 pbuf_free(p);
grzemich 0:d7bd7384a37c 445 p = NULL;
grzemich 0:d7bd7384a37c 446 }
grzemich 0:d7bd7384a37c 447 }
grzemich 0:d7bd7384a37c 448 }
grzemich 0:d7bd7384a37c 449 }
grzemich 0:d7bd7384a37c 450
grzemich 0:d7bd7384a37c 451 /**
grzemich 0:d7bd7384a37c 452 * This task checks phy link status and updates net status
grzemich 0:d7bd7384a37c 453 *
grzemich 0:d7bd7384a37c 454 * \param[in] netif the lwip network interface structure
grzemich 0:d7bd7384a37c 455 */
grzemich 0:d7bd7384a37c 456 static void stm32f4_phy_task(void *arg)
grzemich 0:d7bd7384a37c 457 {
grzemich 0:d7bd7384a37c 458 struct netif *netif = (struct netif*)arg;
grzemich 0:d7bd7384a37c 459 uint32_t phy_status = 0;
grzemich 0:d7bd7384a37c 460
grzemich 0:d7bd7384a37c 461 while (1) {
grzemich 0:d7bd7384a37c 462 uint32_t status;
grzemich 0:d7bd7384a37c 463 if (HAL_ETH_ReadPHYRegister(&heth, PHY_SR, &status) == HAL_OK) {
grzemich 0:d7bd7384a37c 464 if ((status & PHY_LINK_STATUS) && !(phy_status & PHY_LINK_STATUS)) {
grzemich 0:d7bd7384a37c 465 tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_up, (void*) netif, 1);
grzemich 0:d7bd7384a37c 466 } else if (!(status & PHY_LINK_STATUS) && (phy_status & PHY_LINK_STATUS)) {
grzemich 0:d7bd7384a37c 467 tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_down, (void*) netif, 1);
grzemich 0:d7bd7384a37c 468 }
grzemich 0:d7bd7384a37c 469
grzemich 0:d7bd7384a37c 470 phy_status = status;
grzemich 0:d7bd7384a37c 471 }
grzemich 0:d7bd7384a37c 472
grzemich 0:d7bd7384a37c 473 osDelay(PHY_TASK_WAIT);
grzemich 0:d7bd7384a37c 474 }
grzemich 0:d7bd7384a37c 475 }
grzemich 0:d7bd7384a37c 476
grzemich 0:d7bd7384a37c 477 /**
grzemich 0:d7bd7384a37c 478 * This function is the ethernet packet send function. It calls
grzemich 0:d7bd7384a37c 479 * etharp_output after checking link status.
grzemich 0:d7bd7384a37c 480 *
grzemich 0:d7bd7384a37c 481 * \param[in] netif the lwip network interface structure for this lpc_enetif
grzemich 0:d7bd7384a37c 482 * \param[in] q Pointer to pbug to send
grzemich 0:d7bd7384a37c 483 * \param[in] ipaddr IP address
grzemich 0:d7bd7384a37c 484 * \return ERR_OK or error code
grzemich 0:d7bd7384a37c 485 */
grzemich 0:d7bd7384a37c 486 static err_t stm32f4_etharp_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr)
grzemich 0:d7bd7384a37c 487 {
grzemich 0:d7bd7384a37c 488 /* Only send packet is link is up */
grzemich 0:d7bd7384a37c 489 if (netif->flags & NETIF_FLAG_LINK_UP) {
grzemich 0:d7bd7384a37c 490 return etharp_output(netif, q, ipaddr);
grzemich 0:d7bd7384a37c 491 }
grzemich 0:d7bd7384a37c 492
grzemich 0:d7bd7384a37c 493 return ERR_CONN;
grzemich 0:d7bd7384a37c 494 }
grzemich 0:d7bd7384a37c 495
grzemich 0:d7bd7384a37c 496 /**
grzemich 0:d7bd7384a37c 497 * Should be called at the beginning of the program to set up the
grzemich 0:d7bd7384a37c 498 * network interface.
grzemich 0:d7bd7384a37c 499 *
grzemich 0:d7bd7384a37c 500 * This function should be passed as a parameter to netif_add().
grzemich 0:d7bd7384a37c 501 *
grzemich 0:d7bd7384a37c 502 * @param[in] netif the lwip network interface structure for this lpc_enetif
grzemich 0:d7bd7384a37c 503 * @return ERR_OK if the loopif is initialized
grzemich 0:d7bd7384a37c 504 * ERR_MEM if private data couldn't be allocated
grzemich 0:d7bd7384a37c 505 * any other err_t on error
grzemich 0:d7bd7384a37c 506 */
grzemich 0:d7bd7384a37c 507 err_t eth_arch_enetif_init(struct netif *netif)
grzemich 0:d7bd7384a37c 508 {
grzemich 0:d7bd7384a37c 509 /* set MAC hardware address */
grzemich 0:d7bd7384a37c 510 netif->hwaddr_len = ETHARP_HWADDR_LEN;
grzemich 0:d7bd7384a37c 511
grzemich 0:d7bd7384a37c 512 /* maximum transfer unit */
grzemich 0:d7bd7384a37c 513 netif->mtu = 1500;
grzemich 0:d7bd7384a37c 514
grzemich 0:d7bd7384a37c 515 /* device capabilities */
grzemich 0:d7bd7384a37c 516 netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET | NETIF_FLAG_IGMP;
grzemich 0:d7bd7384a37c 517
grzemich 0:d7bd7384a37c 518 #if LWIP_NETIF_HOSTNAME
grzemich 0:d7bd7384a37c 519 /* Initialize interface hostname */
grzemich 0:d7bd7384a37c 520 netif->hostname = "lwipstm32f4";
grzemich 0:d7bd7384a37c 521 #endif /* LWIP_NETIF_HOSTNAME */
grzemich 0:d7bd7384a37c 522
grzemich 0:d7bd7384a37c 523 netif->name[0] = 'e';
grzemich 0:d7bd7384a37c 524 netif->name[1] = 'n';
grzemich 0:d7bd7384a37c 525
grzemich 0:d7bd7384a37c 526 netif->output = stm32f4_etharp_output;
grzemich 0:d7bd7384a37c 527 netif->linkoutput = stm32f4_low_level_output;
grzemich 0:d7bd7384a37c 528
grzemich 0:d7bd7384a37c 529 /* semaphore */
grzemich 0:d7bd7384a37c 530 sys_sem_new(&rx_ready_sem, 0);
grzemich 0:d7bd7384a37c 531
grzemich 0:d7bd7384a37c 532 sys_mutex_new(&tx_lock_mutex);
grzemich 0:d7bd7384a37c 533
grzemich 0:d7bd7384a37c 534 /* task */
grzemich 0:d7bd7384a37c 535 sys_thread_new("stm32f4_recv_task", stm32f4_rx_task, netif, DEFAULT_THREAD_STACKSIZE, RECV_TASK_PRI);
grzemich 0:d7bd7384a37c 536 sys_thread_new("stm32f4_phy_task", stm32f4_phy_task, netif, DEFAULT_THREAD_STACKSIZE, PHY_TASK_PRI);
grzemich 0:d7bd7384a37c 537
grzemich 0:d7bd7384a37c 538 /* initialize the hardware */
grzemich 0:d7bd7384a37c 539 stm32f4_low_level_init(netif);
grzemich 0:d7bd7384a37c 540
grzemich 0:d7bd7384a37c 541 return ERR_OK;
grzemich 0:d7bd7384a37c 542 }
grzemich 0:d7bd7384a37c 543
grzemich 0:d7bd7384a37c 544 void eth_arch_enable_interrupts(void)
grzemich 0:d7bd7384a37c 545 {
grzemich 0:d7bd7384a37c 546 HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
grzemich 0:d7bd7384a37c 547 HAL_NVIC_SetPriority(ETH_IRQn, 0, 0);
grzemich 0:d7bd7384a37c 548 HAL_NVIC_EnableIRQ(ETH_IRQn);
grzemich 0:d7bd7384a37c 549 }
grzemich 0:d7bd7384a37c 550
grzemich 0:d7bd7384a37c 551 void eth_arch_disable_interrupts(void)
grzemich 0:d7bd7384a37c 552 {
grzemich 0:d7bd7384a37c 553 NVIC_DisableIRQ(ETH_IRQn);
grzemich 0:d7bd7384a37c 554 }
grzemich 0:d7bd7384a37c 555
grzemich 0:d7bd7384a37c 556 /**
grzemich 0:d7bd7384a37c 557 * @}
grzemich 0:d7bd7384a37c 558 */
grzemich 0:d7bd7384a37c 559
grzemich 0:d7bd7384a37c 560 /* --------------------------------- End Of File ------------------------------ */