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Dependencies:   STM32L4xx_HAL_Driver CMSIS_DSP_401

core_cmFunc.h@3:ec7e3c37fe80, 2015-11-26 (annotated)

Committer:
EricLew
Date:
Thu Nov 26 22:32:56 2015 +0000
Revision:
3:ec7e3c37fe80
Parent:
0:d4e5ad7ad71c 
FFT is currently not working and commented out

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:d4e5ad7ad71c 1 /**************************************************************************//**
EricLew 0:d4e5ad7ad71c 2 * @file core_cmFunc.h
EricLew 0:d4e5ad7ad71c 3 * @brief CMSIS Cortex-M Core Function Access Header File
EricLew 0:d4e5ad7ad71c 4 * @version V4.10
EricLew 0:d4e5ad7ad71c 5 * @date 18. March 2015
EricLew 0:d4e5ad7ad71c 6 *
EricLew 0:d4e5ad7ad71c 7 * @note
EricLew 0:d4e5ad7ad71c 8 *
EricLew 0:d4e5ad7ad71c 9 ******************************************************************************/
EricLew 0:d4e5ad7ad71c 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
EricLew 0:d4e5ad7ad71c 11
EricLew 0:d4e5ad7ad71c 12 All rights reserved.
EricLew 0:d4e5ad7ad71c 13 Redistribution and use in source and binary forms, with or without
EricLew 0:d4e5ad7ad71c 14 modification, are permitted provided that the following conditions are met:
EricLew 0:d4e5ad7ad71c 15 - Redistributions of source code must retain the above copyright
EricLew 0:d4e5ad7ad71c 16 notice, this list of conditions and the following disclaimer.
EricLew 0:d4e5ad7ad71c 17 - Redistributions in binary form must reproduce the above copyright
EricLew 0:d4e5ad7ad71c 18 notice, this list of conditions and the following disclaimer in the
EricLew 0:d4e5ad7ad71c 19 documentation and/or other materials provided with the distribution.
EricLew 0:d4e5ad7ad71c 20 - Neither the name of ARM nor the names of its contributors may be used
EricLew 0:d4e5ad7ad71c 21 to endorse or promote products derived from this software without
EricLew 0:d4e5ad7ad71c 22 specific prior written permission.
EricLew 0:d4e5ad7ad71c 23 *
EricLew 0:d4e5ad7ad71c 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:d4e5ad7ad71c 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:d4e5ad7ad71c 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
EricLew 0:d4e5ad7ad71c 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
EricLew 0:d4e5ad7ad71c 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
EricLew 0:d4e5ad7ad71c 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
EricLew 0:d4e5ad7ad71c 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
EricLew 0:d4e5ad7ad71c 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
EricLew 0:d4e5ad7ad71c 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
EricLew 0:d4e5ad7ad71c 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
EricLew 0:d4e5ad7ad71c 34 POSSIBILITY OF SUCH DAMAGE.
EricLew 0:d4e5ad7ad71c 35 ---------------------------------------------------------------------------*/
EricLew 0:d4e5ad7ad71c 36
EricLew 0:d4e5ad7ad71c 37
EricLew 0:d4e5ad7ad71c 38 #ifndef __CORE_CMFUNC_H
EricLew 0:d4e5ad7ad71c 39 #define __CORE_CMFUNC_H
EricLew 0:d4e5ad7ad71c 40
EricLew 0:d4e5ad7ad71c 41
EricLew 0:d4e5ad7ad71c 42 /* ########################### Core Function Access ########################### */
EricLew 0:d4e5ad7ad71c 43 /** \ingroup CMSIS_Core_FunctionInterface
EricLew 0:d4e5ad7ad71c 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
EricLew 0:d4e5ad7ad71c 45 @{
EricLew 0:d4e5ad7ad71c 46 */
EricLew 0:d4e5ad7ad71c 47
EricLew 0:d4e5ad7ad71c 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
EricLew 0:d4e5ad7ad71c 49 /* ARM armcc specific functions */
EricLew 0:d4e5ad7ad71c 50
EricLew 0:d4e5ad7ad71c 51 #if (__ARMCC_VERSION < 400677)
EricLew 0:d4e5ad7ad71c 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
EricLew 0:d4e5ad7ad71c 53 #endif
EricLew 0:d4e5ad7ad71c 54
EricLew 0:d4e5ad7ad71c 55 /* intrinsic void __enable_irq(); */
EricLew 0:d4e5ad7ad71c 56 /* intrinsic void __disable_irq(); */
EricLew 0:d4e5ad7ad71c 57
EricLew 0:d4e5ad7ad71c 58 /** \brief Get Control Register
EricLew 0:d4e5ad7ad71c 59
EricLew 0:d4e5ad7ad71c 60 This function returns the content of the Control Register.
EricLew 0:d4e5ad7ad71c 61
EricLew 0:d4e5ad7ad71c 62 \return Control Register value
EricLew 0:d4e5ad7ad71c 63 */
EricLew 0:d4e5ad7ad71c 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
EricLew 0:d4e5ad7ad71c 65 {
EricLew 0:d4e5ad7ad71c 66 register uint32_t __regControl __ASM("control");
EricLew 0:d4e5ad7ad71c 67 return(__regControl);
EricLew 0:d4e5ad7ad71c 68 }
EricLew 0:d4e5ad7ad71c 69
EricLew 0:d4e5ad7ad71c 70
EricLew 0:d4e5ad7ad71c 71 /** \brief Set Control Register
EricLew 0:d4e5ad7ad71c 72
EricLew 0:d4e5ad7ad71c 73 This function writes the given value to the Control Register.
EricLew 0:d4e5ad7ad71c 74
EricLew 0:d4e5ad7ad71c 75 \param [in] control Control Register value to set
EricLew 0:d4e5ad7ad71c 76 */
EricLew 0:d4e5ad7ad71c 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
EricLew 0:d4e5ad7ad71c 78 {
EricLew 0:d4e5ad7ad71c 79 register uint32_t __regControl __ASM("control");
EricLew 0:d4e5ad7ad71c 80 __regControl = control;
EricLew 0:d4e5ad7ad71c 81 }
EricLew 0:d4e5ad7ad71c 82
EricLew 0:d4e5ad7ad71c 83
EricLew 0:d4e5ad7ad71c 84 /** \brief Get IPSR Register
EricLew 0:d4e5ad7ad71c 85
EricLew 0:d4e5ad7ad71c 86 This function returns the content of the IPSR Register.
EricLew 0:d4e5ad7ad71c 87
EricLew 0:d4e5ad7ad71c 88 \return IPSR Register value
EricLew 0:d4e5ad7ad71c 89 */
EricLew 0:d4e5ad7ad71c 90 __STATIC_INLINE uint32_t __get_IPSR(void)
EricLew 0:d4e5ad7ad71c 91 {
EricLew 0:d4e5ad7ad71c 92 register uint32_t __regIPSR __ASM("ipsr");
EricLew 0:d4e5ad7ad71c 93 return(__regIPSR);
EricLew 0:d4e5ad7ad71c 94 }
EricLew 0:d4e5ad7ad71c 95
EricLew 0:d4e5ad7ad71c 96
EricLew 0:d4e5ad7ad71c 97 /** \brief Get APSR Register
EricLew 0:d4e5ad7ad71c 98
EricLew 0:d4e5ad7ad71c 99 This function returns the content of the APSR Register.
EricLew 0:d4e5ad7ad71c 100
EricLew 0:d4e5ad7ad71c 101 \return APSR Register value
EricLew 0:d4e5ad7ad71c 102 */
EricLew 0:d4e5ad7ad71c 103 __STATIC_INLINE uint32_t __get_APSR(void)
EricLew 0:d4e5ad7ad71c 104 {
EricLew 0:d4e5ad7ad71c 105 register uint32_t __regAPSR __ASM("apsr");
EricLew 0:d4e5ad7ad71c 106 return(__regAPSR);
EricLew 0:d4e5ad7ad71c 107 }
EricLew 0:d4e5ad7ad71c 108
EricLew 0:d4e5ad7ad71c 109
EricLew 0:d4e5ad7ad71c 110 /** \brief Get xPSR Register
EricLew 0:d4e5ad7ad71c 111
EricLew 0:d4e5ad7ad71c 112 This function returns the content of the xPSR Register.
EricLew 0:d4e5ad7ad71c 113
EricLew 0:d4e5ad7ad71c 114 \return xPSR Register value
EricLew 0:d4e5ad7ad71c 115 */
EricLew 0:d4e5ad7ad71c 116 __STATIC_INLINE uint32_t __get_xPSR(void)
EricLew 0:d4e5ad7ad71c 117 {
EricLew 0:d4e5ad7ad71c 118 register uint32_t __regXPSR __ASM("xpsr");
EricLew 0:d4e5ad7ad71c 119 return(__regXPSR);
EricLew 0:d4e5ad7ad71c 120 }
EricLew 0:d4e5ad7ad71c 121
EricLew 0:d4e5ad7ad71c 122
EricLew 0:d4e5ad7ad71c 123 /** \brief Get Process Stack Pointer
EricLew 0:d4e5ad7ad71c 124
EricLew 0:d4e5ad7ad71c 125 This function returns the current value of the Process Stack Pointer (PSP).
EricLew 0:d4e5ad7ad71c 126
EricLew 0:d4e5ad7ad71c 127 \return PSP Register value
EricLew 0:d4e5ad7ad71c 128 */
EricLew 0:d4e5ad7ad71c 129 __STATIC_INLINE uint32_t __get_PSP(void)
EricLew 0:d4e5ad7ad71c 130 {
EricLew 0:d4e5ad7ad71c 131 register uint32_t __regProcessStackPointer __ASM("psp");
EricLew 0:d4e5ad7ad71c 132 return(__regProcessStackPointer);
EricLew 0:d4e5ad7ad71c 133 }
EricLew 0:d4e5ad7ad71c 134
EricLew 0:d4e5ad7ad71c 135
EricLew 0:d4e5ad7ad71c 136 /** \brief Set Process Stack Pointer
EricLew 0:d4e5ad7ad71c 137
EricLew 0:d4e5ad7ad71c 138 This function assigns the given value to the Process Stack Pointer (PSP).
EricLew 0:d4e5ad7ad71c 139
EricLew 0:d4e5ad7ad71c 140 \param [in] topOfProcStack Process Stack Pointer value to set
EricLew 0:d4e5ad7ad71c 141 */
EricLew 0:d4e5ad7ad71c 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
EricLew 0:d4e5ad7ad71c 143 {
EricLew 0:d4e5ad7ad71c 144 register uint32_t __regProcessStackPointer __ASM("psp");
EricLew 0:d4e5ad7ad71c 145 __regProcessStackPointer = topOfProcStack;
EricLew 0:d4e5ad7ad71c 146 }
EricLew 0:d4e5ad7ad71c 147
EricLew 0:d4e5ad7ad71c 148
EricLew 0:d4e5ad7ad71c 149 /** \brief Get Main Stack Pointer
EricLew 0:d4e5ad7ad71c 150
EricLew 0:d4e5ad7ad71c 151 This function returns the current value of the Main Stack Pointer (MSP).
EricLew 0:d4e5ad7ad71c 152
EricLew 0:d4e5ad7ad71c 153 \return MSP Register value
EricLew 0:d4e5ad7ad71c 154 */
EricLew 0:d4e5ad7ad71c 155 __STATIC_INLINE uint32_t __get_MSP(void)
EricLew 0:d4e5ad7ad71c 156 {
EricLew 0:d4e5ad7ad71c 157 register uint32_t __regMainStackPointer __ASM("msp");
EricLew 0:d4e5ad7ad71c 158 return(__regMainStackPointer);
EricLew 0:d4e5ad7ad71c 159 }
EricLew 0:d4e5ad7ad71c 160
EricLew 0:d4e5ad7ad71c 161
EricLew 0:d4e5ad7ad71c 162 /** \brief Set Main Stack Pointer
EricLew 0:d4e5ad7ad71c 163
EricLew 0:d4e5ad7ad71c 164 This function assigns the given value to the Main Stack Pointer (MSP).
EricLew 0:d4e5ad7ad71c 165
EricLew 0:d4e5ad7ad71c 166 \param [in] topOfMainStack Main Stack Pointer value to set
EricLew 0:d4e5ad7ad71c 167 */
EricLew 0:d4e5ad7ad71c 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
EricLew 0:d4e5ad7ad71c 169 {
EricLew 0:d4e5ad7ad71c 170 register uint32_t __regMainStackPointer __ASM("msp");
EricLew 0:d4e5ad7ad71c 171 __regMainStackPointer = topOfMainStack;
EricLew 0:d4e5ad7ad71c 172 }
EricLew 0:d4e5ad7ad71c 173
EricLew 0:d4e5ad7ad71c 174
EricLew 0:d4e5ad7ad71c 175 /** \brief Get Priority Mask
EricLew 0:d4e5ad7ad71c 176
EricLew 0:d4e5ad7ad71c 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
EricLew 0:d4e5ad7ad71c 178
EricLew 0:d4e5ad7ad71c 179 \return Priority Mask value
EricLew 0:d4e5ad7ad71c 180 */
EricLew 0:d4e5ad7ad71c 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
EricLew 0:d4e5ad7ad71c 182 {
EricLew 0:d4e5ad7ad71c 183 register uint32_t __regPriMask __ASM("primask");
EricLew 0:d4e5ad7ad71c 184 return(__regPriMask);
EricLew 0:d4e5ad7ad71c 185 }
EricLew 0:d4e5ad7ad71c 186
EricLew 0:d4e5ad7ad71c 187
EricLew 0:d4e5ad7ad71c 188 /** \brief Set Priority Mask
EricLew 0:d4e5ad7ad71c 189
EricLew 0:d4e5ad7ad71c 190 This function assigns the given value to the Priority Mask Register.
EricLew 0:d4e5ad7ad71c 191
EricLew 0:d4e5ad7ad71c 192 \param [in] priMask Priority Mask
EricLew 0:d4e5ad7ad71c 193 */
EricLew 0:d4e5ad7ad71c 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
EricLew 0:d4e5ad7ad71c 195 {
EricLew 0:d4e5ad7ad71c 196 register uint32_t __regPriMask __ASM("primask");
EricLew 0:d4e5ad7ad71c 197 __regPriMask = (priMask);
EricLew 0:d4e5ad7ad71c 198 }
EricLew 0:d4e5ad7ad71c 199
EricLew 0:d4e5ad7ad71c 200
EricLew 0:d4e5ad7ad71c 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
EricLew 0:d4e5ad7ad71c 202
EricLew 0:d4e5ad7ad71c 203 /** \brief Enable FIQ
EricLew 0:d4e5ad7ad71c 204
EricLew 0:d4e5ad7ad71c 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
EricLew 0:d4e5ad7ad71c 206 Can only be executed in Privileged modes.
EricLew 0:d4e5ad7ad71c 207 */
EricLew 0:d4e5ad7ad71c 208 #define __enable_fault_irq __enable_fiq
EricLew 0:d4e5ad7ad71c 209
EricLew 0:d4e5ad7ad71c 210
EricLew 0:d4e5ad7ad71c 211 /** \brief Disable FIQ
EricLew 0:d4e5ad7ad71c 212
EricLew 0:d4e5ad7ad71c 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
EricLew 0:d4e5ad7ad71c 214 Can only be executed in Privileged modes.
EricLew 0:d4e5ad7ad71c 215 */
EricLew 0:d4e5ad7ad71c 216 #define __disable_fault_irq __disable_fiq
EricLew 0:d4e5ad7ad71c 217
EricLew 0:d4e5ad7ad71c 218
EricLew 0:d4e5ad7ad71c 219 /** \brief Get Base Priority
EricLew 0:d4e5ad7ad71c 220
EricLew 0:d4e5ad7ad71c 221 This function returns the current value of the Base Priority register.
EricLew 0:d4e5ad7ad71c 222
EricLew 0:d4e5ad7ad71c 223 \return Base Priority register value
EricLew 0:d4e5ad7ad71c 224 */
EricLew 0:d4e5ad7ad71c 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
EricLew 0:d4e5ad7ad71c 226 {
EricLew 0:d4e5ad7ad71c 227 register uint32_t __regBasePri __ASM("basepri");
EricLew 0:d4e5ad7ad71c 228 return(__regBasePri);
EricLew 0:d4e5ad7ad71c 229 }
EricLew 0:d4e5ad7ad71c 230
EricLew 0:d4e5ad7ad71c 231
EricLew 0:d4e5ad7ad71c 232 /** \brief Set Base Priority
EricLew 0:d4e5ad7ad71c 233
EricLew 0:d4e5ad7ad71c 234 This function assigns the given value to the Base Priority register.
EricLew 0:d4e5ad7ad71c 235
EricLew 0:d4e5ad7ad71c 236 \param [in] basePri Base Priority value to set
EricLew 0:d4e5ad7ad71c 237 */
EricLew 0:d4e5ad7ad71c 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
EricLew 0:d4e5ad7ad71c 239 {
EricLew 0:d4e5ad7ad71c 240 register uint32_t __regBasePri __ASM("basepri");
EricLew 0:d4e5ad7ad71c 241 __regBasePri = (basePri & 0xff);
EricLew 0:d4e5ad7ad71c 242 }
EricLew 0:d4e5ad7ad71c 243
EricLew 0:d4e5ad7ad71c 244
EricLew 0:d4e5ad7ad71c 245 /** \brief Set Base Priority with condition
EricLew 0:d4e5ad7ad71c 246
EricLew 0:d4e5ad7ad71c 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
EricLew 0:d4e5ad7ad71c 248 or the new value increases the BASEPRI priority level.
EricLew 0:d4e5ad7ad71c 249
EricLew 0:d4e5ad7ad71c 250 \param [in] basePri Base Priority value to set
EricLew 0:d4e5ad7ad71c 251 */
EricLew 0:d4e5ad7ad71c 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
EricLew 0:d4e5ad7ad71c 253 {
EricLew 0:d4e5ad7ad71c 254 register uint32_t __regBasePriMax __ASM("basepri_max");
EricLew 0:d4e5ad7ad71c 255 __regBasePriMax = (basePri & 0xff);
EricLew 0:d4e5ad7ad71c 256 }
EricLew 0:d4e5ad7ad71c 257
EricLew 0:d4e5ad7ad71c 258
EricLew 0:d4e5ad7ad71c 259 /** \brief Get Fault Mask
EricLew 0:d4e5ad7ad71c 260
EricLew 0:d4e5ad7ad71c 261 This function returns the current value of the Fault Mask register.
EricLew 0:d4e5ad7ad71c 262
EricLew 0:d4e5ad7ad71c 263 \return Fault Mask register value
EricLew 0:d4e5ad7ad71c 264 */
EricLew 0:d4e5ad7ad71c 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
EricLew 0:d4e5ad7ad71c 266 {
EricLew 0:d4e5ad7ad71c 267 register uint32_t __regFaultMask __ASM("faultmask");
EricLew 0:d4e5ad7ad71c 268 return(__regFaultMask);
EricLew 0:d4e5ad7ad71c 269 }
EricLew 0:d4e5ad7ad71c 270
EricLew 0:d4e5ad7ad71c 271
EricLew 0:d4e5ad7ad71c 272 /** \brief Set Fault Mask
EricLew 0:d4e5ad7ad71c 273
EricLew 0:d4e5ad7ad71c 274 This function assigns the given value to the Fault Mask register.
EricLew 0:d4e5ad7ad71c 275
EricLew 0:d4e5ad7ad71c 276 \param [in] faultMask Fault Mask value to set
EricLew 0:d4e5ad7ad71c 277 */
EricLew 0:d4e5ad7ad71c 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
EricLew 0:d4e5ad7ad71c 279 {
EricLew 0:d4e5ad7ad71c 280 register uint32_t __regFaultMask __ASM("faultmask");
EricLew 0:d4e5ad7ad71c 281 __regFaultMask = (faultMask & (uint32_t)1);
EricLew 0:d4e5ad7ad71c 282 }
EricLew 0:d4e5ad7ad71c 283
EricLew 0:d4e5ad7ad71c 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
EricLew 0:d4e5ad7ad71c 285
EricLew 0:d4e5ad7ad71c 286
EricLew 0:d4e5ad7ad71c 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
EricLew 0:d4e5ad7ad71c 288
EricLew 0:d4e5ad7ad71c 289 /** \brief Get FPSCR
EricLew 0:d4e5ad7ad71c 290
EricLew 0:d4e5ad7ad71c 291 This function returns the current value of the Floating Point Status/Control register.
EricLew 0:d4e5ad7ad71c 292
EricLew 0:d4e5ad7ad71c 293 \return Floating Point Status/Control register value
EricLew 0:d4e5ad7ad71c 294 */
EricLew 0:d4e5ad7ad71c 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
EricLew 0:d4e5ad7ad71c 296 {
EricLew 0:d4e5ad7ad71c 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
EricLew 0:d4e5ad7ad71c 298 register uint32_t __regfpscr __ASM("fpscr");
EricLew 0:d4e5ad7ad71c 299 return(__regfpscr);
EricLew 0:d4e5ad7ad71c 300 #else
EricLew 0:d4e5ad7ad71c 301 return(0);
EricLew 0:d4e5ad7ad71c 302 #endif
EricLew 0:d4e5ad7ad71c 303 }
EricLew 0:d4e5ad7ad71c 304
EricLew 0:d4e5ad7ad71c 305
EricLew 0:d4e5ad7ad71c 306 /** \brief Set FPSCR
EricLew 0:d4e5ad7ad71c 307
EricLew 0:d4e5ad7ad71c 308 This function assigns the given value to the Floating Point Status/Control register.
EricLew 0:d4e5ad7ad71c 309
EricLew 0:d4e5ad7ad71c 310 \param [in] fpscr Floating Point Status/Control value to set
EricLew 0:d4e5ad7ad71c 311 */
EricLew 0:d4e5ad7ad71c 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
EricLew 0:d4e5ad7ad71c 313 {
EricLew 0:d4e5ad7ad71c 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
EricLew 0:d4e5ad7ad71c 315 register uint32_t __regfpscr __ASM("fpscr");
EricLew 0:d4e5ad7ad71c 316 __regfpscr = (fpscr);
EricLew 0:d4e5ad7ad71c 317 #endif
EricLew 0:d4e5ad7ad71c 318 }
EricLew 0:d4e5ad7ad71c 319
EricLew 0:d4e5ad7ad71c 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
EricLew 0:d4e5ad7ad71c 321
EricLew 0:d4e5ad7ad71c 322
EricLew 0:d4e5ad7ad71c 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
EricLew 0:d4e5ad7ad71c 324 /* GNU gcc specific functions */
EricLew 0:d4e5ad7ad71c 325
EricLew 0:d4e5ad7ad71c 326 /** \brief Enable IRQ Interrupts
EricLew 0:d4e5ad7ad71c 327
EricLew 0:d4e5ad7ad71c 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
EricLew 0:d4e5ad7ad71c 329 Can only be executed in Privileged modes.
EricLew 0:d4e5ad7ad71c 330 */
EricLew 0:d4e5ad7ad71c 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
EricLew 0:d4e5ad7ad71c 332 {
EricLew 0:d4e5ad7ad71c 333 __ASM volatile ("cpsie i" : : : "memory");
EricLew 0:d4e5ad7ad71c 334 }
EricLew 0:d4e5ad7ad71c 335
EricLew 0:d4e5ad7ad71c 336
EricLew 0:d4e5ad7ad71c 337 /** \brief Disable IRQ Interrupts
EricLew 0:d4e5ad7ad71c 338
EricLew 0:d4e5ad7ad71c 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
EricLew 0:d4e5ad7ad71c 340 Can only be executed in Privileged modes.
EricLew 0:d4e5ad7ad71c 341 */
EricLew 0:d4e5ad7ad71c 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
EricLew 0:d4e5ad7ad71c 343 {
EricLew 0:d4e5ad7ad71c 344 __ASM volatile ("cpsid i" : : : "memory");
EricLew 0:d4e5ad7ad71c 345 }
EricLew 0:d4e5ad7ad71c 346
EricLew 0:d4e5ad7ad71c 347
EricLew 0:d4e5ad7ad71c 348 /** \brief Get Control Register
EricLew 0:d4e5ad7ad71c 349
EricLew 0:d4e5ad7ad71c 350 This function returns the content of the Control Register.
EricLew 0:d4e5ad7ad71c 351
EricLew 0:d4e5ad7ad71c 352 \return Control Register value
EricLew 0:d4e5ad7ad71c 353 */
EricLew 0:d4e5ad7ad71c 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
EricLew 0:d4e5ad7ad71c 355 {
EricLew 0:d4e5ad7ad71c 356 uint32_t result;
EricLew 0:d4e5ad7ad71c 357
EricLew 0:d4e5ad7ad71c 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
EricLew 0:d4e5ad7ad71c 359 return(result);
EricLew 0:d4e5ad7ad71c 360 }
EricLew 0:d4e5ad7ad71c 361
EricLew 0:d4e5ad7ad71c 362
EricLew 0:d4e5ad7ad71c 363 /** \brief Set Control Register
EricLew 0:d4e5ad7ad71c 364
EricLew 0:d4e5ad7ad71c 365 This function writes the given value to the Control Register.
EricLew 0:d4e5ad7ad71c 366
EricLew 0:d4e5ad7ad71c 367 \param [in] control Control Register value to set
EricLew 0:d4e5ad7ad71c 368 */
EricLew 0:d4e5ad7ad71c 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
EricLew 0:d4e5ad7ad71c 370 {
EricLew 0:d4e5ad7ad71c 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
EricLew 0:d4e5ad7ad71c 372 }
EricLew 0:d4e5ad7ad71c 373
EricLew 0:d4e5ad7ad71c 374
EricLew 0:d4e5ad7ad71c 375 /** \brief Get IPSR Register
EricLew 0:d4e5ad7ad71c 376
EricLew 0:d4e5ad7ad71c 377 This function returns the content of the IPSR Register.
EricLew 0:d4e5ad7ad71c 378
EricLew 0:d4e5ad7ad71c 379 \return IPSR Register value
EricLew 0:d4e5ad7ad71c 380 */
EricLew 0:d4e5ad7ad71c 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
EricLew 0:d4e5ad7ad71c 382 {
EricLew 0:d4e5ad7ad71c 383 uint32_t result;
EricLew 0:d4e5ad7ad71c 384
EricLew 0:d4e5ad7ad71c 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
EricLew 0:d4e5ad7ad71c 386 return(result);
EricLew 0:d4e5ad7ad71c 387 }
EricLew 0:d4e5ad7ad71c 388
EricLew 0:d4e5ad7ad71c 389
EricLew 0:d4e5ad7ad71c 390 /** \brief Get APSR Register
EricLew 0:d4e5ad7ad71c 391
EricLew 0:d4e5ad7ad71c 392 This function returns the content of the APSR Register.
EricLew 0:d4e5ad7ad71c 393
EricLew 0:d4e5ad7ad71c 394 \return APSR Register value
EricLew 0:d4e5ad7ad71c 395 */
EricLew 0:d4e5ad7ad71c 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
EricLew 0:d4e5ad7ad71c 397 {
EricLew 0:d4e5ad7ad71c 398 uint32_t result;
EricLew 0:d4e5ad7ad71c 399
EricLew 0:d4e5ad7ad71c 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
EricLew 0:d4e5ad7ad71c 401 return(result);
EricLew 0:d4e5ad7ad71c 402 }
EricLew 0:d4e5ad7ad71c 403
EricLew 0:d4e5ad7ad71c 404
EricLew 0:d4e5ad7ad71c 405 /** \brief Get xPSR Register
EricLew 0:d4e5ad7ad71c 406
EricLew 0:d4e5ad7ad71c 407 This function returns the content of the xPSR Register.
EricLew 0:d4e5ad7ad71c 408
EricLew 0:d4e5ad7ad71c 409 \return xPSR Register value
EricLew 0:d4e5ad7ad71c 410 */
EricLew 0:d4e5ad7ad71c 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
EricLew 0:d4e5ad7ad71c 412 {
EricLew 0:d4e5ad7ad71c 413 uint32_t result;
EricLew 0:d4e5ad7ad71c 414
EricLew 0:d4e5ad7ad71c 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
EricLew 0:d4e5ad7ad71c 416 return(result);
EricLew 0:d4e5ad7ad71c 417 }
EricLew 0:d4e5ad7ad71c 418
EricLew 0:d4e5ad7ad71c 419
EricLew 0:d4e5ad7ad71c 420 /** \brief Get Process Stack Pointer
EricLew 0:d4e5ad7ad71c 421
EricLew 0:d4e5ad7ad71c 422 This function returns the current value of the Process Stack Pointer (PSP).
EricLew 0:d4e5ad7ad71c 423
EricLew 0:d4e5ad7ad71c 424 \return PSP Register value
EricLew 0:d4e5ad7ad71c 425 */
EricLew 0:d4e5ad7ad71c 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
EricLew 0:d4e5ad7ad71c 427 {
EricLew 0:d4e5ad7ad71c 428 register uint32_t result;
EricLew 0:d4e5ad7ad71c 429
EricLew 0:d4e5ad7ad71c 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
EricLew 0:d4e5ad7ad71c 431 return(result);
EricLew 0:d4e5ad7ad71c 432 }
EricLew 0:d4e5ad7ad71c 433
EricLew 0:d4e5ad7ad71c 434
EricLew 0:d4e5ad7ad71c 435 /** \brief Set Process Stack Pointer
EricLew 0:d4e5ad7ad71c 436
EricLew 0:d4e5ad7ad71c 437 This function assigns the given value to the Process Stack Pointer (PSP).
EricLew 0:d4e5ad7ad71c 438
EricLew 0:d4e5ad7ad71c 439 \param [in] topOfProcStack Process Stack Pointer value to set
EricLew 0:d4e5ad7ad71c 440 */
EricLew 0:d4e5ad7ad71c 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
EricLew 0:d4e5ad7ad71c 442 {
EricLew 0:d4e5ad7ad71c 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
EricLew 0:d4e5ad7ad71c 444 }
EricLew 0:d4e5ad7ad71c 445
EricLew 0:d4e5ad7ad71c 446
EricLew 0:d4e5ad7ad71c 447 /** \brief Get Main Stack Pointer
EricLew 0:d4e5ad7ad71c 448
EricLew 0:d4e5ad7ad71c 449 This function returns the current value of the Main Stack Pointer (MSP).
EricLew 0:d4e5ad7ad71c 450
EricLew 0:d4e5ad7ad71c 451 \return MSP Register value
EricLew 0:d4e5ad7ad71c 452 */
EricLew 0:d4e5ad7ad71c 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
EricLew 0:d4e5ad7ad71c 454 {
EricLew 0:d4e5ad7ad71c 455 register uint32_t result;
EricLew 0:d4e5ad7ad71c 456
EricLew 0:d4e5ad7ad71c 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
EricLew 0:d4e5ad7ad71c 458 return(result);
EricLew 0:d4e5ad7ad71c 459 }
EricLew 0:d4e5ad7ad71c 460
EricLew 0:d4e5ad7ad71c 461
EricLew 0:d4e5ad7ad71c 462 /** \brief Set Main Stack Pointer
EricLew 0:d4e5ad7ad71c 463
EricLew 0:d4e5ad7ad71c 464 This function assigns the given value to the Main Stack Pointer (MSP).
EricLew 0:d4e5ad7ad71c 465
EricLew 0:d4e5ad7ad71c 466 \param [in] topOfMainStack Main Stack Pointer value to set
EricLew 0:d4e5ad7ad71c 467 */
EricLew 0:d4e5ad7ad71c 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
EricLew 0:d4e5ad7ad71c 469 {
EricLew 0:d4e5ad7ad71c 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
EricLew 0:d4e5ad7ad71c 471 }
EricLew 0:d4e5ad7ad71c 472
EricLew 0:d4e5ad7ad71c 473
EricLew 0:d4e5ad7ad71c 474 /** \brief Get Priority Mask
EricLew 0:d4e5ad7ad71c 475
EricLew 0:d4e5ad7ad71c 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
EricLew 0:d4e5ad7ad71c 477
EricLew 0:d4e5ad7ad71c 478 \return Priority Mask value
EricLew 0:d4e5ad7ad71c 479 */
EricLew 0:d4e5ad7ad71c 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
EricLew 0:d4e5ad7ad71c 481 {
EricLew 0:d4e5ad7ad71c 482 uint32_t result;
EricLew 0:d4e5ad7ad71c 483
EricLew 0:d4e5ad7ad71c 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
EricLew 0:d4e5ad7ad71c 485 return(result);
EricLew 0:d4e5ad7ad71c 486 }
EricLew 0:d4e5ad7ad71c 487
EricLew 0:d4e5ad7ad71c 488
EricLew 0:d4e5ad7ad71c 489 /** \brief Set Priority Mask
EricLew 0:d4e5ad7ad71c 490
EricLew 0:d4e5ad7ad71c 491 This function assigns the given value to the Priority Mask Register.
EricLew 0:d4e5ad7ad71c 492
EricLew 0:d4e5ad7ad71c 493 \param [in] priMask Priority Mask
EricLew 0:d4e5ad7ad71c 494 */
EricLew 0:d4e5ad7ad71c 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
EricLew 0:d4e5ad7ad71c 496 {
EricLew 0:d4e5ad7ad71c 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
EricLew 0:d4e5ad7ad71c 498 }
EricLew 0:d4e5ad7ad71c 499
EricLew 0:d4e5ad7ad71c 500
EricLew 0:d4e5ad7ad71c 501 #if (__CORTEX_M >= 0x03)
EricLew 0:d4e5ad7ad71c 502
EricLew 0:d4e5ad7ad71c 503 /** \brief Enable FIQ
EricLew 0:d4e5ad7ad71c 504
EricLew 0:d4e5ad7ad71c 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
EricLew 0:d4e5ad7ad71c 506 Can only be executed in Privileged modes.
EricLew 0:d4e5ad7ad71c 507 */
EricLew 0:d4e5ad7ad71c 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
EricLew 0:d4e5ad7ad71c 509 {
EricLew 0:d4e5ad7ad71c 510 __ASM volatile ("cpsie f" : : : "memory");
EricLew 0:d4e5ad7ad71c 511 }
EricLew 0:d4e5ad7ad71c 512
EricLew 0:d4e5ad7ad71c 513
EricLew 0:d4e5ad7ad71c 514 /** \brief Disable FIQ
EricLew 0:d4e5ad7ad71c 515
EricLew 0:d4e5ad7ad71c 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
EricLew 0:d4e5ad7ad71c 517 Can only be executed in Privileged modes.
EricLew 0:d4e5ad7ad71c 518 */
EricLew 0:d4e5ad7ad71c 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
EricLew 0:d4e5ad7ad71c 520 {
EricLew 0:d4e5ad7ad71c 521 __ASM volatile ("cpsid f" : : : "memory");
EricLew 0:d4e5ad7ad71c 522 }
EricLew 0:d4e5ad7ad71c 523
EricLew 0:d4e5ad7ad71c 524
EricLew 0:d4e5ad7ad71c 525 /** \brief Get Base Priority
EricLew 0:d4e5ad7ad71c 526
EricLew 0:d4e5ad7ad71c 527 This function returns the current value of the Base Priority register.
EricLew 0:d4e5ad7ad71c 528
EricLew 0:d4e5ad7ad71c 529 \return Base Priority register value
EricLew 0:d4e5ad7ad71c 530 */
EricLew 0:d4e5ad7ad71c 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
EricLew 0:d4e5ad7ad71c 532 {
EricLew 0:d4e5ad7ad71c 533 uint32_t result;
EricLew 0:d4e5ad7ad71c 534
EricLew 0:d4e5ad7ad71c 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
EricLew 0:d4e5ad7ad71c 536 return(result);
EricLew 0:d4e5ad7ad71c 537 }
EricLew 0:d4e5ad7ad71c 538
EricLew 0:d4e5ad7ad71c 539
EricLew 0:d4e5ad7ad71c 540 /** \brief Set Base Priority
EricLew 0:d4e5ad7ad71c 541
EricLew 0:d4e5ad7ad71c 542 This function assigns the given value to the Base Priority register.
EricLew 0:d4e5ad7ad71c 543
EricLew 0:d4e5ad7ad71c 544 \param [in] basePri Base Priority value to set
EricLew 0:d4e5ad7ad71c 545 */
EricLew 0:d4e5ad7ad71c 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
EricLew 0:d4e5ad7ad71c 547 {
EricLew 0:d4e5ad7ad71c 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
EricLew 0:d4e5ad7ad71c 549 }
EricLew 0:d4e5ad7ad71c 550
EricLew 0:d4e5ad7ad71c 551
EricLew 0:d4e5ad7ad71c 552 /** \brief Set Base Priority with condition
EricLew 0:d4e5ad7ad71c 553
EricLew 0:d4e5ad7ad71c 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
EricLew 0:d4e5ad7ad71c 555 or the new value increases the BASEPRI priority level.
EricLew 0:d4e5ad7ad71c 556
EricLew 0:d4e5ad7ad71c 557 \param [in] basePri Base Priority value to set
EricLew 0:d4e5ad7ad71c 558 */
EricLew 0:d4e5ad7ad71c 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
EricLew 0:d4e5ad7ad71c 560 {
EricLew 0:d4e5ad7ad71c 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
EricLew 0:d4e5ad7ad71c 562 }
EricLew 0:d4e5ad7ad71c 563
EricLew 0:d4e5ad7ad71c 564
EricLew 0:d4e5ad7ad71c 565 /** \brief Get Fault Mask
EricLew 0:d4e5ad7ad71c 566
EricLew 0:d4e5ad7ad71c 567 This function returns the current value of the Fault Mask register.
EricLew 0:d4e5ad7ad71c 568
EricLew 0:d4e5ad7ad71c 569 \return Fault Mask register value
EricLew 0:d4e5ad7ad71c 570 */
EricLew 0:d4e5ad7ad71c 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
EricLew 0:d4e5ad7ad71c 572 {
EricLew 0:d4e5ad7ad71c 573 uint32_t result;
EricLew 0:d4e5ad7ad71c 574
EricLew 0:d4e5ad7ad71c 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
EricLew 0:d4e5ad7ad71c 576 return(result);
EricLew 0:d4e5ad7ad71c 577 }
EricLew 0:d4e5ad7ad71c 578
EricLew 0:d4e5ad7ad71c 579
EricLew 0:d4e5ad7ad71c 580 /** \brief Set Fault Mask
EricLew 0:d4e5ad7ad71c 581
EricLew 0:d4e5ad7ad71c 582 This function assigns the given value to the Fault Mask register.
EricLew 0:d4e5ad7ad71c 583
EricLew 0:d4e5ad7ad71c 584 \param [in] faultMask Fault Mask value to set
EricLew 0:d4e5ad7ad71c 585 */
EricLew 0:d4e5ad7ad71c 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
EricLew 0:d4e5ad7ad71c 587 {
EricLew 0:d4e5ad7ad71c 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
EricLew 0:d4e5ad7ad71c 589 }
EricLew 0:d4e5ad7ad71c 590
EricLew 0:d4e5ad7ad71c 591 #endif /* (__CORTEX_M >= 0x03) */
EricLew 0:d4e5ad7ad71c 592
EricLew 0:d4e5ad7ad71c 593
EricLew 0:d4e5ad7ad71c 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
EricLew 0:d4e5ad7ad71c 595
EricLew 0:d4e5ad7ad71c 596 /** \brief Get FPSCR
EricLew 0:d4e5ad7ad71c 597
EricLew 0:d4e5ad7ad71c 598 This function returns the current value of the Floating Point Status/Control register.
EricLew 0:d4e5ad7ad71c 599
EricLew 0:d4e5ad7ad71c 600 \return Floating Point Status/Control register value
EricLew 0:d4e5ad7ad71c 601 */
EricLew 0:d4e5ad7ad71c 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
EricLew 0:d4e5ad7ad71c 603 {
EricLew 0:d4e5ad7ad71c 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
EricLew 0:d4e5ad7ad71c 605 uint32_t result;
EricLew 0:d4e5ad7ad71c 606
EricLew 0:d4e5ad7ad71c 607 /* Empty asm statement works as a scheduling barrier */
EricLew 0:d4e5ad7ad71c 608 __ASM volatile ("");
EricLew 0:d4e5ad7ad71c 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
EricLew 0:d4e5ad7ad71c 610 __ASM volatile ("");
EricLew 0:d4e5ad7ad71c 611 return(result);
EricLew 0:d4e5ad7ad71c 612 #else
EricLew 0:d4e5ad7ad71c 613 return(0);
EricLew 0:d4e5ad7ad71c 614 #endif
EricLew 0:d4e5ad7ad71c 615 }
EricLew 0:d4e5ad7ad71c 616
EricLew 0:d4e5ad7ad71c 617
EricLew 0:d4e5ad7ad71c 618 /** \brief Set FPSCR
EricLew 0:d4e5ad7ad71c 619
EricLew 0:d4e5ad7ad71c 620 This function assigns the given value to the Floating Point Status/Control register.
EricLew 0:d4e5ad7ad71c 621
EricLew 0:d4e5ad7ad71c 622 \param [in] fpscr Floating Point Status/Control value to set
EricLew 0:d4e5ad7ad71c 623 */
EricLew 0:d4e5ad7ad71c 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
EricLew 0:d4e5ad7ad71c 625 {
EricLew 0:d4e5ad7ad71c 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
EricLew 0:d4e5ad7ad71c 627 /* Empty asm statement works as a scheduling barrier */
EricLew 0:d4e5ad7ad71c 628 __ASM volatile ("");
EricLew 0:d4e5ad7ad71c 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
EricLew 0:d4e5ad7ad71c 630 __ASM volatile ("");
EricLew 0:d4e5ad7ad71c 631 #endif
EricLew 0:d4e5ad7ad71c 632 }
EricLew 0:d4e5ad7ad71c 633
EricLew 0:d4e5ad7ad71c 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
EricLew 0:d4e5ad7ad71c 635
EricLew 0:d4e5ad7ad71c 636
EricLew 0:d4e5ad7ad71c 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
EricLew 0:d4e5ad7ad71c 638 /* IAR iccarm specific functions */
EricLew 0:d4e5ad7ad71c 639 #include <cmsis_iar.h>
EricLew 0:d4e5ad7ad71c 640
EricLew 0:d4e5ad7ad71c 641
EricLew 0:d4e5ad7ad71c 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
EricLew 0:d4e5ad7ad71c 643 /* TI CCS specific functions */
EricLew 0:d4e5ad7ad71c 644 #include <cmsis_ccs.h>
EricLew 0:d4e5ad7ad71c 645
EricLew 0:d4e5ad7ad71c 646
EricLew 0:d4e5ad7ad71c 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
EricLew 0:d4e5ad7ad71c 648 /* TASKING carm specific functions */
EricLew 0:d4e5ad7ad71c 649 /*
EricLew 0:d4e5ad7ad71c 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
EricLew 0:d4e5ad7ad71c 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
EricLew 0:d4e5ad7ad71c 652 * Including the CMSIS ones.
EricLew 0:d4e5ad7ad71c 653 */
EricLew 0:d4e5ad7ad71c 654
EricLew 0:d4e5ad7ad71c 655
EricLew 0:d4e5ad7ad71c 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
EricLew 0:d4e5ad7ad71c 657 /* Cosmic specific functions */
EricLew 0:d4e5ad7ad71c 658 #include <cmsis_csm.h>
EricLew 0:d4e5ad7ad71c 659
EricLew 0:d4e5ad7ad71c 660 #endif
EricLew 0:d4e5ad7ad71c 661
EricLew 0:d4e5ad7ad71c 662 /*@} end of CMSIS_Core_RegAccFunctions */
EricLew 0:d4e5ad7ad71c 663
EricLew 0:d4e5ad7ad71c 664 #endif /* __CORE_CMFUNC_H */
EricLew 0:d4e5ad7ad71c 665