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Dependencies:   STM32L4xx_HAL_Driver CMSIS_DSP_401

core_cmSimd.h@0:d4e5ad7ad71c, 2015-11-23 (annotated)

Committer:
EricLew
Date:
Mon Nov 23 19:37:13 2015 +0000
Revision:
0:d4e5ad7ad71c
commit;

Who changed what in which revision?

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EricLew 0:d4e5ad7ad71c 1 /**************************************************************************//**
EricLew 0:d4e5ad7ad71c 2 * @file core_cmSimd.h
EricLew 0:d4e5ad7ad71c 3 * @brief CMSIS Cortex-M SIMD Header File
EricLew 0:d4e5ad7ad71c 4 * @version V4.10
EricLew 0:d4e5ad7ad71c 5 * @date 18. March 2015
EricLew 0:d4e5ad7ad71c 6 *
EricLew 0:d4e5ad7ad71c 7 * @note
EricLew 0:d4e5ad7ad71c 8 *
EricLew 0:d4e5ad7ad71c 9 ******************************************************************************/
EricLew 0:d4e5ad7ad71c 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
EricLew 0:d4e5ad7ad71c 11
EricLew 0:d4e5ad7ad71c 12 All rights reserved.
EricLew 0:d4e5ad7ad71c 13 Redistribution and use in source and binary forms, with or without
EricLew 0:d4e5ad7ad71c 14 modification, are permitted provided that the following conditions are met:
EricLew 0:d4e5ad7ad71c 15 - Redistributions of source code must retain the above copyright
EricLew 0:d4e5ad7ad71c 16 notice, this list of conditions and the following disclaimer.
EricLew 0:d4e5ad7ad71c 17 - Redistributions in binary form must reproduce the above copyright
EricLew 0:d4e5ad7ad71c 18 notice, this list of conditions and the following disclaimer in the
EricLew 0:d4e5ad7ad71c 19 documentation and/or other materials provided with the distribution.
EricLew 0:d4e5ad7ad71c 20 - Neither the name of ARM nor the names of its contributors may be used
EricLew 0:d4e5ad7ad71c 21 to endorse or promote products derived from this software without
EricLew 0:d4e5ad7ad71c 22 specific prior written permission.
EricLew 0:d4e5ad7ad71c 23 *
EricLew 0:d4e5ad7ad71c 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:d4e5ad7ad71c 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:d4e5ad7ad71c 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
EricLew 0:d4e5ad7ad71c 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
EricLew 0:d4e5ad7ad71c 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
EricLew 0:d4e5ad7ad71c 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
EricLew 0:d4e5ad7ad71c 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
EricLew 0:d4e5ad7ad71c 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
EricLew 0:d4e5ad7ad71c 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
EricLew 0:d4e5ad7ad71c 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
EricLew 0:d4e5ad7ad71c 34 POSSIBILITY OF SUCH DAMAGE.
EricLew 0:d4e5ad7ad71c 35 ---------------------------------------------------------------------------*/
EricLew 0:d4e5ad7ad71c 36
EricLew 0:d4e5ad7ad71c 37
EricLew 0:d4e5ad7ad71c 38 #if defined ( __ICCARM__ )
EricLew 0:d4e5ad7ad71c 39 #pragma system_include /* treat file as system include file for MISRA check */
EricLew 0:d4e5ad7ad71c 40 #endif
EricLew 0:d4e5ad7ad71c 41
EricLew 0:d4e5ad7ad71c 42 #ifndef __CORE_CMSIMD_H
EricLew 0:d4e5ad7ad71c 43 #define __CORE_CMSIMD_H
EricLew 0:d4e5ad7ad71c 44
EricLew 0:d4e5ad7ad71c 45 #ifdef __cplusplus
EricLew 0:d4e5ad7ad71c 46 extern "C" {
EricLew 0:d4e5ad7ad71c 47 #endif
EricLew 0:d4e5ad7ad71c 48
EricLew 0:d4e5ad7ad71c 49
EricLew 0:d4e5ad7ad71c 50 /*******************************************************************************
EricLew 0:d4e5ad7ad71c 51 * Hardware Abstraction Layer
EricLew 0:d4e5ad7ad71c 52 ******************************************************************************/
EricLew 0:d4e5ad7ad71c 53
EricLew 0:d4e5ad7ad71c 54
EricLew 0:d4e5ad7ad71c 55 /* ################### Compiler specific Intrinsics ########################### */
EricLew 0:d4e5ad7ad71c 56 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
EricLew 0:d4e5ad7ad71c 57 Access to dedicated SIMD instructions
EricLew 0:d4e5ad7ad71c 58 @{
EricLew 0:d4e5ad7ad71c 59 */
EricLew 0:d4e5ad7ad71c 60
EricLew 0:d4e5ad7ad71c 61 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
EricLew 0:d4e5ad7ad71c 62 /* ARM armcc specific functions */
EricLew 0:d4e5ad7ad71c 63 #define __SADD8 __sadd8
EricLew 0:d4e5ad7ad71c 64 #define __QADD8 __qadd8
EricLew 0:d4e5ad7ad71c 65 #define __SHADD8 __shadd8
EricLew 0:d4e5ad7ad71c 66 #define __UADD8 __uadd8
EricLew 0:d4e5ad7ad71c 67 #define __UQADD8 __uqadd8
EricLew 0:d4e5ad7ad71c 68 #define __UHADD8 __uhadd8
EricLew 0:d4e5ad7ad71c 69 #define __SSUB8 __ssub8
EricLew 0:d4e5ad7ad71c 70 #define __QSUB8 __qsub8
EricLew 0:d4e5ad7ad71c 71 #define __SHSUB8 __shsub8
EricLew 0:d4e5ad7ad71c 72 #define __USUB8 __usub8
EricLew 0:d4e5ad7ad71c 73 #define __UQSUB8 __uqsub8
EricLew 0:d4e5ad7ad71c 74 #define __UHSUB8 __uhsub8
EricLew 0:d4e5ad7ad71c 75 #define __SADD16 __sadd16
EricLew 0:d4e5ad7ad71c 76 #define __QADD16 __qadd16
EricLew 0:d4e5ad7ad71c 77 #define __SHADD16 __shadd16
EricLew 0:d4e5ad7ad71c 78 #define __UADD16 __uadd16
EricLew 0:d4e5ad7ad71c 79 #define __UQADD16 __uqadd16
EricLew 0:d4e5ad7ad71c 80 #define __UHADD16 __uhadd16
EricLew 0:d4e5ad7ad71c 81 #define __SSUB16 __ssub16
EricLew 0:d4e5ad7ad71c 82 #define __QSUB16 __qsub16
EricLew 0:d4e5ad7ad71c 83 #define __SHSUB16 __shsub16
EricLew 0:d4e5ad7ad71c 84 #define __USUB16 __usub16
EricLew 0:d4e5ad7ad71c 85 #define __UQSUB16 __uqsub16
EricLew 0:d4e5ad7ad71c 86 #define __UHSUB16 __uhsub16
EricLew 0:d4e5ad7ad71c 87 #define __SASX __sasx
EricLew 0:d4e5ad7ad71c 88 #define __QASX __qasx
EricLew 0:d4e5ad7ad71c 89 #define __SHASX __shasx
EricLew 0:d4e5ad7ad71c 90 #define __UASX __uasx
EricLew 0:d4e5ad7ad71c 91 #define __UQASX __uqasx
EricLew 0:d4e5ad7ad71c 92 #define __UHASX __uhasx
EricLew 0:d4e5ad7ad71c 93 #define __SSAX __ssax
EricLew 0:d4e5ad7ad71c 94 #define __QSAX __qsax
EricLew 0:d4e5ad7ad71c 95 #define __SHSAX __shsax
EricLew 0:d4e5ad7ad71c 96 #define __USAX __usax
EricLew 0:d4e5ad7ad71c 97 #define __UQSAX __uqsax
EricLew 0:d4e5ad7ad71c 98 #define __UHSAX __uhsax
EricLew 0:d4e5ad7ad71c 99 #define __USAD8 __usad8
EricLew 0:d4e5ad7ad71c 100 #define __USADA8 __usada8
EricLew 0:d4e5ad7ad71c 101 #define __SSAT16 __ssat16
EricLew 0:d4e5ad7ad71c 102 #define __USAT16 __usat16
EricLew 0:d4e5ad7ad71c 103 #define __UXTB16 __uxtb16
EricLew 0:d4e5ad7ad71c 104 #define __UXTAB16 __uxtab16
EricLew 0:d4e5ad7ad71c 105 #define __SXTB16 __sxtb16
EricLew 0:d4e5ad7ad71c 106 #define __SXTAB16 __sxtab16
EricLew 0:d4e5ad7ad71c 107 #define __SMUAD __smuad
EricLew 0:d4e5ad7ad71c 108 #define __SMUADX __smuadx
EricLew 0:d4e5ad7ad71c 109 #define __SMLAD __smlad
EricLew 0:d4e5ad7ad71c 110 #define __SMLADX __smladx
EricLew 0:d4e5ad7ad71c 111 #define __SMLALD __smlald
EricLew 0:d4e5ad7ad71c 112 #define __SMLALDX __smlaldx
EricLew 0:d4e5ad7ad71c 113 #define __SMUSD __smusd
EricLew 0:d4e5ad7ad71c 114 #define __SMUSDX __smusdx
EricLew 0:d4e5ad7ad71c 115 #define __SMLSD __smlsd
EricLew 0:d4e5ad7ad71c 116 #define __SMLSDX __smlsdx
EricLew 0:d4e5ad7ad71c 117 #define __SMLSLD __smlsld
EricLew 0:d4e5ad7ad71c 118 #define __SMLSLDX __smlsldx
EricLew 0:d4e5ad7ad71c 119 #define __SEL __sel
EricLew 0:d4e5ad7ad71c 120 #define __QADD __qadd
EricLew 0:d4e5ad7ad71c 121 #define __QSUB __qsub
EricLew 0:d4e5ad7ad71c 122
EricLew 0:d4e5ad7ad71c 123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
EricLew 0:d4e5ad7ad71c 124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
EricLew 0:d4e5ad7ad71c 125
EricLew 0:d4e5ad7ad71c 126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
EricLew 0:d4e5ad7ad71c 127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
EricLew 0:d4e5ad7ad71c 128
EricLew 0:d4e5ad7ad71c 129 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
EricLew 0:d4e5ad7ad71c 130 ((int64_t)(ARG3) << 32) ) >> 32))
EricLew 0:d4e5ad7ad71c 131
EricLew 0:d4e5ad7ad71c 132
EricLew 0:d4e5ad7ad71c 133 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
EricLew 0:d4e5ad7ad71c 134 /* GNU gcc specific functions */
EricLew 0:d4e5ad7ad71c 135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 136 {
EricLew 0:d4e5ad7ad71c 137 uint32_t result;
EricLew 0:d4e5ad7ad71c 138
EricLew 0:d4e5ad7ad71c 139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 140 return(result);
EricLew 0:d4e5ad7ad71c 141 }
EricLew 0:d4e5ad7ad71c 142
EricLew 0:d4e5ad7ad71c 143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 144 {
EricLew 0:d4e5ad7ad71c 145 uint32_t result;
EricLew 0:d4e5ad7ad71c 146
EricLew 0:d4e5ad7ad71c 147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 148 return(result);
EricLew 0:d4e5ad7ad71c 149 }
EricLew 0:d4e5ad7ad71c 150
EricLew 0:d4e5ad7ad71c 151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 152 {
EricLew 0:d4e5ad7ad71c 153 uint32_t result;
EricLew 0:d4e5ad7ad71c 154
EricLew 0:d4e5ad7ad71c 155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 156 return(result);
EricLew 0:d4e5ad7ad71c 157 }
EricLew 0:d4e5ad7ad71c 158
EricLew 0:d4e5ad7ad71c 159 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 160 {
EricLew 0:d4e5ad7ad71c 161 uint32_t result;
EricLew 0:d4e5ad7ad71c 162
EricLew 0:d4e5ad7ad71c 163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 164 return(result);
EricLew 0:d4e5ad7ad71c 165 }
EricLew 0:d4e5ad7ad71c 166
EricLew 0:d4e5ad7ad71c 167 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 168 {
EricLew 0:d4e5ad7ad71c 169 uint32_t result;
EricLew 0:d4e5ad7ad71c 170
EricLew 0:d4e5ad7ad71c 171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 172 return(result);
EricLew 0:d4e5ad7ad71c 173 }
EricLew 0:d4e5ad7ad71c 174
EricLew 0:d4e5ad7ad71c 175 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 176 {
EricLew 0:d4e5ad7ad71c 177 uint32_t result;
EricLew 0:d4e5ad7ad71c 178
EricLew 0:d4e5ad7ad71c 179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 180 return(result);
EricLew 0:d4e5ad7ad71c 181 }
EricLew 0:d4e5ad7ad71c 182
EricLew 0:d4e5ad7ad71c 183
EricLew 0:d4e5ad7ad71c 184 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 185 {
EricLew 0:d4e5ad7ad71c 186 uint32_t result;
EricLew 0:d4e5ad7ad71c 187
EricLew 0:d4e5ad7ad71c 188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 189 return(result);
EricLew 0:d4e5ad7ad71c 190 }
EricLew 0:d4e5ad7ad71c 191
EricLew 0:d4e5ad7ad71c 192 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 193 {
EricLew 0:d4e5ad7ad71c 194 uint32_t result;
EricLew 0:d4e5ad7ad71c 195
EricLew 0:d4e5ad7ad71c 196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 197 return(result);
EricLew 0:d4e5ad7ad71c 198 }
EricLew 0:d4e5ad7ad71c 199
EricLew 0:d4e5ad7ad71c 200 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 201 {
EricLew 0:d4e5ad7ad71c 202 uint32_t result;
EricLew 0:d4e5ad7ad71c 203
EricLew 0:d4e5ad7ad71c 204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 205 return(result);
EricLew 0:d4e5ad7ad71c 206 }
EricLew 0:d4e5ad7ad71c 207
EricLew 0:d4e5ad7ad71c 208 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 209 {
EricLew 0:d4e5ad7ad71c 210 uint32_t result;
EricLew 0:d4e5ad7ad71c 211
EricLew 0:d4e5ad7ad71c 212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 213 return(result);
EricLew 0:d4e5ad7ad71c 214 }
EricLew 0:d4e5ad7ad71c 215
EricLew 0:d4e5ad7ad71c 216 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 217 {
EricLew 0:d4e5ad7ad71c 218 uint32_t result;
EricLew 0:d4e5ad7ad71c 219
EricLew 0:d4e5ad7ad71c 220 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 221 return(result);
EricLew 0:d4e5ad7ad71c 222 }
EricLew 0:d4e5ad7ad71c 223
EricLew 0:d4e5ad7ad71c 224 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 225 {
EricLew 0:d4e5ad7ad71c 226 uint32_t result;
EricLew 0:d4e5ad7ad71c 227
EricLew 0:d4e5ad7ad71c 228 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 229 return(result);
EricLew 0:d4e5ad7ad71c 230 }
EricLew 0:d4e5ad7ad71c 231
EricLew 0:d4e5ad7ad71c 232
EricLew 0:d4e5ad7ad71c 233 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 234 {
EricLew 0:d4e5ad7ad71c 235 uint32_t result;
EricLew 0:d4e5ad7ad71c 236
EricLew 0:d4e5ad7ad71c 237 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 238 return(result);
EricLew 0:d4e5ad7ad71c 239 }
EricLew 0:d4e5ad7ad71c 240
EricLew 0:d4e5ad7ad71c 241 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 242 {
EricLew 0:d4e5ad7ad71c 243 uint32_t result;
EricLew 0:d4e5ad7ad71c 244
EricLew 0:d4e5ad7ad71c 245 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 246 return(result);
EricLew 0:d4e5ad7ad71c 247 }
EricLew 0:d4e5ad7ad71c 248
EricLew 0:d4e5ad7ad71c 249 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 250 {
EricLew 0:d4e5ad7ad71c 251 uint32_t result;
EricLew 0:d4e5ad7ad71c 252
EricLew 0:d4e5ad7ad71c 253 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 254 return(result);
EricLew 0:d4e5ad7ad71c 255 }
EricLew 0:d4e5ad7ad71c 256
EricLew 0:d4e5ad7ad71c 257 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 258 {
EricLew 0:d4e5ad7ad71c 259 uint32_t result;
EricLew 0:d4e5ad7ad71c 260
EricLew 0:d4e5ad7ad71c 261 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 262 return(result);
EricLew 0:d4e5ad7ad71c 263 }
EricLew 0:d4e5ad7ad71c 264
EricLew 0:d4e5ad7ad71c 265 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 266 {
EricLew 0:d4e5ad7ad71c 267 uint32_t result;
EricLew 0:d4e5ad7ad71c 268
EricLew 0:d4e5ad7ad71c 269 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 270 return(result);
EricLew 0:d4e5ad7ad71c 271 }
EricLew 0:d4e5ad7ad71c 272
EricLew 0:d4e5ad7ad71c 273 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 274 {
EricLew 0:d4e5ad7ad71c 275 uint32_t result;
EricLew 0:d4e5ad7ad71c 276
EricLew 0:d4e5ad7ad71c 277 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 278 return(result);
EricLew 0:d4e5ad7ad71c 279 }
EricLew 0:d4e5ad7ad71c 280
EricLew 0:d4e5ad7ad71c 281 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 282 {
EricLew 0:d4e5ad7ad71c 283 uint32_t result;
EricLew 0:d4e5ad7ad71c 284
EricLew 0:d4e5ad7ad71c 285 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 286 return(result);
EricLew 0:d4e5ad7ad71c 287 }
EricLew 0:d4e5ad7ad71c 288
EricLew 0:d4e5ad7ad71c 289 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 290 {
EricLew 0:d4e5ad7ad71c 291 uint32_t result;
EricLew 0:d4e5ad7ad71c 292
EricLew 0:d4e5ad7ad71c 293 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 294 return(result);
EricLew 0:d4e5ad7ad71c 295 }
EricLew 0:d4e5ad7ad71c 296
EricLew 0:d4e5ad7ad71c 297 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 298 {
EricLew 0:d4e5ad7ad71c 299 uint32_t result;
EricLew 0:d4e5ad7ad71c 300
EricLew 0:d4e5ad7ad71c 301 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 302 return(result);
EricLew 0:d4e5ad7ad71c 303 }
EricLew 0:d4e5ad7ad71c 304
EricLew 0:d4e5ad7ad71c 305 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 306 {
EricLew 0:d4e5ad7ad71c 307 uint32_t result;
EricLew 0:d4e5ad7ad71c 308
EricLew 0:d4e5ad7ad71c 309 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 310 return(result);
EricLew 0:d4e5ad7ad71c 311 }
EricLew 0:d4e5ad7ad71c 312
EricLew 0:d4e5ad7ad71c 313 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 314 {
EricLew 0:d4e5ad7ad71c 315 uint32_t result;
EricLew 0:d4e5ad7ad71c 316
EricLew 0:d4e5ad7ad71c 317 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 318 return(result);
EricLew 0:d4e5ad7ad71c 319 }
EricLew 0:d4e5ad7ad71c 320
EricLew 0:d4e5ad7ad71c 321 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 322 {
EricLew 0:d4e5ad7ad71c 323 uint32_t result;
EricLew 0:d4e5ad7ad71c 324
EricLew 0:d4e5ad7ad71c 325 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 326 return(result);
EricLew 0:d4e5ad7ad71c 327 }
EricLew 0:d4e5ad7ad71c 328
EricLew 0:d4e5ad7ad71c 329 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 330 {
EricLew 0:d4e5ad7ad71c 331 uint32_t result;
EricLew 0:d4e5ad7ad71c 332
EricLew 0:d4e5ad7ad71c 333 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 334 return(result);
EricLew 0:d4e5ad7ad71c 335 }
EricLew 0:d4e5ad7ad71c 336
EricLew 0:d4e5ad7ad71c 337 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 338 {
EricLew 0:d4e5ad7ad71c 339 uint32_t result;
EricLew 0:d4e5ad7ad71c 340
EricLew 0:d4e5ad7ad71c 341 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 342 return(result);
EricLew 0:d4e5ad7ad71c 343 }
EricLew 0:d4e5ad7ad71c 344
EricLew 0:d4e5ad7ad71c 345 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 346 {
EricLew 0:d4e5ad7ad71c 347 uint32_t result;
EricLew 0:d4e5ad7ad71c 348
EricLew 0:d4e5ad7ad71c 349 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 350 return(result);
EricLew 0:d4e5ad7ad71c 351 }
EricLew 0:d4e5ad7ad71c 352
EricLew 0:d4e5ad7ad71c 353 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 354 {
EricLew 0:d4e5ad7ad71c 355 uint32_t result;
EricLew 0:d4e5ad7ad71c 356
EricLew 0:d4e5ad7ad71c 357 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 358 return(result);
EricLew 0:d4e5ad7ad71c 359 }
EricLew 0:d4e5ad7ad71c 360
EricLew 0:d4e5ad7ad71c 361 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 362 {
EricLew 0:d4e5ad7ad71c 363 uint32_t result;
EricLew 0:d4e5ad7ad71c 364
EricLew 0:d4e5ad7ad71c 365 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 366 return(result);
EricLew 0:d4e5ad7ad71c 367 }
EricLew 0:d4e5ad7ad71c 368
EricLew 0:d4e5ad7ad71c 369 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 370 {
EricLew 0:d4e5ad7ad71c 371 uint32_t result;
EricLew 0:d4e5ad7ad71c 372
EricLew 0:d4e5ad7ad71c 373 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 374 return(result);
EricLew 0:d4e5ad7ad71c 375 }
EricLew 0:d4e5ad7ad71c 376
EricLew 0:d4e5ad7ad71c 377 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 378 {
EricLew 0:d4e5ad7ad71c 379 uint32_t result;
EricLew 0:d4e5ad7ad71c 380
EricLew 0:d4e5ad7ad71c 381 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 382 return(result);
EricLew 0:d4e5ad7ad71c 383 }
EricLew 0:d4e5ad7ad71c 384
EricLew 0:d4e5ad7ad71c 385 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 386 {
EricLew 0:d4e5ad7ad71c 387 uint32_t result;
EricLew 0:d4e5ad7ad71c 388
EricLew 0:d4e5ad7ad71c 389 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 390 return(result);
EricLew 0:d4e5ad7ad71c 391 }
EricLew 0:d4e5ad7ad71c 392
EricLew 0:d4e5ad7ad71c 393 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 394 {
EricLew 0:d4e5ad7ad71c 395 uint32_t result;
EricLew 0:d4e5ad7ad71c 396
EricLew 0:d4e5ad7ad71c 397 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 398 return(result);
EricLew 0:d4e5ad7ad71c 399 }
EricLew 0:d4e5ad7ad71c 400
EricLew 0:d4e5ad7ad71c 401 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 402 {
EricLew 0:d4e5ad7ad71c 403 uint32_t result;
EricLew 0:d4e5ad7ad71c 404
EricLew 0:d4e5ad7ad71c 405 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 406 return(result);
EricLew 0:d4e5ad7ad71c 407 }
EricLew 0:d4e5ad7ad71c 408
EricLew 0:d4e5ad7ad71c 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 410 {
EricLew 0:d4e5ad7ad71c 411 uint32_t result;
EricLew 0:d4e5ad7ad71c 412
EricLew 0:d4e5ad7ad71c 413 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 414 return(result);
EricLew 0:d4e5ad7ad71c 415 }
EricLew 0:d4e5ad7ad71c 416
EricLew 0:d4e5ad7ad71c 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 418 {
EricLew 0:d4e5ad7ad71c 419 uint32_t result;
EricLew 0:d4e5ad7ad71c 420
EricLew 0:d4e5ad7ad71c 421 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 422 return(result);
EricLew 0:d4e5ad7ad71c 423 }
EricLew 0:d4e5ad7ad71c 424
EricLew 0:d4e5ad7ad71c 425 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 426 {
EricLew 0:d4e5ad7ad71c 427 uint32_t result;
EricLew 0:d4e5ad7ad71c 428
EricLew 0:d4e5ad7ad71c 429 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 430 return(result);
EricLew 0:d4e5ad7ad71c 431 }
EricLew 0:d4e5ad7ad71c 432
EricLew 0:d4e5ad7ad71c 433 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
EricLew 0:d4e5ad7ad71c 434 {
EricLew 0:d4e5ad7ad71c 435 uint32_t result;
EricLew 0:d4e5ad7ad71c 436
EricLew 0:d4e5ad7ad71c 437 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
EricLew 0:d4e5ad7ad71c 438 return(result);
EricLew 0:d4e5ad7ad71c 439 }
EricLew 0:d4e5ad7ad71c 440
EricLew 0:d4e5ad7ad71c 441 #define __SSAT16(ARG1,ARG2) \
EricLew 0:d4e5ad7ad71c 442 ({ \
EricLew 0:d4e5ad7ad71c 443 uint32_t __RES, __ARG1 = (ARG1); \
EricLew 0:d4e5ad7ad71c 444 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
EricLew 0:d4e5ad7ad71c 445 __RES; \
EricLew 0:d4e5ad7ad71c 446 })
EricLew 0:d4e5ad7ad71c 447
EricLew 0:d4e5ad7ad71c 448 #define __USAT16(ARG1,ARG2) \
EricLew 0:d4e5ad7ad71c 449 ({ \
EricLew 0:d4e5ad7ad71c 450 uint32_t __RES, __ARG1 = (ARG1); \
EricLew 0:d4e5ad7ad71c 451 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
EricLew 0:d4e5ad7ad71c 452 __RES; \
EricLew 0:d4e5ad7ad71c 453 })
EricLew 0:d4e5ad7ad71c 454
EricLew 0:d4e5ad7ad71c 455 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
EricLew 0:d4e5ad7ad71c 456 {
EricLew 0:d4e5ad7ad71c 457 uint32_t result;
EricLew 0:d4e5ad7ad71c 458
EricLew 0:d4e5ad7ad71c 459 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
EricLew 0:d4e5ad7ad71c 460 return(result);
EricLew 0:d4e5ad7ad71c 461 }
EricLew 0:d4e5ad7ad71c 462
EricLew 0:d4e5ad7ad71c 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 464 {
EricLew 0:d4e5ad7ad71c 465 uint32_t result;
EricLew 0:d4e5ad7ad71c 466
EricLew 0:d4e5ad7ad71c 467 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 468 return(result);
EricLew 0:d4e5ad7ad71c 469 }
EricLew 0:d4e5ad7ad71c 470
EricLew 0:d4e5ad7ad71c 471 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
EricLew 0:d4e5ad7ad71c 472 {
EricLew 0:d4e5ad7ad71c 473 uint32_t result;
EricLew 0:d4e5ad7ad71c 474
EricLew 0:d4e5ad7ad71c 475 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
EricLew 0:d4e5ad7ad71c 476 return(result);
EricLew 0:d4e5ad7ad71c 477 }
EricLew 0:d4e5ad7ad71c 478
EricLew 0:d4e5ad7ad71c 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 480 {
EricLew 0:d4e5ad7ad71c 481 uint32_t result;
EricLew 0:d4e5ad7ad71c 482
EricLew 0:d4e5ad7ad71c 483 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 484 return(result);
EricLew 0:d4e5ad7ad71c 485 }
EricLew 0:d4e5ad7ad71c 486
EricLew 0:d4e5ad7ad71c 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 488 {
EricLew 0:d4e5ad7ad71c 489 uint32_t result;
EricLew 0:d4e5ad7ad71c 490
EricLew 0:d4e5ad7ad71c 491 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 492 return(result);
EricLew 0:d4e5ad7ad71c 493 }
EricLew 0:d4e5ad7ad71c 494
EricLew 0:d4e5ad7ad71c 495 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 496 {
EricLew 0:d4e5ad7ad71c 497 uint32_t result;
EricLew 0:d4e5ad7ad71c 498
EricLew 0:d4e5ad7ad71c 499 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 500 return(result);
EricLew 0:d4e5ad7ad71c 501 }
EricLew 0:d4e5ad7ad71c 502
EricLew 0:d4e5ad7ad71c 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
EricLew 0:d4e5ad7ad71c 504 {
EricLew 0:d4e5ad7ad71c 505 uint32_t result;
EricLew 0:d4e5ad7ad71c 506
EricLew 0:d4e5ad7ad71c 507 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
EricLew 0:d4e5ad7ad71c 508 return(result);
EricLew 0:d4e5ad7ad71c 509 }
EricLew 0:d4e5ad7ad71c 510
EricLew 0:d4e5ad7ad71c 511 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
EricLew 0:d4e5ad7ad71c 512 {
EricLew 0:d4e5ad7ad71c 513 uint32_t result;
EricLew 0:d4e5ad7ad71c 514
EricLew 0:d4e5ad7ad71c 515 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
EricLew 0:d4e5ad7ad71c 516 return(result);
EricLew 0:d4e5ad7ad71c 517 }
EricLew 0:d4e5ad7ad71c 518
EricLew 0:d4e5ad7ad71c 519 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
EricLew 0:d4e5ad7ad71c 520 {
EricLew 0:d4e5ad7ad71c 521 union llreg_u{
EricLew 0:d4e5ad7ad71c 522 uint32_t w32[2];
EricLew 0:d4e5ad7ad71c 523 uint64_t w64;
EricLew 0:d4e5ad7ad71c 524 } llr;
EricLew 0:d4e5ad7ad71c 525 llr.w64 = acc;
EricLew 0:d4e5ad7ad71c 526
EricLew 0:d4e5ad7ad71c 527 #ifndef __ARMEB__ // Little endian
EricLew 0:d4e5ad7ad71c 528 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
EricLew 0:d4e5ad7ad71c 529 #else // Big endian
EricLew 0:d4e5ad7ad71c 530 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
EricLew 0:d4e5ad7ad71c 531 #endif
EricLew 0:d4e5ad7ad71c 532
EricLew 0:d4e5ad7ad71c 533 return(llr.w64);
EricLew 0:d4e5ad7ad71c 534 }
EricLew 0:d4e5ad7ad71c 535
EricLew 0:d4e5ad7ad71c 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
EricLew 0:d4e5ad7ad71c 537 {
EricLew 0:d4e5ad7ad71c 538 union llreg_u{
EricLew 0:d4e5ad7ad71c 539 uint32_t w32[2];
EricLew 0:d4e5ad7ad71c 540 uint64_t w64;
EricLew 0:d4e5ad7ad71c 541 } llr;
EricLew 0:d4e5ad7ad71c 542 llr.w64 = acc;
EricLew 0:d4e5ad7ad71c 543
EricLew 0:d4e5ad7ad71c 544 #ifndef __ARMEB__ // Little endian
EricLew 0:d4e5ad7ad71c 545 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
EricLew 0:d4e5ad7ad71c 546 #else // Big endian
EricLew 0:d4e5ad7ad71c 547 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
EricLew 0:d4e5ad7ad71c 548 #endif
EricLew 0:d4e5ad7ad71c 549
EricLew 0:d4e5ad7ad71c 550 return(llr.w64);
EricLew 0:d4e5ad7ad71c 551 }
EricLew 0:d4e5ad7ad71c 552
EricLew 0:d4e5ad7ad71c 553 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 554 {
EricLew 0:d4e5ad7ad71c 555 uint32_t result;
EricLew 0:d4e5ad7ad71c 556
EricLew 0:d4e5ad7ad71c 557 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 558 return(result);
EricLew 0:d4e5ad7ad71c 559 }
EricLew 0:d4e5ad7ad71c 560
EricLew 0:d4e5ad7ad71c 561 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 562 {
EricLew 0:d4e5ad7ad71c 563 uint32_t result;
EricLew 0:d4e5ad7ad71c 564
EricLew 0:d4e5ad7ad71c 565 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 566 return(result);
EricLew 0:d4e5ad7ad71c 567 }
EricLew 0:d4e5ad7ad71c 568
EricLew 0:d4e5ad7ad71c 569 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
EricLew 0:d4e5ad7ad71c 570 {
EricLew 0:d4e5ad7ad71c 571 uint32_t result;
EricLew 0:d4e5ad7ad71c 572
EricLew 0:d4e5ad7ad71c 573 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
EricLew 0:d4e5ad7ad71c 574 return(result);
EricLew 0:d4e5ad7ad71c 575 }
EricLew 0:d4e5ad7ad71c 576
EricLew 0:d4e5ad7ad71c 577 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
EricLew 0:d4e5ad7ad71c 578 {
EricLew 0:d4e5ad7ad71c 579 uint32_t result;
EricLew 0:d4e5ad7ad71c 580
EricLew 0:d4e5ad7ad71c 581 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
EricLew 0:d4e5ad7ad71c 582 return(result);
EricLew 0:d4e5ad7ad71c 583 }
EricLew 0:d4e5ad7ad71c 584
EricLew 0:d4e5ad7ad71c 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
EricLew 0:d4e5ad7ad71c 586 {
EricLew 0:d4e5ad7ad71c 587 union llreg_u{
EricLew 0:d4e5ad7ad71c 588 uint32_t w32[2];
EricLew 0:d4e5ad7ad71c 589 uint64_t w64;
EricLew 0:d4e5ad7ad71c 590 } llr;
EricLew 0:d4e5ad7ad71c 591 llr.w64 = acc;
EricLew 0:d4e5ad7ad71c 592
EricLew 0:d4e5ad7ad71c 593 #ifndef __ARMEB__ // Little endian
EricLew 0:d4e5ad7ad71c 594 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
EricLew 0:d4e5ad7ad71c 595 #else // Big endian
EricLew 0:d4e5ad7ad71c 596 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
EricLew 0:d4e5ad7ad71c 597 #endif
EricLew 0:d4e5ad7ad71c 598
EricLew 0:d4e5ad7ad71c 599 return(llr.w64);
EricLew 0:d4e5ad7ad71c 600 }
EricLew 0:d4e5ad7ad71c 601
EricLew 0:d4e5ad7ad71c 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
EricLew 0:d4e5ad7ad71c 603 {
EricLew 0:d4e5ad7ad71c 604 union llreg_u{
EricLew 0:d4e5ad7ad71c 605 uint32_t w32[2];
EricLew 0:d4e5ad7ad71c 606 uint64_t w64;
EricLew 0:d4e5ad7ad71c 607 } llr;
EricLew 0:d4e5ad7ad71c 608 llr.w64 = acc;
EricLew 0:d4e5ad7ad71c 609
EricLew 0:d4e5ad7ad71c 610 #ifndef __ARMEB__ // Little endian
EricLew 0:d4e5ad7ad71c 611 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
EricLew 0:d4e5ad7ad71c 612 #else // Big endian
EricLew 0:d4e5ad7ad71c 613 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
EricLew 0:d4e5ad7ad71c 614 #endif
EricLew 0:d4e5ad7ad71c 615
EricLew 0:d4e5ad7ad71c 616 return(llr.w64);
EricLew 0:d4e5ad7ad71c 617 }
EricLew 0:d4e5ad7ad71c 618
EricLew 0:d4e5ad7ad71c 619 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 620 {
EricLew 0:d4e5ad7ad71c 621 uint32_t result;
EricLew 0:d4e5ad7ad71c 622
EricLew 0:d4e5ad7ad71c 623 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 624 return(result);
EricLew 0:d4e5ad7ad71c 625 }
EricLew 0:d4e5ad7ad71c 626
EricLew 0:d4e5ad7ad71c 627 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 628 {
EricLew 0:d4e5ad7ad71c 629 uint32_t result;
EricLew 0:d4e5ad7ad71c 630
EricLew 0:d4e5ad7ad71c 631 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 632 return(result);
EricLew 0:d4e5ad7ad71c 633 }
EricLew 0:d4e5ad7ad71c 634
EricLew 0:d4e5ad7ad71c 635 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 636 {
EricLew 0:d4e5ad7ad71c 637 uint32_t result;
EricLew 0:d4e5ad7ad71c 638
EricLew 0:d4e5ad7ad71c 639 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:d4e5ad7ad71c 640 return(result);
EricLew 0:d4e5ad7ad71c 641 }
EricLew 0:d4e5ad7ad71c 642
EricLew 0:d4e5ad7ad71c 643 #define __PKHBT(ARG1,ARG2,ARG3) \
EricLew 0:d4e5ad7ad71c 644 ({ \
EricLew 0:d4e5ad7ad71c 645 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
EricLew 0:d4e5ad7ad71c 646 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
EricLew 0:d4e5ad7ad71c 647 __RES; \
EricLew 0:d4e5ad7ad71c 648 })
EricLew 0:d4e5ad7ad71c 649
EricLew 0:d4e5ad7ad71c 650 #define __PKHTB(ARG1,ARG2,ARG3) \
EricLew 0:d4e5ad7ad71c 651 ({ \
EricLew 0:d4e5ad7ad71c 652 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
EricLew 0:d4e5ad7ad71c 653 if (ARG3 == 0) \
EricLew 0:d4e5ad7ad71c 654 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
EricLew 0:d4e5ad7ad71c 655 else \
EricLew 0:d4e5ad7ad71c 656 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
EricLew 0:d4e5ad7ad71c 657 __RES; \
EricLew 0:d4e5ad7ad71c 658 })
EricLew 0:d4e5ad7ad71c 659
EricLew 0:d4e5ad7ad71c 660 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
EricLew 0:d4e5ad7ad71c 661 {
EricLew 0:d4e5ad7ad71c 662 int32_t result;
EricLew 0:d4e5ad7ad71c 663
EricLew 0:d4e5ad7ad71c 664 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
EricLew 0:d4e5ad7ad71c 665 return(result);
EricLew 0:d4e5ad7ad71c 666 }
EricLew 0:d4e5ad7ad71c 667
EricLew 0:d4e5ad7ad71c 668
EricLew 0:d4e5ad7ad71c 669 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
EricLew 0:d4e5ad7ad71c 670 /* IAR iccarm specific functions */
EricLew 0:d4e5ad7ad71c 671 #include <cmsis_iar.h>
EricLew 0:d4e5ad7ad71c 672
EricLew 0:d4e5ad7ad71c 673
EricLew 0:d4e5ad7ad71c 674 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
EricLew 0:d4e5ad7ad71c 675 /* TI CCS specific functions */
EricLew 0:d4e5ad7ad71c 676 #include <cmsis_ccs.h>
EricLew 0:d4e5ad7ad71c 677
EricLew 0:d4e5ad7ad71c 678
EricLew 0:d4e5ad7ad71c 679 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
EricLew 0:d4e5ad7ad71c 680 /* TASKING carm specific functions */
EricLew 0:d4e5ad7ad71c 681 /* not yet supported */
EricLew 0:d4e5ad7ad71c 682
EricLew 0:d4e5ad7ad71c 683
EricLew 0:d4e5ad7ad71c 684 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
EricLew 0:d4e5ad7ad71c 685 /* Cosmic specific functions */
EricLew 0:d4e5ad7ad71c 686 #include <cmsis_csm.h>
EricLew 0:d4e5ad7ad71c 687
EricLew 0:d4e5ad7ad71c 688 #endif
EricLew 0:d4e5ad7ad71c 689
EricLew 0:d4e5ad7ad71c 690 /*@} end of group CMSIS_SIMD_intrinsics */
EricLew 0:d4e5ad7ad71c 691
EricLew 0:d4e5ad7ad71c 692
EricLew 0:d4e5ad7ad71c 693 #ifdef __cplusplus
EricLew 0:d4e5ad7ad71c 694 }
EricLew 0:d4e5ad7ad71c 695 #endif
EricLew 0:d4e5ad7ad71c 696
EricLew 0:d4e5ad7ad71c 697 #endif /* __CORE_CMSIMD_H */
EricLew 0:d4e5ad7ad71c 698