Senior Design: Sound Monitor / FINAL_AUDIO_RECORD

AudioRecord and FFT/MSE comparison. Call AudioRecord_demo for control record and AudioSample for subsequent recordings.

Dependencies:   CMSIS_DSP_401 STM32L4xx_HAL_Driver

Fork of OneHopeOnePrayer by Senior Design: Sound Monitor

Main.c@5:f6afbd3fc47a, 2015-12-05 (annotated)

Committer:
EricLew
Date:
Sat Dec 05 16:17:25 2015 +0000
Revision:
5:f6afbd3fc47a
Parent:
4:652cb54276d0 
Ported to Nucleo

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:d4e5ad7ad71c 1 #include "main.h"
EricLew 0:d4e5ad7ad71c 2
EricLew 4:652cb54276d0 3 uint32_t fftSize = 2048;
EricLew 4:652cb54276d0 4 uint32_t ifftFlag = 0;
EricLew 5:f6afbd3fc47a 5 uint32_t doBitReverse = 0;
EricLew 0:d4e5ad7ad71c 6
EricLew 4:652cb54276d0 7 extern float32_t PWRCONTROLMSE; //CONTROL POWER MSE
EricLew 4:652cb54276d0 8 extern float32_t PHSCONTROLMSE; //CONTROL PHASE MSE
EricLew 4:652cb54276d0 9 extern float32_t CONTROLPWR0[512]; //CONTROL RECRODING 0 MAGNITUDE
EricLew 4:652cb54276d0 10 extern float32_t CONTROLPHASE0[512];//CONTROL RECORDING 0 PHASE
EricLew 0:d4e5ad7ad71c 11
EricLew 4:652cb54276d0 12 extern float32_t DISPLAYFFT[512];
EricLew 0:d4e5ad7ad71c 13
EricLew 4:652cb54276d0 14 extern void AudioRecord_demo(void);
EricLew 4:652cb54276d0 15 extern void AudioSample(void);
EricLew 0:d4e5ad7ad71c 16
EricLew 0:d4e5ad7ad71c 17 int main(void)
EricLew 0:d4e5ad7ad71c 18 {
EricLew 4:652cb54276d0 19 HAL_Init();
EricLew 0:d4e5ad7ad71c 20
EricLew 4:652cb54276d0 21 SystemClock_Config();
EricLew 4:652cb54276d0 22
EricLew 4:652cb54276d0 23 //RECORDS AND COMPARES CONTROL SAMPLES
EricLew 4:652cb54276d0 24 AudioRecord_demo();
EricLew 4:652cb54276d0 25
EricLew 4:652cb54276d0 26 //RECORDS AND COMPARES 1 SAMPLE TO CONTROL SAMPLE
EricLew 4:652cb54276d0 27 AudioSample();
EricLew 4:652cb54276d0 28
EricLew 4:652cb54276d0 29 AudioSample();
EricLew 4:652cb54276d0 30 while(1)
EricLew 4:652cb54276d0 31 {}
EricLew 0:d4e5ad7ad71c 32
EricLew 0:d4e5ad7ad71c 33 }
EricLew 0:d4e5ad7ad71c 34 void SystemClock_Config(void)
EricLew 0:d4e5ad7ad71c 35 {
EricLew 0:d4e5ad7ad71c 36 /* oscillator and clocks configs */
EricLew 0:d4e5ad7ad71c 37 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
EricLew 0:d4e5ad7ad71c 38 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
EricLew 0:d4e5ad7ad71c 39
EricLew 0:d4e5ad7ad71c 40 /* The voltage scaling allows optimizing the power consumption when the device is
EricLew 0:d4e5ad7ad71c 41 clocked below the maximum system frequency, to update the voltage scaling value
EricLew 0:d4e5ad7ad71c 42 regarding system frequency refer to product datasheet. */
EricLew 0:d4e5ad7ad71c 43
EricLew 0:d4e5ad7ad71c 44 /* Enable Power Control clock */
EricLew 0:d4e5ad7ad71c 45 __HAL_RCC_PWR_CLK_ENABLE();
EricLew 0:d4e5ad7ad71c 46
EricLew 4:652cb54276d0 47 HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
EricLew 4:652cb54276d0 48
EricLew 0:d4e5ad7ad71c 49 /* Disable Power Control clock */
EricLew 0:d4e5ad7ad71c 50 __HAL_RCC_PWR_CLK_DISABLE();
EricLew 0:d4e5ad7ad71c 51
EricLew 0:d4e5ad7ad71c 52 /* 80 Mhz from MSI 8Mhz */
EricLew 0:d4e5ad7ad71c 53 /* MSI is enabled after System reset, activate PLL with MSI as source */
EricLew 0:d4e5ad7ad71c 54 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
EricLew 0:d4e5ad7ad71c 55 RCC_OscInitStruct.MSIState = RCC_MSI_ON;
EricLew 0:d4e5ad7ad71c 56 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_7;
EricLew 0:d4e5ad7ad71c 57 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
EricLew 0:d4e5ad7ad71c 58 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
EricLew 0:d4e5ad7ad71c 59 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
EricLew 0:d4e5ad7ad71c 60 RCC_OscInitStruct.PLL.PLLM = 1;
EricLew 0:d4e5ad7ad71c 61 RCC_OscInitStruct.PLL.PLLN = 20;
EricLew 0:d4e5ad7ad71c 62 RCC_OscInitStruct.PLL.PLLR = 2;
EricLew 0:d4e5ad7ad71c 63 RCC_OscInitStruct.PLL.PLLP = 7;
EricLew 0:d4e5ad7ad71c 64 RCC_OscInitStruct.PLL.PLLQ = 4;
EricLew 0:d4e5ad7ad71c 65
EricLew 4:652cb54276d0 66 HAL_RCC_OscConfig(&RCC_OscInitStruct);
EricLew 4:652cb54276d0 67
EricLew 0:d4e5ad7ad71c 68
EricLew 0:d4e5ad7ad71c 69 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
EricLew 0:d4e5ad7ad71c 70 clocks dividers */
EricLew 0:d4e5ad7ad71c 71 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
EricLew 0:d4e5ad7ad71c 72 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
EricLew 0:d4e5ad7ad71c 73 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
EricLew 0:d4e5ad7ad71c 74 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
EricLew 0:d4e5ad7ad71c 75 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
EricLew 4:652cb54276d0 76 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
EricLew 0:d4e5ad7ad71c 77
EricLew 0:d4e5ad7ad71c 78 /* The voltage scaling allows optimizing the power consumption when the device is
EricLew 0:d4e5ad7ad71c 79 clocked below the maximum system frequency, to update the voltage scaling value
EricLew 0:d4e5ad7ad71c 80 regarding system frequency refer to product datasheet. */
EricLew 0:d4e5ad7ad71c 81
EricLew 0:d4e5ad7ad71c 82 /* Enable Power Control clock */
EricLew 0:d4e5ad7ad71c 83 __HAL_RCC_PWR_CLK_ENABLE();
EricLew 0:d4e5ad7ad71c 84
EricLew 4:652cb54276d0 85 HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
EricLew 0:d4e5ad7ad71c 86
EricLew 0:d4e5ad7ad71c 87 /* Disable Power Control clock */
EricLew 0:d4e5ad7ad71c 88 __HAL_RCC_PWR_CLK_DISABLE();
EricLew 0:d4e5ad7ad71c 89 }