Senior Design: Sound Monitor / BSP

BSP Drivers

Dependencies:   CMSIS_STM32L4xx CMSIS_DSP_401 STM32L4xx_HAL_Driver

Dependents:   DiscoAudioRecord

Components/n25q128a/n25q128a.h@4:a1219ef3537f, 2015-11-22 (annotated)

Committer:
EricLew
Date:
Sun Nov 22 21:15:34 2015 +0000
Revision:
4:a1219ef3537f
Parent:
0:ad9dfc0179dc 
11/22/2015

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:ad9dfc0179dc 1 /**
EricLew 0:ad9dfc0179dc 2 ******************************************************************************
EricLew 0:ad9dfc0179dc 3 * @file n25q128a.h
EricLew 0:ad9dfc0179dc 4 * @author MCD Application Team
EricLew 0:ad9dfc0179dc 5 * @version V1.0.0
EricLew 0:ad9dfc0179dc 6 * @date 29-May-2015
EricLew 0:ad9dfc0179dc 7 * @brief This file contains all the description of the N25Q128A QSPI memory.
EricLew 0:ad9dfc0179dc 8 ******************************************************************************
EricLew 0:ad9dfc0179dc 9 * @attention
EricLew 0:ad9dfc0179dc 10 *
EricLew 0:ad9dfc0179dc 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew 0:ad9dfc0179dc 12 *
EricLew 0:ad9dfc0179dc 13 * Redistribution and use in source and binary forms, with or without modification,
EricLew 0:ad9dfc0179dc 14 * are permitted provided that the following conditions are met:
EricLew 0:ad9dfc0179dc 15 * 1. Redistributions of source code must retain the above copyright notice,
EricLew 0:ad9dfc0179dc 16 * this list of conditions and the following disclaimer.
EricLew 0:ad9dfc0179dc 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew 0:ad9dfc0179dc 18 * this list of conditions and the following disclaimer in the documentation
EricLew 0:ad9dfc0179dc 19 * and/or other materials provided with the distribution.
EricLew 0:ad9dfc0179dc 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew 0:ad9dfc0179dc 21 * may be used to endorse or promote products derived from this software
EricLew 0:ad9dfc0179dc 22 * without specific prior written permission.
EricLew 0:ad9dfc0179dc 23 *
EricLew 0:ad9dfc0179dc 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:ad9dfc0179dc 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:ad9dfc0179dc 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew 0:ad9dfc0179dc 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew 0:ad9dfc0179dc 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew 0:ad9dfc0179dc 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew 0:ad9dfc0179dc 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew 0:ad9dfc0179dc 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew 0:ad9dfc0179dc 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew 0:ad9dfc0179dc 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew 0:ad9dfc0179dc 34 *
EricLew 0:ad9dfc0179dc 35 ******************************************************************************
EricLew 0:ad9dfc0179dc 36 */
EricLew 0:ad9dfc0179dc 37
EricLew 0:ad9dfc0179dc 38 /* Define to prevent recursive inclusion -------------------------------------*/
EricLew 0:ad9dfc0179dc 39 #ifndef __N25Q128A_H
EricLew 0:ad9dfc0179dc 40 #define __N25Q128A_H
EricLew 0:ad9dfc0179dc 41
EricLew 0:ad9dfc0179dc 42 #ifdef __cplusplus
EricLew 0:ad9dfc0179dc 43 extern "C" {
EricLew 0:ad9dfc0179dc 44 #endif
EricLew 0:ad9dfc0179dc 45
EricLew 0:ad9dfc0179dc 46 /* Includes ------------------------------------------------------------------*/
EricLew 0:ad9dfc0179dc 47
EricLew 0:ad9dfc0179dc 48 /** @addtogroup BSP
EricLew 0:ad9dfc0179dc 49 * @{
EricLew 0:ad9dfc0179dc 50 */
EricLew 0:ad9dfc0179dc 51
EricLew 0:ad9dfc0179dc 52 /** @addtogroup Components
EricLew 0:ad9dfc0179dc 53 * @{
EricLew 0:ad9dfc0179dc 54 */
EricLew 0:ad9dfc0179dc 55
EricLew 0:ad9dfc0179dc 56 /** @addtogroup n25q128a
EricLew 0:ad9dfc0179dc 57 * @{
EricLew 0:ad9dfc0179dc 58 */
EricLew 0:ad9dfc0179dc 59
EricLew 0:ad9dfc0179dc 60 /** @defgroup N25Q128A_Exported_Types
EricLew 0:ad9dfc0179dc 61 * @{
EricLew 0:ad9dfc0179dc 62 */
EricLew 0:ad9dfc0179dc 63
EricLew 0:ad9dfc0179dc 64 /**
EricLew 0:ad9dfc0179dc 65 * @}
EricLew 0:ad9dfc0179dc 66 */
EricLew 0:ad9dfc0179dc 67
EricLew 0:ad9dfc0179dc 68 /** @defgroup N25Q128A_Exported_Constants
EricLew 0:ad9dfc0179dc 69 * @{
EricLew 0:ad9dfc0179dc 70 */
EricLew 0:ad9dfc0179dc 71
EricLew 0:ad9dfc0179dc 72 /**
EricLew 0:ad9dfc0179dc 73 * @brief N25Q128A Configuration
EricLew 0:ad9dfc0179dc 74 */
EricLew 0:ad9dfc0179dc 75 #define N25Q128A_FLASH_SIZE 0x1000000 /* 128 MBits => 16MBytes */
EricLew 0:ad9dfc0179dc 76 #define N25Q128A_SECTOR_SIZE 0x10000 /* 256 sectors of 64KBytes */
EricLew 0:ad9dfc0179dc 77 #define N25Q128A_SUBSECTOR_SIZE 0x1000 /* 4096 subsectors of 4kBytes */
EricLew 0:ad9dfc0179dc 78 #define N25Q128A_PAGE_SIZE 0x100 /* 65536 pages of 256 bytes */
EricLew 0:ad9dfc0179dc 79
EricLew 0:ad9dfc0179dc 80 #define N25Q128A_DUMMY_CYCLES_READ 8
EricLew 0:ad9dfc0179dc 81 #define N25Q128A_DUMMY_CYCLES_READ_QUAD 10
EricLew 0:ad9dfc0179dc 82
EricLew 0:ad9dfc0179dc 83 #define N25Q128A_BULK_ERASE_MAX_TIME 250000
EricLew 0:ad9dfc0179dc 84 #define N25Q128A_SECTOR_ERASE_MAX_TIME 3000
EricLew 0:ad9dfc0179dc 85 #define N25Q128A_SUBSECTOR_ERASE_MAX_TIME 800
EricLew 0:ad9dfc0179dc 86
EricLew 0:ad9dfc0179dc 87 /**
EricLew 0:ad9dfc0179dc 88 * @brief N25Q128A Commands
EricLew 0:ad9dfc0179dc 89 */
EricLew 0:ad9dfc0179dc 90 /* Reset Operations */
EricLew 0:ad9dfc0179dc 91 #define RESET_ENABLE_CMD 0x66
EricLew 0:ad9dfc0179dc 92 #define RESET_MEMORY_CMD 0x99
EricLew 0:ad9dfc0179dc 93
EricLew 0:ad9dfc0179dc 94 /* Identification Operations */
EricLew 0:ad9dfc0179dc 95 #define READ_ID_CMD 0x9E
EricLew 0:ad9dfc0179dc 96 #define READ_ID_CMD2 0x9F
EricLew 0:ad9dfc0179dc 97 #define MULTIPLE_IO_READ_ID_CMD 0xAF
EricLew 0:ad9dfc0179dc 98 #define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A
EricLew 0:ad9dfc0179dc 99
EricLew 0:ad9dfc0179dc 100 /* Read Operations */
EricLew 0:ad9dfc0179dc 101 #define READ_CMD 0x03
EricLew 0:ad9dfc0179dc 102 #define FAST_READ_CMD 0x0B
EricLew 0:ad9dfc0179dc 103 #define DUAL_OUT_FAST_READ_CMD 0x3B
EricLew 0:ad9dfc0179dc 104 #define DUAL_INOUT_FAST_READ_CMD 0xBB
EricLew 0:ad9dfc0179dc 105 #define QUAD_OUT_FAST_READ_CMD 0x6B
EricLew 0:ad9dfc0179dc 106 #define QUAD_INOUT_FAST_READ_CMD 0xEB
EricLew 0:ad9dfc0179dc 107
EricLew 0:ad9dfc0179dc 108 /* Write Operations */
EricLew 0:ad9dfc0179dc 109 #define WRITE_ENABLE_CMD 0x06
EricLew 0:ad9dfc0179dc 110 #define WRITE_DISABLE_CMD 0x04
EricLew 0:ad9dfc0179dc 111
EricLew 0:ad9dfc0179dc 112 /* Register Operations */
EricLew 0:ad9dfc0179dc 113 #define READ_STATUS_REG_CMD 0x05
EricLew 0:ad9dfc0179dc 114 #define WRITE_STATUS_REG_CMD 0x01
EricLew 0:ad9dfc0179dc 115
EricLew 0:ad9dfc0179dc 116 #define READ_LOCK_REG_CMD 0xE8
EricLew 0:ad9dfc0179dc 117 #define WRITE_LOCK_REG_CMD 0xE5
EricLew 0:ad9dfc0179dc 118
EricLew 0:ad9dfc0179dc 119 #define READ_FLAG_STATUS_REG_CMD 0x70
EricLew 0:ad9dfc0179dc 120 #define CLEAR_FLAG_STATUS_REG_CMD 0x50
EricLew 0:ad9dfc0179dc 121
EricLew 0:ad9dfc0179dc 122 #define READ_NONVOL_CFG_REG_CMD 0xB5
EricLew 0:ad9dfc0179dc 123 #define WRITE_NONVOL_CFG_REG_CMD 0xB1
EricLew 0:ad9dfc0179dc 124
EricLew 0:ad9dfc0179dc 125 #define READ_VOL_CFG_REG_CMD 0x85
EricLew 0:ad9dfc0179dc 126 #define WRITE_VOL_CFG_REG_CMD 0x81
EricLew 0:ad9dfc0179dc 127
EricLew 0:ad9dfc0179dc 128 #define READ_ENHANCED_VOL_CFG_REG_CMD 0x65
EricLew 0:ad9dfc0179dc 129 #define WRITE_ENHANCED_VOL_CFG_REG_CMD 0x61
EricLew 0:ad9dfc0179dc 130
EricLew 0:ad9dfc0179dc 131 /* Program Operations */
EricLew 0:ad9dfc0179dc 132 #define PAGE_PROG_CMD 0x02
EricLew 0:ad9dfc0179dc 133 #define DUAL_IN_FAST_PROG_CMD 0xA2
EricLew 0:ad9dfc0179dc 134 #define EXT_DUAL_IN_FAST_PROG_CMD 0xD2
EricLew 0:ad9dfc0179dc 135 #define QUAD_IN_FAST_PROG_CMD 0x32
EricLew 0:ad9dfc0179dc 136 #define EXT_QUAD_IN_FAST_PROG_CMD 0x12
EricLew 0:ad9dfc0179dc 137
EricLew 0:ad9dfc0179dc 138 /* Erase Operations */
EricLew 0:ad9dfc0179dc 139 #define SUBSECTOR_ERASE_CMD 0x20
EricLew 0:ad9dfc0179dc 140 #define SECTOR_ERASE_CMD 0xD8
EricLew 0:ad9dfc0179dc 141 #define BULK_ERASE_CMD 0xC7
EricLew 0:ad9dfc0179dc 142
EricLew 0:ad9dfc0179dc 143 #define PROG_ERASE_RESUME_CMD 0x7A
EricLew 0:ad9dfc0179dc 144 #define PROG_ERASE_SUSPEND_CMD 0x75
EricLew 0:ad9dfc0179dc 145
EricLew 0:ad9dfc0179dc 146 /* One-Time Programmable Operations */
EricLew 0:ad9dfc0179dc 147 #define READ_OTP_ARRAY_CMD 0x4B
EricLew 0:ad9dfc0179dc 148 #define PROG_OTP_ARRAY_CMD 0x42
EricLew 0:ad9dfc0179dc 149
EricLew 0:ad9dfc0179dc 150 /**
EricLew 0:ad9dfc0179dc 151 * @brief N25Q128A Registers
EricLew 0:ad9dfc0179dc 152 */
EricLew 0:ad9dfc0179dc 153 /* Status Register */
EricLew 0:ad9dfc0179dc 154 #define N25Q128A_SR_WIP ((uint8_t)0x01) /*!< Write in progress */
EricLew 0:ad9dfc0179dc 155 #define N25Q128A_SR_WREN ((uint8_t)0x02) /*!< Write enable latch */
EricLew 0:ad9dfc0179dc 156 #define N25Q128A_SR_BLOCKPR ((uint8_t)0x5C) /*!< Block protected against program and erase operations */
EricLew 0:ad9dfc0179dc 157 #define N25Q128A_SR_PRBOTTOM ((uint8_t)0x20) /*!< Protected memory area defined by BLOCKPR starts from top or bottom */
EricLew 0:ad9dfc0179dc 158 #define N25Q128A_SR_SRWREN ((uint8_t)0x80) /*!< Status register write enable/disable */
EricLew 0:ad9dfc0179dc 159
EricLew 0:ad9dfc0179dc 160 /* Nonvolatile Configuration Register */
EricLew 0:ad9dfc0179dc 161 #define N25Q128A_NVCR_LOCK ((uint16_t)0x0001) /*!< Lock nonvolatile configuration register */
EricLew 0:ad9dfc0179dc 162 #define N25Q128A_NVCR_DUAL ((uint16_t)0x0004) /*!< Dual I/O protocol */
EricLew 0:ad9dfc0179dc 163 #define N25Q128A_NVCR_QUAB ((uint16_t)0x0008) /*!< Quad I/O protocol */
EricLew 0:ad9dfc0179dc 164 #define N25Q128A_NVCR_RH ((uint16_t)0x0010) /*!< Reset/hold */
EricLew 0:ad9dfc0179dc 165 #define N25Q128A_NVCR_ODS ((uint16_t)0x01C0) /*!< Output driver strength */
EricLew 0:ad9dfc0179dc 166 #define N25Q128A_NVCR_XIP ((uint16_t)0x0E00) /*!< XIP mode at power-on reset */
EricLew 0:ad9dfc0179dc 167 #define N25Q128A_NVCR_NB_DUMMY ((uint16_t)0xF000) /*!< Number of dummy clock cycles */
EricLew 0:ad9dfc0179dc 168
EricLew 0:ad9dfc0179dc 169 /* Volatile Configuration Register */
EricLew 0:ad9dfc0179dc 170 #define N25Q128A_VCR_WRAP ((uint8_t)0x03) /*!< Wrap */
EricLew 0:ad9dfc0179dc 171 #define N25Q128A_VCR_XIP ((uint8_t)0x08) /*!< XIP */
EricLew 0:ad9dfc0179dc 172 #define N25Q128A_VCR_NB_DUMMY ((uint8_t)0xF0) /*!< Number of dummy clock cycles */
EricLew 0:ad9dfc0179dc 173
EricLew 0:ad9dfc0179dc 174 /* Enhanced Volatile Configuration Register */
EricLew 0:ad9dfc0179dc 175 #define N25Q128A_EVCR_ODS ((uint8_t)0x07) /*!< Output driver strength */
EricLew 0:ad9dfc0179dc 176 #define N25Q128A_EVCR_VPPA ((uint8_t)0x08) /*!< Vpp accelerator */
EricLew 0:ad9dfc0179dc 177 #define N25Q128A_EVCR_RH ((uint8_t)0x10) /*!< Reset/hold */
EricLew 0:ad9dfc0179dc 178 #define N25Q128A_EVCR_DUAL ((uint8_t)0x40) /*!< Dual I/O protocol */
EricLew 0:ad9dfc0179dc 179 #define N25Q128A_EVCR_QUAD ((uint8_t)0x80) /*!< Quad I/O protocol */
EricLew 0:ad9dfc0179dc 180
EricLew 0:ad9dfc0179dc 181 /* Flag Status Register */
EricLew 0:ad9dfc0179dc 182 #define N25Q128A_FSR_PRERR ((uint8_t)0x02) /*!< Protection error */
EricLew 0:ad9dfc0179dc 183 #define N25Q128A_FSR_PGSUS ((uint8_t)0x04) /*!< Program operation suspended */
EricLew 0:ad9dfc0179dc 184 #define N25Q128A_FSR_VPPERR ((uint8_t)0x08) /*!< Invalid voltage during program or erase */
EricLew 0:ad9dfc0179dc 185 #define N25Q128A_FSR_PGERR ((uint8_t)0x10) /*!< Program error */
EricLew 0:ad9dfc0179dc 186 #define N25Q128A_FSR_ERERR ((uint8_t)0x20) /*!< Erase error */
EricLew 0:ad9dfc0179dc 187 #define N25Q128A_FSR_ERSUS ((uint8_t)0x40) /*!< Erase operation suspended */
EricLew 0:ad9dfc0179dc 188 #define N25Q128A_FSR_READY ((uint8_t)0x80) /*!< Ready or command in progress */
EricLew 0:ad9dfc0179dc 189
EricLew 0:ad9dfc0179dc 190 /**
EricLew 0:ad9dfc0179dc 191 * @}
EricLew 0:ad9dfc0179dc 192 */
EricLew 0:ad9dfc0179dc 193
EricLew 0:ad9dfc0179dc 194 /** @defgroup N25Q128A_Exported_Functions
EricLew 0:ad9dfc0179dc 195 * @{
EricLew 0:ad9dfc0179dc 196 */
EricLew 0:ad9dfc0179dc 197 /**
EricLew 0:ad9dfc0179dc 198 * @}
EricLew 0:ad9dfc0179dc 199 */
EricLew 0:ad9dfc0179dc 200
EricLew 0:ad9dfc0179dc 201 /**
EricLew 0:ad9dfc0179dc 202 * @}
EricLew 0:ad9dfc0179dc 203 */
EricLew 0:ad9dfc0179dc 204
EricLew 0:ad9dfc0179dc 205 /**
EricLew 0:ad9dfc0179dc 206 * @}
EricLew 0:ad9dfc0179dc 207 */
EricLew 0:ad9dfc0179dc 208
EricLew 0:ad9dfc0179dc 209 /**
EricLew 0:ad9dfc0179dc 210 * @}
EricLew 0:ad9dfc0179dc 211 */
EricLew 0:ad9dfc0179dc 212
EricLew 0:ad9dfc0179dc 213 #ifdef __cplusplus
EricLew 0:ad9dfc0179dc 214 }
EricLew 0:ad9dfc0179dc 215 #endif
EricLew 0:ad9dfc0179dc 216
EricLew 0:ad9dfc0179dc 217 #endif /* __N25Q128A_H */
EricLew 0:ad9dfc0179dc 218
EricLew 0:ad9dfc0179dc 219 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
EricLew 0:ad9dfc0179dc 220