Senior Design: Sound Monitor / BSP

BSP Drivers

Dependencies:   CMSIS_STM32L4xx CMSIS_DSP_401 STM32L4xx_HAL_Driver

Dependents:   DiscoAudioRecord

Components/mfxstm32l152/mfxstm32l152.h@4:a1219ef3537f, 2015-11-22 (annotated)

Committer:
EricLew
Date:
Sun Nov 22 21:15:34 2015 +0000
Revision:
4:a1219ef3537f
Parent:
0:ad9dfc0179dc 
11/22/2015

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:ad9dfc0179dc 1 /**
EricLew 0:ad9dfc0179dc 2 ******************************************************************************
EricLew 0:ad9dfc0179dc 3 * @file mfxstm32l152.h
EricLew 0:ad9dfc0179dc 4 * @author MCD Application Team
EricLew 0:ad9dfc0179dc 5 * @version V2.0.0
EricLew 0:ad9dfc0179dc 6 * @date 24-June-2015
EricLew 0:ad9dfc0179dc 7 * @brief This file contains all the functions prototypes for the
EricLew 0:ad9dfc0179dc 8 * mfxstm32l152.c IO expander driver.
EricLew 0:ad9dfc0179dc 9 ******************************************************************************
EricLew 0:ad9dfc0179dc 10 * @attention
EricLew 0:ad9dfc0179dc 11 *
EricLew 0:ad9dfc0179dc 12 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew 0:ad9dfc0179dc 13 *
EricLew 0:ad9dfc0179dc 14 * Redistribution and use in source and binary forms, with or without modification,
EricLew 0:ad9dfc0179dc 15 * are permitted provided that the following conditions are met:
EricLew 0:ad9dfc0179dc 16 * 1. Redistributions of source code must retain the above copyright notice,
EricLew 0:ad9dfc0179dc 17 * this list of conditions and the following disclaimer.
EricLew 0:ad9dfc0179dc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew 0:ad9dfc0179dc 19 * this list of conditions and the following disclaimer in the documentation
EricLew 0:ad9dfc0179dc 20 * and/or other materials provided with the distribution.
EricLew 0:ad9dfc0179dc 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew 0:ad9dfc0179dc 22 * may be used to endorse or promote products derived from this software
EricLew 0:ad9dfc0179dc 23 * without specific prior written permission.
EricLew 0:ad9dfc0179dc 24 *
EricLew 0:ad9dfc0179dc 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:ad9dfc0179dc 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:ad9dfc0179dc 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew 0:ad9dfc0179dc 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew 0:ad9dfc0179dc 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew 0:ad9dfc0179dc 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew 0:ad9dfc0179dc 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew 0:ad9dfc0179dc 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew 0:ad9dfc0179dc 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew 0:ad9dfc0179dc 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew 0:ad9dfc0179dc 35 *
EricLew 0:ad9dfc0179dc 36 ******************************************************************************
EricLew 0:ad9dfc0179dc 37 */
EricLew 0:ad9dfc0179dc 38
EricLew 0:ad9dfc0179dc 39 /* Define to prevent recursive inclusion -------------------------------------*/
EricLew 0:ad9dfc0179dc 40 #ifndef __MFXSTM32L152_H
EricLew 0:ad9dfc0179dc 41 #define __MFXSTM32L152_H
EricLew 0:ad9dfc0179dc 42
EricLew 0:ad9dfc0179dc 43 #ifdef __cplusplus
EricLew 0:ad9dfc0179dc 44 extern "C" {
EricLew 0:ad9dfc0179dc 45 #endif
EricLew 0:ad9dfc0179dc 46
EricLew 0:ad9dfc0179dc 47 /* Includes ------------------------------------------------------------------*/
EricLew 0:ad9dfc0179dc 48 #include "../Common/ts.h"
EricLew 0:ad9dfc0179dc 49 #include "../Common/io.h"
EricLew 0:ad9dfc0179dc 50 #include "../Common/idd.h"
EricLew 0:ad9dfc0179dc 51
EricLew 0:ad9dfc0179dc 52 /** @addtogroup BSP
EricLew 0:ad9dfc0179dc 53 * @{
EricLew 0:ad9dfc0179dc 54 */
EricLew 0:ad9dfc0179dc 55
EricLew 0:ad9dfc0179dc 56 /** @addtogroup Component
EricLew 0:ad9dfc0179dc 57 * @{
EricLew 0:ad9dfc0179dc 58 */
EricLew 0:ad9dfc0179dc 59
EricLew 0:ad9dfc0179dc 60 /** @defgroup MFXSTM32L152
EricLew 0:ad9dfc0179dc 61 * @{
EricLew 0:ad9dfc0179dc 62 */
EricLew 0:ad9dfc0179dc 63
EricLew 0:ad9dfc0179dc 64 /* Exported types ------------------------------------------------------------*/
EricLew 0:ad9dfc0179dc 65
EricLew 0:ad9dfc0179dc 66 /** @defgroup MFXSTM32L152_Exported_Types
EricLew 0:ad9dfc0179dc 67 * @{
EricLew 0:ad9dfc0179dc 68 */
EricLew 0:ad9dfc0179dc 69 typedef struct
EricLew 0:ad9dfc0179dc 70 {
EricLew 0:ad9dfc0179dc 71 uint8_t SYS_CTRL;
EricLew 0:ad9dfc0179dc 72 uint8_t ERROR_SRC;
EricLew 0:ad9dfc0179dc 73 uint8_t ERROR_MSG;
EricLew 0:ad9dfc0179dc 74 uint8_t IRQ_OUT;
EricLew 0:ad9dfc0179dc 75 uint8_t IRQ_SRC_EN;
EricLew 0:ad9dfc0179dc 76 uint8_t IRQ_PENDING;
EricLew 0:ad9dfc0179dc 77 uint8_t IDD_CTRL;
EricLew 0:ad9dfc0179dc 78 uint8_t IDD_PRE_DELAY;
EricLew 0:ad9dfc0179dc 79 uint8_t IDD_SHUNT0_MSB;
EricLew 0:ad9dfc0179dc 80 uint8_t IDD_SHUNT0_LSB;
EricLew 0:ad9dfc0179dc 81 uint8_t IDD_SHUNT1_MSB;
EricLew 0:ad9dfc0179dc 82 uint8_t IDD_SHUNT1_LSB;
EricLew 0:ad9dfc0179dc 83 uint8_t IDD_SHUNT2_MSB;
EricLew 0:ad9dfc0179dc 84 uint8_t IDD_SHUNT2_LSB;
EricLew 0:ad9dfc0179dc 85 uint8_t IDD_SHUNT3_MSB;
EricLew 0:ad9dfc0179dc 86 uint8_t IDD_SHUNT3_LSB;
EricLew 0:ad9dfc0179dc 87 uint8_t IDD_SHUNT4_MSB;
EricLew 0:ad9dfc0179dc 88 uint8_t IDD_SHUNT4_LSB;
EricLew 0:ad9dfc0179dc 89 uint8_t IDD_GAIN_MSB;
EricLew 0:ad9dfc0179dc 90 uint8_t IDD_GAIN_LSB;
EricLew 0:ad9dfc0179dc 91 uint8_t IDD_VDD_MIN_MSB;
EricLew 0:ad9dfc0179dc 92 uint8_t IDD_VDD_MIN_LSB;
EricLew 0:ad9dfc0179dc 93 uint8_t IDD_VALUE_MSB;
EricLew 0:ad9dfc0179dc 94 uint8_t IDD_VALUE_MID;
EricLew 0:ad9dfc0179dc 95 uint8_t IDD_VALUE_LSB;
EricLew 0:ad9dfc0179dc 96 uint8_t IDD_CAL_OFFSET_MSB;
EricLew 0:ad9dfc0179dc 97 uint8_t IDD_CAL_OFFSET_LSB;
EricLew 0:ad9dfc0179dc 98 uint8_t IDD_SHUNT_USED;
EricLew 0:ad9dfc0179dc 99 }IDD_dbgTypeDef;
EricLew 0:ad9dfc0179dc 100
EricLew 0:ad9dfc0179dc 101 /**
EricLew 0:ad9dfc0179dc 102 * @}
EricLew 0:ad9dfc0179dc 103 */
EricLew 0:ad9dfc0179dc 104
EricLew 0:ad9dfc0179dc 105 /* Exported constants --------------------------------------------------------*/
EricLew 0:ad9dfc0179dc 106
EricLew 0:ad9dfc0179dc 107 /** @defgroup MFXSTM32L152_Exported_Constants
EricLew 0:ad9dfc0179dc 108 * @{
EricLew 0:ad9dfc0179dc 109 */
EricLew 0:ad9dfc0179dc 110
EricLew 0:ad9dfc0179dc 111 /**
EricLew 0:ad9dfc0179dc 112 * @brief MFX COMMON defines
EricLew 0:ad9dfc0179dc 113 */
EricLew 0:ad9dfc0179dc 114
EricLew 0:ad9dfc0179dc 115 /**
EricLew 0:ad9dfc0179dc 116 * @brief Register address: chip IDs (R)
EricLew 0:ad9dfc0179dc 117 */
EricLew 0:ad9dfc0179dc 118 #define MFXSTM32L152_REG_ADR_ID ((uint8_t)0x00)
EricLew 0:ad9dfc0179dc 119 /**
EricLew 0:ad9dfc0179dc 120 * @brief Register address: chip FW_VERSION (R)
EricLew 0:ad9dfc0179dc 121 */
EricLew 0:ad9dfc0179dc 122 #define MFXSTM32L152_REG_ADR_FW_VERSION_MSB ((uint8_t)0x01)
EricLew 0:ad9dfc0179dc 123 #define MFXSTM32L152_REG_ADR_FW_VERSION_LSB ((uint8_t)0x00)
EricLew 0:ad9dfc0179dc 124 /**
EricLew 0:ad9dfc0179dc 125 * @brief Register address: System Control Register (R/W)
EricLew 0:ad9dfc0179dc 126 */
EricLew 0:ad9dfc0179dc 127 #define MFXSTM32L152_REG_ADR_SYS_CTRL ((uint8_t)0x40)
EricLew 0:ad9dfc0179dc 128 /**
EricLew 0:ad9dfc0179dc 129 * @brief Register address: Vdd monitoring (R)
EricLew 0:ad9dfc0179dc 130 */
EricLew 0:ad9dfc0179dc 131 #define MFXSTM32L152_REG_ADR_VDD_REF_MSB ((uint8_t)0x06)
EricLew 0:ad9dfc0179dc 132 #define MFXSTM32L152_REG_ADR_VDD_REF_LSB ((uint8_t)0x07)
EricLew 0:ad9dfc0179dc 133 /**
EricLew 0:ad9dfc0179dc 134 * @brief Register address: Error source
EricLew 0:ad9dfc0179dc 135 */
EricLew 0:ad9dfc0179dc 136 #define MFXSTM32L152_REG_ADR_ERROR_SRC ((uint8_t)0x03)
EricLew 0:ad9dfc0179dc 137 /**
EricLew 0:ad9dfc0179dc 138 * @brief Register address: Error Message
EricLew 0:ad9dfc0179dc 139 */
EricLew 0:ad9dfc0179dc 140 #define MFXSTM32L152_REG_ADR_ERROR_MSG ((uint8_t)0x04)
EricLew 0:ad9dfc0179dc 141
EricLew 0:ad9dfc0179dc 142 /**
EricLew 0:ad9dfc0179dc 143 * @brief Reg Addr IRQs: to config the pin that informs Main MCU that MFX events appear
EricLew 0:ad9dfc0179dc 144 */
EricLew 0:ad9dfc0179dc 145 #define MFXSTM32L152_REG_ADR_MFX_IRQ_OUT ((uint8_t)0x41)
EricLew 0:ad9dfc0179dc 146 /**
EricLew 0:ad9dfc0179dc 147 * @brief Reg Addr IRQs: to select the events which activate the MFXSTM32L152_IRQ_OUT signal
EricLew 0:ad9dfc0179dc 148 */
EricLew 0:ad9dfc0179dc 149 #define MFXSTM32L152_REG_ADR_IRQ_SRC_EN ((uint8_t)0x42)
EricLew 0:ad9dfc0179dc 150 /**
EricLew 0:ad9dfc0179dc 151 * @brief Reg Addr IRQs: the Main MCU must read the IRQ_PENDING register to know the interrupt reason
EricLew 0:ad9dfc0179dc 152 */
EricLew 0:ad9dfc0179dc 153 #define MFXSTM32L152_REG_ADR_IRQ_PENDING ((uint8_t)0x08)
EricLew 0:ad9dfc0179dc 154 /**
EricLew 0:ad9dfc0179dc 155 * @brief Reg Addr IRQs: the Main MCU must acknowledge it thanks to a writing access to the IRQ_ACK register
EricLew 0:ad9dfc0179dc 156 */
EricLew 0:ad9dfc0179dc 157 #define MFXSTM32L152_REG_ADR_IRQ_ACK ((uint8_t)0x44)
EricLew 0:ad9dfc0179dc 158
EricLew 0:ad9dfc0179dc 159 /**
EricLew 0:ad9dfc0179dc 160 * @brief MFXSTM32L152_REG_ADR_ID choices
EricLew 0:ad9dfc0179dc 161 */
EricLew 0:ad9dfc0179dc 162 #define MFXSTM32L152_ID_1 ((uint8_t)0x7B)
EricLew 0:ad9dfc0179dc 163 #define MFXSTM32L152_ID_2 ((uint8_t)0x79)
EricLew 0:ad9dfc0179dc 164
EricLew 0:ad9dfc0179dc 165 /**
EricLew 0:ad9dfc0179dc 166 * @brief MFXSTM32L152_REG_ADR_SYS_CTRL choices
EricLew 0:ad9dfc0179dc 167 */
EricLew 0:ad9dfc0179dc 168 #define MFXSTM32L152_SWRST ((uint8_t)0x80)
EricLew 0:ad9dfc0179dc 169 #define MFXSTM32L152_STANDBY ((uint8_t)0x40)
EricLew 0:ad9dfc0179dc 170 #define MFXSTM32L152_ALTERNATE_GPIO_EN ((uint8_t)0x08) /* by the way if IDD and TS are enabled they take automatically the AF pins*/
EricLew 0:ad9dfc0179dc 171 #define MFXSTM32L152_IDD_EN ((uint8_t)0x04)
EricLew 0:ad9dfc0179dc 172 #define MFXSTM32L152_TS_EN ((uint8_t)0x02)
EricLew 0:ad9dfc0179dc 173 #define MFXSTM32L152_GPIO_EN ((uint8_t)0x01)
EricLew 0:ad9dfc0179dc 174
EricLew 0:ad9dfc0179dc 175 /**
EricLew 0:ad9dfc0179dc 176 * @brief MFXSTM32L152_REG_ADR_ERROR_SRC choices
EricLew 0:ad9dfc0179dc 177 */
EricLew 0:ad9dfc0179dc 178 #define MFXSTM32L152_IDD_ERROR_SRC ((uint8_t)0x04) /* Error raised by Idd */
EricLew 0:ad9dfc0179dc 179 #define MFXSTM32L152_TS_ERROR_SRC ((uint8_t)0x02) /* Error raised by Touch Screen */
EricLew 0:ad9dfc0179dc 180 #define MFXSTM32L152_GPIO_ERROR_SRC ((uint8_t)0x01) /* Error raised by Gpio */
EricLew 0:ad9dfc0179dc 181
EricLew 0:ad9dfc0179dc 182 /**
EricLew 0:ad9dfc0179dc 183 * @brief MFXSTM32L152_REG_ADR_MFX_IRQ_OUT choices
EricLew 0:ad9dfc0179dc 184 */
EricLew 0:ad9dfc0179dc 185 #define MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN ((uint8_t)0x00)
EricLew 0:ad9dfc0179dc 186 #define MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL ((uint8_t)0x01)
EricLew 0:ad9dfc0179dc 187 #define MFXSTM32L152_OUT_PIN_POLARITY_LOW ((uint8_t)0x00)
EricLew 0:ad9dfc0179dc 188 #define MFXSTM32L152_OUT_PIN_POLARITY_HIGH ((uint8_t)0x02)
EricLew 0:ad9dfc0179dc 189
EricLew 0:ad9dfc0179dc 190 /**
EricLew 0:ad9dfc0179dc 191 * @brief REG_ADR_IRQ_SRC_EN, REG_ADR_IRQ_PENDING & REG_ADR_IRQ_ACK choices
EricLew 0:ad9dfc0179dc 192 */
EricLew 0:ad9dfc0179dc 193 #define MFXSTM32L152_IRQ_TS_OVF ((uint8_t)0x80) /* TouchScreen FIFO Overflow irq*/
EricLew 0:ad9dfc0179dc 194 #define MFXSTM32L152_IRQ_TS_FULL ((uint8_t)0x40) /* TouchScreen FIFO Full irq*/
EricLew 0:ad9dfc0179dc 195 #define MFXSTM32L152_IRQ_TS_TH ((uint8_t)0x20) /* TouchScreen FIFO threshold triggered irq*/
EricLew 0:ad9dfc0179dc 196 #define MFXSTM32L152_IRQ_TS_NE ((uint8_t)0x10) /* TouchScreen FIFO Not Empty irq*/
EricLew 0:ad9dfc0179dc 197 #define MFXSTM32L152_IRQ_TS_DET ((uint8_t)0x08) /* TouchScreen Detect irq*/
EricLew 0:ad9dfc0179dc 198 #define MFXSTM32L152_IRQ_ERROR ((uint8_t)0x04) /* Error message from MFXSTM32L152 firmware irq */
EricLew 0:ad9dfc0179dc 199 #define MFXSTM32L152_IRQ_IDD ((uint8_t)0x02) /* IDD function irq */
EricLew 0:ad9dfc0179dc 200 #define MFXSTM32L152_IRQ_GPIO ((uint8_t)0x01) /* General GPIO irq (only for SRC_EN and PENDING) */
EricLew 0:ad9dfc0179dc 201 #define MFXSTM32L152_IRQ_ALL ((uint8_t)0xFF) /* All global interrupts */
EricLew 0:ad9dfc0179dc 202 #define MFXSTM32L152_IRQ_TS (MFXSTM32L152_IRQ_TS_DET | MFXSTM32L152_IRQ_TS_NE | MFXSTM32L152_IRQ_TS_TH | MFXSTM32L152_IRQ_TS_FULL | MFXSTM32L152_IRQ_TS_OVF )
EricLew 0:ad9dfc0179dc 203
EricLew 0:ad9dfc0179dc 204
EricLew 0:ad9dfc0179dc 205 /**
EricLew 0:ad9dfc0179dc 206 * @brief GPIO: 24 programmable input/output called MFXSTM32L152_GPIO[23:0] are provided
EricLew 0:ad9dfc0179dc 207 */
EricLew 0:ad9dfc0179dc 208
EricLew 0:ad9dfc0179dc 209 /**
EricLew 0:ad9dfc0179dc 210 * @brief Reg addr: GPIO DIRECTION (R/W): GPIO pins direction: (0) input, (1) output.
EricLew 0:ad9dfc0179dc 211 */
EricLew 0:ad9dfc0179dc 212 #define MFXSTM32L152_REG_ADR_GPIO_DIR1 ((uint8_t)0x60) /* gpio [0:7] */
EricLew 0:ad9dfc0179dc 213 #define MFXSTM32L152_REG_ADR_GPIO_DIR2 ((uint8_t)0x61) /* gpio [8:15] */
EricLew 0:ad9dfc0179dc 214 #define MFXSTM32L152_REG_ADR_GPIO_DIR3 ((uint8_t)0x62) /* agpio [0:7] */
EricLew 0:ad9dfc0179dc 215 /**
EricLew 0:ad9dfc0179dc 216 * @brief Reg addr: GPIO TYPE (R/W): If GPIO in output: (0) output push pull, (1) output open drain.
EricLew 0:ad9dfc0179dc 217 * If GPIO in input: (0) input without pull resistor, (1) input with pull resistor.
EricLew 0:ad9dfc0179dc 218 */
EricLew 0:ad9dfc0179dc 219 #define MFXSTM32L152_REG_ADR_GPIO_TYPE1 ((uint8_t)0x64) /* gpio [0:7] */
EricLew 0:ad9dfc0179dc 220 #define MFXSTM32L152_REG_ADR_GPIO_TYPE2 ((uint8_t)0x65) /* gpio [8:15] */
EricLew 0:ad9dfc0179dc 221 #define MFXSTM32L152_REG_ADR_GPIO_TYPE3 ((uint8_t)0x66) /* agpio [0:7] */
EricLew 0:ad9dfc0179dc 222 /**
EricLew 0:ad9dfc0179dc 223 * @brief Reg addr: GPIO PULL_UP_PULL_DOWN (R/W): discussion open with Jean Claude
EricLew 0:ad9dfc0179dc 224 */
EricLew 0:ad9dfc0179dc 225 #define MFXSTM32L152_REG_ADR_GPIO_PUPD1 ((uint8_t)0x68) /* gpio [0:7] */
EricLew 0:ad9dfc0179dc 226 #define MFXSTM32L152_REG_ADR_GPIO_PUPD2 ((uint8_t)0x69) /* gpio [8:15] */
EricLew 0:ad9dfc0179dc 227 #define MFXSTM32L152_REG_ADR_GPIO_PUPD3 ((uint8_t)0x6A) /* agpio [0:7] */
EricLew 0:ad9dfc0179dc 228 /**
EricLew 0:ad9dfc0179dc 229 * @brief Reg addr: GPIO SET (W): When GPIO is in output mode, write (1) puts the corresponding GPO in High level.
EricLew 0:ad9dfc0179dc 230 */
EricLew 0:ad9dfc0179dc 231 #define MFXSTM32L152_REG_ADR_GPO_SET1 ((uint8_t)0x6C) /* gpio [0:7] */
EricLew 0:ad9dfc0179dc 232 #define MFXSTM32L152_REG_ADR_GPO_SET2 ((uint8_t)0x6D) /* gpio [8:15] */
EricLew 0:ad9dfc0179dc 233 #define MFXSTM32L152_REG_ADR_GPO_SET3 ((uint8_t)0x6E) /* agpio [0:7] */
EricLew 0:ad9dfc0179dc 234 /**
EricLew 0:ad9dfc0179dc 235 * @brief Reg addr: GPIO CLEAR (W): When GPIO is in output mode, write (1) puts the corresponding GPO in Low level.
EricLew 0:ad9dfc0179dc 236 */
EricLew 0:ad9dfc0179dc 237 #define MFXSTM32L152_REG_ADR_GPO_CLR1 ((uint8_t)0x70) /* gpio [0:7] */
EricLew 0:ad9dfc0179dc 238 #define MFXSTM32L152_REG_ADR_GPO_CLR2 ((uint8_t)0x71) /* gpio [8:15] */
EricLew 0:ad9dfc0179dc 239 #define MFXSTM32L152_REG_ADR_GPO_CLR3 ((uint8_t)0x72) /* agpio [0:7] */
EricLew 0:ad9dfc0179dc 240 /**
EricLew 0:ad9dfc0179dc 241 * @brief Reg addr: GPIO STATE (R): Give state of the GPIO pin.
EricLew 0:ad9dfc0179dc 242 */
EricLew 0:ad9dfc0179dc 243 #define MFXSTM32L152_REG_ADR_GPIO_STATE1 ((uint8_t)0x10) /* gpio [0:7] */
EricLew 0:ad9dfc0179dc 244 #define MFXSTM32L152_REG_ADR_GPIO_STATE2 ((uint8_t)0x11) /* gpio [8:15] */
EricLew 0:ad9dfc0179dc 245 #define MFXSTM32L152_REG_ADR_GPIO_STATE3 ((uint8_t)0x12) /* agpio [0:7] */
EricLew 0:ad9dfc0179dc 246
EricLew 0:ad9dfc0179dc 247 /**
EricLew 0:ad9dfc0179dc 248 * @brief GPIO IRQ_GPIs
EricLew 0:ad9dfc0179dc 249 */
EricLew 0:ad9dfc0179dc 250 /* GPIOs can INDIVIDUALLY generate interruption to the Main MCU thanks to the MFXSTM32L152_IRQ_OUT signal */
EricLew 0:ad9dfc0179dc 251 /* the general MFXSTM32L152_IRQ_GPIO_SRC_EN shall be enabled too */
EricLew 0:ad9dfc0179dc 252 /**
EricLew 0:ad9dfc0179dc 253 * @brief GPIO IRQ_GPI_SRC1/2/3 (R/W): registers enable or not the feature to generate irq
EricLew 0:ad9dfc0179dc 254 */
EricLew 0:ad9dfc0179dc 255 #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1 ((uint8_t)0x48) /* gpio [0:7] */
EricLew 0:ad9dfc0179dc 256 #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC2 ((uint8_t)0x49) /* gpio [8:15] */
EricLew 0:ad9dfc0179dc 257 #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC3 ((uint8_t)0x4A) /* agpio [0:7] */
EricLew 0:ad9dfc0179dc 258 /**
EricLew 0:ad9dfc0179dc 259 * @brief GPIO IRQ_GPI_EVT1/2/3 (R/W): Irq generated on level (0) or edge (1).
EricLew 0:ad9dfc0179dc 260 */
EricLew 0:ad9dfc0179dc 261 #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1 ((uint8_t)0x4C) /* gpio [0:7] */
EricLew 0:ad9dfc0179dc 262 #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT2 ((uint8_t)0x4D) /* gpio [8:15] */
EricLew 0:ad9dfc0179dc 263 #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT3 ((uint8_t)0x4E) /* agpio [0:7] */
EricLew 0:ad9dfc0179dc 264 /**
EricLew 0:ad9dfc0179dc 265 * @brief GPIO IRQ_GPI_TYPE1/2/3 (R/W): Irq generated on (0) : Low level or Falling edge. (1) : High level or Rising edge.
EricLew 0:ad9dfc0179dc 266 */
EricLew 0:ad9dfc0179dc 267 #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1 ((uint8_t)0x50) /* gpio [0:7] */
EricLew 0:ad9dfc0179dc 268 #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE2 ((uint8_t)0x51) /* gpio [8:15] */
EricLew 0:ad9dfc0179dc 269 #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE3 ((uint8_t)0x52) /* agpio [0:7] */
EricLew 0:ad9dfc0179dc 270 /**
EricLew 0:ad9dfc0179dc 271 * @brief GPIO IRQ_GPI_PENDING1/2/3 (R): irq occurs
EricLew 0:ad9dfc0179dc 272 */
EricLew 0:ad9dfc0179dc 273 #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1 ((uint8_t)0x0C) /* gpio [0:7] */
EricLew 0:ad9dfc0179dc 274 #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2 ((uint8_t)0x0D) /* gpio [8:15] */
EricLew 0:ad9dfc0179dc 275 #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3 ((uint8_t)0x0E) /* agpio [0:7] */
EricLew 0:ad9dfc0179dc 276 /**
EricLew 0:ad9dfc0179dc 277 * @brief GPIO IRQ_GPI_ACK1/2/3 (W): Write (1) to acknowledge IRQ event
EricLew 0:ad9dfc0179dc 278 */
EricLew 0:ad9dfc0179dc 279 #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1 ((uint8_t)0x54) /* gpio [0:7] */
EricLew 0:ad9dfc0179dc 280 #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2 ((uint8_t)0x55) /* gpio [8:15] */
EricLew 0:ad9dfc0179dc 281 #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3 ((uint8_t)0x56) /* agpio [0:7] */
EricLew 0:ad9dfc0179dc 282
EricLew 0:ad9dfc0179dc 283
EricLew 0:ad9dfc0179dc 284 /**
EricLew 0:ad9dfc0179dc 285 * @brief GPIO: IO Pins definition
EricLew 0:ad9dfc0179dc 286 */
EricLew 0:ad9dfc0179dc 287 #define MFXSTM32L152_GPIO_PIN_0 ((uint32_t)0x0001)
EricLew 0:ad9dfc0179dc 288 #define MFXSTM32L152_GPIO_PIN_1 ((uint32_t)0x0002)
EricLew 0:ad9dfc0179dc 289 #define MFXSTM32L152_GPIO_PIN_2 ((uint32_t)0x0004)
EricLew 0:ad9dfc0179dc 290 #define MFXSTM32L152_GPIO_PIN_3 ((uint32_t)0x0008)
EricLew 0:ad9dfc0179dc 291 #define MFXSTM32L152_GPIO_PIN_4 ((uint32_t)0x0010)
EricLew 0:ad9dfc0179dc 292 #define MFXSTM32L152_GPIO_PIN_5 ((uint32_t)0x0020)
EricLew 0:ad9dfc0179dc 293 #define MFXSTM32L152_GPIO_PIN_6 ((uint32_t)0x0040)
EricLew 0:ad9dfc0179dc 294 #define MFXSTM32L152_GPIO_PIN_7 ((uint32_t)0x0080)
EricLew 0:ad9dfc0179dc 295
EricLew 0:ad9dfc0179dc 296 #define MFXSTM32L152_GPIO_PIN_8 ((uint32_t)0x0100)
EricLew 0:ad9dfc0179dc 297 #define MFXSTM32L152_GPIO_PIN_9 ((uint32_t)0x0200)
EricLew 0:ad9dfc0179dc 298 #define MFXSTM32L152_GPIO_PIN_10 ((uint32_t)0x0400)
EricLew 0:ad9dfc0179dc 299 #define MFXSTM32L152_GPIO_PIN_11 ((uint32_t)0x0800)
EricLew 0:ad9dfc0179dc 300 #define MFXSTM32L152_GPIO_PIN_12 ((uint32_t)0x1000)
EricLew 0:ad9dfc0179dc 301 #define MFXSTM32L152_GPIO_PIN_13 ((uint32_t)0x2000)
EricLew 0:ad9dfc0179dc 302 #define MFXSTM32L152_GPIO_PIN_14 ((uint32_t)0x4000)
EricLew 0:ad9dfc0179dc 303 #define MFXSTM32L152_GPIO_PIN_15 ((uint32_t)0x8000)
EricLew 0:ad9dfc0179dc 304
EricLew 0:ad9dfc0179dc 305 #define MFXSTM32L152_GPIO_PIN_16 ((uint32_t)0x010000)
EricLew 0:ad9dfc0179dc 306 #define MFXSTM32L152_GPIO_PIN_17 ((uint32_t)0x020000)
EricLew 0:ad9dfc0179dc 307 #define MFXSTM32L152_GPIO_PIN_18 ((uint32_t)0x040000)
EricLew 0:ad9dfc0179dc 308 #define MFXSTM32L152_GPIO_PIN_19 ((uint32_t)0x080000)
EricLew 0:ad9dfc0179dc 309 #define MFXSTM32L152_GPIO_PIN_20 ((uint32_t)0x100000)
EricLew 0:ad9dfc0179dc 310 #define MFXSTM32L152_GPIO_PIN_21 ((uint32_t)0x200000)
EricLew 0:ad9dfc0179dc 311 #define MFXSTM32L152_GPIO_PIN_22 ((uint32_t)0x400000)
EricLew 0:ad9dfc0179dc 312 #define MFXSTM32L152_GPIO_PIN_23 ((uint32_t)0x800000)
EricLew 0:ad9dfc0179dc 313
EricLew 0:ad9dfc0179dc 314 #define MFXSTM32L152_AGPIO_PIN_0 MFXSTM32L152_GPIO_PIN_16
EricLew 0:ad9dfc0179dc 315 #define MFXSTM32L152_AGPIO_PIN_1 MFXSTM32L152_GPIO_PIN_17
EricLew 0:ad9dfc0179dc 316 #define MFXSTM32L152_AGPIO_PIN_2 MFXSTM32L152_GPIO_PIN_18
EricLew 0:ad9dfc0179dc 317 #define MFXSTM32L152_AGPIO_PIN_3 MFXSTM32L152_GPIO_PIN_19
EricLew 0:ad9dfc0179dc 318 #define MFXSTM32L152_AGPIO_PIN_4 MFXSTM32L152_GPIO_PIN_20
EricLew 0:ad9dfc0179dc 319 #define MFXSTM32L152_AGPIO_PIN_5 MFXSTM32L152_GPIO_PIN_21
EricLew 0:ad9dfc0179dc 320 #define MFXSTM32L152_AGPIO_PIN_6 MFXSTM32L152_GPIO_PIN_22
EricLew 0:ad9dfc0179dc 321 #define MFXSTM32L152_AGPIO_PIN_7 MFXSTM32L152_GPIO_PIN_23
EricLew 0:ad9dfc0179dc 322
EricLew 0:ad9dfc0179dc 323 #define MFXSTM32L152_GPIO_PINS_ALL ((uint32_t)0xFFFFFF)
EricLew 0:ad9dfc0179dc 324
EricLew 0:ad9dfc0179dc 325 /**
EricLew 0:ad9dfc0179dc 326 * @brief GPIO: constant
EricLew 0:ad9dfc0179dc 327 */
EricLew 0:ad9dfc0179dc 328 #define MFXSTM32L152_GPIO_DIR_IN ((uint8_t)0x0)
EricLew 0:ad9dfc0179dc 329 #define MFXSTM32L152_GPIO_DIR_OUT ((uint8_t)0x1)
EricLew 0:ad9dfc0179dc 330 #define MFXSTM32L152_IRQ_GPI_EVT_LEVEL ((uint8_t)0x0)
EricLew 0:ad9dfc0179dc 331 #define MFXSTM32L152_IRQ_GPI_EVT_EDGE ((uint8_t)0x1)
EricLew 0:ad9dfc0179dc 332 #define MFXSTM32L152_IRQ_GPI_TYPE_LLFE ((uint8_t)0x0) /* Low Level Falling Edge */
EricLew 0:ad9dfc0179dc 333 #define MFXSTM32L152_IRQ_GPI_TYPE_HLRE ((uint8_t)0x1) /*High Level Raising Edge */
EricLew 0:ad9dfc0179dc 334 #define MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR ((uint8_t)0x0)
EricLew 0:ad9dfc0179dc 335 #define MFXSTM32L152_GPI_WITH_PULL_RESISTOR ((uint8_t)0x1)
EricLew 0:ad9dfc0179dc 336 #define MFXSTM32L152_GPO_PUSH_PULL ((uint8_t)0x0)
EricLew 0:ad9dfc0179dc 337 #define MFXSTM32L152_GPO_OPEN_DRAIN ((uint8_t)0x1)
EricLew 0:ad9dfc0179dc 338 #define MFXSTM32L152_GPIO_PULL_DOWN ((uint8_t)0x0)
EricLew 0:ad9dfc0179dc 339 #define MFXSTM32L152_GPIO_PULL_UP ((uint8_t)0x1)
EricLew 0:ad9dfc0179dc 340
EricLew 0:ad9dfc0179dc 341
EricLew 0:ad9dfc0179dc 342 /**
EricLew 0:ad9dfc0179dc 343 * @brief TOUCH SCREEN Registers
EricLew 0:ad9dfc0179dc 344 */
EricLew 0:ad9dfc0179dc 345
EricLew 0:ad9dfc0179dc 346 /**
EricLew 0:ad9dfc0179dc 347 * @brief Touch Screen Registers
EricLew 0:ad9dfc0179dc 348 */
EricLew 0:ad9dfc0179dc 349 #define MFXSTM32L152_TS_SETTLING ((uint8_t)0xA0)
EricLew 0:ad9dfc0179dc 350 #define MFXSTM32L152_TS_TOUCH_DET_DELAY ((uint8_t)0xA1)
EricLew 0:ad9dfc0179dc 351 #define MFXSTM32L152_TS_AVE ((uint8_t)0xA2)
EricLew 0:ad9dfc0179dc 352 #define MFXSTM32L152_TS_TRACK ((uint8_t)0xA3)
EricLew 0:ad9dfc0179dc 353 #define MFXSTM32L152_TS_FIFO_TH ((uint8_t)0xA4)
EricLew 0:ad9dfc0179dc 354 #define MFXSTM32L152_TS_FIFO_STA ((uint8_t)0x20)
EricLew 0:ad9dfc0179dc 355 #define MFXSTM32L152_TS_FIFO_LEVEL ((uint8_t)0x21)
EricLew 0:ad9dfc0179dc 356 #define MFXSTM32L152_TS_XY_DATA ((uint8_t)0x24)
EricLew 0:ad9dfc0179dc 357
EricLew 0:ad9dfc0179dc 358 /**
EricLew 0:ad9dfc0179dc 359 * @brief TS registers masks
EricLew 0:ad9dfc0179dc 360 */
EricLew 0:ad9dfc0179dc 361 #define MFXSTM32L152_TS_CTRL_STATUS ((uint8_t)0x08)
EricLew 0:ad9dfc0179dc 362 #define MFXSTM32L152_TS_CLEAR_FIFO ((uint8_t)0x80)
EricLew 0:ad9dfc0179dc 363
EricLew 0:ad9dfc0179dc 364
EricLew 0:ad9dfc0179dc 365 /**
EricLew 0:ad9dfc0179dc 366 * @brief Register address: Idd control register (R/W)
EricLew 0:ad9dfc0179dc 367 */
EricLew 0:ad9dfc0179dc 368 #define MFXSTM32L152_REG_ADR_IDD_CTRL ((uint8_t)0x80)
EricLew 0:ad9dfc0179dc 369
EricLew 0:ad9dfc0179dc 370 /**
EricLew 0:ad9dfc0179dc 371 * @brief Register address: Idd pre delay register (R/W)
EricLew 0:ad9dfc0179dc 372 */
EricLew 0:ad9dfc0179dc 373 #define MFXSTM32L152_REG_ADR_IDD_PRE_DELAY ((uint8_t)0x81)
EricLew 0:ad9dfc0179dc 374
EricLew 0:ad9dfc0179dc 375 /**
EricLew 0:ad9dfc0179dc 376 * @brief Register address: Idd Shunt registers (R/W)
EricLew 0:ad9dfc0179dc 377 */
EricLew 0:ad9dfc0179dc 378 #define MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB ((uint8_t)0x82)
EricLew 0:ad9dfc0179dc 379 #define MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB ((uint8_t)0x83)
EricLew 0:ad9dfc0179dc 380 #define MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB ((uint8_t)0x84)
EricLew 0:ad9dfc0179dc 381 #define MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB ((uint8_t)0x85)
EricLew 0:ad9dfc0179dc 382 #define MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB ((uint8_t)0x86)
EricLew 0:ad9dfc0179dc 383 #define MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB ((uint8_t)0x87)
EricLew 0:ad9dfc0179dc 384 #define MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB ((uint8_t)0x88)
EricLew 0:ad9dfc0179dc 385 #define MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB ((uint8_t)0x89)
EricLew 0:ad9dfc0179dc 386 #define MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB ((uint8_t)0x8A)
EricLew 0:ad9dfc0179dc 387 #define MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB ((uint8_t)0x8B)
EricLew 0:ad9dfc0179dc 388
EricLew 0:ad9dfc0179dc 389 /**
EricLew 0:ad9dfc0179dc 390 * @brief Register address: Idd ampli gain register (R/W)
EricLew 0:ad9dfc0179dc 391 */
EricLew 0:ad9dfc0179dc 392 #define MFXSTM32L152_REG_ADR_IDD_GAIN_MSB ((uint8_t)0x8C)
EricLew 0:ad9dfc0179dc 393 #define MFXSTM32L152_REG_ADR_IDD_GAIN_LSB ((uint8_t)0x8D)
EricLew 0:ad9dfc0179dc 394
EricLew 0:ad9dfc0179dc 395 /**
EricLew 0:ad9dfc0179dc 396 * @brief Register address: Idd VDD min register (R/W)
EricLew 0:ad9dfc0179dc 397 */
EricLew 0:ad9dfc0179dc 398 #define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB ((uint8_t)0x8E)
EricLew 0:ad9dfc0179dc 399 #define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB ((uint8_t)0x8F)
EricLew 0:ad9dfc0179dc 400
EricLew 0:ad9dfc0179dc 401 /**
EricLew 0:ad9dfc0179dc 402 * @brief Register address: Idd value register (R)
EricLew 0:ad9dfc0179dc 403 */
EricLew 0:ad9dfc0179dc 404 #define MFXSTM32L152_REG_ADR_IDD_VALUE_MSB ((uint8_t)0x14)
EricLew 0:ad9dfc0179dc 405 #define MFXSTM32L152_REG_ADR_IDD_VALUE_MID ((uint8_t)0x15)
EricLew 0:ad9dfc0179dc 406 #define MFXSTM32L152_REG_ADR_IDD_VALUE_LSB ((uint8_t)0x16)
EricLew 0:ad9dfc0179dc 407
EricLew 0:ad9dfc0179dc 408 /**
EricLew 0:ad9dfc0179dc 409 * @brief Register address: Idd calibration offset register (R)
EricLew 0:ad9dfc0179dc 410 */
EricLew 0:ad9dfc0179dc 411 #define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_MSB ((uint8_t)0x18)
EricLew 0:ad9dfc0179dc 412 #define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_LSB ((uint8_t)0x19)
EricLew 0:ad9dfc0179dc 413
EricLew 0:ad9dfc0179dc 414 /**
EricLew 0:ad9dfc0179dc 415 * @brief Register address: Idd shunt used offset register (R)
EricLew 0:ad9dfc0179dc 416 */
EricLew 0:ad9dfc0179dc 417 #define MFXSTM32L152_REG_ADR_IDD_SHUNT_USED ((uint8_t)0x1A)
EricLew 0:ad9dfc0179dc 418
EricLew 0:ad9dfc0179dc 419 /**
EricLew 0:ad9dfc0179dc 420 * @brief Register address: shunt stabilisation delay registers (R/W)
EricLew 0:ad9dfc0179dc 421 */
EricLew 0:ad9dfc0179dc 422 #define MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION ((uint8_t)0x90)
EricLew 0:ad9dfc0179dc 423 #define MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION ((uint8_t)0x91)
EricLew 0:ad9dfc0179dc 424 #define MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION ((uint8_t)0x92)
EricLew 0:ad9dfc0179dc 425 #define MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION ((uint8_t)0x93)
EricLew 0:ad9dfc0179dc 426 #define MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION ((uint8_t)0x94)
EricLew 0:ad9dfc0179dc 427
EricLew 0:ad9dfc0179dc 428 /**
EricLew 0:ad9dfc0179dc 429 * @brief Register address: Idd number of measurements register (R/W)
EricLew 0:ad9dfc0179dc 430 */
EricLew 0:ad9dfc0179dc 431 #define MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS ((uint8_t)0x96)
EricLew 0:ad9dfc0179dc 432
EricLew 0:ad9dfc0179dc 433 /**
EricLew 0:ad9dfc0179dc 434 * @brief Register address: Idd delta delay between 2 measurements register (R/W)
EricLew 0:ad9dfc0179dc 435 */
EricLew 0:ad9dfc0179dc 436 #define MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY ((uint8_t)0x97)
EricLew 0:ad9dfc0179dc 437
EricLew 0:ad9dfc0179dc 438 /**
EricLew 0:ad9dfc0179dc 439 * @brief Register address: Idd number of shunt on board register (R/W)
EricLew 0:ad9dfc0179dc 440 */
EricLew 0:ad9dfc0179dc 441 #define MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD ((uint8_t)0x98)
EricLew 0:ad9dfc0179dc 442
EricLew 0:ad9dfc0179dc 443
EricLew 0:ad9dfc0179dc 444
EricLew 0:ad9dfc0179dc 445 /** @defgroup IDD_Control_Register_Defines IDD Control Register Defines
EricLew 0:ad9dfc0179dc 446 * @{
EricLew 0:ad9dfc0179dc 447 */
EricLew 0:ad9dfc0179dc 448 /**
EricLew 0:ad9dfc0179dc 449 * @brief IDD control register masks
EricLew 0:ad9dfc0179dc 450 */
EricLew 0:ad9dfc0179dc 451 #define MFXSTM32L152_IDD_CTRL_REQ ((uint8_t)0x01)
EricLew 0:ad9dfc0179dc 452 #define MFXSTM32L152_IDD_CTRL_SHUNT_NB ((uint8_t)0x0E)
EricLew 0:ad9dfc0179dc 453 #define MFXSTM32L152_IDD_CTRL_VREF_DIS ((uint8_t)0x40)
EricLew 0:ad9dfc0179dc 454 #define MFXSTM32L152_IDD_CTRL_CAL_DIS ((uint8_t)0x80)
EricLew 0:ad9dfc0179dc 455
EricLew 0:ad9dfc0179dc 456 /**
EricLew 0:ad9dfc0179dc 457 * @brief IDD Shunt Number
EricLew 0:ad9dfc0179dc 458 */
EricLew 0:ad9dfc0179dc 459 #define MFXSTM32L152_IDD_SHUNT_NB_1 ((uint8_t) 0x01)
EricLew 0:ad9dfc0179dc 460 #define MFXSTM32L152_IDD_SHUNT_NB_2 ((uint8_t) 0x02)
EricLew 0:ad9dfc0179dc 461 #define MFXSTM32L152_IDD_SHUNT_NB_3 ((uint8_t) 0x03)
EricLew 0:ad9dfc0179dc 462 #define MFXSTM32L152_IDD_SHUNT_NB_4 ((uint8_t) 0x04)
EricLew 0:ad9dfc0179dc 463 #define MFXSTM32L152_IDD_SHUNT_NB_5 ((uint8_t) 0x05)
EricLew 0:ad9dfc0179dc 464
EricLew 0:ad9dfc0179dc 465 /**
EricLew 0:ad9dfc0179dc 466 * @brief Vref Measurement
EricLew 0:ad9dfc0179dc 467 */
EricLew 0:ad9dfc0179dc 468 #define MFXSTM32L152_IDD_VREF_AUTO_MEASUREMENT_ENABLE ((uint8_t) 0x00)
EricLew 0:ad9dfc0179dc 469 #define MFXSTM32L152_IDD_VREF_AUTO_MEASUREMENT_DISABLE ((uint8_t) 0x70)
EricLew 0:ad9dfc0179dc 470
EricLew 0:ad9dfc0179dc 471 /**
EricLew 0:ad9dfc0179dc 472 * @brief IDD Calibration
EricLew 0:ad9dfc0179dc 473 */
EricLew 0:ad9dfc0179dc 474 #define MFXSTM32L152_IDD_AUTO_CALIBRATION_ENABLE ((uint8_t) 0x00)
EricLew 0:ad9dfc0179dc 475 #define MFXSTM32L152_IDD_AUTO_CALIBRATION_DISABLE ((uint8_t) 0x80)
EricLew 0:ad9dfc0179dc 476 /**
EricLew 0:ad9dfc0179dc 477 * @}
EricLew 0:ad9dfc0179dc 478 */
EricLew 0:ad9dfc0179dc 479
EricLew 0:ad9dfc0179dc 480 /** @defgroup IDD_PreDelay_Defines IDD PreDelay Defines
EricLew 0:ad9dfc0179dc 481 * @{
EricLew 0:ad9dfc0179dc 482 */
EricLew 0:ad9dfc0179dc 483 /**
EricLew 0:ad9dfc0179dc 484 * @brief IDD PreDelay masks
EricLew 0:ad9dfc0179dc 485 */
EricLew 0:ad9dfc0179dc 486 #define MFXSTM32L152_IDD_PREDELAY_UNIT ((uint8_t) 0x80)
EricLew 0:ad9dfc0179dc 487 #define MFXSTM32L152_IDD_PREDELAY_VALUE ((uint8_t) 0x7F)
EricLew 0:ad9dfc0179dc 488
EricLew 0:ad9dfc0179dc 489
EricLew 0:ad9dfc0179dc 490 /**
EricLew 0:ad9dfc0179dc 491 * @brief IDD PreDelay unit
EricLew 0:ad9dfc0179dc 492 */
EricLew 0:ad9dfc0179dc 493 #define MFXSTM32L152_IDD_PREDELAY_0_5_MS ((uint8_t) 0x00)
EricLew 0:ad9dfc0179dc 494 #define MFXSTM32L152_IDD_PREDELAY_20_MS ((uint8_t) 0x80)
EricLew 0:ad9dfc0179dc 495 /**
EricLew 0:ad9dfc0179dc 496 * @}
EricLew 0:ad9dfc0179dc 497 */
EricLew 0:ad9dfc0179dc 498
EricLew 0:ad9dfc0179dc 499 /** @defgroup IDD_DeltaDelay_Defines IDD Delta DElay Defines
EricLew 0:ad9dfc0179dc 500 * @{
EricLew 0:ad9dfc0179dc 501 */
EricLew 0:ad9dfc0179dc 502 /**
EricLew 0:ad9dfc0179dc 503 * @brief IDD Delta Delay masks
EricLew 0:ad9dfc0179dc 504 */
EricLew 0:ad9dfc0179dc 505 #define MFXSTM32L152_IDD_DELTADELAY_UNIT ((uint8_t) 0x80)
EricLew 0:ad9dfc0179dc 506 #define MFXSTM32L152_IDD_DELTADELAY_VALUE ((uint8_t) 0x7F)
EricLew 0:ad9dfc0179dc 507
EricLew 0:ad9dfc0179dc 508
EricLew 0:ad9dfc0179dc 509 /**
EricLew 0:ad9dfc0179dc 510 * @brief IDD Delta Delay unit
EricLew 0:ad9dfc0179dc 511 */
EricLew 0:ad9dfc0179dc 512 #define MFXSTM32L152_IDD_DELTADELAY_0_5_MS ((uint8_t) 0x00)
EricLew 0:ad9dfc0179dc 513 #define MFXSTM32L152_IDD_DELTADELAY_20_MS ((uint8_t) 0x80)
EricLew 0:ad9dfc0179dc 514
EricLew 0:ad9dfc0179dc 515
EricLew 0:ad9dfc0179dc 516 /**
EricLew 0:ad9dfc0179dc 517 * @}
EricLew 0:ad9dfc0179dc 518 */
EricLew 0:ad9dfc0179dc 519
EricLew 0:ad9dfc0179dc 520 /**
EricLew 0:ad9dfc0179dc 521 * @}
EricLew 0:ad9dfc0179dc 522 */
EricLew 0:ad9dfc0179dc 523
EricLew 0:ad9dfc0179dc 524
EricLew 0:ad9dfc0179dc 525 /* Exported macro ------------------------------------------------------------*/
EricLew 0:ad9dfc0179dc 526
EricLew 0:ad9dfc0179dc 527 /** @defgroup MFXSTM32L152_Exported_Macros
EricLew 0:ad9dfc0179dc 528 * @{
EricLew 0:ad9dfc0179dc 529 */
EricLew 0:ad9dfc0179dc 530
EricLew 0:ad9dfc0179dc 531 /**
EricLew 0:ad9dfc0179dc 532 * @}
EricLew 0:ad9dfc0179dc 533 */
EricLew 0:ad9dfc0179dc 534
EricLew 0:ad9dfc0179dc 535 /* Exported functions --------------------------------------------------------*/
EricLew 0:ad9dfc0179dc 536
EricLew 0:ad9dfc0179dc 537 /** @defgroup MFXSTM32L152_Exported_Functions
EricLew 0:ad9dfc0179dc 538 * @{
EricLew 0:ad9dfc0179dc 539 */
EricLew 0:ad9dfc0179dc 540
EricLew 0:ad9dfc0179dc 541 /**
EricLew 0:ad9dfc0179dc 542 * @brief MFXSTM32L152 Control functions
EricLew 0:ad9dfc0179dc 543 */
EricLew 0:ad9dfc0179dc 544 void mfxstm32l152_Init(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 545 void mfxstm32l152_DeInit(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 546 void mfxstm32l152_Reset(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 547 uint16_t mfxstm32l152_ReadID(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 548 uint16_t mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 549 void mfxstm32l152_LowPower(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 550 void mfxstm32l152_WakeUp(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 551
EricLew 0:ad9dfc0179dc 552 void mfxstm32l152_EnableITSource(uint16_t DeviceAddr, uint8_t Source);
EricLew 0:ad9dfc0179dc 553 void mfxstm32l152_DisableITSource(uint16_t DeviceAddr, uint8_t Source);
EricLew 0:ad9dfc0179dc 554 uint8_t mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source);
EricLew 0:ad9dfc0179dc 555 void mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source);
EricLew 0:ad9dfc0179dc 556
EricLew 0:ad9dfc0179dc 557 void mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr, uint8_t Polarity);
EricLew 0:ad9dfc0179dc 558 void mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr, uint8_t Type);
EricLew 0:ad9dfc0179dc 559
EricLew 0:ad9dfc0179dc 560
EricLew 0:ad9dfc0179dc 561 /**
EricLew 0:ad9dfc0179dc 562 * @brief MFXSTM32L152 IO functionalities functions
EricLew 0:ad9dfc0179dc 563 */
EricLew 0:ad9dfc0179dc 564 void mfxstm32l152_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin);
EricLew 0:ad9dfc0179dc 565 uint8_t mfxstm32l152_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode);
EricLew 0:ad9dfc0179dc 566 void mfxstm32l152_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState);
EricLew 0:ad9dfc0179dc 567 uint32_t mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin);
EricLew 0:ad9dfc0179dc 568 void mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 569 void mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 570 uint32_t mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin);
EricLew 0:ad9dfc0179dc 571 void mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin);
EricLew 0:ad9dfc0179dc 572
EricLew 0:ad9dfc0179dc 573 void mfxstm32l152_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction);
EricLew 0:ad9dfc0179dc 574 void mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 575 void mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 576 void mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Type);
EricLew 0:ad9dfc0179dc 577 void mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Evt);
EricLew 0:ad9dfc0179dc 578 void mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin);
EricLew 0:ad9dfc0179dc 579 void mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin);
EricLew 0:ad9dfc0179dc 580
EricLew 0:ad9dfc0179dc 581 /**
EricLew 0:ad9dfc0179dc 582 * @brief MFXSTM32L152 Touch screen functionalities functions
EricLew 0:ad9dfc0179dc 583 */
EricLew 0:ad9dfc0179dc 584 void mfxstm32l152_TS_Start(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 585 uint8_t mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 586 void mfxstm32l152_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y);
EricLew 0:ad9dfc0179dc 587 void mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 588 void mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 589 uint8_t mfxstm32l152_TS_ITStatus (uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 590 void mfxstm32l152_TS_ClearIT (uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 591
EricLew 0:ad9dfc0179dc 592 /**
EricLew 0:ad9dfc0179dc 593 * @brief MFXSTM32L152 IDD current measurement functionalities functions
EricLew 0:ad9dfc0179dc 594 */
EricLew 0:ad9dfc0179dc 595 void mfxstm32l152_IDD_Start(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 596 void mfxstm32l152_IDD_Config(uint16_t DeviceAddr, IDD_ConfigTypeDef MfxIddConfig);
EricLew 0:ad9dfc0179dc 597 void mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr, uint8_t ShuntNbLimit);
EricLew 0:ad9dfc0179dc 598 void mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr, uint32_t *ReadValue);
EricLew 0:ad9dfc0179dc 599 uint8_t mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 600 void mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 601 void mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 602 uint8_t mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 603 void mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 604
EricLew 0:ad9dfc0179dc 605 /**
EricLew 0:ad9dfc0179dc 606 * @brief MFXSTM32L152 Error management functions
EricLew 0:ad9dfc0179dc 607 */
EricLew 0:ad9dfc0179dc 608 uint8_t mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 609 uint8_t mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 610 void mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 611 void mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 612 uint8_t mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 613 void mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr);
EricLew 0:ad9dfc0179dc 614
EricLew 0:ad9dfc0179dc 615 uint8_t mfxstm32l152_ReadReg(uint16_t DeviceAddr, uint8_t RegAddr);
EricLew 0:ad9dfc0179dc 616 void mfxstm32l152_WriteReg(uint16_t DeviceAddr, uint8_t RegAddr, uint8_t Value);
EricLew 0:ad9dfc0179dc 617
EricLew 0:ad9dfc0179dc 618
EricLew 0:ad9dfc0179dc 619
EricLew 0:ad9dfc0179dc 620 /**
EricLew 0:ad9dfc0179dc 621 * @brief iobus prototypes (they should be defined in common/stm32_iobus.h)
EricLew 0:ad9dfc0179dc 622 */
EricLew 0:ad9dfc0179dc 623 void MFX_IO_Init(void);
EricLew 0:ad9dfc0179dc 624 void MFX_IO_DeInit(void);
EricLew 0:ad9dfc0179dc 625 void MFX_IO_ITConfig (void);
EricLew 0:ad9dfc0179dc 626 void MFX_IO_EnableWakeupPin(void);
EricLew 0:ad9dfc0179dc 627 void MFX_IO_Wakeup(void);
EricLew 0:ad9dfc0179dc 628 void MFX_IO_Delay(uint32_t delay);
EricLew 0:ad9dfc0179dc 629 void MFX_IO_Write(uint16_t addr, uint8_t reg, uint8_t value);
EricLew 0:ad9dfc0179dc 630 uint8_t MFX_IO_Read(uint16_t addr, uint8_t reg);
EricLew 0:ad9dfc0179dc 631 uint16_t MFX_IO_ReadMultiple(uint16_t addr, uint8_t reg, uint8_t *buffer, uint16_t length);
EricLew 0:ad9dfc0179dc 632
EricLew 0:ad9dfc0179dc 633 /**
EricLew 0:ad9dfc0179dc 634 * @}
EricLew 0:ad9dfc0179dc 635 */
EricLew 0:ad9dfc0179dc 636
EricLew 0:ad9dfc0179dc 637 /* Touch screen driver structure */
EricLew 0:ad9dfc0179dc 638 extern TS_DrvTypeDef mfxstm32l152_ts_drv;
EricLew 0:ad9dfc0179dc 639
EricLew 0:ad9dfc0179dc 640 /* IO driver structure */
EricLew 0:ad9dfc0179dc 641 extern IO_DrvTypeDef mfxstm32l152_io_drv;
EricLew 0:ad9dfc0179dc 642
EricLew 0:ad9dfc0179dc 643 /* IDD driver structure */
EricLew 0:ad9dfc0179dc 644 extern IDD_DrvTypeDef mfxstm32l152_idd_drv;
EricLew 0:ad9dfc0179dc 645
EricLew 0:ad9dfc0179dc 646
EricLew 0:ad9dfc0179dc 647 #ifdef __cplusplus
EricLew 0:ad9dfc0179dc 648 }
EricLew 0:ad9dfc0179dc 649 #endif
EricLew 0:ad9dfc0179dc 650 #endif /* __MFXSTM32L152_H */
EricLew 0:ad9dfc0179dc 651
EricLew 0:ad9dfc0179dc 652
EricLew 0:ad9dfc0179dc 653 /**
EricLew 0:ad9dfc0179dc 654 * @}
EricLew 0:ad9dfc0179dc 655 */
EricLew 0:ad9dfc0179dc 656
EricLew 0:ad9dfc0179dc 657 /**
EricLew 0:ad9dfc0179dc 658 * @}
EricLew 0:ad9dfc0179dc 659 */
EricLew 0:ad9dfc0179dc 660
EricLew 0:ad9dfc0179dc 661 /**
EricLew 0:ad9dfc0179dc 662 * @}
EricLew 0:ad9dfc0179dc 663 */
EricLew 0:ad9dfc0179dc 664
EricLew 0:ad9dfc0179dc 665 /**
EricLew 0:ad9dfc0179dc 666 * @}
EricLew 0:ad9dfc0179dc 667 */
EricLew 0:ad9dfc0179dc 668 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
EricLew 0:ad9dfc0179dc 669