BSP - BSP Drivers

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BSP Drivers

Dependencies: CMSIS_STM32L4xx CMSIS_DSP_401 STM32L4xx_HAL_Driver

Components/mfxstm32l152/mfxstm32l152.c@4:a1219ef3537f, 2015-11-22 (annotated)

Committer:: EricLew
Date:: Sun Nov 22 21:15:34 2015 +0000
Revision:: 4:a1219ef3537f
Parent:: 0:ad9dfc0179dc

11/22/2015

Who changed what in which revision?

User	Revision	Line number	New contents of line
EricLew	0:ad9dfc0179dc	1	/**
EricLew	0:ad9dfc0179dc	2	******************************************************************************
EricLew	0:ad9dfc0179dc	3	* @file mfxstm32l152.c
EricLew	0:ad9dfc0179dc	4	* @author MCD Application Team
EricLew	0:ad9dfc0179dc	5	* @version V2.0.0
EricLew	0:ad9dfc0179dc	6	* @date 24-June-2015
EricLew	0:ad9dfc0179dc	7	* @brief This file provides a set of functions needed to manage the MFXSTM32L152
EricLew	0:ad9dfc0179dc	8	* IO Expander devices.
EricLew	0:ad9dfc0179dc	9	******************************************************************************
EricLew	0:ad9dfc0179dc	10	* @attention
EricLew	0:ad9dfc0179dc	11	*
EricLew	0:ad9dfc0179dc	12	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew	0:ad9dfc0179dc	13	*
EricLew	0:ad9dfc0179dc	14	* Redistribution and use in source and binary forms, with or without modification,
EricLew	0:ad9dfc0179dc	15	* are permitted provided that the following conditions are met:
EricLew	0:ad9dfc0179dc	16	* 1. Redistributions of source code must retain the above copyright notice,
EricLew	0:ad9dfc0179dc	17	* this list of conditions and the following disclaimer.
EricLew	0:ad9dfc0179dc	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew	0:ad9dfc0179dc	19	* this list of conditions and the following disclaimer in the documentation
EricLew	0:ad9dfc0179dc	20	* and/or other materials provided with the distribution.
EricLew	0:ad9dfc0179dc	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew	0:ad9dfc0179dc	22	* may be used to endorse or promote products derived from this software
EricLew	0:ad9dfc0179dc	23	* without specific prior written permission.
EricLew	0:ad9dfc0179dc	24	*
EricLew	0:ad9dfc0179dc	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew	0:ad9dfc0179dc	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew	0:ad9dfc0179dc	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew	0:ad9dfc0179dc	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew	0:ad9dfc0179dc	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew	0:ad9dfc0179dc	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew	0:ad9dfc0179dc	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew	0:ad9dfc0179dc	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew	0:ad9dfc0179dc	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew	0:ad9dfc0179dc	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew	0:ad9dfc0179dc	35	*
EricLew	0:ad9dfc0179dc	36	******************************************************************************
EricLew	0:ad9dfc0179dc	37	*/
EricLew	0:ad9dfc0179dc	38
EricLew	0:ad9dfc0179dc	39	/* Includes ------------------------------------------------------------------*/
EricLew	0:ad9dfc0179dc	40	#include "mfxstm32l152.h"
EricLew	0:ad9dfc0179dc	41
EricLew	0:ad9dfc0179dc	42	/** @addtogroup BSP
EricLew	0:ad9dfc0179dc	43	* @{
EricLew	0:ad9dfc0179dc	44	*/
EricLew	0:ad9dfc0179dc	45
EricLew	0:ad9dfc0179dc	46	/** @addtogroup Component
EricLew	0:ad9dfc0179dc	47	* @{
EricLew	0:ad9dfc0179dc	48	*/
EricLew	0:ad9dfc0179dc	49
EricLew	0:ad9dfc0179dc	50	/** @defgroup MFXSTM32L152
EricLew	0:ad9dfc0179dc	51	* @{
EricLew	0:ad9dfc0179dc	52	*/
EricLew	0:ad9dfc0179dc	53
EricLew	0:ad9dfc0179dc	54	/* Private typedef -----------------------------------------------------------*/
EricLew	0:ad9dfc0179dc	55
EricLew	0:ad9dfc0179dc	56	/** @defgroup MFXSTM32L152_Private_Types_Definitions
EricLew	0:ad9dfc0179dc	57	* @{
EricLew	0:ad9dfc0179dc	58	*/
EricLew	0:ad9dfc0179dc	59
EricLew	0:ad9dfc0179dc	60	/* Private define ------------------------------------------------------------*/
EricLew	0:ad9dfc0179dc	61
EricLew	0:ad9dfc0179dc	62	/** @defgroup MFXSTM32L152_Private_Defines
EricLew	0:ad9dfc0179dc	63	* @{
EricLew	0:ad9dfc0179dc	64	*/
EricLew	0:ad9dfc0179dc	65	#define MFXSTM32L152_MAX_INSTANCE 3
EricLew	0:ad9dfc0179dc	66
EricLew	0:ad9dfc0179dc	67	/* Private macro -------------------------------------------------------------*/
EricLew	0:ad9dfc0179dc	68
EricLew	0:ad9dfc0179dc	69	/** @defgroup MFXSTM32L152_Private_Macros
EricLew	0:ad9dfc0179dc	70	* @{
EricLew	0:ad9dfc0179dc	71	*/
EricLew	0:ad9dfc0179dc	72
EricLew	0:ad9dfc0179dc	73	/* Private variables ---------------------------------------------------------*/
EricLew	0:ad9dfc0179dc	74
EricLew	0:ad9dfc0179dc	75	/** @defgroup MFXSTM32L152_Private_Variables
EricLew	0:ad9dfc0179dc	76	* @{
EricLew	0:ad9dfc0179dc	77	*/
EricLew	0:ad9dfc0179dc	78
EricLew	0:ad9dfc0179dc	79	/* Touch screen driver structure initialization */
EricLew	0:ad9dfc0179dc	80	TS_DrvTypeDef mfxstm32l152_ts_drv =
EricLew	0:ad9dfc0179dc	81	{
EricLew	0:ad9dfc0179dc	82	mfxstm32l152_Init,
EricLew	0:ad9dfc0179dc	83	mfxstm32l152_ReadID,
EricLew	0:ad9dfc0179dc	84	mfxstm32l152_Reset,
EricLew	0:ad9dfc0179dc	85
EricLew	0:ad9dfc0179dc	86	mfxstm32l152_TS_Start,
EricLew	0:ad9dfc0179dc	87	mfxstm32l152_TS_DetectTouch,
EricLew	0:ad9dfc0179dc	88	mfxstm32l152_TS_GetXY,
EricLew	0:ad9dfc0179dc	89
EricLew	0:ad9dfc0179dc	90	mfxstm32l152_TS_EnableIT,
EricLew	0:ad9dfc0179dc	91	mfxstm32l152_TS_ClearIT,
EricLew	0:ad9dfc0179dc	92	mfxstm32l152_TS_ITStatus,
EricLew	0:ad9dfc0179dc	93	mfxstm32l152_TS_DisableIT,
EricLew	0:ad9dfc0179dc	94	};
EricLew	0:ad9dfc0179dc	95
EricLew	0:ad9dfc0179dc	96	/* IO driver structure initialization */
EricLew	0:ad9dfc0179dc	97	IO_DrvTypeDef mfxstm32l152_io_drv =
EricLew	0:ad9dfc0179dc	98	{
EricLew	0:ad9dfc0179dc	99	mfxstm32l152_Init,
EricLew	0:ad9dfc0179dc	100	mfxstm32l152_ReadID,
EricLew	0:ad9dfc0179dc	101	mfxstm32l152_Reset,
EricLew	0:ad9dfc0179dc	102
EricLew	0:ad9dfc0179dc	103	mfxstm32l152_IO_Start,
EricLew	0:ad9dfc0179dc	104	mfxstm32l152_IO_Config,
EricLew	0:ad9dfc0179dc	105	mfxstm32l152_IO_WritePin,
EricLew	0:ad9dfc0179dc	106	mfxstm32l152_IO_ReadPin,
EricLew	0:ad9dfc0179dc	107
EricLew	0:ad9dfc0179dc	108	mfxstm32l152_IO_EnableIT,
EricLew	0:ad9dfc0179dc	109	mfxstm32l152_IO_DisableIT,
EricLew	0:ad9dfc0179dc	110	mfxstm32l152_IO_ITStatus,
EricLew	0:ad9dfc0179dc	111	mfxstm32l152_IO_ClearIT,
EricLew	0:ad9dfc0179dc	112	};
EricLew	0:ad9dfc0179dc	113
EricLew	0:ad9dfc0179dc	114	/* IDD driver structure initialization */
EricLew	0:ad9dfc0179dc	115	IDD_DrvTypeDef mfxstm32l152_idd_drv =
EricLew	0:ad9dfc0179dc	116	{
EricLew	0:ad9dfc0179dc	117	mfxstm32l152_Init,
EricLew	0:ad9dfc0179dc	118	mfxstm32l152_DeInit,
EricLew	0:ad9dfc0179dc	119	mfxstm32l152_ReadID,
EricLew	0:ad9dfc0179dc	120	mfxstm32l152_Reset,
EricLew	0:ad9dfc0179dc	121	mfxstm32l152_LowPower,
EricLew	0:ad9dfc0179dc	122	mfxstm32l152_WakeUp,
EricLew	0:ad9dfc0179dc	123
EricLew	0:ad9dfc0179dc	124	mfxstm32l152_IDD_Start,
EricLew	0:ad9dfc0179dc	125	mfxstm32l152_IDD_Config,
EricLew	0:ad9dfc0179dc	126	mfxstm32l152_IDD_GetValue,
EricLew	0:ad9dfc0179dc	127
EricLew	0:ad9dfc0179dc	128	mfxstm32l152_IDD_EnableIT,
EricLew	0:ad9dfc0179dc	129	mfxstm32l152_IDD_ClearIT,
EricLew	0:ad9dfc0179dc	130	mfxstm32l152_IDD_GetITStatus,
EricLew	0:ad9dfc0179dc	131	mfxstm32l152_IDD_DisableIT,
EricLew	0:ad9dfc0179dc	132
EricLew	0:ad9dfc0179dc	133	mfxstm32l152_Error_EnableIT,
EricLew	0:ad9dfc0179dc	134	mfxstm32l152_Error_ClearIT,
EricLew	0:ad9dfc0179dc	135	mfxstm32l152_Error_GetITStatus,
EricLew	0:ad9dfc0179dc	136	mfxstm32l152_Error_DisableIT,
EricLew	0:ad9dfc0179dc	137	mfxstm32l152_Error_ReadSrc,
EricLew	0:ad9dfc0179dc	138	mfxstm32l152_Error_ReadMsg
EricLew	0:ad9dfc0179dc	139	};
EricLew	0:ad9dfc0179dc	140
EricLew	0:ad9dfc0179dc	141
EricLew	0:ad9dfc0179dc	142	/* mfxstm32l152 instances by address */
EricLew	0:ad9dfc0179dc	143	uint8_t mfxstm32l152[MFXSTM32L152_MAX_INSTANCE] = {0};
EricLew	0:ad9dfc0179dc	144	/**
EricLew	0:ad9dfc0179dc	145	* @}
EricLew	0:ad9dfc0179dc	146	*/
EricLew	0:ad9dfc0179dc	147
EricLew	0:ad9dfc0179dc	148	/* Private function prototypes -----------------------------------------------*/
EricLew	0:ad9dfc0179dc	149
EricLew	0:ad9dfc0179dc	150	/** @defgroup MFXSTM32L152_Private_Function_Prototypes
EricLew	0:ad9dfc0179dc	151	* @{
EricLew	0:ad9dfc0179dc	152	*/
EricLew	0:ad9dfc0179dc	153	static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr);
EricLew	0:ad9dfc0179dc	154	static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr);
EricLew	0:ad9dfc0179dc	155	static void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue );
EricLew	0:ad9dfc0179dc	156
EricLew	0:ad9dfc0179dc	157	/* Private functions ---------------------------------------------------------*/
EricLew	0:ad9dfc0179dc	158
EricLew	0:ad9dfc0179dc	159	/** @defgroup MFXSTM32L152_Private_Functions
EricLew	0:ad9dfc0179dc	160	* @{
EricLew	0:ad9dfc0179dc	161	*/
EricLew	0:ad9dfc0179dc	162
EricLew	0:ad9dfc0179dc	163	/**
EricLew	0:ad9dfc0179dc	164	* @brief Initialize the mfxstm32l152 and configure the needed hardware resources
EricLew	0:ad9dfc0179dc	165	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	166	* @retval None
EricLew	0:ad9dfc0179dc	167	*/
EricLew	0:ad9dfc0179dc	168	void mfxstm32l152_Init(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	169	{
EricLew	0:ad9dfc0179dc	170	uint8_t instance;
EricLew	0:ad9dfc0179dc	171	uint8_t empty;
EricLew	0:ad9dfc0179dc	172
EricLew	0:ad9dfc0179dc	173	/* Check if device instance already exists */
EricLew	0:ad9dfc0179dc	174	instance = mfxstm32l152_GetInstance(DeviceAddr);
EricLew	0:ad9dfc0179dc	175
EricLew	0:ad9dfc0179dc	176	/* To prevent double initialization */
EricLew	0:ad9dfc0179dc	177	if(instance == 0xFF)
EricLew	0:ad9dfc0179dc	178	{
EricLew	0:ad9dfc0179dc	179	/* Look for empty instance */
EricLew	0:ad9dfc0179dc	180	empty = mfxstm32l152_GetInstance(0);
EricLew	0:ad9dfc0179dc	181
EricLew	0:ad9dfc0179dc	182	if(empty < MFXSTM32L152_MAX_INSTANCE)
EricLew	0:ad9dfc0179dc	183	{
EricLew	0:ad9dfc0179dc	184	/* Register the current device instance */
EricLew	0:ad9dfc0179dc	185	mfxstm32l152[empty] = DeviceAddr;
EricLew	0:ad9dfc0179dc	186
EricLew	0:ad9dfc0179dc	187	/* Initialize IO BUS layer */
EricLew	0:ad9dfc0179dc	188	MFX_IO_Init();
EricLew	0:ad9dfc0179dc	189	}
EricLew	0:ad9dfc0179dc	190	}
EricLew	0:ad9dfc0179dc	191
EricLew	0:ad9dfc0179dc	192	mfxstm32l152_SetIrqOutPinPolarity(DeviceAddr, MFXSTM32L152_OUT_PIN_POLARITY_HIGH);
EricLew	0:ad9dfc0179dc	193	mfxstm32l152_SetIrqOutPinType(DeviceAddr, MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL);
EricLew	0:ad9dfc0179dc	194	}
EricLew	0:ad9dfc0179dc	195
EricLew	0:ad9dfc0179dc	196	/**
EricLew	0:ad9dfc0179dc	197	* @brief DeInitialize the mfxstm32l152 and unconfigure the needed hardware resources
EricLew	0:ad9dfc0179dc	198	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	199	* @retval None
EricLew	0:ad9dfc0179dc	200	*/
EricLew	0:ad9dfc0179dc	201	void mfxstm32l152_DeInit(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	202	{
EricLew	0:ad9dfc0179dc	203	uint8_t instance;
EricLew	0:ad9dfc0179dc	204
EricLew	0:ad9dfc0179dc	205	/* release existing instance */
EricLew	0:ad9dfc0179dc	206	instance = mfxstm32l152_ReleaseInstance(DeviceAddr);
EricLew	0:ad9dfc0179dc	207
EricLew	0:ad9dfc0179dc	208	/* De-Init only if instance was previously registered */
EricLew	0:ad9dfc0179dc	209	if(instance != 0xFF)
EricLew	0:ad9dfc0179dc	210	{
EricLew	0:ad9dfc0179dc	211	/* De-Initialize IO BUS layer */
EricLew	0:ad9dfc0179dc	212	MFX_IO_DeInit();
EricLew	0:ad9dfc0179dc	213	}
EricLew	0:ad9dfc0179dc	214	}
EricLew	0:ad9dfc0179dc	215
EricLew	0:ad9dfc0179dc	216	/**
EricLew	0:ad9dfc0179dc	217	* @brief Reset the mfxstm32l152 by Software.
EricLew	0:ad9dfc0179dc	218	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	219	* @retval None
EricLew	0:ad9dfc0179dc	220	*/
EricLew	0:ad9dfc0179dc	221	void mfxstm32l152_Reset(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	222	{
EricLew	0:ad9dfc0179dc	223	/* Soft Reset */
EricLew	0:ad9dfc0179dc	224	MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_SWRST);
EricLew	0:ad9dfc0179dc	225
EricLew	0:ad9dfc0179dc	226	/* Wait for a delay to ensure registers erasing */
EricLew	0:ad9dfc0179dc	227	MFX_IO_Delay(10);
EricLew	0:ad9dfc0179dc	228	}
EricLew	0:ad9dfc0179dc	229
EricLew	0:ad9dfc0179dc	230	/**
EricLew	0:ad9dfc0179dc	231	* @brief Put mfxstm32l152 Device in Low Power standby mode
EricLew	0:ad9dfc0179dc	232	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	233	* @retval None
EricLew	0:ad9dfc0179dc	234	*/
EricLew	0:ad9dfc0179dc	235	void mfxstm32l152_LowPower(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	236	{
EricLew	0:ad9dfc0179dc	237	/* Enter standby mode */
EricLew	0:ad9dfc0179dc	238	MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_STANDBY);
EricLew	0:ad9dfc0179dc	239
EricLew	0:ad9dfc0179dc	240	/* enable wakeup pin */
EricLew	0:ad9dfc0179dc	241	MFX_IO_EnableWakeupPin();
EricLew	0:ad9dfc0179dc	242	}
EricLew	0:ad9dfc0179dc	243
EricLew	0:ad9dfc0179dc	244	/**
EricLew	0:ad9dfc0179dc	245	* @brief WakeUp mfxstm32l152 from standby mode
EricLew	0:ad9dfc0179dc	246	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	247	* @retval None
EricLew	0:ad9dfc0179dc	248	*/
EricLew	0:ad9dfc0179dc	249	void mfxstm32l152_WakeUp(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	250	{
EricLew	0:ad9dfc0179dc	251	uint8_t instance;
EricLew	0:ad9dfc0179dc	252
EricLew	0:ad9dfc0179dc	253	/* Check if device instance already exists */
EricLew	0:ad9dfc0179dc	254	instance = mfxstm32l152_GetInstance(DeviceAddr);
EricLew	0:ad9dfc0179dc	255
EricLew	0:ad9dfc0179dc	256	/* if instance does not exist, first initialize pins*/
EricLew	0:ad9dfc0179dc	257	if(instance == 0xFF)
EricLew	0:ad9dfc0179dc	258	{
EricLew	0:ad9dfc0179dc	259	/* enable wakeup pin */
EricLew	0:ad9dfc0179dc	260	MFX_IO_EnableWakeupPin();
EricLew	0:ad9dfc0179dc	261	}
EricLew	0:ad9dfc0179dc	262
EricLew	0:ad9dfc0179dc	263	/* toggle wakeup pin */
EricLew	0:ad9dfc0179dc	264	MFX_IO_Wakeup();
EricLew	0:ad9dfc0179dc	265	}
EricLew	0:ad9dfc0179dc	266
EricLew	0:ad9dfc0179dc	267	/**
EricLew	0:ad9dfc0179dc	268	* @brief Read the MFXSTM32L152 IO Expander device ID.
EricLew	0:ad9dfc0179dc	269	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	270	* @retval The Device ID (two bytes).
EricLew	0:ad9dfc0179dc	271	*/
EricLew	0:ad9dfc0179dc	272	uint16_t mfxstm32l152_ReadID(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	273	{
EricLew	0:ad9dfc0179dc	274	uint8_t id;
EricLew	0:ad9dfc0179dc	275
EricLew	0:ad9dfc0179dc	276	/* Wait for a delay to ensure the state of registers */
EricLew	0:ad9dfc0179dc	277	MFX_IO_Delay(1);
EricLew	0:ad9dfc0179dc	278
EricLew	0:ad9dfc0179dc	279	/* Initialize IO BUS layer */
EricLew	0:ad9dfc0179dc	280	MFX_IO_Init();
EricLew	0:ad9dfc0179dc	281
EricLew	0:ad9dfc0179dc	282	id = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_ID);
EricLew	0:ad9dfc0179dc	283
EricLew	0:ad9dfc0179dc	284	/* Return the device ID value */
EricLew	0:ad9dfc0179dc	285	return (id);
EricLew	0:ad9dfc0179dc	286	}
EricLew	0:ad9dfc0179dc	287
EricLew	0:ad9dfc0179dc	288	/**
EricLew	0:ad9dfc0179dc	289	* @brief Read the MFXSTM32L152 device firmware version.
EricLew	0:ad9dfc0179dc	290	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	291	* @retval The Device FW version (two bytes).
EricLew	0:ad9dfc0179dc	292	*/
EricLew	0:ad9dfc0179dc	293	uint16_t mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	294	{
EricLew	0:ad9dfc0179dc	295	uint8_t data[2];
EricLew	0:ad9dfc0179dc	296
EricLew	0:ad9dfc0179dc	297	MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_FW_VERSION_MSB, data, sizeof(data)) ;
EricLew	0:ad9dfc0179dc	298
EricLew	0:ad9dfc0179dc	299	/* Recompose MFX firmware value */
EricLew	0:ad9dfc0179dc	300	return ((data[0] << 8) \| data[1]);
EricLew	0:ad9dfc0179dc	301	}
EricLew	0:ad9dfc0179dc	302
EricLew	0:ad9dfc0179dc	303	/**
EricLew	0:ad9dfc0179dc	304	* @brief Enable the interrupt mode for the selected IT source
EricLew	0:ad9dfc0179dc	305	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	306	* @param Source: The interrupt source to be configured, could be:
EricLew	0:ad9dfc0179dc	307	* @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
EricLew	0:ad9dfc0179dc	308	* @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
EricLew	0:ad9dfc0179dc	309	* @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
EricLew	0:ad9dfc0179dc	310	* @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
EricLew	0:ad9dfc0179dc	311	* @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
EricLew	0:ad9dfc0179dc	312	* @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
EricLew	0:ad9dfc0179dc	313	* @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
EricLew	0:ad9dfc0179dc	314	* @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
EricLew	0:ad9dfc0179dc	315	* @retval None
EricLew	0:ad9dfc0179dc	316	*/
EricLew	0:ad9dfc0179dc	317	void mfxstm32l152_EnableITSource(uint16_t DeviceAddr, uint8_t Source)
EricLew	0:ad9dfc0179dc	318	{
EricLew	0:ad9dfc0179dc	319	uint8_t tmp = 0;
EricLew	0:ad9dfc0179dc	320
EricLew	0:ad9dfc0179dc	321	/* Get the current value of the INT_EN register */
EricLew	0:ad9dfc0179dc	322	tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN);
EricLew	0:ad9dfc0179dc	323
EricLew	0:ad9dfc0179dc	324	/* Set the interrupts to be Enabled */
EricLew	0:ad9dfc0179dc	325	tmp \|= Source;
EricLew	0:ad9dfc0179dc	326
EricLew	0:ad9dfc0179dc	327	/* Set the register */
EricLew	0:ad9dfc0179dc	328	MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp);
EricLew	0:ad9dfc0179dc	329	}
EricLew	0:ad9dfc0179dc	330
EricLew	0:ad9dfc0179dc	331	/**
EricLew	0:ad9dfc0179dc	332	* @brief Disable the interrupt mode for the selected IT source
EricLew	0:ad9dfc0179dc	333	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	334	* @param Source: The interrupt source to be configured, could be:
EricLew	0:ad9dfc0179dc	335	* @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
EricLew	0:ad9dfc0179dc	336	* @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
EricLew	0:ad9dfc0179dc	337	* @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
EricLew	0:ad9dfc0179dc	338	* @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
EricLew	0:ad9dfc0179dc	339	* @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
EricLew	0:ad9dfc0179dc	340	* @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
EricLew	0:ad9dfc0179dc	341	* @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
EricLew	0:ad9dfc0179dc	342	* @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
EricLew	0:ad9dfc0179dc	343	* @retval None
EricLew	0:ad9dfc0179dc	344	*/
EricLew	0:ad9dfc0179dc	345	void mfxstm32l152_DisableITSource(uint16_t DeviceAddr, uint8_t Source)
EricLew	0:ad9dfc0179dc	346	{
EricLew	0:ad9dfc0179dc	347	uint8_t tmp = 0;
EricLew	0:ad9dfc0179dc	348
EricLew	0:ad9dfc0179dc	349	/* Get the current value of the INT_EN register */
EricLew	0:ad9dfc0179dc	350	tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN);
EricLew	0:ad9dfc0179dc	351
EricLew	0:ad9dfc0179dc	352	/* Set the interrupts to be Enabled */
EricLew	0:ad9dfc0179dc	353	tmp &= ~Source;
EricLew	0:ad9dfc0179dc	354
EricLew	0:ad9dfc0179dc	355	/* Set the register */
EricLew	0:ad9dfc0179dc	356	MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp);
EricLew	0:ad9dfc0179dc	357	}
EricLew	0:ad9dfc0179dc	358
EricLew	0:ad9dfc0179dc	359
EricLew	0:ad9dfc0179dc	360	/**
EricLew	0:ad9dfc0179dc	361	* @brief Returns the selected Global interrupt source pending bit value
EricLew	0:ad9dfc0179dc	362	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	363	* @param Source: the Global interrupt source to be checked, could be:
EricLew	0:ad9dfc0179dc	364	* @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
EricLew	0:ad9dfc0179dc	365	* @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
EricLew	0:ad9dfc0179dc	366	* @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
EricLew	0:ad9dfc0179dc	367	* @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
EricLew	0:ad9dfc0179dc	368	* @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
EricLew	0:ad9dfc0179dc	369	* @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
EricLew	0:ad9dfc0179dc	370	* @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
EricLew	0:ad9dfc0179dc	371	* @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
EricLew	0:ad9dfc0179dc	372	* @retval The value of the checked Global interrupt source status.
EricLew	0:ad9dfc0179dc	373	*/
EricLew	0:ad9dfc0179dc	374	uint8_t mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source)
EricLew	0:ad9dfc0179dc	375	{
EricLew	0:ad9dfc0179dc	376	/* Return the global IT source status (pending or not)*/
EricLew	0:ad9dfc0179dc	377	return((MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_PENDING) & Source));
EricLew	0:ad9dfc0179dc	378	}
EricLew	0:ad9dfc0179dc	379
EricLew	0:ad9dfc0179dc	380	/**
EricLew	0:ad9dfc0179dc	381	* @brief Clear the selected Global interrupt pending bit(s)
EricLew	0:ad9dfc0179dc	382	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	383	* @param Source: the Global interrupt source to be cleared, could be any combination
EricLew	0:ad9dfc0179dc	384	* of the below values. The acknowledge signal for MFXSTM32L152_GPIOs configured in input
EricLew	0:ad9dfc0179dc	385	* with interrupt is not on this register but in IRQ_GPI_ACK1, IRQ_GPI_ACK2 registers.
EricLew	0:ad9dfc0179dc	386	* @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
EricLew	0:ad9dfc0179dc	387	* @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
EricLew	0:ad9dfc0179dc	388	* @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
EricLew	0:ad9dfc0179dc	389	* @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
EricLew	0:ad9dfc0179dc	390	* @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
EricLew	0:ad9dfc0179dc	391	* @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
EricLew	0:ad9dfc0179dc	392	* @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
EricLew	0:ad9dfc0179dc	393	* /\/\ IMPORTANT NOTE /\/\ must not use MFXSTM32L152_IRQ_GPIO as argument, see IRQ_GPI_ACK1 and IRQ_GPI_ACK2 registers
EricLew	0:ad9dfc0179dc	394	* @retval None
EricLew	0:ad9dfc0179dc	395	*/
EricLew	0:ad9dfc0179dc	396	void mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source)
EricLew	0:ad9dfc0179dc	397	{
EricLew	0:ad9dfc0179dc	398	/* Write 1 to the bits that have to be cleared */
EricLew	0:ad9dfc0179dc	399	MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_ACK, Source);
EricLew	0:ad9dfc0179dc	400	}
EricLew	0:ad9dfc0179dc	401
EricLew	0:ad9dfc0179dc	402	/**
EricLew	0:ad9dfc0179dc	403	* @brief Set the global interrupt Polarity of IRQ_OUT_PIN.
EricLew	0:ad9dfc0179dc	404	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	405	* @param Polarity: the IT mode polarity, could be one of the following values:
EricLew	0:ad9dfc0179dc	406	* @arg MFXSTM32L152_OUT_PIN_POLARITY_LOW: Interrupt output line is active Low edge
EricLew	0:ad9dfc0179dc	407	* @arg MFXSTM32L152_OUT_PIN_POLARITY_HIGH: Interrupt line output is active High edge
EricLew	0:ad9dfc0179dc	408	* @retval None
EricLew	0:ad9dfc0179dc	409	*/
EricLew	0:ad9dfc0179dc	410	void mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr, uint8_t Polarity)
EricLew	0:ad9dfc0179dc	411	{
EricLew	0:ad9dfc0179dc	412	uint8_t tmp = 0;
EricLew	0:ad9dfc0179dc	413
EricLew	0:ad9dfc0179dc	414	/* Get the current register value */
EricLew	0:ad9dfc0179dc	415	tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT);
EricLew	0:ad9dfc0179dc	416
EricLew	0:ad9dfc0179dc	417	/* Mask the polarity bits */
EricLew	0:ad9dfc0179dc	418	tmp &= ~(uint8_t)0x02;
EricLew	0:ad9dfc0179dc	419
EricLew	0:ad9dfc0179dc	420	/* Modify the Interrupt Output line configuration */
EricLew	0:ad9dfc0179dc	421	tmp \|= Polarity;
EricLew	0:ad9dfc0179dc	422
EricLew	0:ad9dfc0179dc	423	/* Set the new register value */
EricLew	0:ad9dfc0179dc	424	MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp);
EricLew	0:ad9dfc0179dc	425
EricLew	0:ad9dfc0179dc	426	/* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
EricLew	0:ad9dfc0179dc	427	MFX_IO_Delay(1);
EricLew	0:ad9dfc0179dc	428
EricLew	0:ad9dfc0179dc	429	}
EricLew	0:ad9dfc0179dc	430
EricLew	0:ad9dfc0179dc	431	/**
EricLew	0:ad9dfc0179dc	432	* @brief Set the global interrupt Type of IRQ_OUT_PIN.
EricLew	0:ad9dfc0179dc	433	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	434	* @param Type: Interrupt line activity type, could be one of the following values:
EricLew	0:ad9dfc0179dc	435	* @arg MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN: Open Drain output Interrupt line
EricLew	0:ad9dfc0179dc	436	* @arg MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL: Push Pull output Interrupt line
EricLew	0:ad9dfc0179dc	437	* @retval None
EricLew	0:ad9dfc0179dc	438	*/
EricLew	0:ad9dfc0179dc	439	void mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr, uint8_t Type)
EricLew	0:ad9dfc0179dc	440	{
EricLew	0:ad9dfc0179dc	441	uint8_t tmp = 0;
EricLew	0:ad9dfc0179dc	442
EricLew	0:ad9dfc0179dc	443	/* Get the current register value */
EricLew	0:ad9dfc0179dc	444	tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT);
EricLew	0:ad9dfc0179dc	445
EricLew	0:ad9dfc0179dc	446	/* Mask the type bits */
EricLew	0:ad9dfc0179dc	447	tmp &= ~(uint8_t)0x01;
EricLew	0:ad9dfc0179dc	448
EricLew	0:ad9dfc0179dc	449	/* Modify the Interrupt Output line configuration */
EricLew	0:ad9dfc0179dc	450	tmp \|= Type;
EricLew	0:ad9dfc0179dc	451
EricLew	0:ad9dfc0179dc	452	/* Set the new register value */
EricLew	0:ad9dfc0179dc	453	MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp);
EricLew	0:ad9dfc0179dc	454
EricLew	0:ad9dfc0179dc	455	/* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
EricLew	0:ad9dfc0179dc	456	MFX_IO_Delay(1);
EricLew	0:ad9dfc0179dc	457
EricLew	0:ad9dfc0179dc	458	}
EricLew	0:ad9dfc0179dc	459
EricLew	0:ad9dfc0179dc	460
EricLew	0:ad9dfc0179dc	461	/* ------------------------------------------------------------------ */
EricLew	0:ad9dfc0179dc	462	/* ----------------------- GPIO ------------------------------------- */
EricLew	0:ad9dfc0179dc	463	/* ------------------------------------------------------------------ */
EricLew	0:ad9dfc0179dc	464
EricLew	0:ad9dfc0179dc	465
EricLew	0:ad9dfc0179dc	466	/**
EricLew	0:ad9dfc0179dc	467	* @brief Start the IO functionality used and enable the AF for selected IO pin(s).
EricLew	0:ad9dfc0179dc	468	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	469	* @param AF_en: 0 to disable, else enabled.
EricLew	0:ad9dfc0179dc	470	* @retval None
EricLew	0:ad9dfc0179dc	471	*/
EricLew	0:ad9dfc0179dc	472	void mfxstm32l152_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin)
EricLew	0:ad9dfc0179dc	473	{
EricLew	0:ad9dfc0179dc	474	uint8_t mode;
EricLew	0:ad9dfc0179dc	475
EricLew	0:ad9dfc0179dc	476	/* Get the current register value */
EricLew	0:ad9dfc0179dc	477	mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
EricLew	0:ad9dfc0179dc	478
EricLew	0:ad9dfc0179dc	479	/* Set the IO Functionalities to be Enabled */
EricLew	0:ad9dfc0179dc	480	mode \|= MFXSTM32L152_GPIO_EN;
EricLew	0:ad9dfc0179dc	481
EricLew	0:ad9dfc0179dc	482	/* Enable ALTERNATE functions */
EricLew	0:ad9dfc0179dc	483	/* AGPIO[0..3] can be either IDD or GPIO */
EricLew	0:ad9dfc0179dc	484	/* AGPIO[4..7] can be either TS or GPIO */
EricLew	0:ad9dfc0179dc	485	/* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
EricLew	0:ad9dfc0179dc	486	/* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
EricLew	0:ad9dfc0179dc	487	/* so if IDD and TS are both active it is better to let ALTERNATE off (0) */
EricLew	0:ad9dfc0179dc	488	/* if however IDD or TS are not connected then set it on gives more GPIOs availability */
EricLew	0:ad9dfc0179dc	489	/* remind that AGPIO are less efficient then normal GPIO (They use pooling rather then EXTI */
EricLew	0:ad9dfc0179dc	490	if (IO_Pin > 0xFFFF)
EricLew	0:ad9dfc0179dc	491	{
EricLew	0:ad9dfc0179dc	492	mode \|= MFXSTM32L152_ALTERNATE_GPIO_EN;
EricLew	0:ad9dfc0179dc	493	}
EricLew	0:ad9dfc0179dc	494	else
EricLew	0:ad9dfc0179dc	495	{
EricLew	0:ad9dfc0179dc	496	mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN;
EricLew	0:ad9dfc0179dc	497	}
EricLew	0:ad9dfc0179dc	498
EricLew	0:ad9dfc0179dc	499	/* Write the new register value */
EricLew	0:ad9dfc0179dc	500	MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
EricLew	0:ad9dfc0179dc	501
EricLew	0:ad9dfc0179dc	502	/* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
EricLew	0:ad9dfc0179dc	503	MFX_IO_Delay(1);
EricLew	0:ad9dfc0179dc	504	}
EricLew	0:ad9dfc0179dc	505
EricLew	0:ad9dfc0179dc	506	/**
EricLew	0:ad9dfc0179dc	507	* @brief Configures the IO pin(s) according to IO mode structure value.
EricLew	0:ad9dfc0179dc	508	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	509	* @param IO_Pin: The output pin to be set or reset. This parameter can be one
EricLew	0:ad9dfc0179dc	510	* of the following values:
EricLew	0:ad9dfc0179dc	511	* @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
EricLew	0:ad9dfc0179dc	512	* @param IO_Mode: The IO pin mode to configure, could be one of the following values:
EricLew	0:ad9dfc0179dc	513	* @arg IO_MODE_INPUT
EricLew	0:ad9dfc0179dc	514	* @arg IO_MODE_OUTPUT
EricLew	0:ad9dfc0179dc	515	* @arg IO_MODE_IT_RISING_EDGE
EricLew	0:ad9dfc0179dc	516	* @arg IO_MODE_IT_FALLING_EDGE
EricLew	0:ad9dfc0179dc	517	* @arg IO_MODE_IT_LOW_LEVEL
EricLew	0:ad9dfc0179dc	518	* @arg IO_MODE_IT_HIGH_LEVEL
EricLew	0:ad9dfc0179dc	519	* @arg IO_MODE_INPUT_PU,
EricLew	0:ad9dfc0179dc	520	* @arg IO_MODE_INPUT_PD,
EricLew	0:ad9dfc0179dc	521	* @arg IO_MODE_OUTPUT_OD_PU,
EricLew	0:ad9dfc0179dc	522	* @arg IO_MODE_OUTPUT_OD_PD,
EricLew	0:ad9dfc0179dc	523	* @arg IO_MODE_OUTPUT_PP_PU,
EricLew	0:ad9dfc0179dc	524	* @arg IO_MODE_OUTPUT_PP_PD,
EricLew	0:ad9dfc0179dc	525	* @arg IO_MODE_IT_RISING_EDGE_PU
EricLew	0:ad9dfc0179dc	526	* @arg IO_MODE_IT_FALLING_EDGE_PU
EricLew	0:ad9dfc0179dc	527	* @arg IO_MODE_IT_LOW_LEVEL_PU
EricLew	0:ad9dfc0179dc	528	* @arg IO_MODE_IT_HIGH_LEVEL_PU
EricLew	0:ad9dfc0179dc	529	* @arg IO_MODE_IT_RISING_EDGE_PD
EricLew	0:ad9dfc0179dc	530	* @arg IO_MODE_IT_FALLING_EDGE_PD
EricLew	0:ad9dfc0179dc	531	* @arg IO_MODE_IT_LOW_LEVEL_PD
EricLew	0:ad9dfc0179dc	532	* @arg IO_MODE_IT_HIGH_LEVEL_PD
EricLew	0:ad9dfc0179dc	533	* @retval None
EricLew	0:ad9dfc0179dc	534	*/
EricLew	0:ad9dfc0179dc	535	uint8_t mfxstm32l152_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode)
EricLew	0:ad9dfc0179dc	536	{
EricLew	0:ad9dfc0179dc	537	uint8_t error_code = 0;
EricLew	0:ad9dfc0179dc	538
EricLew	0:ad9dfc0179dc	539	/* Configure IO pin according to selected IO mode */
EricLew	0:ad9dfc0179dc	540	switch(IO_Mode)
EricLew	0:ad9dfc0179dc	541	{
EricLew	0:ad9dfc0179dc	542	case IO_MODE_OFF: /* Off or analog mode */
EricLew	0:ad9dfc0179dc	543	case IO_MODE_ANALOG: /* Off or analog mode */
EricLew	0:ad9dfc0179dc	544	mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
EricLew	0:ad9dfc0179dc	545	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
EricLew	0:ad9dfc0179dc	546	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
EricLew	0:ad9dfc0179dc	547	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
EricLew	0:ad9dfc0179dc	548	break;
EricLew	0:ad9dfc0179dc	549
EricLew	0:ad9dfc0179dc	550	case IO_MODE_INPUT: /* Input mode */
EricLew	0:ad9dfc0179dc	551	mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
EricLew	0:ad9dfc0179dc	552	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
EricLew	0:ad9dfc0179dc	553	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
EricLew	0:ad9dfc0179dc	554	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
EricLew	0:ad9dfc0179dc	555	break;
EricLew	0:ad9dfc0179dc	556
EricLew	0:ad9dfc0179dc	557	case IO_MODE_INPUT_PU: /* Input mode */
EricLew	0:ad9dfc0179dc	558	mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
EricLew	0:ad9dfc0179dc	559	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
EricLew	0:ad9dfc0179dc	560	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
EricLew	0:ad9dfc0179dc	561	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
EricLew	0:ad9dfc0179dc	562	break;
EricLew	0:ad9dfc0179dc	563
EricLew	0:ad9dfc0179dc	564	case IO_MODE_INPUT_PD: /* Input mode */
EricLew	0:ad9dfc0179dc	565	mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
EricLew	0:ad9dfc0179dc	566	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
EricLew	0:ad9dfc0179dc	567	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
EricLew	0:ad9dfc0179dc	568	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
EricLew	0:ad9dfc0179dc	569	break;
EricLew	0:ad9dfc0179dc	570
EricLew	0:ad9dfc0179dc	571	case IO_MODE_OUTPUT: /* Output mode */
EricLew	0:ad9dfc0179dc	572	case IO_MODE_OUTPUT_PP_PD: /* Output mode */
EricLew	0:ad9dfc0179dc	573	mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
EricLew	0:ad9dfc0179dc	574	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
EricLew	0:ad9dfc0179dc	575	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL);
EricLew	0:ad9dfc0179dc	576	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
EricLew	0:ad9dfc0179dc	577	break;
EricLew	0:ad9dfc0179dc	578
EricLew	0:ad9dfc0179dc	579	case IO_MODE_OUTPUT_PP_PU: /* Output mode */
EricLew	0:ad9dfc0179dc	580	mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
EricLew	0:ad9dfc0179dc	581	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
EricLew	0:ad9dfc0179dc	582	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL);
EricLew	0:ad9dfc0179dc	583	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
EricLew	0:ad9dfc0179dc	584	break;
EricLew	0:ad9dfc0179dc	585
EricLew	0:ad9dfc0179dc	586	case IO_MODE_OUTPUT_OD_PD: /* Output mode */
EricLew	0:ad9dfc0179dc	587	mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
EricLew	0:ad9dfc0179dc	588	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
EricLew	0:ad9dfc0179dc	589	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN);
EricLew	0:ad9dfc0179dc	590	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
EricLew	0:ad9dfc0179dc	591	break;
EricLew	0:ad9dfc0179dc	592
EricLew	0:ad9dfc0179dc	593	case IO_MODE_OUTPUT_OD_PU: /* Output mode */
EricLew	0:ad9dfc0179dc	594	mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
EricLew	0:ad9dfc0179dc	595	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
EricLew	0:ad9dfc0179dc	596	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN);
EricLew	0:ad9dfc0179dc	597	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
EricLew	0:ad9dfc0179dc	598	break;
EricLew	0:ad9dfc0179dc	599
EricLew	0:ad9dfc0179dc	600	case IO_MODE_IT_RISING_EDGE: /* Interrupt rising edge mode */
EricLew	0:ad9dfc0179dc	601	mfxstm32l152_IO_EnableIT(DeviceAddr);
EricLew	0:ad9dfc0179dc	602	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
EricLew	0:ad9dfc0179dc	603	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
EricLew	0:ad9dfc0179dc	604	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
EricLew	0:ad9dfc0179dc	605	mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
EricLew	0:ad9dfc0179dc	606	mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
EricLew	0:ad9dfc0179dc	607	mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
EricLew	0:ad9dfc0179dc	608	break;
EricLew	0:ad9dfc0179dc	609
EricLew	0:ad9dfc0179dc	610	case IO_MODE_IT_RISING_EDGE_PU: /* Interrupt rising edge mode */
EricLew	0:ad9dfc0179dc	611	mfxstm32l152_IO_EnableIT(DeviceAddr);
EricLew	0:ad9dfc0179dc	612	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
EricLew	0:ad9dfc0179dc	613	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
EricLew	0:ad9dfc0179dc	614	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
EricLew	0:ad9dfc0179dc	615	mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
EricLew	0:ad9dfc0179dc	616	mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
EricLew	0:ad9dfc0179dc	617	mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
EricLew	0:ad9dfc0179dc	618	break;
EricLew	0:ad9dfc0179dc	619
EricLew	0:ad9dfc0179dc	620	case IO_MODE_IT_RISING_EDGE_PD: /* Interrupt rising edge mode */
EricLew	0:ad9dfc0179dc	621	mfxstm32l152_IO_EnableIT(DeviceAddr);
EricLew	0:ad9dfc0179dc	622	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
EricLew	0:ad9dfc0179dc	623	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
EricLew	0:ad9dfc0179dc	624	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
EricLew	0:ad9dfc0179dc	625	mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
EricLew	0:ad9dfc0179dc	626	mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
EricLew	0:ad9dfc0179dc	627	mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
EricLew	0:ad9dfc0179dc	628	break;
EricLew	0:ad9dfc0179dc	629
EricLew	0:ad9dfc0179dc	630	case IO_MODE_IT_FALLING_EDGE: /* Interrupt falling edge mode */
EricLew	0:ad9dfc0179dc	631	mfxstm32l152_IO_EnableIT(DeviceAddr);
EricLew	0:ad9dfc0179dc	632	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
EricLew	0:ad9dfc0179dc	633	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
EricLew	0:ad9dfc0179dc	634	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
EricLew	0:ad9dfc0179dc	635	mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
EricLew	0:ad9dfc0179dc	636	mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
EricLew	0:ad9dfc0179dc	637	mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
EricLew	0:ad9dfc0179dc	638	break;
EricLew	0:ad9dfc0179dc	639
EricLew	0:ad9dfc0179dc	640	case IO_MODE_IT_FALLING_EDGE_PU: /* Interrupt falling edge mode */
EricLew	0:ad9dfc0179dc	641	mfxstm32l152_IO_EnableIT(DeviceAddr);
EricLew	0:ad9dfc0179dc	642	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
EricLew	0:ad9dfc0179dc	643	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
EricLew	0:ad9dfc0179dc	644	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
EricLew	0:ad9dfc0179dc	645	mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
EricLew	0:ad9dfc0179dc	646	mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
EricLew	0:ad9dfc0179dc	647	mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
EricLew	0:ad9dfc0179dc	648	break;
EricLew	0:ad9dfc0179dc	649
EricLew	0:ad9dfc0179dc	650	case IO_MODE_IT_FALLING_EDGE_PD: /* Interrupt falling edge mode */
EricLew	0:ad9dfc0179dc	651	mfxstm32l152_IO_EnableIT(DeviceAddr);
EricLew	0:ad9dfc0179dc	652	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
EricLew	0:ad9dfc0179dc	653	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
EricLew	0:ad9dfc0179dc	654	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
EricLew	0:ad9dfc0179dc	655	mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
EricLew	0:ad9dfc0179dc	656	mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
EricLew	0:ad9dfc0179dc	657	mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
EricLew	0:ad9dfc0179dc	658	break;
EricLew	0:ad9dfc0179dc	659
EricLew	0:ad9dfc0179dc	660	case IO_MODE_IT_LOW_LEVEL: /* Low level interrupt mode */
EricLew	0:ad9dfc0179dc	661	mfxstm32l152_IO_EnableIT(DeviceAddr);
EricLew	0:ad9dfc0179dc	662	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
EricLew	0:ad9dfc0179dc	663	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
EricLew	0:ad9dfc0179dc	664	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
EricLew	0:ad9dfc0179dc	665	mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
EricLew	0:ad9dfc0179dc	666	mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
EricLew	0:ad9dfc0179dc	667	mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
EricLew	0:ad9dfc0179dc	668	break;
EricLew	0:ad9dfc0179dc	669
EricLew	0:ad9dfc0179dc	670	case IO_MODE_IT_LOW_LEVEL_PU: /* Low level interrupt mode */
EricLew	0:ad9dfc0179dc	671	mfxstm32l152_IO_EnableIT(DeviceAddr);
EricLew	0:ad9dfc0179dc	672	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
EricLew	0:ad9dfc0179dc	673	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
EricLew	0:ad9dfc0179dc	674	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
EricLew	0:ad9dfc0179dc	675	mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
EricLew	0:ad9dfc0179dc	676	mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
EricLew	0:ad9dfc0179dc	677	mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
EricLew	0:ad9dfc0179dc	678	break;
EricLew	0:ad9dfc0179dc	679
EricLew	0:ad9dfc0179dc	680	case IO_MODE_IT_LOW_LEVEL_PD: /* Low level interrupt mode */
EricLew	0:ad9dfc0179dc	681	mfxstm32l152_IO_EnableIT(DeviceAddr);
EricLew	0:ad9dfc0179dc	682	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
EricLew	0:ad9dfc0179dc	683	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
EricLew	0:ad9dfc0179dc	684	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
EricLew	0:ad9dfc0179dc	685	mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
EricLew	0:ad9dfc0179dc	686	mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
EricLew	0:ad9dfc0179dc	687	mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
EricLew	0:ad9dfc0179dc	688	break;
EricLew	0:ad9dfc0179dc	689
EricLew	0:ad9dfc0179dc	690	case IO_MODE_IT_HIGH_LEVEL: /* High level interrupt mode */
EricLew	0:ad9dfc0179dc	691	mfxstm32l152_IO_EnableIT(DeviceAddr);
EricLew	0:ad9dfc0179dc	692	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
EricLew	0:ad9dfc0179dc	693	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
EricLew	0:ad9dfc0179dc	694	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
EricLew	0:ad9dfc0179dc	695	mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
EricLew	0:ad9dfc0179dc	696	mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
EricLew	0:ad9dfc0179dc	697	mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
EricLew	0:ad9dfc0179dc	698	break;
EricLew	0:ad9dfc0179dc	699
EricLew	0:ad9dfc0179dc	700	case IO_MODE_IT_HIGH_LEVEL_PU: /* High level interrupt mode */
EricLew	0:ad9dfc0179dc	701	mfxstm32l152_IO_EnableIT(DeviceAddr);
EricLew	0:ad9dfc0179dc	702	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
EricLew	0:ad9dfc0179dc	703	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
EricLew	0:ad9dfc0179dc	704	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
EricLew	0:ad9dfc0179dc	705	mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
EricLew	0:ad9dfc0179dc	706	mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
EricLew	0:ad9dfc0179dc	707	mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
EricLew	0:ad9dfc0179dc	708	break;
EricLew	0:ad9dfc0179dc	709
EricLew	0:ad9dfc0179dc	710	case IO_MODE_IT_HIGH_LEVEL_PD: /* High level interrupt mode */
EricLew	0:ad9dfc0179dc	711	mfxstm32l152_IO_EnableIT(DeviceAddr);
EricLew	0:ad9dfc0179dc	712	mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
EricLew	0:ad9dfc0179dc	713	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
EricLew	0:ad9dfc0179dc	714	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
EricLew	0:ad9dfc0179dc	715	mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
EricLew	0:ad9dfc0179dc	716	mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
EricLew	0:ad9dfc0179dc	717	mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
EricLew	0:ad9dfc0179dc	718	break;
EricLew	0:ad9dfc0179dc	719
EricLew	0:ad9dfc0179dc	720	default:
EricLew	0:ad9dfc0179dc	721	error_code = (uint8_t) IO_Mode;
EricLew	0:ad9dfc0179dc	722	break;
EricLew	0:ad9dfc0179dc	723	}
EricLew	0:ad9dfc0179dc	724
EricLew	0:ad9dfc0179dc	725	return error_code;
EricLew	0:ad9dfc0179dc	726	}
EricLew	0:ad9dfc0179dc	727
EricLew	0:ad9dfc0179dc	728	/**
EricLew	0:ad9dfc0179dc	729	* @brief Initialize the selected IO pin direction.
EricLew	0:ad9dfc0179dc	730	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	731	* @param IO_Pin: The IO pin to be configured. This parameter could be any
EricLew	0:ad9dfc0179dc	732	* combination of the following values:
EricLew	0:ad9dfc0179dc	733	* @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
EricLew	0:ad9dfc0179dc	734	* @param Direction: could be MFXSTM32L152_GPIO_DIR_IN or MFXSTM32L152_GPIO_DIR_OUT.
EricLew	0:ad9dfc0179dc	735	* @retval None
EricLew	0:ad9dfc0179dc	736	*/
EricLew	0:ad9dfc0179dc	737	void mfxstm32l152_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction)
EricLew	0:ad9dfc0179dc	738	{
EricLew	0:ad9dfc0179dc	739	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_DIR1, IO_Pin, Direction);
EricLew	0:ad9dfc0179dc	740	}
EricLew	0:ad9dfc0179dc	741
EricLew	0:ad9dfc0179dc	742	/**
EricLew	0:ad9dfc0179dc	743	* @brief Set the global interrupt Type.
EricLew	0:ad9dfc0179dc	744	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	745	* @param IO_Pin: The IO pin to be configured. This parameter could be any
EricLew	0:ad9dfc0179dc	746	* combination of the following values:
EricLew	0:ad9dfc0179dc	747	* @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
EricLew	0:ad9dfc0179dc	748	* @param Evt: Interrupt line activity type, could be one of the following values:
EricLew	0:ad9dfc0179dc	749	* @arg MFXSTM32L152_IRQ_GPI_EVT_LEVEL: Interrupt line is active in level model
EricLew	0:ad9dfc0179dc	750	* @arg MFXSTM32L152_IRQ_GPI_EVT_EDGE: Interrupt line is active in edge model
EricLew	0:ad9dfc0179dc	751	* @retval None
EricLew	0:ad9dfc0179dc	752	*/
EricLew	0:ad9dfc0179dc	753	void mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Evt)
EricLew	0:ad9dfc0179dc	754	{
EricLew	0:ad9dfc0179dc	755	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1, IO_Pin, Evt);
EricLew	0:ad9dfc0179dc	756	MFX_IO_Delay(1);
EricLew	0:ad9dfc0179dc	757	}
EricLew	0:ad9dfc0179dc	758
EricLew	0:ad9dfc0179dc	759	/**
EricLew	0:ad9dfc0179dc	760	* @brief Configure the Edge for which a transition is detectable for the
EricLew	0:ad9dfc0179dc	761	* selected pin.
EricLew	0:ad9dfc0179dc	762	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	763	* @param IO_Pin: The IO pin to be configured. This parameter could be any
EricLew	0:ad9dfc0179dc	764	* combination of the following values:
EricLew	0:ad9dfc0179dc	765	* @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
EricLew	0:ad9dfc0179dc	766	* @param Evt: Interrupt line activity type, could be one of the following values:
EricLew	0:ad9dfc0179dc	767	* @arg MFXSTM32L152_IRQ_GPI_TYPE_LLFE: Interrupt line is active in Low Level or Falling Edge
EricLew	0:ad9dfc0179dc	768	* @arg MFXSTM32L152_IRQ_GPI_TYPE_HLRE: Interrupt line is active in High Level or Rising Edge
EricLew	0:ad9dfc0179dc	769	* @retval None
EricLew	0:ad9dfc0179dc	770	*/
EricLew	0:ad9dfc0179dc	771	void mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Type)
EricLew	0:ad9dfc0179dc	772	{
EricLew	0:ad9dfc0179dc	773	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1, IO_Pin, Type);
EricLew	0:ad9dfc0179dc	774	MFX_IO_Delay(1);
EricLew	0:ad9dfc0179dc	775	}
EricLew	0:ad9dfc0179dc	776
EricLew	0:ad9dfc0179dc	777	/**
EricLew	0:ad9dfc0179dc	778	* @brief When GPIO is in output mode, puts the corresponding GPO in High (1) or Low (0) level.
EricLew	0:ad9dfc0179dc	779	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	780	* @param IO_Pin: The output pin to be set or reset. This parameter can be one
EricLew	0:ad9dfc0179dc	781	* of the following values:
EricLew	0:ad9dfc0179dc	782	* @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
EricLew	0:ad9dfc0179dc	783	* @param PinState: The new IO pin state.
EricLew	0:ad9dfc0179dc	784	* @retval None
EricLew	0:ad9dfc0179dc	785	*/
EricLew	0:ad9dfc0179dc	786	void mfxstm32l152_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState)
EricLew	0:ad9dfc0179dc	787	{
EricLew	0:ad9dfc0179dc	788	/* Apply the bit value to the selected pin */
EricLew	0:ad9dfc0179dc	789	if (PinState != 0)
EricLew	0:ad9dfc0179dc	790	{
EricLew	0:ad9dfc0179dc	791	/* Set the SET register */
EricLew	0:ad9dfc0179dc	792	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_SET1, IO_Pin, 1);
EricLew	0:ad9dfc0179dc	793	}
EricLew	0:ad9dfc0179dc	794	else
EricLew	0:ad9dfc0179dc	795	{
EricLew	0:ad9dfc0179dc	796	/* Set the CLEAR register */
EricLew	0:ad9dfc0179dc	797	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_CLR1, IO_Pin, 1);
EricLew	0:ad9dfc0179dc	798	}
EricLew	0:ad9dfc0179dc	799	}
EricLew	0:ad9dfc0179dc	800
EricLew	0:ad9dfc0179dc	801	/**
EricLew	0:ad9dfc0179dc	802	* @brief Return the state of the selected IO pin(s).
EricLew	0:ad9dfc0179dc	803	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	804	* @param IO_Pin: The output pin to be set or reset. This parameter can be one
EricLew	0:ad9dfc0179dc	805	* of the following values:
EricLew	0:ad9dfc0179dc	806	* @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
EricLew	0:ad9dfc0179dc	807	* @retval IO pin(s) state.
EricLew	0:ad9dfc0179dc	808	*/
EricLew	0:ad9dfc0179dc	809	uint32_t mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin)
EricLew	0:ad9dfc0179dc	810	{
EricLew	0:ad9dfc0179dc	811	uint8_t tmp1;
EricLew	0:ad9dfc0179dc	812	uint16_t tmp2;
EricLew	0:ad9dfc0179dc	813	uint32_t tmp3;
EricLew	0:ad9dfc0179dc	814
EricLew	0:ad9dfc0179dc	815	tmp1 = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE1);
EricLew	0:ad9dfc0179dc	816	tmp2 = (uint16_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE2);
EricLew	0:ad9dfc0179dc	817	tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE3);
EricLew	0:ad9dfc0179dc	818	tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16);
EricLew	0:ad9dfc0179dc	819
EricLew	0:ad9dfc0179dc	820	return(tmp3 & IO_Pin);
EricLew	0:ad9dfc0179dc	821	}
EricLew	0:ad9dfc0179dc	822
EricLew	0:ad9dfc0179dc	823	/**
EricLew	0:ad9dfc0179dc	824	* @brief Enable the global IO interrupt source.
EricLew	0:ad9dfc0179dc	825	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	826	* @retval None
EricLew	0:ad9dfc0179dc	827	*/
EricLew	0:ad9dfc0179dc	828	void mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	829	{
EricLew	0:ad9dfc0179dc	830	MFX_IO_ITConfig();
EricLew	0:ad9dfc0179dc	831
EricLew	0:ad9dfc0179dc	832	/* Enable global IO IT source */
EricLew	0:ad9dfc0179dc	833	mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO);
EricLew	0:ad9dfc0179dc	834	}
EricLew	0:ad9dfc0179dc	835
EricLew	0:ad9dfc0179dc	836	/**
EricLew	0:ad9dfc0179dc	837	* @brief Disable the global IO interrupt source.
EricLew	0:ad9dfc0179dc	838	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	839	* @retval None
EricLew	0:ad9dfc0179dc	840	*/
EricLew	0:ad9dfc0179dc	841	void mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	842	{
EricLew	0:ad9dfc0179dc	843	/* Disable global IO IT source */
EricLew	0:ad9dfc0179dc	844	mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO);
EricLew	0:ad9dfc0179dc	845	}
EricLew	0:ad9dfc0179dc	846
EricLew	0:ad9dfc0179dc	847	/**
EricLew	0:ad9dfc0179dc	848	* @brief Enable interrupt mode for the selected IO pin(s).
EricLew	0:ad9dfc0179dc	849	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	850	* @param IO_Pin: The IO interrupt to be enabled. This parameter could be any
EricLew	0:ad9dfc0179dc	851	* combination of the following values:
EricLew	0:ad9dfc0179dc	852	* @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
EricLew	0:ad9dfc0179dc	853	* @retval None
EricLew	0:ad9dfc0179dc	854	*/
EricLew	0:ad9dfc0179dc	855	void mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin)
EricLew	0:ad9dfc0179dc	856	{
EricLew	0:ad9dfc0179dc	857	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 1);
EricLew	0:ad9dfc0179dc	858	}
EricLew	0:ad9dfc0179dc	859
EricLew	0:ad9dfc0179dc	860	/**
EricLew	0:ad9dfc0179dc	861	* @brief Disable interrupt mode for the selected IO pin(s).
EricLew	0:ad9dfc0179dc	862	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	863	* @param IO_Pin: The IO interrupt to be disabled. This parameter could be any
EricLew	0:ad9dfc0179dc	864	* combination of the following values:
EricLew	0:ad9dfc0179dc	865	* @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
EricLew	0:ad9dfc0179dc	866	* @retval None
EricLew	0:ad9dfc0179dc	867	*/
EricLew	0:ad9dfc0179dc	868	void mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin)
EricLew	0:ad9dfc0179dc	869	{
EricLew	0:ad9dfc0179dc	870	mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 0);
EricLew	0:ad9dfc0179dc	871	}
EricLew	0:ad9dfc0179dc	872
EricLew	0:ad9dfc0179dc	873
EricLew	0:ad9dfc0179dc	874	/**
EricLew	0:ad9dfc0179dc	875	* @brief Check the status of the selected IO interrupt pending bit
EricLew	0:ad9dfc0179dc	876	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	877	* @param IO_Pin: The IO interrupt to be checked could be:
EricLew	0:ad9dfc0179dc	878	* @arg MFXSTM32L152_GPIO_PIN_x Where x can be from 0 to 23.
EricLew	0:ad9dfc0179dc	879	* @retval Status of the checked IO pin(s).
EricLew	0:ad9dfc0179dc	880	*/
EricLew	0:ad9dfc0179dc	881	uint32_t mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin)
EricLew	0:ad9dfc0179dc	882	{
EricLew	0:ad9dfc0179dc	883	/* Get the Interrupt status */
EricLew	0:ad9dfc0179dc	884	uint8_t tmp1;
EricLew	0:ad9dfc0179dc	885	uint16_t tmp2;
EricLew	0:ad9dfc0179dc	886	uint32_t tmp3;
EricLew	0:ad9dfc0179dc	887
EricLew	0:ad9dfc0179dc	888	tmp1 = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1);
EricLew	0:ad9dfc0179dc	889	tmp2 = (uint16_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2);
EricLew	0:ad9dfc0179dc	890	tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3);
EricLew	0:ad9dfc0179dc	891	tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16);
EricLew	0:ad9dfc0179dc	892
EricLew	0:ad9dfc0179dc	893	return(tmp3 & IO_Pin);
EricLew	0:ad9dfc0179dc	894	}
EricLew	0:ad9dfc0179dc	895
EricLew	0:ad9dfc0179dc	896	/**
EricLew	0:ad9dfc0179dc	897	* @brief Clear the selected IO interrupt pending bit(s). It clear automatically also the general MFXSTM32L152_REG_ADR_IRQ_PENDING
EricLew	0:ad9dfc0179dc	898	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	899	* @param IO_Pin: the IO interrupt to be cleared, could be:
EricLew	0:ad9dfc0179dc	900	* @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
EricLew	0:ad9dfc0179dc	901	* @retval None
EricLew	0:ad9dfc0179dc	902	*/
EricLew	0:ad9dfc0179dc	903	void mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin)
EricLew	0:ad9dfc0179dc	904	{
EricLew	0:ad9dfc0179dc	905	/* Clear the IO IT pending bit(s) by acknowledging */
EricLew	0:ad9dfc0179dc	906	/* it cleans automatically also the Global IRQ_GPIO */
EricLew	0:ad9dfc0179dc	907	/* normally this function is called under interrupt */
EricLew	0:ad9dfc0179dc	908	uint8_t pin_0_7, pin_8_15, pin_16_23;
EricLew	0:ad9dfc0179dc	909
EricLew	0:ad9dfc0179dc	910	pin_0_7 = IO_Pin & 0x0000ff;
EricLew	0:ad9dfc0179dc	911	pin_8_15 = IO_Pin >> 8;
EricLew	0:ad9dfc0179dc	912	pin_8_15 = pin_8_15 & 0x00ff;
EricLew	0:ad9dfc0179dc	913	pin_16_23 = IO_Pin >> 16;
EricLew	0:ad9dfc0179dc	914
EricLew	0:ad9dfc0179dc	915	if (pin_0_7)
EricLew	0:ad9dfc0179dc	916	{
EricLew	0:ad9dfc0179dc	917	MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1, pin_0_7);
EricLew	0:ad9dfc0179dc	918	}
EricLew	0:ad9dfc0179dc	919	if (pin_8_15)
EricLew	0:ad9dfc0179dc	920	{
EricLew	0:ad9dfc0179dc	921	MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2, pin_8_15);
EricLew	0:ad9dfc0179dc	922	}
EricLew	0:ad9dfc0179dc	923	if (pin_16_23)
EricLew	0:ad9dfc0179dc	924	{
EricLew	0:ad9dfc0179dc	925	MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3, pin_16_23);
EricLew	0:ad9dfc0179dc	926	}
EricLew	0:ad9dfc0179dc	927	}
EricLew	0:ad9dfc0179dc	928
EricLew	0:ad9dfc0179dc	929
EricLew	0:ad9dfc0179dc	930	/**
EricLew	0:ad9dfc0179dc	931	* @brief Enable the AF for aGPIO.
EricLew	0:ad9dfc0179dc	932	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	933	* @retval None
EricLew	0:ad9dfc0179dc	934	*/
EricLew	0:ad9dfc0179dc	935	void mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	936	{
EricLew	0:ad9dfc0179dc	937	uint8_t mode;
EricLew	0:ad9dfc0179dc	938
EricLew	0:ad9dfc0179dc	939	/* Get the current register value */
EricLew	0:ad9dfc0179dc	940	mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
EricLew	0:ad9dfc0179dc	941
EricLew	0:ad9dfc0179dc	942	/* Enable ALTERNATE functions */
EricLew	0:ad9dfc0179dc	943	/* AGPIO[0..3] can be either IDD or GPIO */
EricLew	0:ad9dfc0179dc	944	/* AGPIO[4..7] can be either TS or GPIO */
EricLew	0:ad9dfc0179dc	945	/* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
EricLew	0:ad9dfc0179dc	946	/* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
EricLew	0:ad9dfc0179dc	947	/* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */
EricLew	0:ad9dfc0179dc	948	/* if however IDD or TS are not connected then set it on gives more GPIOs availability */
EricLew	0:ad9dfc0179dc	949	/* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */
EricLew	0:ad9dfc0179dc	950	mode \|= MFXSTM32L152_ALTERNATE_GPIO_EN;
EricLew	0:ad9dfc0179dc	951
EricLew	0:ad9dfc0179dc	952	/* Write the new register value */
EricLew	0:ad9dfc0179dc	953	MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
EricLew	0:ad9dfc0179dc	954	}
EricLew	0:ad9dfc0179dc	955
EricLew	0:ad9dfc0179dc	956	/**
EricLew	0:ad9dfc0179dc	957	* @brief Disable the AF for aGPIO.
EricLew	0:ad9dfc0179dc	958	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	959	* @retval None
EricLew	0:ad9dfc0179dc	960	*/
EricLew	0:ad9dfc0179dc	961	void mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	962	{
EricLew	0:ad9dfc0179dc	963	uint8_t mode;
EricLew	0:ad9dfc0179dc	964
EricLew	0:ad9dfc0179dc	965	/* Get the current register value */
EricLew	0:ad9dfc0179dc	966	mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
EricLew	0:ad9dfc0179dc	967
EricLew	0:ad9dfc0179dc	968	/* Enable ALTERNATE functions */
EricLew	0:ad9dfc0179dc	969	/* AGPIO[0..3] can be either IDD or GPIO */
EricLew	0:ad9dfc0179dc	970	/* AGPIO[4..7] can be either TS or GPIO */
EricLew	0:ad9dfc0179dc	971	/* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
EricLew	0:ad9dfc0179dc	972	/* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
EricLew	0:ad9dfc0179dc	973	/* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */
EricLew	0:ad9dfc0179dc	974	/* if however IDD or TS are not connected then set it on gives more GPIOs availability */
EricLew	0:ad9dfc0179dc	975	/* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */
EricLew	0:ad9dfc0179dc	976	mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN;
EricLew	0:ad9dfc0179dc	977
EricLew	0:ad9dfc0179dc	978	/* Write the new register value */
EricLew	0:ad9dfc0179dc	979	MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
EricLew	0:ad9dfc0179dc	980
EricLew	0:ad9dfc0179dc	981	}
EricLew	0:ad9dfc0179dc	982
EricLew	0:ad9dfc0179dc	983
EricLew	0:ad9dfc0179dc	984	/* ------------------------------------------------------------------ */
EricLew	0:ad9dfc0179dc	985	/* --------------------- TOUCH SCREEN ------------------------------- */
EricLew	0:ad9dfc0179dc	986	/* ------------------------------------------------------------------ */
EricLew	0:ad9dfc0179dc	987
EricLew	0:ad9dfc0179dc	988	/**
EricLew	0:ad9dfc0179dc	989	* @brief Configures the touch Screen Controller (Single point detection)
EricLew	0:ad9dfc0179dc	990	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	991	* @retval None.
EricLew	0:ad9dfc0179dc	992	*/
EricLew	0:ad9dfc0179dc	993	void mfxstm32l152_TS_Start(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	994	{
EricLew	0:ad9dfc0179dc	995	uint8_t mode;
EricLew	0:ad9dfc0179dc	996
EricLew	0:ad9dfc0179dc	997	/* Get the current register value */
EricLew	0:ad9dfc0179dc	998	mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
EricLew	0:ad9dfc0179dc	999
EricLew	0:ad9dfc0179dc	1000	/* Set the Functionalities to be Enabled */
EricLew	0:ad9dfc0179dc	1001	mode \|= MFXSTM32L152_TS_EN;
EricLew	0:ad9dfc0179dc	1002
EricLew	0:ad9dfc0179dc	1003	/* Set the new register value */
EricLew	0:ad9dfc0179dc	1004	MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
EricLew	0:ad9dfc0179dc	1005
EricLew	0:ad9dfc0179dc	1006	/* Wait for 2 ms */
EricLew	0:ad9dfc0179dc	1007	MFX_IO_Delay(2);
EricLew	0:ad9dfc0179dc	1008
EricLew	0:ad9dfc0179dc	1009	/* Select 2 nF filter capacitor */
EricLew	0:ad9dfc0179dc	1010	/* Configuration:
EricLew	0:ad9dfc0179dc	1011	- Touch average control : 4 samples
EricLew	0:ad9dfc0179dc	1012	- Touch delay time : 500 uS
EricLew	0:ad9dfc0179dc	1013	- Panel driver setting time: 500 uS
EricLew	0:ad9dfc0179dc	1014	*/
EricLew	0:ad9dfc0179dc	1015	MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_SETTLING, 0x32);
EricLew	0:ad9dfc0179dc	1016	MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TOUCH_DET_DELAY, 0x5);
EricLew	0:ad9dfc0179dc	1017	MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_AVE, 0x04);
EricLew	0:ad9dfc0179dc	1018
EricLew	0:ad9dfc0179dc	1019	/* Configure the Touch FIFO threshold: single point reading */
EricLew	0:ad9dfc0179dc	1020	MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, 0x01);
EricLew	0:ad9dfc0179dc	1021
EricLew	0:ad9dfc0179dc	1022	/* Clear the FIFO memory content. */
EricLew	0:ad9dfc0179dc	1023	MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO);
EricLew	0:ad9dfc0179dc	1024
EricLew	0:ad9dfc0179dc	1025	/* Touch screen control configuration :
EricLew	0:ad9dfc0179dc	1026	- No window tracking index
EricLew	0:ad9dfc0179dc	1027	*/
EricLew	0:ad9dfc0179dc	1028	MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TRACK, 0x00);
EricLew	0:ad9dfc0179dc	1029
EricLew	0:ad9dfc0179dc	1030
EricLew	0:ad9dfc0179dc	1031	/* Clear all the IT status pending bits if any */
EricLew	0:ad9dfc0179dc	1032	mfxstm32l152_IO_ClearIT(DeviceAddr, 0xFFFFFF);
EricLew	0:ad9dfc0179dc	1033
EricLew	0:ad9dfc0179dc	1034	/* Wait for 1 ms delay */
EricLew	0:ad9dfc0179dc	1035	MFX_IO_Delay(1);
EricLew	0:ad9dfc0179dc	1036	}
EricLew	0:ad9dfc0179dc	1037
EricLew	0:ad9dfc0179dc	1038	/**
EricLew	0:ad9dfc0179dc	1039	* @brief Return if there is touch detected or not.
EricLew	0:ad9dfc0179dc	1040	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1041	* @retval Touch detected state.
EricLew	0:ad9dfc0179dc	1042	*/
EricLew	0:ad9dfc0179dc	1043	uint8_t mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1044	{
EricLew	0:ad9dfc0179dc	1045	uint8_t state;
EricLew	0:ad9dfc0179dc	1046	uint8_t ret = 0;
EricLew	0:ad9dfc0179dc	1047
EricLew	0:ad9dfc0179dc	1048	state = MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_STA);
EricLew	0:ad9dfc0179dc	1049	state = ((state & (uint8_t)MFXSTM32L152_TS_CTRL_STATUS) == (uint8_t)MFXSTM32L152_TS_CTRL_STATUS);
EricLew	0:ad9dfc0179dc	1050
EricLew	0:ad9dfc0179dc	1051	if(state > 0)
EricLew	0:ad9dfc0179dc	1052	{
EricLew	0:ad9dfc0179dc	1053	if(MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_LEVEL) > 0)
EricLew	0:ad9dfc0179dc	1054	{
EricLew	0:ad9dfc0179dc	1055	ret = 1;
EricLew	0:ad9dfc0179dc	1056	}
EricLew	0:ad9dfc0179dc	1057	}
EricLew	0:ad9dfc0179dc	1058
EricLew	0:ad9dfc0179dc	1059	return ret;
EricLew	0:ad9dfc0179dc	1060	}
EricLew	0:ad9dfc0179dc	1061
EricLew	0:ad9dfc0179dc	1062	/**
EricLew	0:ad9dfc0179dc	1063	* @brief Get the touch screen X and Y positions values
EricLew	0:ad9dfc0179dc	1064	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1065	* @param X: Pointer to X position value
EricLew	0:ad9dfc0179dc	1066	* @param Y: Pointer to Y position value
EricLew	0:ad9dfc0179dc	1067	* @retval None.
EricLew	0:ad9dfc0179dc	1068	*/
EricLew	0:ad9dfc0179dc	1069	void mfxstm32l152_TS_GetXY(uint16_t DeviceAddr, uint16_t X, uint16_t Y)
EricLew	0:ad9dfc0179dc	1070	{
EricLew	0:ad9dfc0179dc	1071	uint8_t data_xy[3];
EricLew	0:ad9dfc0179dc	1072
EricLew	0:ad9dfc0179dc	1073	MFX_IO_ReadMultiple(DeviceAddr, MFXSTM32L152_TS_XY_DATA, data_xy, sizeof(data_xy)) ;
EricLew	0:ad9dfc0179dc	1074
EricLew	0:ad9dfc0179dc	1075	/* Calculate positions values */
EricLew	0:ad9dfc0179dc	1076	*X = (data_xy[1]<<4) + (data_xy[0]>>4);
EricLew	0:ad9dfc0179dc	1077	*Y = (data_xy[2]<<4) + (data_xy[0]&4);
EricLew	0:ad9dfc0179dc	1078
EricLew	0:ad9dfc0179dc	1079	/* Reset the FIFO memory content. */
EricLew	0:ad9dfc0179dc	1080	MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO);
EricLew	0:ad9dfc0179dc	1081	}
EricLew	0:ad9dfc0179dc	1082
EricLew	0:ad9dfc0179dc	1083	/**
EricLew	0:ad9dfc0179dc	1084	* @brief Configure the selected source to generate a global interrupt or not
EricLew	0:ad9dfc0179dc	1085	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1086	* @retval None
EricLew	0:ad9dfc0179dc	1087	*/
EricLew	0:ad9dfc0179dc	1088	void mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1089	{
EricLew	0:ad9dfc0179dc	1090	MFX_IO_ITConfig();
EricLew	0:ad9dfc0179dc	1091
EricLew	0:ad9dfc0179dc	1092	/* Enable global TS IT source */
EricLew	0:ad9dfc0179dc	1093	mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET);
EricLew	0:ad9dfc0179dc	1094	}
EricLew	0:ad9dfc0179dc	1095
EricLew	0:ad9dfc0179dc	1096	/**
EricLew	0:ad9dfc0179dc	1097	* @brief Configure the selected source to generate a global interrupt or not
EricLew	0:ad9dfc0179dc	1098	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1099	* @retval None
EricLew	0:ad9dfc0179dc	1100	*/
EricLew	0:ad9dfc0179dc	1101	void mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1102	{
EricLew	0:ad9dfc0179dc	1103	/* Disable global TS IT source */
EricLew	0:ad9dfc0179dc	1104	mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET);
EricLew	0:ad9dfc0179dc	1105	}
EricLew	0:ad9dfc0179dc	1106
EricLew	0:ad9dfc0179dc	1107	/**
EricLew	0:ad9dfc0179dc	1108	* @brief Configure the selected source to generate a global interrupt or not
EricLew	0:ad9dfc0179dc	1109	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1110	* @retval TS interrupts status
EricLew	0:ad9dfc0179dc	1111	*/
EricLew	0:ad9dfc0179dc	1112	uint8_t mfxstm32l152_TS_ITStatus(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1113	{
EricLew	0:ad9dfc0179dc	1114	/* Return TS interrupts status */
EricLew	0:ad9dfc0179dc	1115	return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_TS));
EricLew	0:ad9dfc0179dc	1116	}
EricLew	0:ad9dfc0179dc	1117
EricLew	0:ad9dfc0179dc	1118	/**
EricLew	0:ad9dfc0179dc	1119	* @brief Configure the selected source to generate a global interrupt or not
EricLew	0:ad9dfc0179dc	1120	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1121	* @retval None
EricLew	0:ad9dfc0179dc	1122	*/
EricLew	0:ad9dfc0179dc	1123	void mfxstm32l152_TS_ClearIT(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1124	{
EricLew	0:ad9dfc0179dc	1125	/* Clear the global TS IT source */
EricLew	0:ad9dfc0179dc	1126	mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_TS);
EricLew	0:ad9dfc0179dc	1127	}
EricLew	0:ad9dfc0179dc	1128
EricLew	0:ad9dfc0179dc	1129	/* ------------------------------------------------------------------ */
EricLew	0:ad9dfc0179dc	1130	/* --------------------- IDD MEASUREMENT ---------------------------- */
EricLew	0:ad9dfc0179dc	1131	/* ------------------------------------------------------------------ */
EricLew	0:ad9dfc0179dc	1132
EricLew	0:ad9dfc0179dc	1133	/**
EricLew	0:ad9dfc0179dc	1134	* @brief Launch IDD current measurement
EricLew	0:ad9dfc0179dc	1135	* @param DeviceAddr: Device address on communication Bus
EricLew	0:ad9dfc0179dc	1136	* @retval None.
EricLew	0:ad9dfc0179dc	1137	*/
EricLew	0:ad9dfc0179dc	1138	void mfxstm32l152_IDD_Start(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1139	{
EricLew	0:ad9dfc0179dc	1140	uint8_t mode = 0;
EricLew	0:ad9dfc0179dc	1141
EricLew	0:ad9dfc0179dc	1142	/* Get the current register value */
EricLew	0:ad9dfc0179dc	1143	mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL);
EricLew	0:ad9dfc0179dc	1144
EricLew	0:ad9dfc0179dc	1145	/* Set the Functionalities to be enabled */
EricLew	0:ad9dfc0179dc	1146	mode \|= MFXSTM32L152_IDD_CTRL_REQ;
EricLew	0:ad9dfc0179dc	1147
EricLew	0:ad9dfc0179dc	1148	/* Start measurement campaign */
EricLew	0:ad9dfc0179dc	1149	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode);
EricLew	0:ad9dfc0179dc	1150	}
EricLew	0:ad9dfc0179dc	1151
EricLew	0:ad9dfc0179dc	1152	/**
EricLew	0:ad9dfc0179dc	1153	* @brief Configures the IDD current measurement
EricLew	0:ad9dfc0179dc	1154	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1155	* @param MfxIddConfig: Parameters depending on hardware config.
EricLew	0:ad9dfc0179dc	1156	* @retval None
EricLew	0:ad9dfc0179dc	1157	*/
EricLew	0:ad9dfc0179dc	1158	void mfxstm32l152_IDD_Config(uint16_t DeviceAddr, IDD_ConfigTypeDef MfxIddConfig)
EricLew	0:ad9dfc0179dc	1159	{
EricLew	0:ad9dfc0179dc	1160	uint8_t value = 0;
EricLew	0:ad9dfc0179dc	1161	uint8_t mode = 0;
EricLew	0:ad9dfc0179dc	1162
EricLew	0:ad9dfc0179dc	1163	/* Get the current register value */
EricLew	0:ad9dfc0179dc	1164	mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
EricLew	0:ad9dfc0179dc	1165
EricLew	0:ad9dfc0179dc	1166	if((mode & MFXSTM32L152_IDD_EN) != MFXSTM32L152_IDD_EN)
EricLew	0:ad9dfc0179dc	1167	{
EricLew	0:ad9dfc0179dc	1168	/* Set the Functionalities to be enabled */
EricLew	0:ad9dfc0179dc	1169	mode \|= MFXSTM32L152_IDD_EN;
EricLew	0:ad9dfc0179dc	1170
EricLew	0:ad9dfc0179dc	1171	/* Set the new register value */
EricLew	0:ad9dfc0179dc	1172	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
EricLew	0:ad9dfc0179dc	1173	}
EricLew	0:ad9dfc0179dc	1174
EricLew	0:ad9dfc0179dc	1175	/* Control register setting: number of shunts */
EricLew	0:ad9dfc0179dc	1176	value = ((MfxIddConfig.ShuntNbUsed << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB);
EricLew	0:ad9dfc0179dc	1177	value \|= (MfxIddConfig.VrefMeasurement & MFXSTM32L152_IDD_CTRL_VREF_DIS);
EricLew	0:ad9dfc0179dc	1178	value \|= (MfxIddConfig.Calibration & MFXSTM32L152_IDD_CTRL_CAL_DIS);
EricLew	0:ad9dfc0179dc	1179	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, value);
EricLew	0:ad9dfc0179dc	1180
EricLew	0:ad9dfc0179dc	1181	/* Idd pre delay configuration: unit and value*/
EricLew	0:ad9dfc0179dc	1182	value = (MfxIddConfig.PreDelayUnit & MFXSTM32L152_IDD_PREDELAY_UNIT) \|
EricLew	0:ad9dfc0179dc	1183	(MfxIddConfig.PreDelayValue & MFXSTM32L152_IDD_PREDELAY_VALUE);
EricLew	0:ad9dfc0179dc	1184	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_PRE_DELAY, value);
EricLew	0:ad9dfc0179dc	1185
EricLew	0:ad9dfc0179dc	1186	/* Shunt 0 register value: MSB then LSB */
EricLew	0:ad9dfc0179dc	1187	value = (uint8_t) (MfxIddConfig.Shunt0Value >> 8);
EricLew	0:ad9dfc0179dc	1188	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB, value);
EricLew	0:ad9dfc0179dc	1189	value = (uint8_t) (MfxIddConfig.Shunt0Value);
EricLew	0:ad9dfc0179dc	1190	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB, value);
EricLew	0:ad9dfc0179dc	1191
EricLew	0:ad9dfc0179dc	1192	/* Shunt 1 register value: MSB then LSB */
EricLew	0:ad9dfc0179dc	1193	value = (uint8_t) (MfxIddConfig.Shunt1Value >> 8);
EricLew	0:ad9dfc0179dc	1194	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB, value);
EricLew	0:ad9dfc0179dc	1195	value = (uint8_t) (MfxIddConfig.Shunt1Value);
EricLew	0:ad9dfc0179dc	1196	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB, value);
EricLew	0:ad9dfc0179dc	1197
EricLew	0:ad9dfc0179dc	1198	/* Shunt 2 register value: MSB then LSB */
EricLew	0:ad9dfc0179dc	1199	value = (uint8_t) (MfxIddConfig.Shunt2Value >> 8);
EricLew	0:ad9dfc0179dc	1200	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB, value);
EricLew	0:ad9dfc0179dc	1201	value = (uint8_t) (MfxIddConfig.Shunt2Value);
EricLew	0:ad9dfc0179dc	1202	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB, value);
EricLew	0:ad9dfc0179dc	1203
EricLew	0:ad9dfc0179dc	1204	/* Shunt 3 register value: MSB then LSB */
EricLew	0:ad9dfc0179dc	1205	value = (uint8_t) (MfxIddConfig.Shunt3Value >> 8);
EricLew	0:ad9dfc0179dc	1206	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB, value);
EricLew	0:ad9dfc0179dc	1207	value = (uint8_t) (MfxIddConfig.Shunt3Value);
EricLew	0:ad9dfc0179dc	1208	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB, value);
EricLew	0:ad9dfc0179dc	1209
EricLew	0:ad9dfc0179dc	1210	/* Shunt 4 register value: MSB then LSB */
EricLew	0:ad9dfc0179dc	1211	value = (uint8_t) (MfxIddConfig.Shunt4Value >> 8);
EricLew	0:ad9dfc0179dc	1212	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB, value);
EricLew	0:ad9dfc0179dc	1213	value = (uint8_t) (MfxIddConfig.Shunt4Value);
EricLew	0:ad9dfc0179dc	1214	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB, value);
EricLew	0:ad9dfc0179dc	1215
EricLew	0:ad9dfc0179dc	1216	/* Shunt 0 stabilization delay */
EricLew	0:ad9dfc0179dc	1217	value = MfxIddConfig.Shunt0StabDelay;
EricLew	0:ad9dfc0179dc	1218	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION, value);
EricLew	0:ad9dfc0179dc	1219
EricLew	0:ad9dfc0179dc	1220	/* Shunt 1 stabilization delay */
EricLew	0:ad9dfc0179dc	1221	value = MfxIddConfig.Shunt1StabDelay;
EricLew	0:ad9dfc0179dc	1222	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION, value);
EricLew	0:ad9dfc0179dc	1223
EricLew	0:ad9dfc0179dc	1224	/* Shunt 2 stabilization delay */
EricLew	0:ad9dfc0179dc	1225	value = MfxIddConfig.Shunt2StabDelay;
EricLew	0:ad9dfc0179dc	1226	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION, value);
EricLew	0:ad9dfc0179dc	1227
EricLew	0:ad9dfc0179dc	1228	/* Shunt 3 stabilization delay */
EricLew	0:ad9dfc0179dc	1229	value = MfxIddConfig.Shunt3StabDelay;
EricLew	0:ad9dfc0179dc	1230	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION, value);
EricLew	0:ad9dfc0179dc	1231
EricLew	0:ad9dfc0179dc	1232	/* Shunt 4 stabilization delay */
EricLew	0:ad9dfc0179dc	1233	value = MfxIddConfig.Shunt4StabDelay;
EricLew	0:ad9dfc0179dc	1234	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION, value);
EricLew	0:ad9dfc0179dc	1235
EricLew	0:ad9dfc0179dc	1236	/* Idd ampli gain value: MSB then LSB */
EricLew	0:ad9dfc0179dc	1237	value = (uint8_t) (MfxIddConfig.AmpliGain >> 8);
EricLew	0:ad9dfc0179dc	1238	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_MSB, value);
EricLew	0:ad9dfc0179dc	1239	value = (uint8_t) (MfxIddConfig.AmpliGain);
EricLew	0:ad9dfc0179dc	1240	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_LSB, value);
EricLew	0:ad9dfc0179dc	1241
EricLew	0:ad9dfc0179dc	1242	/* Idd VDD min value: MSB then LSB */
EricLew	0:ad9dfc0179dc	1243	value = (uint8_t) (MfxIddConfig.VddMin >> 8);
EricLew	0:ad9dfc0179dc	1244	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB, value);
EricLew	0:ad9dfc0179dc	1245	value = (uint8_t) (MfxIddConfig.VddMin);
EricLew	0:ad9dfc0179dc	1246	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB, value);
EricLew	0:ad9dfc0179dc	1247
EricLew	0:ad9dfc0179dc	1248	/* Idd number of measurements */
EricLew	0:ad9dfc0179dc	1249	value = MfxIddConfig.MeasureNb;
EricLew	0:ad9dfc0179dc	1250	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS, value);
EricLew	0:ad9dfc0179dc	1251
EricLew	0:ad9dfc0179dc	1252	/* Idd delta delay configuration: unit and value */
EricLew	0:ad9dfc0179dc	1253	value = (MfxIddConfig.DeltaDelayUnit & MFXSTM32L152_IDD_DELTADELAY_UNIT) \|
EricLew	0:ad9dfc0179dc	1254	(MfxIddConfig.DeltaDelayValue & MFXSTM32L152_IDD_DELTADELAY_VALUE);
EricLew	0:ad9dfc0179dc	1255	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY, value);
EricLew	0:ad9dfc0179dc	1256
EricLew	0:ad9dfc0179dc	1257	/* Idd number of shut on board */
EricLew	0:ad9dfc0179dc	1258	value = MfxIddConfig.ShuntNbOnBoard;
EricLew	0:ad9dfc0179dc	1259	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD, value);
EricLew	0:ad9dfc0179dc	1260	}
EricLew	0:ad9dfc0179dc	1261
EricLew	0:ad9dfc0179dc	1262	/**
EricLew	0:ad9dfc0179dc	1263	* @brief This function allows to modify number of shunt used for a measurement
EricLew	0:ad9dfc0179dc	1264	* @param DeviceAddr: Device address on communication Bus
EricLew	0:ad9dfc0179dc	1265	* @retval None.
EricLew	0:ad9dfc0179dc	1266	*/
EricLew	0:ad9dfc0179dc	1267	void mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr, uint8_t ShuntNbLimit)
EricLew	0:ad9dfc0179dc	1268	{
EricLew	0:ad9dfc0179dc	1269	uint8_t mode = 0;
EricLew	0:ad9dfc0179dc	1270
EricLew	0:ad9dfc0179dc	1271	/* Get the current register value */
EricLew	0:ad9dfc0179dc	1272	mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL);
EricLew	0:ad9dfc0179dc	1273
EricLew	0:ad9dfc0179dc	1274	/* Clear number of shunt limit */
EricLew	0:ad9dfc0179dc	1275	mode &= ~(MFXSTM32L152_IDD_CTRL_SHUNT_NB);
EricLew	0:ad9dfc0179dc	1276
EricLew	0:ad9dfc0179dc	1277	/* Clear number of shunt limit */
EricLew	0:ad9dfc0179dc	1278	mode \|= ((ShuntNbLimit << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB);
EricLew	0:ad9dfc0179dc	1279
EricLew	0:ad9dfc0179dc	1280	/* Write noewx desired limit */
EricLew	0:ad9dfc0179dc	1281	MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode);
EricLew	0:ad9dfc0179dc	1282	}
EricLew	0:ad9dfc0179dc	1283
EricLew	0:ad9dfc0179dc	1284	/**
EricLew	0:ad9dfc0179dc	1285	* @brief Get Idd current value
EricLew	0:ad9dfc0179dc	1286	* @param DeviceAddr: Device address on communication Bus
EricLew	0:ad9dfc0179dc	1287	* @param ReadValue: Pointer on value to be read
EricLew	0:ad9dfc0179dc	1288	* @retval Idd value in 10 nA.
EricLew	0:ad9dfc0179dc	1289	*/
EricLew	0:ad9dfc0179dc	1290	void mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr, uint32_t *ReadValue)
EricLew	0:ad9dfc0179dc	1291	{
EricLew	0:ad9dfc0179dc	1292	uint8_t data[3];
EricLew	0:ad9dfc0179dc	1293
EricLew	0:ad9dfc0179dc	1294	MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VALUE_MSB, data, sizeof(data)) ;
EricLew	0:ad9dfc0179dc	1295
EricLew	0:ad9dfc0179dc	1296	/* Recompose Idd current value */
EricLew	0:ad9dfc0179dc	1297	*ReadValue = (data[0] << 16) \| (data[1] << 8) \| data[2];
EricLew	0:ad9dfc0179dc	1298
EricLew	0:ad9dfc0179dc	1299	}
EricLew	0:ad9dfc0179dc	1300
EricLew	0:ad9dfc0179dc	1301	/**
EricLew	0:ad9dfc0179dc	1302	* @brief Get Last shunt used for measurement
EricLew	0:ad9dfc0179dc	1303	* @param DeviceAddr: Device address on communication Bus
EricLew	0:ad9dfc0179dc	1304	* @retval Last shunt used
EricLew	0:ad9dfc0179dc	1305	*/
EricLew	0:ad9dfc0179dc	1306	uint8_t mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1307	{
EricLew	0:ad9dfc0179dc	1308	return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT_USED));
EricLew	0:ad9dfc0179dc	1309	}
EricLew	0:ad9dfc0179dc	1310
EricLew	0:ad9dfc0179dc	1311	/**
EricLew	0:ad9dfc0179dc	1312	* @brief Configure mfx to enable Idd interrupt
EricLew	0:ad9dfc0179dc	1313	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1314	* @retval None
EricLew	0:ad9dfc0179dc	1315	*/
EricLew	0:ad9dfc0179dc	1316	void mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1317	{
EricLew	0:ad9dfc0179dc	1318	MFX_IO_ITConfig();
EricLew	0:ad9dfc0179dc	1319
EricLew	0:ad9dfc0179dc	1320	/* Enable global IDD interrupt source */
EricLew	0:ad9dfc0179dc	1321	mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD);
EricLew	0:ad9dfc0179dc	1322	}
EricLew	0:ad9dfc0179dc	1323
EricLew	0:ad9dfc0179dc	1324	/**
EricLew	0:ad9dfc0179dc	1325	* @brief Clear Idd global interrupt
EricLew	0:ad9dfc0179dc	1326	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1327	* @retval None
EricLew	0:ad9dfc0179dc	1328	*/
EricLew	0:ad9dfc0179dc	1329	void mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1330	{
EricLew	0:ad9dfc0179dc	1331	/* Clear the global IDD interrupt source */
EricLew	0:ad9dfc0179dc	1332	mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_IDD);
EricLew	0:ad9dfc0179dc	1333	}
EricLew	0:ad9dfc0179dc	1334
EricLew	0:ad9dfc0179dc	1335	/**
EricLew	0:ad9dfc0179dc	1336	* @brief get Idd interrupt status
EricLew	0:ad9dfc0179dc	1337	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1338	* @retval IDD interrupts status
EricLew	0:ad9dfc0179dc	1339	*/
EricLew	0:ad9dfc0179dc	1340	uint8_t mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1341	{
EricLew	0:ad9dfc0179dc	1342	/* Return IDD interrupt status */
EricLew	0:ad9dfc0179dc	1343	return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_IDD));
EricLew	0:ad9dfc0179dc	1344	}
EricLew	0:ad9dfc0179dc	1345
EricLew	0:ad9dfc0179dc	1346	/**
EricLew	0:ad9dfc0179dc	1347	* @brief disable Idd interrupt
EricLew	0:ad9dfc0179dc	1348	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1349	* @retval None.
EricLew	0:ad9dfc0179dc	1350	*/
EricLew	0:ad9dfc0179dc	1351	void mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1352	{
EricLew	0:ad9dfc0179dc	1353	/* Disable global IDD interrupt source */
EricLew	0:ad9dfc0179dc	1354	mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD);
EricLew	0:ad9dfc0179dc	1355	}
EricLew	0:ad9dfc0179dc	1356
EricLew	0:ad9dfc0179dc	1357
EricLew	0:ad9dfc0179dc	1358	/* ------------------------------------------------------------------ */
EricLew	0:ad9dfc0179dc	1359	/* --------------------- ERROR MANAGEMENT --------------------------- */
EricLew	0:ad9dfc0179dc	1360	/* ------------------------------------------------------------------ */
EricLew	0:ad9dfc0179dc	1361
EricLew	0:ad9dfc0179dc	1362	/**
EricLew	0:ad9dfc0179dc	1363	* @brief Read Error Source.
EricLew	0:ad9dfc0179dc	1364	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1365	* @retval Error message code with error source
EricLew	0:ad9dfc0179dc	1366	*/
EricLew	0:ad9dfc0179dc	1367	uint8_t mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1368	{
EricLew	0:ad9dfc0179dc	1369	/* Get the current source register value */
EricLew	0:ad9dfc0179dc	1370	return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_SRC));
EricLew	0:ad9dfc0179dc	1371	}
EricLew	0:ad9dfc0179dc	1372
EricLew	0:ad9dfc0179dc	1373	/**
EricLew	0:ad9dfc0179dc	1374	* @brief Read Error Message
EricLew	0:ad9dfc0179dc	1375	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1376	* @retval Error message code with error source
EricLew	0:ad9dfc0179dc	1377	*/
EricLew	0:ad9dfc0179dc	1378	uint8_t mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1379	{
EricLew	0:ad9dfc0179dc	1380	/* Get the current message register value */
EricLew	0:ad9dfc0179dc	1381	return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_MSG));
EricLew	0:ad9dfc0179dc	1382	}
EricLew	0:ad9dfc0179dc	1383
EricLew	0:ad9dfc0179dc	1384	/**
EricLew	0:ad9dfc0179dc	1385	* @brief Enable Error global interrupt
EricLew	0:ad9dfc0179dc	1386	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1387	* @retval None
EricLew	0:ad9dfc0179dc	1388	*/
EricLew	0:ad9dfc0179dc	1389
EricLew	0:ad9dfc0179dc	1390	void mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1391	{
EricLew	0:ad9dfc0179dc	1392	MFX_IO_ITConfig();
EricLew	0:ad9dfc0179dc	1393
EricLew	0:ad9dfc0179dc	1394	/* Enable global Error interrupt source */
EricLew	0:ad9dfc0179dc	1395	mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
EricLew	0:ad9dfc0179dc	1396	}
EricLew	0:ad9dfc0179dc	1397
EricLew	0:ad9dfc0179dc	1398	/**
EricLew	0:ad9dfc0179dc	1399	* @brief Clear Error global interrupt
EricLew	0:ad9dfc0179dc	1400	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1401	* @retval None
EricLew	0:ad9dfc0179dc	1402	*/
EricLew	0:ad9dfc0179dc	1403	void mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1404	{
EricLew	0:ad9dfc0179dc	1405	/* Clear the global Error interrupt source */
EricLew	0:ad9dfc0179dc	1406	mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
EricLew	0:ad9dfc0179dc	1407	}
EricLew	0:ad9dfc0179dc	1408
EricLew	0:ad9dfc0179dc	1409	/**
EricLew	0:ad9dfc0179dc	1410	* @brief get Error interrupt status
EricLew	0:ad9dfc0179dc	1411	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1412	* @retval Error interrupts status
EricLew	0:ad9dfc0179dc	1413	*/
EricLew	0:ad9dfc0179dc	1414	uint8_t mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1415	{
EricLew	0:ad9dfc0179dc	1416	/* Return Error interrupt status */
EricLew	0:ad9dfc0179dc	1417	return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_ERROR));
EricLew	0:ad9dfc0179dc	1418	}
EricLew	0:ad9dfc0179dc	1419
EricLew	0:ad9dfc0179dc	1420	/**
EricLew	0:ad9dfc0179dc	1421	* @brief disable Error interrupt
EricLew	0:ad9dfc0179dc	1422	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1423	* @retval None.
EricLew	0:ad9dfc0179dc	1424	*/
EricLew	0:ad9dfc0179dc	1425	void mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1426	{
EricLew	0:ad9dfc0179dc	1427	/* Disable global Error interrupt source */
EricLew	0:ad9dfc0179dc	1428	mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
EricLew	0:ad9dfc0179dc	1429	}
EricLew	0:ad9dfc0179dc	1430
EricLew	0:ad9dfc0179dc	1431	/**
EricLew	0:ad9dfc0179dc	1432	* @brief FOR DEBUG ONLY
EricLew	0:ad9dfc0179dc	1433	*/
EricLew	0:ad9dfc0179dc	1434	uint8_t mfxstm32l152_ReadReg(uint16_t DeviceAddr, uint8_t RegAddr)
EricLew	0:ad9dfc0179dc	1435	{
EricLew	0:ad9dfc0179dc	1436	/* Get the current register value */
EricLew	0:ad9dfc0179dc	1437	return(MFX_IO_Read((uint8_t) DeviceAddr, RegAddr));
EricLew	0:ad9dfc0179dc	1438	}
EricLew	0:ad9dfc0179dc	1439
EricLew	0:ad9dfc0179dc	1440	void mfxstm32l152_WriteReg(uint16_t DeviceAddr, uint8_t RegAddr, uint8_t Value)
EricLew	0:ad9dfc0179dc	1441	{
EricLew	0:ad9dfc0179dc	1442	/* set the current register value */
EricLew	0:ad9dfc0179dc	1443	MFX_IO_Write((uint8_t) DeviceAddr, RegAddr, Value);
EricLew	0:ad9dfc0179dc	1444	}
EricLew	0:ad9dfc0179dc	1445
EricLew	0:ad9dfc0179dc	1446	/* ------------------------------------------------------------------ */
EricLew	0:ad9dfc0179dc	1447	/* ----------------------- Private functions ------------------------ */
EricLew	0:ad9dfc0179dc	1448	/* ------------------------------------------------------------------ */
EricLew	0:ad9dfc0179dc	1449	/**
EricLew	0:ad9dfc0179dc	1450	* @brief Check if the device instance of the selected address is already registered
EricLew	0:ad9dfc0179dc	1451	* and return its index
EricLew	0:ad9dfc0179dc	1452	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1453	* @retval Index of the device instance if registered, 0xFF if not.
EricLew	0:ad9dfc0179dc	1454	*/
EricLew	0:ad9dfc0179dc	1455	static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1456	{
EricLew	0:ad9dfc0179dc	1457	uint8_t idx = 0;
EricLew	0:ad9dfc0179dc	1458
EricLew	0:ad9dfc0179dc	1459	/* Check all the registered instances */
EricLew	0:ad9dfc0179dc	1460	for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++)
EricLew	0:ad9dfc0179dc	1461	{
EricLew	0:ad9dfc0179dc	1462	if(mfxstm32l152[idx] == DeviceAddr)
EricLew	0:ad9dfc0179dc	1463	{
EricLew	0:ad9dfc0179dc	1464	return idx;
EricLew	0:ad9dfc0179dc	1465	}
EricLew	0:ad9dfc0179dc	1466	}
EricLew	0:ad9dfc0179dc	1467
EricLew	0:ad9dfc0179dc	1468	return 0xFF;
EricLew	0:ad9dfc0179dc	1469	}
EricLew	0:ad9dfc0179dc	1470
EricLew	0:ad9dfc0179dc	1471	/**
EricLew	0:ad9dfc0179dc	1472	* @brief Release registered device instance
EricLew	0:ad9dfc0179dc	1473	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1474	* @retval Index of released device instance, 0xFF if not.
EricLew	0:ad9dfc0179dc	1475	*/
EricLew	0:ad9dfc0179dc	1476	static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr)
EricLew	0:ad9dfc0179dc	1477	{
EricLew	0:ad9dfc0179dc	1478	uint8_t idx = 0;
EricLew	0:ad9dfc0179dc	1479
EricLew	0:ad9dfc0179dc	1480	/* Check for all the registered instances */
EricLew	0:ad9dfc0179dc	1481	for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++)
EricLew	0:ad9dfc0179dc	1482	{
EricLew	0:ad9dfc0179dc	1483	if(mfxstm32l152[idx] == DeviceAddr)
EricLew	0:ad9dfc0179dc	1484	{
EricLew	0:ad9dfc0179dc	1485	mfxstm32l152[idx] = 0;
EricLew	0:ad9dfc0179dc	1486	return idx;
EricLew	0:ad9dfc0179dc	1487	}
EricLew	0:ad9dfc0179dc	1488	}
EricLew	0:ad9dfc0179dc	1489	return 0xFF;
EricLew	0:ad9dfc0179dc	1490	}
EricLew	0:ad9dfc0179dc	1491
EricLew	0:ad9dfc0179dc	1492	/**
EricLew	0:ad9dfc0179dc	1493	* @brief Internal routine
EricLew	0:ad9dfc0179dc	1494	* @param DeviceAddr: Device address on communication Bus.
EricLew	0:ad9dfc0179dc	1495	* @param RegisterAddr: Register Address
EricLew	0:ad9dfc0179dc	1496	* @param PinPosition: Pin [0:23]
EricLew	0:ad9dfc0179dc	1497	* @param PinValue: 0/1
EricLew	0:ad9dfc0179dc	1498	* @retval None
EricLew	0:ad9dfc0179dc	1499	*/
EricLew	0:ad9dfc0179dc	1500	void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue )
EricLew	0:ad9dfc0179dc	1501	{
EricLew	0:ad9dfc0179dc	1502	uint8_t tmp = 0;
EricLew	0:ad9dfc0179dc	1503	uint8_t pin_0_7, pin_8_15, pin_16_23;
EricLew	0:ad9dfc0179dc	1504
EricLew	0:ad9dfc0179dc	1505	pin_0_7 = PinPosition & 0x0000ff;
EricLew	0:ad9dfc0179dc	1506	pin_8_15 = PinPosition >> 8;
EricLew	0:ad9dfc0179dc	1507	pin_8_15 = pin_8_15 & 0x00ff;
EricLew	0:ad9dfc0179dc	1508	pin_16_23 = PinPosition >> 16;
EricLew	0:ad9dfc0179dc	1509
EricLew	0:ad9dfc0179dc	1510	if (pin_0_7)
EricLew	0:ad9dfc0179dc	1511	{
EricLew	0:ad9dfc0179dc	1512	/* Get the current register value */
EricLew	0:ad9dfc0179dc	1513	tmp = MFX_IO_Read(DeviceAddr, RegisterAddr);
EricLew	0:ad9dfc0179dc	1514
EricLew	0:ad9dfc0179dc	1515	/* Set the selected pin direction */
EricLew	0:ad9dfc0179dc	1516	if (PinValue != 0)
EricLew	0:ad9dfc0179dc	1517	{
EricLew	0:ad9dfc0179dc	1518	tmp \|= (uint8_t)pin_0_7;
EricLew	0:ad9dfc0179dc	1519	}
EricLew	0:ad9dfc0179dc	1520	else
EricLew	0:ad9dfc0179dc	1521	{
EricLew	0:ad9dfc0179dc	1522	tmp &= ~(uint8_t)pin_0_7;
EricLew	0:ad9dfc0179dc	1523	}
EricLew	0:ad9dfc0179dc	1524
EricLew	0:ad9dfc0179dc	1525	/* Set the new register value */
EricLew	0:ad9dfc0179dc	1526	MFX_IO_Write(DeviceAddr, RegisterAddr, tmp);
EricLew	0:ad9dfc0179dc	1527	}
EricLew	0:ad9dfc0179dc	1528
EricLew	0:ad9dfc0179dc	1529	if (pin_8_15)
EricLew	0:ad9dfc0179dc	1530	{
EricLew	0:ad9dfc0179dc	1531	/* Get the current register value */
EricLew	0:ad9dfc0179dc	1532	tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+1);
EricLew	0:ad9dfc0179dc	1533
EricLew	0:ad9dfc0179dc	1534	/* Set the selected pin direction */
EricLew	0:ad9dfc0179dc	1535	if (PinValue != 0)
EricLew	0:ad9dfc0179dc	1536	{
EricLew	0:ad9dfc0179dc	1537	tmp \|= (uint8_t)pin_8_15;
EricLew	0:ad9dfc0179dc	1538	}
EricLew	0:ad9dfc0179dc	1539	else
EricLew	0:ad9dfc0179dc	1540	{
EricLew	0:ad9dfc0179dc	1541	tmp &= ~(uint8_t)pin_8_15;
EricLew	0:ad9dfc0179dc	1542	}
EricLew	0:ad9dfc0179dc	1543
EricLew	0:ad9dfc0179dc	1544	/* Set the new register value */
EricLew	0:ad9dfc0179dc	1545	MFX_IO_Write(DeviceAddr, RegisterAddr+1, tmp);
EricLew	0:ad9dfc0179dc	1546	}
EricLew	0:ad9dfc0179dc	1547
EricLew	0:ad9dfc0179dc	1548	if (pin_16_23)
EricLew	0:ad9dfc0179dc	1549	{
EricLew	0:ad9dfc0179dc	1550	/* Get the current register value */
EricLew	0:ad9dfc0179dc	1551	tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+2);
EricLew	0:ad9dfc0179dc	1552
EricLew	0:ad9dfc0179dc	1553	/* Set the selected pin direction */
EricLew	0:ad9dfc0179dc	1554	if (PinValue != 0)
EricLew	0:ad9dfc0179dc	1555	{
EricLew	0:ad9dfc0179dc	1556	tmp \|= (uint8_t)pin_16_23;
EricLew	0:ad9dfc0179dc	1557	}
EricLew	0:ad9dfc0179dc	1558	else
EricLew	0:ad9dfc0179dc	1559	{
EricLew	0:ad9dfc0179dc	1560	tmp &= ~(uint8_t)pin_16_23;
EricLew	0:ad9dfc0179dc	1561	}
EricLew	0:ad9dfc0179dc	1562
EricLew	0:ad9dfc0179dc	1563	/* Set the new register value */
EricLew	0:ad9dfc0179dc	1564	MFX_IO_Write(DeviceAddr, RegisterAddr+2, tmp);
EricLew	0:ad9dfc0179dc	1565	}
EricLew	0:ad9dfc0179dc	1566	}
EricLew	0:ad9dfc0179dc	1567
EricLew	0:ad9dfc0179dc	1568
EricLew	0:ad9dfc0179dc	1569	/**
EricLew	0:ad9dfc0179dc	1570	* @}
EricLew	0:ad9dfc0179dc	1571	*/
EricLew	0:ad9dfc0179dc	1572
EricLew	0:ad9dfc0179dc	1573	/**
EricLew	0:ad9dfc0179dc	1574	* @}
EricLew	0:ad9dfc0179dc	1575	*/
EricLew	0:ad9dfc0179dc	1576
EricLew	0:ad9dfc0179dc	1577	/**
EricLew	0:ad9dfc0179dc	1578	* @}
EricLew	0:ad9dfc0179dc	1579	*/
EricLew	0:ad9dfc0179dc	1580
EricLew	0:ad9dfc0179dc	1581	/**
EricLew	0:ad9dfc0179dc	1582	* @}
EricLew	0:ad9dfc0179dc	1583	*/
EricLew	0:ad9dfc0179dc	1584	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
EricLew	0:ad9dfc0179dc	1585

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Type:	Library
Created:	02 Nov 2015
Imports:	35
Forks:	0
Commits:	5
Dependents:	1
Dependencies:	3
Followers:	7

Components/mfxstm32l152/mfxstm32l152.c@4:a1219ef3537f, 2015-11-22 (annotated)

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