Senior Design: Sound Monitor / AudioDemo

Audio Demo with DISCO Board, takes control samples, waits for user input, samples regularly.

Dependencies:   CMSIS_DSP_401 STM32L4xx_HAL_Driver mbed-src_DISO_AUDIO_DEMO

core_cmSimd.h@0:3eee9435dd17, 2015-12-13 (annotated)

Committer:
EricLew
Date:
Sun Dec 13 19:12:11 2015 +0000
Revision:
0:3eee9435dd17
Audio Demo using DISCO Board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:3eee9435dd17 1 /**************************************************************************//**
EricLew 0:3eee9435dd17 2 * @file core_cmSimd.h
EricLew 0:3eee9435dd17 3 * @brief CMSIS Cortex-M SIMD Header File
EricLew 0:3eee9435dd17 4 * @version V4.10
EricLew 0:3eee9435dd17 5 * @date 18. March 2015
EricLew 0:3eee9435dd17 6 *
EricLew 0:3eee9435dd17 7 * @note
EricLew 0:3eee9435dd17 8 *
EricLew 0:3eee9435dd17 9 ******************************************************************************/
EricLew 0:3eee9435dd17 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
EricLew 0:3eee9435dd17 11
EricLew 0:3eee9435dd17 12 All rights reserved.
EricLew 0:3eee9435dd17 13 Redistribution and use in source and binary forms, with or without
EricLew 0:3eee9435dd17 14 modification, are permitted provided that the following conditions are met:
EricLew 0:3eee9435dd17 15 - Redistributions of source code must retain the above copyright
EricLew 0:3eee9435dd17 16 notice, this list of conditions and the following disclaimer.
EricLew 0:3eee9435dd17 17 - Redistributions in binary form must reproduce the above copyright
EricLew 0:3eee9435dd17 18 notice, this list of conditions and the following disclaimer in the
EricLew 0:3eee9435dd17 19 documentation and/or other materials provided with the distribution.
EricLew 0:3eee9435dd17 20 - Neither the name of ARM nor the names of its contributors may be used
EricLew 0:3eee9435dd17 21 to endorse or promote products derived from this software without
EricLew 0:3eee9435dd17 22 specific prior written permission.
EricLew 0:3eee9435dd17 23 *
EricLew 0:3eee9435dd17 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:3eee9435dd17 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:3eee9435dd17 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
EricLew 0:3eee9435dd17 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
EricLew 0:3eee9435dd17 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
EricLew 0:3eee9435dd17 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
EricLew 0:3eee9435dd17 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
EricLew 0:3eee9435dd17 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
EricLew 0:3eee9435dd17 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
EricLew 0:3eee9435dd17 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
EricLew 0:3eee9435dd17 34 POSSIBILITY OF SUCH DAMAGE.
EricLew 0:3eee9435dd17 35 ---------------------------------------------------------------------------*/
EricLew 0:3eee9435dd17 36
EricLew 0:3eee9435dd17 37
EricLew 0:3eee9435dd17 38 #if defined ( __ICCARM__ )
EricLew 0:3eee9435dd17 39 #pragma system_include /* treat file as system include file for MISRA check */
EricLew 0:3eee9435dd17 40 #endif
EricLew 0:3eee9435dd17 41
EricLew 0:3eee9435dd17 42 #ifndef __CORE_CMSIMD_H
EricLew 0:3eee9435dd17 43 #define __CORE_CMSIMD_H
EricLew 0:3eee9435dd17 44
EricLew 0:3eee9435dd17 45 #ifdef __cplusplus
EricLew 0:3eee9435dd17 46 extern "C" {
EricLew 0:3eee9435dd17 47 #endif
EricLew 0:3eee9435dd17 48
EricLew 0:3eee9435dd17 49
EricLew 0:3eee9435dd17 50 /*******************************************************************************
EricLew 0:3eee9435dd17 51 * Hardware Abstraction Layer
EricLew 0:3eee9435dd17 52 ******************************************************************************/
EricLew 0:3eee9435dd17 53
EricLew 0:3eee9435dd17 54
EricLew 0:3eee9435dd17 55 /* ################### Compiler specific Intrinsics ########################### */
EricLew 0:3eee9435dd17 56 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
EricLew 0:3eee9435dd17 57 Access to dedicated SIMD instructions
EricLew 0:3eee9435dd17 58 @{
EricLew 0:3eee9435dd17 59 */
EricLew 0:3eee9435dd17 60
EricLew 0:3eee9435dd17 61 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
EricLew 0:3eee9435dd17 62 /* ARM armcc specific functions */
EricLew 0:3eee9435dd17 63 #define __SADD8 __sadd8
EricLew 0:3eee9435dd17 64 #define __QADD8 __qadd8
EricLew 0:3eee9435dd17 65 #define __SHADD8 __shadd8
EricLew 0:3eee9435dd17 66 #define __UADD8 __uadd8
EricLew 0:3eee9435dd17 67 #define __UQADD8 __uqadd8
EricLew 0:3eee9435dd17 68 #define __UHADD8 __uhadd8
EricLew 0:3eee9435dd17 69 #define __SSUB8 __ssub8
EricLew 0:3eee9435dd17 70 #define __QSUB8 __qsub8
EricLew 0:3eee9435dd17 71 #define __SHSUB8 __shsub8
EricLew 0:3eee9435dd17 72 #define __USUB8 __usub8
EricLew 0:3eee9435dd17 73 #define __UQSUB8 __uqsub8
EricLew 0:3eee9435dd17 74 #define __UHSUB8 __uhsub8
EricLew 0:3eee9435dd17 75 #define __SADD16 __sadd16
EricLew 0:3eee9435dd17 76 #define __QADD16 __qadd16
EricLew 0:3eee9435dd17 77 #define __SHADD16 __shadd16
EricLew 0:3eee9435dd17 78 #define __UADD16 __uadd16
EricLew 0:3eee9435dd17 79 #define __UQADD16 __uqadd16
EricLew 0:3eee9435dd17 80 #define __UHADD16 __uhadd16
EricLew 0:3eee9435dd17 81 #define __SSUB16 __ssub16
EricLew 0:3eee9435dd17 82 #define __QSUB16 __qsub16
EricLew 0:3eee9435dd17 83 #define __SHSUB16 __shsub16
EricLew 0:3eee9435dd17 84 #define __USUB16 __usub16
EricLew 0:3eee9435dd17 85 #define __UQSUB16 __uqsub16
EricLew 0:3eee9435dd17 86 #define __UHSUB16 __uhsub16
EricLew 0:3eee9435dd17 87 #define __SASX __sasx
EricLew 0:3eee9435dd17 88 #define __QASX __qasx
EricLew 0:3eee9435dd17 89 #define __SHASX __shasx
EricLew 0:3eee9435dd17 90 #define __UASX __uasx
EricLew 0:3eee9435dd17 91 #define __UQASX __uqasx
EricLew 0:3eee9435dd17 92 #define __UHASX __uhasx
EricLew 0:3eee9435dd17 93 #define __SSAX __ssax
EricLew 0:3eee9435dd17 94 #define __QSAX __qsax
EricLew 0:3eee9435dd17 95 #define __SHSAX __shsax
EricLew 0:3eee9435dd17 96 #define __USAX __usax
EricLew 0:3eee9435dd17 97 #define __UQSAX __uqsax
EricLew 0:3eee9435dd17 98 #define __UHSAX __uhsax
EricLew 0:3eee9435dd17 99 #define __USAD8 __usad8
EricLew 0:3eee9435dd17 100 #define __USADA8 __usada8
EricLew 0:3eee9435dd17 101 #define __SSAT16 __ssat16
EricLew 0:3eee9435dd17 102 #define __USAT16 __usat16
EricLew 0:3eee9435dd17 103 #define __UXTB16 __uxtb16
EricLew 0:3eee9435dd17 104 #define __UXTAB16 __uxtab16
EricLew 0:3eee9435dd17 105 #define __SXTB16 __sxtb16
EricLew 0:3eee9435dd17 106 #define __SXTAB16 __sxtab16
EricLew 0:3eee9435dd17 107 #define __SMUAD __smuad
EricLew 0:3eee9435dd17 108 #define __SMUADX __smuadx
EricLew 0:3eee9435dd17 109 #define __SMLAD __smlad
EricLew 0:3eee9435dd17 110 #define __SMLADX __smladx
EricLew 0:3eee9435dd17 111 #define __SMLALD __smlald
EricLew 0:3eee9435dd17 112 #define __SMLALDX __smlaldx
EricLew 0:3eee9435dd17 113 #define __SMUSD __smusd
EricLew 0:3eee9435dd17 114 #define __SMUSDX __smusdx
EricLew 0:3eee9435dd17 115 #define __SMLSD __smlsd
EricLew 0:3eee9435dd17 116 #define __SMLSDX __smlsdx
EricLew 0:3eee9435dd17 117 #define __SMLSLD __smlsld
EricLew 0:3eee9435dd17 118 #define __SMLSLDX __smlsldx
EricLew 0:3eee9435dd17 119 #define __SEL __sel
EricLew 0:3eee9435dd17 120 #define __QADD __qadd
EricLew 0:3eee9435dd17 121 #define __QSUB __qsub
EricLew 0:3eee9435dd17 122
EricLew 0:3eee9435dd17 123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
EricLew 0:3eee9435dd17 124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
EricLew 0:3eee9435dd17 125
EricLew 0:3eee9435dd17 126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
EricLew 0:3eee9435dd17 127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
EricLew 0:3eee9435dd17 128
EricLew 0:3eee9435dd17 129 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
EricLew 0:3eee9435dd17 130 ((int64_t)(ARG3) << 32) ) >> 32))
EricLew 0:3eee9435dd17 131
EricLew 0:3eee9435dd17 132
EricLew 0:3eee9435dd17 133 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
EricLew 0:3eee9435dd17 134 /* GNU gcc specific functions */
EricLew 0:3eee9435dd17 135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 136 {
EricLew 0:3eee9435dd17 137 uint32_t result;
EricLew 0:3eee9435dd17 138
EricLew 0:3eee9435dd17 139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 140 return(result);
EricLew 0:3eee9435dd17 141 }
EricLew 0:3eee9435dd17 142
EricLew 0:3eee9435dd17 143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 144 {
EricLew 0:3eee9435dd17 145 uint32_t result;
EricLew 0:3eee9435dd17 146
EricLew 0:3eee9435dd17 147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 148 return(result);
EricLew 0:3eee9435dd17 149 }
EricLew 0:3eee9435dd17 150
EricLew 0:3eee9435dd17 151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 152 {
EricLew 0:3eee9435dd17 153 uint32_t result;
EricLew 0:3eee9435dd17 154
EricLew 0:3eee9435dd17 155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 156 return(result);
EricLew 0:3eee9435dd17 157 }
EricLew 0:3eee9435dd17 158
EricLew 0:3eee9435dd17 159 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 160 {
EricLew 0:3eee9435dd17 161 uint32_t result;
EricLew 0:3eee9435dd17 162
EricLew 0:3eee9435dd17 163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 164 return(result);
EricLew 0:3eee9435dd17 165 }
EricLew 0:3eee9435dd17 166
EricLew 0:3eee9435dd17 167 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 168 {
EricLew 0:3eee9435dd17 169 uint32_t result;
EricLew 0:3eee9435dd17 170
EricLew 0:3eee9435dd17 171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 172 return(result);
EricLew 0:3eee9435dd17 173 }
EricLew 0:3eee9435dd17 174
EricLew 0:3eee9435dd17 175 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 176 {
EricLew 0:3eee9435dd17 177 uint32_t result;
EricLew 0:3eee9435dd17 178
EricLew 0:3eee9435dd17 179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 180 return(result);
EricLew 0:3eee9435dd17 181 }
EricLew 0:3eee9435dd17 182
EricLew 0:3eee9435dd17 183
EricLew 0:3eee9435dd17 184 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 185 {
EricLew 0:3eee9435dd17 186 uint32_t result;
EricLew 0:3eee9435dd17 187
EricLew 0:3eee9435dd17 188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 189 return(result);
EricLew 0:3eee9435dd17 190 }
EricLew 0:3eee9435dd17 191
EricLew 0:3eee9435dd17 192 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 193 {
EricLew 0:3eee9435dd17 194 uint32_t result;
EricLew 0:3eee9435dd17 195
EricLew 0:3eee9435dd17 196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 197 return(result);
EricLew 0:3eee9435dd17 198 }
EricLew 0:3eee9435dd17 199
EricLew 0:3eee9435dd17 200 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 201 {
EricLew 0:3eee9435dd17 202 uint32_t result;
EricLew 0:3eee9435dd17 203
EricLew 0:3eee9435dd17 204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 205 return(result);
EricLew 0:3eee9435dd17 206 }
EricLew 0:3eee9435dd17 207
EricLew 0:3eee9435dd17 208 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 209 {
EricLew 0:3eee9435dd17 210 uint32_t result;
EricLew 0:3eee9435dd17 211
EricLew 0:3eee9435dd17 212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 213 return(result);
EricLew 0:3eee9435dd17 214 }
EricLew 0:3eee9435dd17 215
EricLew 0:3eee9435dd17 216 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 217 {
EricLew 0:3eee9435dd17 218 uint32_t result;
EricLew 0:3eee9435dd17 219
EricLew 0:3eee9435dd17 220 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 221 return(result);
EricLew 0:3eee9435dd17 222 }
EricLew 0:3eee9435dd17 223
EricLew 0:3eee9435dd17 224 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 225 {
EricLew 0:3eee9435dd17 226 uint32_t result;
EricLew 0:3eee9435dd17 227
EricLew 0:3eee9435dd17 228 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 229 return(result);
EricLew 0:3eee9435dd17 230 }
EricLew 0:3eee9435dd17 231
EricLew 0:3eee9435dd17 232
EricLew 0:3eee9435dd17 233 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 234 {
EricLew 0:3eee9435dd17 235 uint32_t result;
EricLew 0:3eee9435dd17 236
EricLew 0:3eee9435dd17 237 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 238 return(result);
EricLew 0:3eee9435dd17 239 }
EricLew 0:3eee9435dd17 240
EricLew 0:3eee9435dd17 241 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 242 {
EricLew 0:3eee9435dd17 243 uint32_t result;
EricLew 0:3eee9435dd17 244
EricLew 0:3eee9435dd17 245 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 246 return(result);
EricLew 0:3eee9435dd17 247 }
EricLew 0:3eee9435dd17 248
EricLew 0:3eee9435dd17 249 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 250 {
EricLew 0:3eee9435dd17 251 uint32_t result;
EricLew 0:3eee9435dd17 252
EricLew 0:3eee9435dd17 253 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 254 return(result);
EricLew 0:3eee9435dd17 255 }
EricLew 0:3eee9435dd17 256
EricLew 0:3eee9435dd17 257 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 258 {
EricLew 0:3eee9435dd17 259 uint32_t result;
EricLew 0:3eee9435dd17 260
EricLew 0:3eee9435dd17 261 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 262 return(result);
EricLew 0:3eee9435dd17 263 }
EricLew 0:3eee9435dd17 264
EricLew 0:3eee9435dd17 265 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 266 {
EricLew 0:3eee9435dd17 267 uint32_t result;
EricLew 0:3eee9435dd17 268
EricLew 0:3eee9435dd17 269 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 270 return(result);
EricLew 0:3eee9435dd17 271 }
EricLew 0:3eee9435dd17 272
EricLew 0:3eee9435dd17 273 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 274 {
EricLew 0:3eee9435dd17 275 uint32_t result;
EricLew 0:3eee9435dd17 276
EricLew 0:3eee9435dd17 277 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 278 return(result);
EricLew 0:3eee9435dd17 279 }
EricLew 0:3eee9435dd17 280
EricLew 0:3eee9435dd17 281 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 282 {
EricLew 0:3eee9435dd17 283 uint32_t result;
EricLew 0:3eee9435dd17 284
EricLew 0:3eee9435dd17 285 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 286 return(result);
EricLew 0:3eee9435dd17 287 }
EricLew 0:3eee9435dd17 288
EricLew 0:3eee9435dd17 289 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 290 {
EricLew 0:3eee9435dd17 291 uint32_t result;
EricLew 0:3eee9435dd17 292
EricLew 0:3eee9435dd17 293 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 294 return(result);
EricLew 0:3eee9435dd17 295 }
EricLew 0:3eee9435dd17 296
EricLew 0:3eee9435dd17 297 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 298 {
EricLew 0:3eee9435dd17 299 uint32_t result;
EricLew 0:3eee9435dd17 300
EricLew 0:3eee9435dd17 301 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 302 return(result);
EricLew 0:3eee9435dd17 303 }
EricLew 0:3eee9435dd17 304
EricLew 0:3eee9435dd17 305 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 306 {
EricLew 0:3eee9435dd17 307 uint32_t result;
EricLew 0:3eee9435dd17 308
EricLew 0:3eee9435dd17 309 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 310 return(result);
EricLew 0:3eee9435dd17 311 }
EricLew 0:3eee9435dd17 312
EricLew 0:3eee9435dd17 313 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 314 {
EricLew 0:3eee9435dd17 315 uint32_t result;
EricLew 0:3eee9435dd17 316
EricLew 0:3eee9435dd17 317 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 318 return(result);
EricLew 0:3eee9435dd17 319 }
EricLew 0:3eee9435dd17 320
EricLew 0:3eee9435dd17 321 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 322 {
EricLew 0:3eee9435dd17 323 uint32_t result;
EricLew 0:3eee9435dd17 324
EricLew 0:3eee9435dd17 325 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 326 return(result);
EricLew 0:3eee9435dd17 327 }
EricLew 0:3eee9435dd17 328
EricLew 0:3eee9435dd17 329 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 330 {
EricLew 0:3eee9435dd17 331 uint32_t result;
EricLew 0:3eee9435dd17 332
EricLew 0:3eee9435dd17 333 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 334 return(result);
EricLew 0:3eee9435dd17 335 }
EricLew 0:3eee9435dd17 336
EricLew 0:3eee9435dd17 337 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 338 {
EricLew 0:3eee9435dd17 339 uint32_t result;
EricLew 0:3eee9435dd17 340
EricLew 0:3eee9435dd17 341 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 342 return(result);
EricLew 0:3eee9435dd17 343 }
EricLew 0:3eee9435dd17 344
EricLew 0:3eee9435dd17 345 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 346 {
EricLew 0:3eee9435dd17 347 uint32_t result;
EricLew 0:3eee9435dd17 348
EricLew 0:3eee9435dd17 349 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 350 return(result);
EricLew 0:3eee9435dd17 351 }
EricLew 0:3eee9435dd17 352
EricLew 0:3eee9435dd17 353 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 354 {
EricLew 0:3eee9435dd17 355 uint32_t result;
EricLew 0:3eee9435dd17 356
EricLew 0:3eee9435dd17 357 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 358 return(result);
EricLew 0:3eee9435dd17 359 }
EricLew 0:3eee9435dd17 360
EricLew 0:3eee9435dd17 361 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 362 {
EricLew 0:3eee9435dd17 363 uint32_t result;
EricLew 0:3eee9435dd17 364
EricLew 0:3eee9435dd17 365 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 366 return(result);
EricLew 0:3eee9435dd17 367 }
EricLew 0:3eee9435dd17 368
EricLew 0:3eee9435dd17 369 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 370 {
EricLew 0:3eee9435dd17 371 uint32_t result;
EricLew 0:3eee9435dd17 372
EricLew 0:3eee9435dd17 373 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 374 return(result);
EricLew 0:3eee9435dd17 375 }
EricLew 0:3eee9435dd17 376
EricLew 0:3eee9435dd17 377 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 378 {
EricLew 0:3eee9435dd17 379 uint32_t result;
EricLew 0:3eee9435dd17 380
EricLew 0:3eee9435dd17 381 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 382 return(result);
EricLew 0:3eee9435dd17 383 }
EricLew 0:3eee9435dd17 384
EricLew 0:3eee9435dd17 385 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 386 {
EricLew 0:3eee9435dd17 387 uint32_t result;
EricLew 0:3eee9435dd17 388
EricLew 0:3eee9435dd17 389 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 390 return(result);
EricLew 0:3eee9435dd17 391 }
EricLew 0:3eee9435dd17 392
EricLew 0:3eee9435dd17 393 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 394 {
EricLew 0:3eee9435dd17 395 uint32_t result;
EricLew 0:3eee9435dd17 396
EricLew 0:3eee9435dd17 397 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 398 return(result);
EricLew 0:3eee9435dd17 399 }
EricLew 0:3eee9435dd17 400
EricLew 0:3eee9435dd17 401 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 402 {
EricLew 0:3eee9435dd17 403 uint32_t result;
EricLew 0:3eee9435dd17 404
EricLew 0:3eee9435dd17 405 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 406 return(result);
EricLew 0:3eee9435dd17 407 }
EricLew 0:3eee9435dd17 408
EricLew 0:3eee9435dd17 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 410 {
EricLew 0:3eee9435dd17 411 uint32_t result;
EricLew 0:3eee9435dd17 412
EricLew 0:3eee9435dd17 413 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 414 return(result);
EricLew 0:3eee9435dd17 415 }
EricLew 0:3eee9435dd17 416
EricLew 0:3eee9435dd17 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 418 {
EricLew 0:3eee9435dd17 419 uint32_t result;
EricLew 0:3eee9435dd17 420
EricLew 0:3eee9435dd17 421 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 422 return(result);
EricLew 0:3eee9435dd17 423 }
EricLew 0:3eee9435dd17 424
EricLew 0:3eee9435dd17 425 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 426 {
EricLew 0:3eee9435dd17 427 uint32_t result;
EricLew 0:3eee9435dd17 428
EricLew 0:3eee9435dd17 429 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 430 return(result);
EricLew 0:3eee9435dd17 431 }
EricLew 0:3eee9435dd17 432
EricLew 0:3eee9435dd17 433 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
EricLew 0:3eee9435dd17 434 {
EricLew 0:3eee9435dd17 435 uint32_t result;
EricLew 0:3eee9435dd17 436
EricLew 0:3eee9435dd17 437 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
EricLew 0:3eee9435dd17 438 return(result);
EricLew 0:3eee9435dd17 439 }
EricLew 0:3eee9435dd17 440
EricLew 0:3eee9435dd17 441 #define __SSAT16(ARG1,ARG2) \
EricLew 0:3eee9435dd17 442 ({ \
EricLew 0:3eee9435dd17 443 uint32_t __RES, __ARG1 = (ARG1); \
EricLew 0:3eee9435dd17 444 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
EricLew 0:3eee9435dd17 445 __RES; \
EricLew 0:3eee9435dd17 446 })
EricLew 0:3eee9435dd17 447
EricLew 0:3eee9435dd17 448 #define __USAT16(ARG1,ARG2) \
EricLew 0:3eee9435dd17 449 ({ \
EricLew 0:3eee9435dd17 450 uint32_t __RES, __ARG1 = (ARG1); \
EricLew 0:3eee9435dd17 451 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
EricLew 0:3eee9435dd17 452 __RES; \
EricLew 0:3eee9435dd17 453 })
EricLew 0:3eee9435dd17 454
EricLew 0:3eee9435dd17 455 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
EricLew 0:3eee9435dd17 456 {
EricLew 0:3eee9435dd17 457 uint32_t result;
EricLew 0:3eee9435dd17 458
EricLew 0:3eee9435dd17 459 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
EricLew 0:3eee9435dd17 460 return(result);
EricLew 0:3eee9435dd17 461 }
EricLew 0:3eee9435dd17 462
EricLew 0:3eee9435dd17 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 464 {
EricLew 0:3eee9435dd17 465 uint32_t result;
EricLew 0:3eee9435dd17 466
EricLew 0:3eee9435dd17 467 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 468 return(result);
EricLew 0:3eee9435dd17 469 }
EricLew 0:3eee9435dd17 470
EricLew 0:3eee9435dd17 471 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
EricLew 0:3eee9435dd17 472 {
EricLew 0:3eee9435dd17 473 uint32_t result;
EricLew 0:3eee9435dd17 474
EricLew 0:3eee9435dd17 475 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
EricLew 0:3eee9435dd17 476 return(result);
EricLew 0:3eee9435dd17 477 }
EricLew 0:3eee9435dd17 478
EricLew 0:3eee9435dd17 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 480 {
EricLew 0:3eee9435dd17 481 uint32_t result;
EricLew 0:3eee9435dd17 482
EricLew 0:3eee9435dd17 483 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 484 return(result);
EricLew 0:3eee9435dd17 485 }
EricLew 0:3eee9435dd17 486
EricLew 0:3eee9435dd17 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 488 {
EricLew 0:3eee9435dd17 489 uint32_t result;
EricLew 0:3eee9435dd17 490
EricLew 0:3eee9435dd17 491 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 492 return(result);
EricLew 0:3eee9435dd17 493 }
EricLew 0:3eee9435dd17 494
EricLew 0:3eee9435dd17 495 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 496 {
EricLew 0:3eee9435dd17 497 uint32_t result;
EricLew 0:3eee9435dd17 498
EricLew 0:3eee9435dd17 499 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 500 return(result);
EricLew 0:3eee9435dd17 501 }
EricLew 0:3eee9435dd17 502
EricLew 0:3eee9435dd17 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
EricLew 0:3eee9435dd17 504 {
EricLew 0:3eee9435dd17 505 uint32_t result;
EricLew 0:3eee9435dd17 506
EricLew 0:3eee9435dd17 507 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
EricLew 0:3eee9435dd17 508 return(result);
EricLew 0:3eee9435dd17 509 }
EricLew 0:3eee9435dd17 510
EricLew 0:3eee9435dd17 511 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
EricLew 0:3eee9435dd17 512 {
EricLew 0:3eee9435dd17 513 uint32_t result;
EricLew 0:3eee9435dd17 514
EricLew 0:3eee9435dd17 515 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
EricLew 0:3eee9435dd17 516 return(result);
EricLew 0:3eee9435dd17 517 }
EricLew 0:3eee9435dd17 518
EricLew 0:3eee9435dd17 519 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
EricLew 0:3eee9435dd17 520 {
EricLew 0:3eee9435dd17 521 union llreg_u{
EricLew 0:3eee9435dd17 522 uint32_t w32[2];
EricLew 0:3eee9435dd17 523 uint64_t w64;
EricLew 0:3eee9435dd17 524 } llr;
EricLew 0:3eee9435dd17 525 llr.w64 = acc;
EricLew 0:3eee9435dd17 526
EricLew 0:3eee9435dd17 527 #ifndef __ARMEB__ // Little endian
EricLew 0:3eee9435dd17 528 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
EricLew 0:3eee9435dd17 529 #else // Big endian
EricLew 0:3eee9435dd17 530 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
EricLew 0:3eee9435dd17 531 #endif
EricLew 0:3eee9435dd17 532
EricLew 0:3eee9435dd17 533 return(llr.w64);
EricLew 0:3eee9435dd17 534 }
EricLew 0:3eee9435dd17 535
EricLew 0:3eee9435dd17 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
EricLew 0:3eee9435dd17 537 {
EricLew 0:3eee9435dd17 538 union llreg_u{
EricLew 0:3eee9435dd17 539 uint32_t w32[2];
EricLew 0:3eee9435dd17 540 uint64_t w64;
EricLew 0:3eee9435dd17 541 } llr;
EricLew 0:3eee9435dd17 542 llr.w64 = acc;
EricLew 0:3eee9435dd17 543
EricLew 0:3eee9435dd17 544 #ifndef __ARMEB__ // Little endian
EricLew 0:3eee9435dd17 545 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
EricLew 0:3eee9435dd17 546 #else // Big endian
EricLew 0:3eee9435dd17 547 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
EricLew 0:3eee9435dd17 548 #endif
EricLew 0:3eee9435dd17 549
EricLew 0:3eee9435dd17 550 return(llr.w64);
EricLew 0:3eee9435dd17 551 }
EricLew 0:3eee9435dd17 552
EricLew 0:3eee9435dd17 553 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 554 {
EricLew 0:3eee9435dd17 555 uint32_t result;
EricLew 0:3eee9435dd17 556
EricLew 0:3eee9435dd17 557 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 558 return(result);
EricLew 0:3eee9435dd17 559 }
EricLew 0:3eee9435dd17 560
EricLew 0:3eee9435dd17 561 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 562 {
EricLew 0:3eee9435dd17 563 uint32_t result;
EricLew 0:3eee9435dd17 564
EricLew 0:3eee9435dd17 565 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 566 return(result);
EricLew 0:3eee9435dd17 567 }
EricLew 0:3eee9435dd17 568
EricLew 0:3eee9435dd17 569 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
EricLew 0:3eee9435dd17 570 {
EricLew 0:3eee9435dd17 571 uint32_t result;
EricLew 0:3eee9435dd17 572
EricLew 0:3eee9435dd17 573 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
EricLew 0:3eee9435dd17 574 return(result);
EricLew 0:3eee9435dd17 575 }
EricLew 0:3eee9435dd17 576
EricLew 0:3eee9435dd17 577 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
EricLew 0:3eee9435dd17 578 {
EricLew 0:3eee9435dd17 579 uint32_t result;
EricLew 0:3eee9435dd17 580
EricLew 0:3eee9435dd17 581 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
EricLew 0:3eee9435dd17 582 return(result);
EricLew 0:3eee9435dd17 583 }
EricLew 0:3eee9435dd17 584
EricLew 0:3eee9435dd17 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
EricLew 0:3eee9435dd17 586 {
EricLew 0:3eee9435dd17 587 union llreg_u{
EricLew 0:3eee9435dd17 588 uint32_t w32[2];
EricLew 0:3eee9435dd17 589 uint64_t w64;
EricLew 0:3eee9435dd17 590 } llr;
EricLew 0:3eee9435dd17 591 llr.w64 = acc;
EricLew 0:3eee9435dd17 592
EricLew 0:3eee9435dd17 593 #ifndef __ARMEB__ // Little endian
EricLew 0:3eee9435dd17 594 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
EricLew 0:3eee9435dd17 595 #else // Big endian
EricLew 0:3eee9435dd17 596 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
EricLew 0:3eee9435dd17 597 #endif
EricLew 0:3eee9435dd17 598
EricLew 0:3eee9435dd17 599 return(llr.w64);
EricLew 0:3eee9435dd17 600 }
EricLew 0:3eee9435dd17 601
EricLew 0:3eee9435dd17 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
EricLew 0:3eee9435dd17 603 {
EricLew 0:3eee9435dd17 604 union llreg_u{
EricLew 0:3eee9435dd17 605 uint32_t w32[2];
EricLew 0:3eee9435dd17 606 uint64_t w64;
EricLew 0:3eee9435dd17 607 } llr;
EricLew 0:3eee9435dd17 608 llr.w64 = acc;
EricLew 0:3eee9435dd17 609
EricLew 0:3eee9435dd17 610 #ifndef __ARMEB__ // Little endian
EricLew 0:3eee9435dd17 611 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
EricLew 0:3eee9435dd17 612 #else // Big endian
EricLew 0:3eee9435dd17 613 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
EricLew 0:3eee9435dd17 614 #endif
EricLew 0:3eee9435dd17 615
EricLew 0:3eee9435dd17 616 return(llr.w64);
EricLew 0:3eee9435dd17 617 }
EricLew 0:3eee9435dd17 618
EricLew 0:3eee9435dd17 619 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 620 {
EricLew 0:3eee9435dd17 621 uint32_t result;
EricLew 0:3eee9435dd17 622
EricLew 0:3eee9435dd17 623 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 624 return(result);
EricLew 0:3eee9435dd17 625 }
EricLew 0:3eee9435dd17 626
EricLew 0:3eee9435dd17 627 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 628 {
EricLew 0:3eee9435dd17 629 uint32_t result;
EricLew 0:3eee9435dd17 630
EricLew 0:3eee9435dd17 631 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 632 return(result);
EricLew 0:3eee9435dd17 633 }
EricLew 0:3eee9435dd17 634
EricLew 0:3eee9435dd17 635 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
EricLew 0:3eee9435dd17 636 {
EricLew 0:3eee9435dd17 637 uint32_t result;
EricLew 0:3eee9435dd17 638
EricLew 0:3eee9435dd17 639 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
EricLew 0:3eee9435dd17 640 return(result);
EricLew 0:3eee9435dd17 641 }
EricLew 0:3eee9435dd17 642
EricLew 0:3eee9435dd17 643 #define __PKHBT(ARG1,ARG2,ARG3) \
EricLew 0:3eee9435dd17 644 ({ \
EricLew 0:3eee9435dd17 645 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
EricLew 0:3eee9435dd17 646 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
EricLew 0:3eee9435dd17 647 __RES; \
EricLew 0:3eee9435dd17 648 })
EricLew 0:3eee9435dd17 649
EricLew 0:3eee9435dd17 650 #define __PKHTB(ARG1,ARG2,ARG3) \
EricLew 0:3eee9435dd17 651 ({ \
EricLew 0:3eee9435dd17 652 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
EricLew 0:3eee9435dd17 653 if (ARG3 == 0) \
EricLew 0:3eee9435dd17 654 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
EricLew 0:3eee9435dd17 655 else \
EricLew 0:3eee9435dd17 656 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
EricLew 0:3eee9435dd17 657 __RES; \
EricLew 0:3eee9435dd17 658 })
EricLew 0:3eee9435dd17 659
EricLew 0:3eee9435dd17 660 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
EricLew 0:3eee9435dd17 661 {
EricLew 0:3eee9435dd17 662 int32_t result;
EricLew 0:3eee9435dd17 663
EricLew 0:3eee9435dd17 664 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
EricLew 0:3eee9435dd17 665 return(result);
EricLew 0:3eee9435dd17 666 }
EricLew 0:3eee9435dd17 667
EricLew 0:3eee9435dd17 668
EricLew 0:3eee9435dd17 669 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
EricLew 0:3eee9435dd17 670 /* IAR iccarm specific functions */
EricLew 0:3eee9435dd17 671 #include <cmsis_iar.h>
EricLew 0:3eee9435dd17 672
EricLew 0:3eee9435dd17 673
EricLew 0:3eee9435dd17 674 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
EricLew 0:3eee9435dd17 675 /* TI CCS specific functions */
EricLew 0:3eee9435dd17 676 #include <cmsis_ccs.h>
EricLew 0:3eee9435dd17 677
EricLew 0:3eee9435dd17 678
EricLew 0:3eee9435dd17 679 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
EricLew 0:3eee9435dd17 680 /* TASKING carm specific functions */
EricLew 0:3eee9435dd17 681 /* not yet supported */
EricLew 0:3eee9435dd17 682
EricLew 0:3eee9435dd17 683
EricLew 0:3eee9435dd17 684 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
EricLew 0:3eee9435dd17 685 /* Cosmic specific functions */
EricLew 0:3eee9435dd17 686 #include <cmsis_csm.h>
EricLew 0:3eee9435dd17 687
EricLew 0:3eee9435dd17 688 #endif
EricLew 0:3eee9435dd17 689
EricLew 0:3eee9435dd17 690 /*@} end of group CMSIS_SIMD_intrinsics */
EricLew 0:3eee9435dd17 691
EricLew 0:3eee9435dd17 692
EricLew 0:3eee9435dd17 693 #ifdef __cplusplus
EricLew 0:3eee9435dd17 694 }
EricLew 0:3eee9435dd17 695 #endif
EricLew 0:3eee9435dd17 696
EricLew 0:3eee9435dd17 697 #endif /* __CORE_CMSIMD_H */
EricLew 0:3eee9435dd17 698
EricLew 0:3eee9435dd17 699