Senior Design: Sound Monitor / AudioDemo

Audio Demo with DISCO Board, takes control samples, waits for user input, samples regularly.

Dependencies:   CMSIS_DSP_401 STM32L4xx_HAL_Driver mbed-src_DISO_AUDIO_DEMO

core_cmFunc.h@0:3eee9435dd17, 2015-12-13 (annotated)

Committer:
EricLew
Date:
Sun Dec 13 19:12:11 2015 +0000
Revision:
0:3eee9435dd17
Audio Demo using DISCO Board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:3eee9435dd17 1 /**************************************************************************//**
EricLew 0:3eee9435dd17 2 * @file core_cmFunc.h
EricLew 0:3eee9435dd17 3 * @brief CMSIS Cortex-M Core Function Access Header File
EricLew 0:3eee9435dd17 4 * @version V4.10
EricLew 0:3eee9435dd17 5 * @date 18. March 2015
EricLew 0:3eee9435dd17 6 *
EricLew 0:3eee9435dd17 7 * @note
EricLew 0:3eee9435dd17 8 *
EricLew 0:3eee9435dd17 9 ******************************************************************************/
EricLew 0:3eee9435dd17 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
EricLew 0:3eee9435dd17 11
EricLew 0:3eee9435dd17 12 All rights reserved.
EricLew 0:3eee9435dd17 13 Redistribution and use in source and binary forms, with or without
EricLew 0:3eee9435dd17 14 modification, are permitted provided that the following conditions are met:
EricLew 0:3eee9435dd17 15 - Redistributions of source code must retain the above copyright
EricLew 0:3eee9435dd17 16 notice, this list of conditions and the following disclaimer.
EricLew 0:3eee9435dd17 17 - Redistributions in binary form must reproduce the above copyright
EricLew 0:3eee9435dd17 18 notice, this list of conditions and the following disclaimer in the
EricLew 0:3eee9435dd17 19 documentation and/or other materials provided with the distribution.
EricLew 0:3eee9435dd17 20 - Neither the name of ARM nor the names of its contributors may be used
EricLew 0:3eee9435dd17 21 to endorse or promote products derived from this software without
EricLew 0:3eee9435dd17 22 specific prior written permission.
EricLew 0:3eee9435dd17 23 *
EricLew 0:3eee9435dd17 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:3eee9435dd17 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:3eee9435dd17 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
EricLew 0:3eee9435dd17 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
EricLew 0:3eee9435dd17 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
EricLew 0:3eee9435dd17 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
EricLew 0:3eee9435dd17 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
EricLew 0:3eee9435dd17 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
EricLew 0:3eee9435dd17 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
EricLew 0:3eee9435dd17 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
EricLew 0:3eee9435dd17 34 POSSIBILITY OF SUCH DAMAGE.
EricLew 0:3eee9435dd17 35 ---------------------------------------------------------------------------*/
EricLew 0:3eee9435dd17 36
EricLew 0:3eee9435dd17 37
EricLew 0:3eee9435dd17 38 #ifndef __CORE_CMFUNC_H
EricLew 0:3eee9435dd17 39 #define __CORE_CMFUNC_H
EricLew 0:3eee9435dd17 40
EricLew 0:3eee9435dd17 41
EricLew 0:3eee9435dd17 42 /* ########################### Core Function Access ########################### */
EricLew 0:3eee9435dd17 43 /** \ingroup CMSIS_Core_FunctionInterface
EricLew 0:3eee9435dd17 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
EricLew 0:3eee9435dd17 45 @{
EricLew 0:3eee9435dd17 46 */
EricLew 0:3eee9435dd17 47
EricLew 0:3eee9435dd17 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
EricLew 0:3eee9435dd17 49 /* ARM armcc specific functions */
EricLew 0:3eee9435dd17 50
EricLew 0:3eee9435dd17 51 #if (__ARMCC_VERSION < 400677)
EricLew 0:3eee9435dd17 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
EricLew 0:3eee9435dd17 53 #endif
EricLew 0:3eee9435dd17 54
EricLew 0:3eee9435dd17 55 /* intrinsic void __enable_irq(); */
EricLew 0:3eee9435dd17 56 /* intrinsic void __disable_irq(); */
EricLew 0:3eee9435dd17 57
EricLew 0:3eee9435dd17 58 /** \brief Get Control Register
EricLew 0:3eee9435dd17 59
EricLew 0:3eee9435dd17 60 This function returns the content of the Control Register.
EricLew 0:3eee9435dd17 61
EricLew 0:3eee9435dd17 62 \return Control Register value
EricLew 0:3eee9435dd17 63 */
EricLew 0:3eee9435dd17 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
EricLew 0:3eee9435dd17 65 {
EricLew 0:3eee9435dd17 66 register uint32_t __regControl __ASM("control");
EricLew 0:3eee9435dd17 67 return(__regControl);
EricLew 0:3eee9435dd17 68 }
EricLew 0:3eee9435dd17 69
EricLew 0:3eee9435dd17 70
EricLew 0:3eee9435dd17 71 /** \brief Set Control Register
EricLew 0:3eee9435dd17 72
EricLew 0:3eee9435dd17 73 This function writes the given value to the Control Register.
EricLew 0:3eee9435dd17 74
EricLew 0:3eee9435dd17 75 \param [in] control Control Register value to set
EricLew 0:3eee9435dd17 76 */
EricLew 0:3eee9435dd17 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
EricLew 0:3eee9435dd17 78 {
EricLew 0:3eee9435dd17 79 register uint32_t __regControl __ASM("control");
EricLew 0:3eee9435dd17 80 __regControl = control;
EricLew 0:3eee9435dd17 81 }
EricLew 0:3eee9435dd17 82
EricLew 0:3eee9435dd17 83
EricLew 0:3eee9435dd17 84 /** \brief Get IPSR Register
EricLew 0:3eee9435dd17 85
EricLew 0:3eee9435dd17 86 This function returns the content of the IPSR Register.
EricLew 0:3eee9435dd17 87
EricLew 0:3eee9435dd17 88 \return IPSR Register value
EricLew 0:3eee9435dd17 89 */
EricLew 0:3eee9435dd17 90 __STATIC_INLINE uint32_t __get_IPSR(void)
EricLew 0:3eee9435dd17 91 {
EricLew 0:3eee9435dd17 92 register uint32_t __regIPSR __ASM("ipsr");
EricLew 0:3eee9435dd17 93 return(__regIPSR);
EricLew 0:3eee9435dd17 94 }
EricLew 0:3eee9435dd17 95
EricLew 0:3eee9435dd17 96
EricLew 0:3eee9435dd17 97 /** \brief Get APSR Register
EricLew 0:3eee9435dd17 98
EricLew 0:3eee9435dd17 99 This function returns the content of the APSR Register.
EricLew 0:3eee9435dd17 100
EricLew 0:3eee9435dd17 101 \return APSR Register value
EricLew 0:3eee9435dd17 102 */
EricLew 0:3eee9435dd17 103 __STATIC_INLINE uint32_t __get_APSR(void)
EricLew 0:3eee9435dd17 104 {
EricLew 0:3eee9435dd17 105 register uint32_t __regAPSR __ASM("apsr");
EricLew 0:3eee9435dd17 106 return(__regAPSR);
EricLew 0:3eee9435dd17 107 }
EricLew 0:3eee9435dd17 108
EricLew 0:3eee9435dd17 109
EricLew 0:3eee9435dd17 110 /** \brief Get xPSR Register
EricLew 0:3eee9435dd17 111
EricLew 0:3eee9435dd17 112 This function returns the content of the xPSR Register.
EricLew 0:3eee9435dd17 113
EricLew 0:3eee9435dd17 114 \return xPSR Register value
EricLew 0:3eee9435dd17 115 */
EricLew 0:3eee9435dd17 116 __STATIC_INLINE uint32_t __get_xPSR(void)
EricLew 0:3eee9435dd17 117 {
EricLew 0:3eee9435dd17 118 register uint32_t __regXPSR __ASM("xpsr");
EricLew 0:3eee9435dd17 119 return(__regXPSR);
EricLew 0:3eee9435dd17 120 }
EricLew 0:3eee9435dd17 121
EricLew 0:3eee9435dd17 122
EricLew 0:3eee9435dd17 123 /** \brief Get Process Stack Pointer
EricLew 0:3eee9435dd17 124
EricLew 0:3eee9435dd17 125 This function returns the current value of the Process Stack Pointer (PSP).
EricLew 0:3eee9435dd17 126
EricLew 0:3eee9435dd17 127 \return PSP Register value
EricLew 0:3eee9435dd17 128 */
EricLew 0:3eee9435dd17 129 __STATIC_INLINE uint32_t __get_PSP(void)
EricLew 0:3eee9435dd17 130 {
EricLew 0:3eee9435dd17 131 register uint32_t __regProcessStackPointer __ASM("psp");
EricLew 0:3eee9435dd17 132 return(__regProcessStackPointer);
EricLew 0:3eee9435dd17 133 }
EricLew 0:3eee9435dd17 134
EricLew 0:3eee9435dd17 135
EricLew 0:3eee9435dd17 136 /** \brief Set Process Stack Pointer
EricLew 0:3eee9435dd17 137
EricLew 0:3eee9435dd17 138 This function assigns the given value to the Process Stack Pointer (PSP).
EricLew 0:3eee9435dd17 139
EricLew 0:3eee9435dd17 140 \param [in] topOfProcStack Process Stack Pointer value to set
EricLew 0:3eee9435dd17 141 */
EricLew 0:3eee9435dd17 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
EricLew 0:3eee9435dd17 143 {
EricLew 0:3eee9435dd17 144 register uint32_t __regProcessStackPointer __ASM("psp");
EricLew 0:3eee9435dd17 145 __regProcessStackPointer = topOfProcStack;
EricLew 0:3eee9435dd17 146 }
EricLew 0:3eee9435dd17 147
EricLew 0:3eee9435dd17 148
EricLew 0:3eee9435dd17 149 /** \brief Get Main Stack Pointer
EricLew 0:3eee9435dd17 150
EricLew 0:3eee9435dd17 151 This function returns the current value of the Main Stack Pointer (MSP).
EricLew 0:3eee9435dd17 152
EricLew 0:3eee9435dd17 153 \return MSP Register value
EricLew 0:3eee9435dd17 154 */
EricLew 0:3eee9435dd17 155 __STATIC_INLINE uint32_t __get_MSP(void)
EricLew 0:3eee9435dd17 156 {
EricLew 0:3eee9435dd17 157 register uint32_t __regMainStackPointer __ASM("msp");
EricLew 0:3eee9435dd17 158 return(__regMainStackPointer);
EricLew 0:3eee9435dd17 159 }
EricLew 0:3eee9435dd17 160
EricLew 0:3eee9435dd17 161
EricLew 0:3eee9435dd17 162 /** \brief Set Main Stack Pointer
EricLew 0:3eee9435dd17 163
EricLew 0:3eee9435dd17 164 This function assigns the given value to the Main Stack Pointer (MSP).
EricLew 0:3eee9435dd17 165
EricLew 0:3eee9435dd17 166 \param [in] topOfMainStack Main Stack Pointer value to set
EricLew 0:3eee9435dd17 167 */
EricLew 0:3eee9435dd17 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
EricLew 0:3eee9435dd17 169 {
EricLew 0:3eee9435dd17 170 register uint32_t __regMainStackPointer __ASM("msp");
EricLew 0:3eee9435dd17 171 __regMainStackPointer = topOfMainStack;
EricLew 0:3eee9435dd17 172 }
EricLew 0:3eee9435dd17 173
EricLew 0:3eee9435dd17 174
EricLew 0:3eee9435dd17 175 /** \brief Get Priority Mask
EricLew 0:3eee9435dd17 176
EricLew 0:3eee9435dd17 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
EricLew 0:3eee9435dd17 178
EricLew 0:3eee9435dd17 179 \return Priority Mask value
EricLew 0:3eee9435dd17 180 */
EricLew 0:3eee9435dd17 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
EricLew 0:3eee9435dd17 182 {
EricLew 0:3eee9435dd17 183 register uint32_t __regPriMask __ASM("primask");
EricLew 0:3eee9435dd17 184 return(__regPriMask);
EricLew 0:3eee9435dd17 185 }
EricLew 0:3eee9435dd17 186
EricLew 0:3eee9435dd17 187
EricLew 0:3eee9435dd17 188 /** \brief Set Priority Mask
EricLew 0:3eee9435dd17 189
EricLew 0:3eee9435dd17 190 This function assigns the given value to the Priority Mask Register.
EricLew 0:3eee9435dd17 191
EricLew 0:3eee9435dd17 192 \param [in] priMask Priority Mask
EricLew 0:3eee9435dd17 193 */
EricLew 0:3eee9435dd17 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
EricLew 0:3eee9435dd17 195 {
EricLew 0:3eee9435dd17 196 register uint32_t __regPriMask __ASM("primask");
EricLew 0:3eee9435dd17 197 __regPriMask = (priMask);
EricLew 0:3eee9435dd17 198 }
EricLew 0:3eee9435dd17 199
EricLew 0:3eee9435dd17 200
EricLew 0:3eee9435dd17 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
EricLew 0:3eee9435dd17 202
EricLew 0:3eee9435dd17 203 /** \brief Enable FIQ
EricLew 0:3eee9435dd17 204
EricLew 0:3eee9435dd17 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
EricLew 0:3eee9435dd17 206 Can only be executed in Privileged modes.
EricLew 0:3eee9435dd17 207 */
EricLew 0:3eee9435dd17 208 #define __enable_fault_irq __enable_fiq
EricLew 0:3eee9435dd17 209
EricLew 0:3eee9435dd17 210
EricLew 0:3eee9435dd17 211 /** \brief Disable FIQ
EricLew 0:3eee9435dd17 212
EricLew 0:3eee9435dd17 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
EricLew 0:3eee9435dd17 214 Can only be executed in Privileged modes.
EricLew 0:3eee9435dd17 215 */
EricLew 0:3eee9435dd17 216 #define __disable_fault_irq __disable_fiq
EricLew 0:3eee9435dd17 217
EricLew 0:3eee9435dd17 218
EricLew 0:3eee9435dd17 219 /** \brief Get Base Priority
EricLew 0:3eee9435dd17 220
EricLew 0:3eee9435dd17 221 This function returns the current value of the Base Priority register.
EricLew 0:3eee9435dd17 222
EricLew 0:3eee9435dd17 223 \return Base Priority register value
EricLew 0:3eee9435dd17 224 */
EricLew 0:3eee9435dd17 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
EricLew 0:3eee9435dd17 226 {
EricLew 0:3eee9435dd17 227 register uint32_t __regBasePri __ASM("basepri");
EricLew 0:3eee9435dd17 228 return(__regBasePri);
EricLew 0:3eee9435dd17 229 }
EricLew 0:3eee9435dd17 230
EricLew 0:3eee9435dd17 231
EricLew 0:3eee9435dd17 232 /** \brief Set Base Priority
EricLew 0:3eee9435dd17 233
EricLew 0:3eee9435dd17 234 This function assigns the given value to the Base Priority register.
EricLew 0:3eee9435dd17 235
EricLew 0:3eee9435dd17 236 \param [in] basePri Base Priority value to set
EricLew 0:3eee9435dd17 237 */
EricLew 0:3eee9435dd17 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
EricLew 0:3eee9435dd17 239 {
EricLew 0:3eee9435dd17 240 register uint32_t __regBasePri __ASM("basepri");
EricLew 0:3eee9435dd17 241 __regBasePri = (basePri & 0xff);
EricLew 0:3eee9435dd17 242 }
EricLew 0:3eee9435dd17 243
EricLew 0:3eee9435dd17 244
EricLew 0:3eee9435dd17 245 /** \brief Set Base Priority with condition
EricLew 0:3eee9435dd17 246
EricLew 0:3eee9435dd17 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
EricLew 0:3eee9435dd17 248 or the new value increases the BASEPRI priority level.
EricLew 0:3eee9435dd17 249
EricLew 0:3eee9435dd17 250 \param [in] basePri Base Priority value to set
EricLew 0:3eee9435dd17 251 */
EricLew 0:3eee9435dd17 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
EricLew 0:3eee9435dd17 253 {
EricLew 0:3eee9435dd17 254 register uint32_t __regBasePriMax __ASM("basepri_max");
EricLew 0:3eee9435dd17 255 __regBasePriMax = (basePri & 0xff);
EricLew 0:3eee9435dd17 256 }
EricLew 0:3eee9435dd17 257
EricLew 0:3eee9435dd17 258
EricLew 0:3eee9435dd17 259 /** \brief Get Fault Mask
EricLew 0:3eee9435dd17 260
EricLew 0:3eee9435dd17 261 This function returns the current value of the Fault Mask register.
EricLew 0:3eee9435dd17 262
EricLew 0:3eee9435dd17 263 \return Fault Mask register value
EricLew 0:3eee9435dd17 264 */
EricLew 0:3eee9435dd17 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
EricLew 0:3eee9435dd17 266 {
EricLew 0:3eee9435dd17 267 register uint32_t __regFaultMask __ASM("faultmask");
EricLew 0:3eee9435dd17 268 return(__regFaultMask);
EricLew 0:3eee9435dd17 269 }
EricLew 0:3eee9435dd17 270
EricLew 0:3eee9435dd17 271
EricLew 0:3eee9435dd17 272 /** \brief Set Fault Mask
EricLew 0:3eee9435dd17 273
EricLew 0:3eee9435dd17 274 This function assigns the given value to the Fault Mask register.
EricLew 0:3eee9435dd17 275
EricLew 0:3eee9435dd17 276 \param [in] faultMask Fault Mask value to set
EricLew 0:3eee9435dd17 277 */
EricLew 0:3eee9435dd17 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
EricLew 0:3eee9435dd17 279 {
EricLew 0:3eee9435dd17 280 register uint32_t __regFaultMask __ASM("faultmask");
EricLew 0:3eee9435dd17 281 __regFaultMask = (faultMask & (uint32_t)1);
EricLew 0:3eee9435dd17 282 }
EricLew 0:3eee9435dd17 283
EricLew 0:3eee9435dd17 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
EricLew 0:3eee9435dd17 285
EricLew 0:3eee9435dd17 286
EricLew 0:3eee9435dd17 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
EricLew 0:3eee9435dd17 288
EricLew 0:3eee9435dd17 289 /** \brief Get FPSCR
EricLew 0:3eee9435dd17 290
EricLew 0:3eee9435dd17 291 This function returns the current value of the Floating Point Status/Control register.
EricLew 0:3eee9435dd17 292
EricLew 0:3eee9435dd17 293 \return Floating Point Status/Control register value
EricLew 0:3eee9435dd17 294 */
EricLew 0:3eee9435dd17 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
EricLew 0:3eee9435dd17 296 {
EricLew 0:3eee9435dd17 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
EricLew 0:3eee9435dd17 298 register uint32_t __regfpscr __ASM("fpscr");
EricLew 0:3eee9435dd17 299 return(__regfpscr);
EricLew 0:3eee9435dd17 300 #else
EricLew 0:3eee9435dd17 301 return(0);
EricLew 0:3eee9435dd17 302 #endif
EricLew 0:3eee9435dd17 303 }
EricLew 0:3eee9435dd17 304
EricLew 0:3eee9435dd17 305
EricLew 0:3eee9435dd17 306 /** \brief Set FPSCR
EricLew 0:3eee9435dd17 307
EricLew 0:3eee9435dd17 308 This function assigns the given value to the Floating Point Status/Control register.
EricLew 0:3eee9435dd17 309
EricLew 0:3eee9435dd17 310 \param [in] fpscr Floating Point Status/Control value to set
EricLew 0:3eee9435dd17 311 */
EricLew 0:3eee9435dd17 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
EricLew 0:3eee9435dd17 313 {
EricLew 0:3eee9435dd17 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
EricLew 0:3eee9435dd17 315 register uint32_t __regfpscr __ASM("fpscr");
EricLew 0:3eee9435dd17 316 __regfpscr = (fpscr);
EricLew 0:3eee9435dd17 317 #endif
EricLew 0:3eee9435dd17 318 }
EricLew 0:3eee9435dd17 319
EricLew 0:3eee9435dd17 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
EricLew 0:3eee9435dd17 321
EricLew 0:3eee9435dd17 322
EricLew 0:3eee9435dd17 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
EricLew 0:3eee9435dd17 324 /* GNU gcc specific functions */
EricLew 0:3eee9435dd17 325
EricLew 0:3eee9435dd17 326 /** \brief Enable IRQ Interrupts
EricLew 0:3eee9435dd17 327
EricLew 0:3eee9435dd17 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
EricLew 0:3eee9435dd17 329 Can only be executed in Privileged modes.
EricLew 0:3eee9435dd17 330 */
EricLew 0:3eee9435dd17 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
EricLew 0:3eee9435dd17 332 {
EricLew 0:3eee9435dd17 333 __ASM volatile ("cpsie i" : : : "memory");
EricLew 0:3eee9435dd17 334 }
EricLew 0:3eee9435dd17 335
EricLew 0:3eee9435dd17 336
EricLew 0:3eee9435dd17 337 /** \brief Disable IRQ Interrupts
EricLew 0:3eee9435dd17 338
EricLew 0:3eee9435dd17 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
EricLew 0:3eee9435dd17 340 Can only be executed in Privileged modes.
EricLew 0:3eee9435dd17 341 */
EricLew 0:3eee9435dd17 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
EricLew 0:3eee9435dd17 343 {
EricLew 0:3eee9435dd17 344 __ASM volatile ("cpsid i" : : : "memory");
EricLew 0:3eee9435dd17 345 }
EricLew 0:3eee9435dd17 346
EricLew 0:3eee9435dd17 347
EricLew 0:3eee9435dd17 348 /** \brief Get Control Register
EricLew 0:3eee9435dd17 349
EricLew 0:3eee9435dd17 350 This function returns the content of the Control Register.
EricLew 0:3eee9435dd17 351
EricLew 0:3eee9435dd17 352 \return Control Register value
EricLew 0:3eee9435dd17 353 */
EricLew 0:3eee9435dd17 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
EricLew 0:3eee9435dd17 355 {
EricLew 0:3eee9435dd17 356 uint32_t result;
EricLew 0:3eee9435dd17 357
EricLew 0:3eee9435dd17 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
EricLew 0:3eee9435dd17 359 return(result);
EricLew 0:3eee9435dd17 360 }
EricLew 0:3eee9435dd17 361
EricLew 0:3eee9435dd17 362
EricLew 0:3eee9435dd17 363 /** \brief Set Control Register
EricLew 0:3eee9435dd17 364
EricLew 0:3eee9435dd17 365 This function writes the given value to the Control Register.
EricLew 0:3eee9435dd17 366
EricLew 0:3eee9435dd17 367 \param [in] control Control Register value to set
EricLew 0:3eee9435dd17 368 */
EricLew 0:3eee9435dd17 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
EricLew 0:3eee9435dd17 370 {
EricLew 0:3eee9435dd17 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
EricLew 0:3eee9435dd17 372 }
EricLew 0:3eee9435dd17 373
EricLew 0:3eee9435dd17 374
EricLew 0:3eee9435dd17 375 /** \brief Get IPSR Register
EricLew 0:3eee9435dd17 376
EricLew 0:3eee9435dd17 377 This function returns the content of the IPSR Register.
EricLew 0:3eee9435dd17 378
EricLew 0:3eee9435dd17 379 \return IPSR Register value
EricLew 0:3eee9435dd17 380 */
EricLew 0:3eee9435dd17 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
EricLew 0:3eee9435dd17 382 {
EricLew 0:3eee9435dd17 383 uint32_t result;
EricLew 0:3eee9435dd17 384
EricLew 0:3eee9435dd17 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
EricLew 0:3eee9435dd17 386 return(result);
EricLew 0:3eee9435dd17 387 }
EricLew 0:3eee9435dd17 388
EricLew 0:3eee9435dd17 389
EricLew 0:3eee9435dd17 390 /** \brief Get APSR Register
EricLew 0:3eee9435dd17 391
EricLew 0:3eee9435dd17 392 This function returns the content of the APSR Register.
EricLew 0:3eee9435dd17 393
EricLew 0:3eee9435dd17 394 \return APSR Register value
EricLew 0:3eee9435dd17 395 */
EricLew 0:3eee9435dd17 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
EricLew 0:3eee9435dd17 397 {
EricLew 0:3eee9435dd17 398 uint32_t result;
EricLew 0:3eee9435dd17 399
EricLew 0:3eee9435dd17 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
EricLew 0:3eee9435dd17 401 return(result);
EricLew 0:3eee9435dd17 402 }
EricLew 0:3eee9435dd17 403
EricLew 0:3eee9435dd17 404
EricLew 0:3eee9435dd17 405 /** \brief Get xPSR Register
EricLew 0:3eee9435dd17 406
EricLew 0:3eee9435dd17 407 This function returns the content of the xPSR Register.
EricLew 0:3eee9435dd17 408
EricLew 0:3eee9435dd17 409 \return xPSR Register value
EricLew 0:3eee9435dd17 410 */
EricLew 0:3eee9435dd17 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
EricLew 0:3eee9435dd17 412 {
EricLew 0:3eee9435dd17 413 uint32_t result;
EricLew 0:3eee9435dd17 414
EricLew 0:3eee9435dd17 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
EricLew 0:3eee9435dd17 416 return(result);
EricLew 0:3eee9435dd17 417 }
EricLew 0:3eee9435dd17 418
EricLew 0:3eee9435dd17 419
EricLew 0:3eee9435dd17 420 /** \brief Get Process Stack Pointer
EricLew 0:3eee9435dd17 421
EricLew 0:3eee9435dd17 422 This function returns the current value of the Process Stack Pointer (PSP).
EricLew 0:3eee9435dd17 423
EricLew 0:3eee9435dd17 424 \return PSP Register value
EricLew 0:3eee9435dd17 425 */
EricLew 0:3eee9435dd17 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
EricLew 0:3eee9435dd17 427 {
EricLew 0:3eee9435dd17 428 register uint32_t result;
EricLew 0:3eee9435dd17 429
EricLew 0:3eee9435dd17 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
EricLew 0:3eee9435dd17 431 return(result);
EricLew 0:3eee9435dd17 432 }
EricLew 0:3eee9435dd17 433
EricLew 0:3eee9435dd17 434
EricLew 0:3eee9435dd17 435 /** \brief Set Process Stack Pointer
EricLew 0:3eee9435dd17 436
EricLew 0:3eee9435dd17 437 This function assigns the given value to the Process Stack Pointer (PSP).
EricLew 0:3eee9435dd17 438
EricLew 0:3eee9435dd17 439 \param [in] topOfProcStack Process Stack Pointer value to set
EricLew 0:3eee9435dd17 440 */
EricLew 0:3eee9435dd17 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
EricLew 0:3eee9435dd17 442 {
EricLew 0:3eee9435dd17 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
EricLew 0:3eee9435dd17 444 }
EricLew 0:3eee9435dd17 445
EricLew 0:3eee9435dd17 446
EricLew 0:3eee9435dd17 447 /** \brief Get Main Stack Pointer
EricLew 0:3eee9435dd17 448
EricLew 0:3eee9435dd17 449 This function returns the current value of the Main Stack Pointer (MSP).
EricLew 0:3eee9435dd17 450
EricLew 0:3eee9435dd17 451 \return MSP Register value
EricLew 0:3eee9435dd17 452 */
EricLew 0:3eee9435dd17 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
EricLew 0:3eee9435dd17 454 {
EricLew 0:3eee9435dd17 455 register uint32_t result;
EricLew 0:3eee9435dd17 456
EricLew 0:3eee9435dd17 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
EricLew 0:3eee9435dd17 458 return(result);
EricLew 0:3eee9435dd17 459 }
EricLew 0:3eee9435dd17 460
EricLew 0:3eee9435dd17 461
EricLew 0:3eee9435dd17 462 /** \brief Set Main Stack Pointer
EricLew 0:3eee9435dd17 463
EricLew 0:3eee9435dd17 464 This function assigns the given value to the Main Stack Pointer (MSP).
EricLew 0:3eee9435dd17 465
EricLew 0:3eee9435dd17 466 \param [in] topOfMainStack Main Stack Pointer value to set
EricLew 0:3eee9435dd17 467 */
EricLew 0:3eee9435dd17 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
EricLew 0:3eee9435dd17 469 {
EricLew 0:3eee9435dd17 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
EricLew 0:3eee9435dd17 471 }
EricLew 0:3eee9435dd17 472
EricLew 0:3eee9435dd17 473
EricLew 0:3eee9435dd17 474 /** \brief Get Priority Mask
EricLew 0:3eee9435dd17 475
EricLew 0:3eee9435dd17 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
EricLew 0:3eee9435dd17 477
EricLew 0:3eee9435dd17 478 \return Priority Mask value
EricLew 0:3eee9435dd17 479 */
EricLew 0:3eee9435dd17 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
EricLew 0:3eee9435dd17 481 {
EricLew 0:3eee9435dd17 482 uint32_t result;
EricLew 0:3eee9435dd17 483
EricLew 0:3eee9435dd17 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
EricLew 0:3eee9435dd17 485 return(result);
EricLew 0:3eee9435dd17 486 }
EricLew 0:3eee9435dd17 487
EricLew 0:3eee9435dd17 488
EricLew 0:3eee9435dd17 489 /** \brief Set Priority Mask
EricLew 0:3eee9435dd17 490
EricLew 0:3eee9435dd17 491 This function assigns the given value to the Priority Mask Register.
EricLew 0:3eee9435dd17 492
EricLew 0:3eee9435dd17 493 \param [in] priMask Priority Mask
EricLew 0:3eee9435dd17 494 */
EricLew 0:3eee9435dd17 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
EricLew 0:3eee9435dd17 496 {
EricLew 0:3eee9435dd17 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
EricLew 0:3eee9435dd17 498 }
EricLew 0:3eee9435dd17 499
EricLew 0:3eee9435dd17 500
EricLew 0:3eee9435dd17 501 #if (__CORTEX_M >= 0x03)
EricLew 0:3eee9435dd17 502
EricLew 0:3eee9435dd17 503 /** \brief Enable FIQ
EricLew 0:3eee9435dd17 504
EricLew 0:3eee9435dd17 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
EricLew 0:3eee9435dd17 506 Can only be executed in Privileged modes.
EricLew 0:3eee9435dd17 507 */
EricLew 0:3eee9435dd17 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
EricLew 0:3eee9435dd17 509 {
EricLew 0:3eee9435dd17 510 __ASM volatile ("cpsie f" : : : "memory");
EricLew 0:3eee9435dd17 511 }
EricLew 0:3eee9435dd17 512
EricLew 0:3eee9435dd17 513
EricLew 0:3eee9435dd17 514 /** \brief Disable FIQ
EricLew 0:3eee9435dd17 515
EricLew 0:3eee9435dd17 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
EricLew 0:3eee9435dd17 517 Can only be executed in Privileged modes.
EricLew 0:3eee9435dd17 518 */
EricLew 0:3eee9435dd17 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
EricLew 0:3eee9435dd17 520 {
EricLew 0:3eee9435dd17 521 __ASM volatile ("cpsid f" : : : "memory");
EricLew 0:3eee9435dd17 522 }
EricLew 0:3eee9435dd17 523
EricLew 0:3eee9435dd17 524
EricLew 0:3eee9435dd17 525 /** \brief Get Base Priority
EricLew 0:3eee9435dd17 526
EricLew 0:3eee9435dd17 527 This function returns the current value of the Base Priority register.
EricLew 0:3eee9435dd17 528
EricLew 0:3eee9435dd17 529 \return Base Priority register value
EricLew 0:3eee9435dd17 530 */
EricLew 0:3eee9435dd17 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
EricLew 0:3eee9435dd17 532 {
EricLew 0:3eee9435dd17 533 uint32_t result;
EricLew 0:3eee9435dd17 534
EricLew 0:3eee9435dd17 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
EricLew 0:3eee9435dd17 536 return(result);
EricLew 0:3eee9435dd17 537 }
EricLew 0:3eee9435dd17 538
EricLew 0:3eee9435dd17 539
EricLew 0:3eee9435dd17 540 /** \brief Set Base Priority
EricLew 0:3eee9435dd17 541
EricLew 0:3eee9435dd17 542 This function assigns the given value to the Base Priority register.
EricLew 0:3eee9435dd17 543
EricLew 0:3eee9435dd17 544 \param [in] basePri Base Priority value to set
EricLew 0:3eee9435dd17 545 */
EricLew 0:3eee9435dd17 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
EricLew 0:3eee9435dd17 547 {
EricLew 0:3eee9435dd17 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
EricLew 0:3eee9435dd17 549 }
EricLew 0:3eee9435dd17 550
EricLew 0:3eee9435dd17 551
EricLew 0:3eee9435dd17 552 /** \brief Set Base Priority with condition
EricLew 0:3eee9435dd17 553
EricLew 0:3eee9435dd17 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
EricLew 0:3eee9435dd17 555 or the new value increases the BASEPRI priority level.
EricLew 0:3eee9435dd17 556
EricLew 0:3eee9435dd17 557 \param [in] basePri Base Priority value to set
EricLew 0:3eee9435dd17 558 */
EricLew 0:3eee9435dd17 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
EricLew 0:3eee9435dd17 560 {
EricLew 0:3eee9435dd17 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
EricLew 0:3eee9435dd17 562 }
EricLew 0:3eee9435dd17 563
EricLew 0:3eee9435dd17 564
EricLew 0:3eee9435dd17 565 /** \brief Get Fault Mask
EricLew 0:3eee9435dd17 566
EricLew 0:3eee9435dd17 567 This function returns the current value of the Fault Mask register.
EricLew 0:3eee9435dd17 568
EricLew 0:3eee9435dd17 569 \return Fault Mask register value
EricLew 0:3eee9435dd17 570 */
EricLew 0:3eee9435dd17 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
EricLew 0:3eee9435dd17 572 {
EricLew 0:3eee9435dd17 573 uint32_t result;
EricLew 0:3eee9435dd17 574
EricLew 0:3eee9435dd17 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
EricLew 0:3eee9435dd17 576 return(result);
EricLew 0:3eee9435dd17 577 }
EricLew 0:3eee9435dd17 578
EricLew 0:3eee9435dd17 579
EricLew 0:3eee9435dd17 580 /** \brief Set Fault Mask
EricLew 0:3eee9435dd17 581
EricLew 0:3eee9435dd17 582 This function assigns the given value to the Fault Mask register.
EricLew 0:3eee9435dd17 583
EricLew 0:3eee9435dd17 584 \param [in] faultMask Fault Mask value to set
EricLew 0:3eee9435dd17 585 */
EricLew 0:3eee9435dd17 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
EricLew 0:3eee9435dd17 587 {
EricLew 0:3eee9435dd17 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
EricLew 0:3eee9435dd17 589 }
EricLew 0:3eee9435dd17 590
EricLew 0:3eee9435dd17 591 #endif /* (__CORTEX_M >= 0x03) */
EricLew 0:3eee9435dd17 592
EricLew 0:3eee9435dd17 593
EricLew 0:3eee9435dd17 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
EricLew 0:3eee9435dd17 595
EricLew 0:3eee9435dd17 596 /** \brief Get FPSCR
EricLew 0:3eee9435dd17 597
EricLew 0:3eee9435dd17 598 This function returns the current value of the Floating Point Status/Control register.
EricLew 0:3eee9435dd17 599
EricLew 0:3eee9435dd17 600 \return Floating Point Status/Control register value
EricLew 0:3eee9435dd17 601 */
EricLew 0:3eee9435dd17 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
EricLew 0:3eee9435dd17 603 {
EricLew 0:3eee9435dd17 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
EricLew 0:3eee9435dd17 605 uint32_t result;
EricLew 0:3eee9435dd17 606
EricLew 0:3eee9435dd17 607 /* Empty asm statement works as a scheduling barrier */
EricLew 0:3eee9435dd17 608 __ASM volatile ("");
EricLew 0:3eee9435dd17 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
EricLew 0:3eee9435dd17 610 __ASM volatile ("");
EricLew 0:3eee9435dd17 611 return(result);
EricLew 0:3eee9435dd17 612 #else
EricLew 0:3eee9435dd17 613 return(0);
EricLew 0:3eee9435dd17 614 #endif
EricLew 0:3eee9435dd17 615 }
EricLew 0:3eee9435dd17 616
EricLew 0:3eee9435dd17 617
EricLew 0:3eee9435dd17 618 /** \brief Set FPSCR
EricLew 0:3eee9435dd17 619
EricLew 0:3eee9435dd17 620 This function assigns the given value to the Floating Point Status/Control register.
EricLew 0:3eee9435dd17 621
EricLew 0:3eee9435dd17 622 \param [in] fpscr Floating Point Status/Control value to set
EricLew 0:3eee9435dd17 623 */
EricLew 0:3eee9435dd17 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
EricLew 0:3eee9435dd17 625 {
EricLew 0:3eee9435dd17 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
EricLew 0:3eee9435dd17 627 /* Empty asm statement works as a scheduling barrier */
EricLew 0:3eee9435dd17 628 __ASM volatile ("");
EricLew 0:3eee9435dd17 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
EricLew 0:3eee9435dd17 630 __ASM volatile ("");
EricLew 0:3eee9435dd17 631 #endif
EricLew 0:3eee9435dd17 632 }
EricLew 0:3eee9435dd17 633
EricLew 0:3eee9435dd17 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
EricLew 0:3eee9435dd17 635
EricLew 0:3eee9435dd17 636
EricLew 0:3eee9435dd17 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
EricLew 0:3eee9435dd17 638 /* IAR iccarm specific functions */
EricLew 0:3eee9435dd17 639 #include <cmsis_iar.h>
EricLew 0:3eee9435dd17 640
EricLew 0:3eee9435dd17 641
EricLew 0:3eee9435dd17 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
EricLew 0:3eee9435dd17 643 /* TI CCS specific functions */
EricLew 0:3eee9435dd17 644 #include <cmsis_ccs.h>
EricLew 0:3eee9435dd17 645
EricLew 0:3eee9435dd17 646
EricLew 0:3eee9435dd17 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
EricLew 0:3eee9435dd17 648 /* TASKING carm specific functions */
EricLew 0:3eee9435dd17 649 /*
EricLew 0:3eee9435dd17 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
EricLew 0:3eee9435dd17 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
EricLew 0:3eee9435dd17 652 * Including the CMSIS ones.
EricLew 0:3eee9435dd17 653 */
EricLew 0:3eee9435dd17 654
EricLew 0:3eee9435dd17 655
EricLew 0:3eee9435dd17 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
EricLew 0:3eee9435dd17 657 /* Cosmic specific functions */
EricLew 0:3eee9435dd17 658 #include <cmsis_csm.h>
EricLew 0:3eee9435dd17 659
EricLew 0:3eee9435dd17 660 #endif
EricLew 0:3eee9435dd17 661
EricLew 0:3eee9435dd17 662 /*@} end of CMSIS_Core_RegAccFunctions */
EricLew 0:3eee9435dd17 663
EricLew 0:3eee9435dd17 664 #endif /* __CORE_CMFUNC_H */
EricLew 0:3eee9435dd17 665
EricLew 0:3eee9435dd17 666