Senior Design: Sound Monitor / AudioDemo

Audio Demo with DISCO Board, takes control samples, waits for user input, samples regularly.

Dependencies:   CMSIS_DSP_401 STM32L4xx_HAL_Driver mbed-src_DISO_AUDIO_DEMO

core_cm4.h@0:3eee9435dd17, 2015-12-13 (annotated)

Committer:
EricLew
Date:
Sun Dec 13 19:12:11 2015 +0000
Revision:
0:3eee9435dd17
Audio Demo using DISCO Board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:3eee9435dd17 1 /**************************************************************************//**
EricLew 0:3eee9435dd17 2 * @file core_cm4.h
EricLew 0:3eee9435dd17 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
EricLew 0:3eee9435dd17 4 * @version V4.10
EricLew 0:3eee9435dd17 5 * @date 18. March 2015
EricLew 0:3eee9435dd17 6 *
EricLew 0:3eee9435dd17 7 * @note
EricLew 0:3eee9435dd17 8 *
EricLew 0:3eee9435dd17 9 ******************************************************************************/
EricLew 0:3eee9435dd17 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
EricLew 0:3eee9435dd17 11
EricLew 0:3eee9435dd17 12 All rights reserved.
EricLew 0:3eee9435dd17 13 Redistribution and use in source and binary forms, with or without
EricLew 0:3eee9435dd17 14 modification, are permitted provided that the following conditions are met:
EricLew 0:3eee9435dd17 15 - Redistributions of source code must retain the above copyright
EricLew 0:3eee9435dd17 16 notice, this list of conditions and the following disclaimer.
EricLew 0:3eee9435dd17 17 - Redistributions in binary form must reproduce the above copyright
EricLew 0:3eee9435dd17 18 notice, this list of conditions and the following disclaimer in the
EricLew 0:3eee9435dd17 19 documentation and/or other materials provided with the distribution.
EricLew 0:3eee9435dd17 20 - Neither the name of ARM nor the names of its contributors may be used
EricLew 0:3eee9435dd17 21 to endorse or promote products derived from this software without
EricLew 0:3eee9435dd17 22 specific prior written permission.
EricLew 0:3eee9435dd17 23 *
EricLew 0:3eee9435dd17 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:3eee9435dd17 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:3eee9435dd17 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
EricLew 0:3eee9435dd17 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
EricLew 0:3eee9435dd17 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
EricLew 0:3eee9435dd17 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
EricLew 0:3eee9435dd17 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
EricLew 0:3eee9435dd17 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
EricLew 0:3eee9435dd17 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
EricLew 0:3eee9435dd17 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
EricLew 0:3eee9435dd17 34 POSSIBILITY OF SUCH DAMAGE.
EricLew 0:3eee9435dd17 35 ---------------------------------------------------------------------------*/
EricLew 0:3eee9435dd17 36
EricLew 0:3eee9435dd17 37
EricLew 0:3eee9435dd17 38 #if defined ( __ICCARM__ )
EricLew 0:3eee9435dd17 39 #pragma system_include /* treat file as system include file for MISRA check */
EricLew 0:3eee9435dd17 40 #endif
EricLew 0:3eee9435dd17 41
EricLew 0:3eee9435dd17 42 #ifndef __CORE_CM4_H_GENERIC
EricLew 0:3eee9435dd17 43 #define __CORE_CM4_H_GENERIC
EricLew 0:3eee9435dd17 44
EricLew 0:3eee9435dd17 45 #ifdef __cplusplus
EricLew 0:3eee9435dd17 46 extern "C" {
EricLew 0:3eee9435dd17 47 #endif
EricLew 0:3eee9435dd17 48
EricLew 0:3eee9435dd17 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
EricLew 0:3eee9435dd17 50 CMSIS violates the following MISRA-C:2004 rules:
EricLew 0:3eee9435dd17 51
EricLew 0:3eee9435dd17 52 \li Required Rule 8.5, object/function definition in header file.<br>
EricLew 0:3eee9435dd17 53 Function definitions in header files are used to allow 'inlining'.
EricLew 0:3eee9435dd17 54
EricLew 0:3eee9435dd17 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
EricLew 0:3eee9435dd17 56 Unions are used for effective representation of core registers.
EricLew 0:3eee9435dd17 57
EricLew 0:3eee9435dd17 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
EricLew 0:3eee9435dd17 59 Function-like macros are used to allow more efficient code.
EricLew 0:3eee9435dd17 60 */
EricLew 0:3eee9435dd17 61
EricLew 0:3eee9435dd17 62
EricLew 0:3eee9435dd17 63 /*******************************************************************************
EricLew 0:3eee9435dd17 64 * CMSIS definitions
EricLew 0:3eee9435dd17 65 ******************************************************************************/
EricLew 0:3eee9435dd17 66 /** \ingroup Cortex_M4
EricLew 0:3eee9435dd17 67 @{
EricLew 0:3eee9435dd17 68 */
EricLew 0:3eee9435dd17 69
EricLew 0:3eee9435dd17 70 /* CMSIS CM4 definitions */
EricLew 0:3eee9435dd17 71 #define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
EricLew 0:3eee9435dd17 72 #define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
EricLew 0:3eee9435dd17 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
EricLew 0:3eee9435dd17 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
EricLew 0:3eee9435dd17 75
EricLew 0:3eee9435dd17 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
EricLew 0:3eee9435dd17 77
EricLew 0:3eee9435dd17 78
EricLew 0:3eee9435dd17 79 #if defined ( __CC_ARM )
EricLew 0:3eee9435dd17 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
EricLew 0:3eee9435dd17 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
EricLew 0:3eee9435dd17 82 #define __STATIC_INLINE static __inline
EricLew 0:3eee9435dd17 83
EricLew 0:3eee9435dd17 84 #elif defined ( __GNUC__ )
EricLew 0:3eee9435dd17 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
EricLew 0:3eee9435dd17 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
EricLew 0:3eee9435dd17 87 #define __STATIC_INLINE static inline
EricLew 0:3eee9435dd17 88
EricLew 0:3eee9435dd17 89 #elif defined ( __ICCARM__ )
EricLew 0:3eee9435dd17 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
EricLew 0:3eee9435dd17 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
EricLew 0:3eee9435dd17 92 #define __STATIC_INLINE static inline
EricLew 0:3eee9435dd17 93
EricLew 0:3eee9435dd17 94 #elif defined ( __TMS470__ )
EricLew 0:3eee9435dd17 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
EricLew 0:3eee9435dd17 96 #define __STATIC_INLINE static inline
EricLew 0:3eee9435dd17 97
EricLew 0:3eee9435dd17 98 #elif defined ( __TASKING__ )
EricLew 0:3eee9435dd17 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
EricLew 0:3eee9435dd17 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
EricLew 0:3eee9435dd17 101 #define __STATIC_INLINE static inline
EricLew 0:3eee9435dd17 102
EricLew 0:3eee9435dd17 103 #elif defined ( __CSMC__ )
EricLew 0:3eee9435dd17 104 #define __packed
EricLew 0:3eee9435dd17 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
EricLew 0:3eee9435dd17 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
EricLew 0:3eee9435dd17 107 #define __STATIC_INLINE static inline
EricLew 0:3eee9435dd17 108
EricLew 0:3eee9435dd17 109 #endif
EricLew 0:3eee9435dd17 110
EricLew 0:3eee9435dd17 111 /** __FPU_USED indicates whether an FPU is used or not.
EricLew 0:3eee9435dd17 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
EricLew 0:3eee9435dd17 113 */
EricLew 0:3eee9435dd17 114 #if defined ( __CC_ARM )
EricLew 0:3eee9435dd17 115 #if defined __TARGET_FPU_VFP
EricLew 0:3eee9435dd17 116 #if (__FPU_PRESENT == 1)
EricLew 0:3eee9435dd17 117 #define __FPU_USED 1
EricLew 0:3eee9435dd17 118 #else
EricLew 0:3eee9435dd17 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
EricLew 0:3eee9435dd17 120 #define __FPU_USED 0
EricLew 0:3eee9435dd17 121 #endif
EricLew 0:3eee9435dd17 122 #else
EricLew 0:3eee9435dd17 123 #define __FPU_USED 0
EricLew 0:3eee9435dd17 124 #endif
EricLew 0:3eee9435dd17 125
EricLew 0:3eee9435dd17 126 #elif defined ( __GNUC__ )
EricLew 0:3eee9435dd17 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
EricLew 0:3eee9435dd17 128 #if (__FPU_PRESENT == 1)
EricLew 0:3eee9435dd17 129 #define __FPU_USED 1
EricLew 0:3eee9435dd17 130 #else
EricLew 0:3eee9435dd17 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
EricLew 0:3eee9435dd17 132 #define __FPU_USED 0
EricLew 0:3eee9435dd17 133 #endif
EricLew 0:3eee9435dd17 134 #else
EricLew 0:3eee9435dd17 135 #define __FPU_USED 0
EricLew 0:3eee9435dd17 136 #endif
EricLew 0:3eee9435dd17 137
EricLew 0:3eee9435dd17 138 #elif defined ( __ICCARM__ )
EricLew 0:3eee9435dd17 139 #if defined __ARMVFP__
EricLew 0:3eee9435dd17 140 #if (__FPU_PRESENT == 1)
EricLew 0:3eee9435dd17 141 #define __FPU_USED 1
EricLew 0:3eee9435dd17 142 #else
EricLew 0:3eee9435dd17 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
EricLew 0:3eee9435dd17 144 #define __FPU_USED 0
EricLew 0:3eee9435dd17 145 #endif
EricLew 0:3eee9435dd17 146 #else
EricLew 0:3eee9435dd17 147 #define __FPU_USED 0
EricLew 0:3eee9435dd17 148 #endif
EricLew 0:3eee9435dd17 149
EricLew 0:3eee9435dd17 150 #elif defined ( __TMS470__ )
EricLew 0:3eee9435dd17 151 #if defined __TI_VFP_SUPPORT__
EricLew 0:3eee9435dd17 152 #if (__FPU_PRESENT == 1)
EricLew 0:3eee9435dd17 153 #define __FPU_USED 1
EricLew 0:3eee9435dd17 154 #else
EricLew 0:3eee9435dd17 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
EricLew 0:3eee9435dd17 156 #define __FPU_USED 0
EricLew 0:3eee9435dd17 157 #endif
EricLew 0:3eee9435dd17 158 #else
EricLew 0:3eee9435dd17 159 #define __FPU_USED 0
EricLew 0:3eee9435dd17 160 #endif
EricLew 0:3eee9435dd17 161
EricLew 0:3eee9435dd17 162 #elif defined ( __TASKING__ )
EricLew 0:3eee9435dd17 163 #if defined __FPU_VFP__
EricLew 0:3eee9435dd17 164 #if (__FPU_PRESENT == 1)
EricLew 0:3eee9435dd17 165 #define __FPU_USED 1
EricLew 0:3eee9435dd17 166 #else
EricLew 0:3eee9435dd17 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
EricLew 0:3eee9435dd17 168 #define __FPU_USED 0
EricLew 0:3eee9435dd17 169 #endif
EricLew 0:3eee9435dd17 170 #else
EricLew 0:3eee9435dd17 171 #define __FPU_USED 0
EricLew 0:3eee9435dd17 172 #endif
EricLew 0:3eee9435dd17 173
EricLew 0:3eee9435dd17 174 #elif defined ( __CSMC__ ) /* Cosmic */
EricLew 0:3eee9435dd17 175 #if ( __CSMC__ & 0x400) // FPU present for parser
EricLew 0:3eee9435dd17 176 #if (__FPU_PRESENT == 1)
EricLew 0:3eee9435dd17 177 #define __FPU_USED 1
EricLew 0:3eee9435dd17 178 #else
EricLew 0:3eee9435dd17 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
EricLew 0:3eee9435dd17 180 #define __FPU_USED 0
EricLew 0:3eee9435dd17 181 #endif
EricLew 0:3eee9435dd17 182 #else
EricLew 0:3eee9435dd17 183 #define __FPU_USED 0
EricLew 0:3eee9435dd17 184 #endif
EricLew 0:3eee9435dd17 185 #endif
EricLew 0:3eee9435dd17 186
EricLew 0:3eee9435dd17 187 #include <stdint.h> /* standard types definitions */
EricLew 0:3eee9435dd17 188 #include <core_cmInstr.h> /* Core Instruction Access */
EricLew 0:3eee9435dd17 189 #include <core_cmFunc.h> /* Core Function Access */
EricLew 0:3eee9435dd17 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
EricLew 0:3eee9435dd17 191
EricLew 0:3eee9435dd17 192 #ifdef __cplusplus
EricLew 0:3eee9435dd17 193 }
EricLew 0:3eee9435dd17 194 #endif
EricLew 0:3eee9435dd17 195
EricLew 0:3eee9435dd17 196 #endif /* __CORE_CM4_H_GENERIC */
EricLew 0:3eee9435dd17 197
EricLew 0:3eee9435dd17 198 #ifndef __CMSIS_GENERIC
EricLew 0:3eee9435dd17 199
EricLew 0:3eee9435dd17 200 #ifndef __CORE_CM4_H_DEPENDANT
EricLew 0:3eee9435dd17 201 #define __CORE_CM4_H_DEPENDANT
EricLew 0:3eee9435dd17 202
EricLew 0:3eee9435dd17 203 #ifdef __cplusplus
EricLew 0:3eee9435dd17 204 extern "C" {
EricLew 0:3eee9435dd17 205 #endif
EricLew 0:3eee9435dd17 206
EricLew 0:3eee9435dd17 207 /* check device defines and use defaults */
EricLew 0:3eee9435dd17 208 #if defined __CHECK_DEVICE_DEFINES
EricLew 0:3eee9435dd17 209 #ifndef __CM4_REV
EricLew 0:3eee9435dd17 210 #define __CM4_REV 0x0000
EricLew 0:3eee9435dd17 211 #warning "__CM4_REV not defined in device header file; using default!"
EricLew 0:3eee9435dd17 212 #endif
EricLew 0:3eee9435dd17 213
EricLew 0:3eee9435dd17 214 #ifndef __FPU_PRESENT
EricLew 0:3eee9435dd17 215 #define __FPU_PRESENT 0
EricLew 0:3eee9435dd17 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
EricLew 0:3eee9435dd17 217 #endif
EricLew 0:3eee9435dd17 218
EricLew 0:3eee9435dd17 219 #ifndef __MPU_PRESENT
EricLew 0:3eee9435dd17 220 #define __MPU_PRESENT 0
EricLew 0:3eee9435dd17 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
EricLew 0:3eee9435dd17 222 #endif
EricLew 0:3eee9435dd17 223
EricLew 0:3eee9435dd17 224 #ifndef __NVIC_PRIO_BITS
EricLew 0:3eee9435dd17 225 #define __NVIC_PRIO_BITS 4
EricLew 0:3eee9435dd17 226 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
EricLew 0:3eee9435dd17 227 #endif
EricLew 0:3eee9435dd17 228
EricLew 0:3eee9435dd17 229 #ifndef __Vendor_SysTickConfig
EricLew 0:3eee9435dd17 230 #define __Vendor_SysTickConfig 0
EricLew 0:3eee9435dd17 231 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
EricLew 0:3eee9435dd17 232 #endif
EricLew 0:3eee9435dd17 233 #endif
EricLew 0:3eee9435dd17 234
EricLew 0:3eee9435dd17 235 /* IO definitions (access restrictions to peripheral registers) */
EricLew 0:3eee9435dd17 236 /**
EricLew 0:3eee9435dd17 237 \defgroup CMSIS_glob_defs CMSIS Global Defines
EricLew 0:3eee9435dd17 238
EricLew 0:3eee9435dd17 239 <strong>IO Type Qualifiers</strong> are used
EricLew 0:3eee9435dd17 240 \li to specify the access to peripheral variables.
EricLew 0:3eee9435dd17 241 \li for automatic generation of peripheral register debug information.
EricLew 0:3eee9435dd17 242 */
EricLew 0:3eee9435dd17 243 #ifdef __cplusplus
EricLew 0:3eee9435dd17 244 #define __I volatile /*!< Defines 'read only' permissions */
EricLew 0:3eee9435dd17 245 #else
EricLew 0:3eee9435dd17 246 #define __I volatile const /*!< Defines 'read only' permissions */
EricLew 0:3eee9435dd17 247 #endif
EricLew 0:3eee9435dd17 248 #define __O volatile /*!< Defines 'write only' permissions */
EricLew 0:3eee9435dd17 249 #define __IO volatile /*!< Defines 'read / write' permissions */
EricLew 0:3eee9435dd17 250
EricLew 0:3eee9435dd17 251 /*@} end of group Cortex_M4 */
EricLew 0:3eee9435dd17 252
EricLew 0:3eee9435dd17 253
EricLew 0:3eee9435dd17 254
EricLew 0:3eee9435dd17 255 /*******************************************************************************
EricLew 0:3eee9435dd17 256 * Register Abstraction
EricLew 0:3eee9435dd17 257 Core Register contain:
EricLew 0:3eee9435dd17 258 - Core Register
EricLew 0:3eee9435dd17 259 - Core NVIC Register
EricLew 0:3eee9435dd17 260 - Core SCB Register
EricLew 0:3eee9435dd17 261 - Core SysTick Register
EricLew 0:3eee9435dd17 262 - Core Debug Register
EricLew 0:3eee9435dd17 263 - Core MPU Register
EricLew 0:3eee9435dd17 264 - Core FPU Register
EricLew 0:3eee9435dd17 265 ******************************************************************************/
EricLew 0:3eee9435dd17 266 /** \defgroup CMSIS_core_register Defines and Type Definitions
EricLew 0:3eee9435dd17 267 \brief Type definitions and defines for Cortex-M processor based devices.
EricLew 0:3eee9435dd17 268 */
EricLew 0:3eee9435dd17 269
EricLew 0:3eee9435dd17 270 /** \ingroup CMSIS_core_register
EricLew 0:3eee9435dd17 271 \defgroup CMSIS_CORE Status and Control Registers
EricLew 0:3eee9435dd17 272 \brief Core Register type definitions.
EricLew 0:3eee9435dd17 273 @{
EricLew 0:3eee9435dd17 274 */
EricLew 0:3eee9435dd17 275
EricLew 0:3eee9435dd17 276 /** \brief Union type to access the Application Program Status Register (APSR).
EricLew 0:3eee9435dd17 277 */
EricLew 0:3eee9435dd17 278 typedef union
EricLew 0:3eee9435dd17 279 {
EricLew 0:3eee9435dd17 280 struct
EricLew 0:3eee9435dd17 281 {
EricLew 0:3eee9435dd17 282 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
EricLew 0:3eee9435dd17 283 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
EricLew 0:3eee9435dd17 284 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
EricLew 0:3eee9435dd17 285 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
EricLew 0:3eee9435dd17 286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
EricLew 0:3eee9435dd17 287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
EricLew 0:3eee9435dd17 288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
EricLew 0:3eee9435dd17 289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
EricLew 0:3eee9435dd17 290 } b; /*!< Structure used for bit access */
EricLew 0:3eee9435dd17 291 uint32_t w; /*!< Type used for word access */
EricLew 0:3eee9435dd17 292 } APSR_Type;
EricLew 0:3eee9435dd17 293
EricLew 0:3eee9435dd17 294 /* APSR Register Definitions */
EricLew 0:3eee9435dd17 295 #define APSR_N_Pos 31 /*!< APSR: N Position */
EricLew 0:3eee9435dd17 296 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
EricLew 0:3eee9435dd17 297
EricLew 0:3eee9435dd17 298 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
EricLew 0:3eee9435dd17 299 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
EricLew 0:3eee9435dd17 300
EricLew 0:3eee9435dd17 301 #define APSR_C_Pos 29 /*!< APSR: C Position */
EricLew 0:3eee9435dd17 302 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
EricLew 0:3eee9435dd17 303
EricLew 0:3eee9435dd17 304 #define APSR_V_Pos 28 /*!< APSR: V Position */
EricLew 0:3eee9435dd17 305 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
EricLew 0:3eee9435dd17 306
EricLew 0:3eee9435dd17 307 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
EricLew 0:3eee9435dd17 308 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
EricLew 0:3eee9435dd17 309
EricLew 0:3eee9435dd17 310 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
EricLew 0:3eee9435dd17 311 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
EricLew 0:3eee9435dd17 312
EricLew 0:3eee9435dd17 313
EricLew 0:3eee9435dd17 314 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
EricLew 0:3eee9435dd17 315 */
EricLew 0:3eee9435dd17 316 typedef union
EricLew 0:3eee9435dd17 317 {
EricLew 0:3eee9435dd17 318 struct
EricLew 0:3eee9435dd17 319 {
EricLew 0:3eee9435dd17 320 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
EricLew 0:3eee9435dd17 321 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
EricLew 0:3eee9435dd17 322 } b; /*!< Structure used for bit access */
EricLew 0:3eee9435dd17 323 uint32_t w; /*!< Type used for word access */
EricLew 0:3eee9435dd17 324 } IPSR_Type;
EricLew 0:3eee9435dd17 325
EricLew 0:3eee9435dd17 326 /* IPSR Register Definitions */
EricLew 0:3eee9435dd17 327 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
EricLew 0:3eee9435dd17 328 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
EricLew 0:3eee9435dd17 329
EricLew 0:3eee9435dd17 330
EricLew 0:3eee9435dd17 331 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
EricLew 0:3eee9435dd17 332 */
EricLew 0:3eee9435dd17 333 typedef union
EricLew 0:3eee9435dd17 334 {
EricLew 0:3eee9435dd17 335 struct
EricLew 0:3eee9435dd17 336 {
EricLew 0:3eee9435dd17 337 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
EricLew 0:3eee9435dd17 338 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
EricLew 0:3eee9435dd17 339 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
EricLew 0:3eee9435dd17 340 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
EricLew 0:3eee9435dd17 341 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
EricLew 0:3eee9435dd17 342 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
EricLew 0:3eee9435dd17 343 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
EricLew 0:3eee9435dd17 344 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
EricLew 0:3eee9435dd17 345 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
EricLew 0:3eee9435dd17 346 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
EricLew 0:3eee9435dd17 347 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
EricLew 0:3eee9435dd17 348 } b; /*!< Structure used for bit access */
EricLew 0:3eee9435dd17 349 uint32_t w; /*!< Type used for word access */
EricLew 0:3eee9435dd17 350 } xPSR_Type;
EricLew 0:3eee9435dd17 351
EricLew 0:3eee9435dd17 352 /* xPSR Register Definitions */
EricLew 0:3eee9435dd17 353 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
EricLew 0:3eee9435dd17 354 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
EricLew 0:3eee9435dd17 355
EricLew 0:3eee9435dd17 356 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
EricLew 0:3eee9435dd17 357 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
EricLew 0:3eee9435dd17 358
EricLew 0:3eee9435dd17 359 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
EricLew 0:3eee9435dd17 360 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
EricLew 0:3eee9435dd17 361
EricLew 0:3eee9435dd17 362 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
EricLew 0:3eee9435dd17 363 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
EricLew 0:3eee9435dd17 364
EricLew 0:3eee9435dd17 365 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
EricLew 0:3eee9435dd17 366 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
EricLew 0:3eee9435dd17 367
EricLew 0:3eee9435dd17 368 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
EricLew 0:3eee9435dd17 369 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
EricLew 0:3eee9435dd17 370
EricLew 0:3eee9435dd17 371 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
EricLew 0:3eee9435dd17 372 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
EricLew 0:3eee9435dd17 373
EricLew 0:3eee9435dd17 374 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
EricLew 0:3eee9435dd17 375 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
EricLew 0:3eee9435dd17 376
EricLew 0:3eee9435dd17 377 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
EricLew 0:3eee9435dd17 378 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
EricLew 0:3eee9435dd17 379
EricLew 0:3eee9435dd17 380
EricLew 0:3eee9435dd17 381 /** \brief Union type to access the Control Registers (CONTROL).
EricLew 0:3eee9435dd17 382 */
EricLew 0:3eee9435dd17 383 typedef union
EricLew 0:3eee9435dd17 384 {
EricLew 0:3eee9435dd17 385 struct
EricLew 0:3eee9435dd17 386 {
EricLew 0:3eee9435dd17 387 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
EricLew 0:3eee9435dd17 388 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
EricLew 0:3eee9435dd17 389 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
EricLew 0:3eee9435dd17 390 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
EricLew 0:3eee9435dd17 391 } b; /*!< Structure used for bit access */
EricLew 0:3eee9435dd17 392 uint32_t w; /*!< Type used for word access */
EricLew 0:3eee9435dd17 393 } CONTROL_Type;
EricLew 0:3eee9435dd17 394
EricLew 0:3eee9435dd17 395 /* CONTROL Register Definitions */
EricLew 0:3eee9435dd17 396 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
EricLew 0:3eee9435dd17 397 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
EricLew 0:3eee9435dd17 398
EricLew 0:3eee9435dd17 399 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
EricLew 0:3eee9435dd17 400 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
EricLew 0:3eee9435dd17 401
EricLew 0:3eee9435dd17 402 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
EricLew 0:3eee9435dd17 403 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
EricLew 0:3eee9435dd17 404
EricLew 0:3eee9435dd17 405 /*@} end of group CMSIS_CORE */
EricLew 0:3eee9435dd17 406
EricLew 0:3eee9435dd17 407
EricLew 0:3eee9435dd17 408 /** \ingroup CMSIS_core_register
EricLew 0:3eee9435dd17 409 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
EricLew 0:3eee9435dd17 410 \brief Type definitions for the NVIC Registers
EricLew 0:3eee9435dd17 411 @{
EricLew 0:3eee9435dd17 412 */
EricLew 0:3eee9435dd17 413
EricLew 0:3eee9435dd17 414 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
EricLew 0:3eee9435dd17 415 */
EricLew 0:3eee9435dd17 416 typedef struct
EricLew 0:3eee9435dd17 417 {
EricLew 0:3eee9435dd17 418 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
EricLew 0:3eee9435dd17 419 uint32_t RESERVED0[24];
EricLew 0:3eee9435dd17 420 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
EricLew 0:3eee9435dd17 421 uint32_t RSERVED1[24];
EricLew 0:3eee9435dd17 422 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
EricLew 0:3eee9435dd17 423 uint32_t RESERVED2[24];
EricLew 0:3eee9435dd17 424 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
EricLew 0:3eee9435dd17 425 uint32_t RESERVED3[24];
EricLew 0:3eee9435dd17 426 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
EricLew 0:3eee9435dd17 427 uint32_t RESERVED4[56];
EricLew 0:3eee9435dd17 428 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
EricLew 0:3eee9435dd17 429 uint32_t RESERVED5[644];
EricLew 0:3eee9435dd17 430 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
EricLew 0:3eee9435dd17 431 } NVIC_Type;
EricLew 0:3eee9435dd17 432
EricLew 0:3eee9435dd17 433 /* Software Triggered Interrupt Register Definitions */
EricLew 0:3eee9435dd17 434 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
EricLew 0:3eee9435dd17 435 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
EricLew 0:3eee9435dd17 436
EricLew 0:3eee9435dd17 437 /*@} end of group CMSIS_NVIC */
EricLew 0:3eee9435dd17 438
EricLew 0:3eee9435dd17 439
EricLew 0:3eee9435dd17 440 /** \ingroup CMSIS_core_register
EricLew 0:3eee9435dd17 441 \defgroup CMSIS_SCB System Control Block (SCB)
EricLew 0:3eee9435dd17 442 \brief Type definitions for the System Control Block Registers
EricLew 0:3eee9435dd17 443 @{
EricLew 0:3eee9435dd17 444 */
EricLew 0:3eee9435dd17 445
EricLew 0:3eee9435dd17 446 /** \brief Structure type to access the System Control Block (SCB).
EricLew 0:3eee9435dd17 447 */
EricLew 0:3eee9435dd17 448 typedef struct
EricLew 0:3eee9435dd17 449 {
EricLew 0:3eee9435dd17 450 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
EricLew 0:3eee9435dd17 451 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
EricLew 0:3eee9435dd17 452 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
EricLew 0:3eee9435dd17 453 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
EricLew 0:3eee9435dd17 454 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
EricLew 0:3eee9435dd17 455 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
EricLew 0:3eee9435dd17 456 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
EricLew 0:3eee9435dd17 457 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
EricLew 0:3eee9435dd17 458 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
EricLew 0:3eee9435dd17 459 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
EricLew 0:3eee9435dd17 460 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
EricLew 0:3eee9435dd17 461 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
EricLew 0:3eee9435dd17 462 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
EricLew 0:3eee9435dd17 463 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
EricLew 0:3eee9435dd17 464 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
EricLew 0:3eee9435dd17 465 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
EricLew 0:3eee9435dd17 466 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
EricLew 0:3eee9435dd17 467 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
EricLew 0:3eee9435dd17 468 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
EricLew 0:3eee9435dd17 469 uint32_t RESERVED0[5];
EricLew 0:3eee9435dd17 470 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
EricLew 0:3eee9435dd17 471 } SCB_Type;
EricLew 0:3eee9435dd17 472
EricLew 0:3eee9435dd17 473 /* SCB CPUID Register Definitions */
EricLew 0:3eee9435dd17 474 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
EricLew 0:3eee9435dd17 475 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
EricLew 0:3eee9435dd17 476
EricLew 0:3eee9435dd17 477 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
EricLew 0:3eee9435dd17 478 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
EricLew 0:3eee9435dd17 479
EricLew 0:3eee9435dd17 480 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
EricLew 0:3eee9435dd17 481 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
EricLew 0:3eee9435dd17 482
EricLew 0:3eee9435dd17 483 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
EricLew 0:3eee9435dd17 484 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
EricLew 0:3eee9435dd17 485
EricLew 0:3eee9435dd17 486 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
EricLew 0:3eee9435dd17 487 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
EricLew 0:3eee9435dd17 488
EricLew 0:3eee9435dd17 489 /* SCB Interrupt Control State Register Definitions */
EricLew 0:3eee9435dd17 490 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
EricLew 0:3eee9435dd17 491 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
EricLew 0:3eee9435dd17 492
EricLew 0:3eee9435dd17 493 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
EricLew 0:3eee9435dd17 494 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
EricLew 0:3eee9435dd17 495
EricLew 0:3eee9435dd17 496 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
EricLew 0:3eee9435dd17 497 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
EricLew 0:3eee9435dd17 498
EricLew 0:3eee9435dd17 499 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
EricLew 0:3eee9435dd17 500 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
EricLew 0:3eee9435dd17 501
EricLew 0:3eee9435dd17 502 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
EricLew 0:3eee9435dd17 503 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
EricLew 0:3eee9435dd17 504
EricLew 0:3eee9435dd17 505 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
EricLew 0:3eee9435dd17 506 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
EricLew 0:3eee9435dd17 507
EricLew 0:3eee9435dd17 508 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
EricLew 0:3eee9435dd17 509 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
EricLew 0:3eee9435dd17 510
EricLew 0:3eee9435dd17 511 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
EricLew 0:3eee9435dd17 512 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
EricLew 0:3eee9435dd17 513
EricLew 0:3eee9435dd17 514 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
EricLew 0:3eee9435dd17 515 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
EricLew 0:3eee9435dd17 516
EricLew 0:3eee9435dd17 517 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
EricLew 0:3eee9435dd17 518 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
EricLew 0:3eee9435dd17 519
EricLew 0:3eee9435dd17 520 /* SCB Vector Table Offset Register Definitions */
EricLew 0:3eee9435dd17 521 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
EricLew 0:3eee9435dd17 522 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
EricLew 0:3eee9435dd17 523
EricLew 0:3eee9435dd17 524 /* SCB Application Interrupt and Reset Control Register Definitions */
EricLew 0:3eee9435dd17 525 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
EricLew 0:3eee9435dd17 526 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
EricLew 0:3eee9435dd17 527
EricLew 0:3eee9435dd17 528 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
EricLew 0:3eee9435dd17 529 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
EricLew 0:3eee9435dd17 530
EricLew 0:3eee9435dd17 531 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
EricLew 0:3eee9435dd17 532 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
EricLew 0:3eee9435dd17 533
EricLew 0:3eee9435dd17 534 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
EricLew 0:3eee9435dd17 535 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
EricLew 0:3eee9435dd17 536
EricLew 0:3eee9435dd17 537 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
EricLew 0:3eee9435dd17 538 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
EricLew 0:3eee9435dd17 539
EricLew 0:3eee9435dd17 540 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
EricLew 0:3eee9435dd17 541 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
EricLew 0:3eee9435dd17 542
EricLew 0:3eee9435dd17 543 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
EricLew 0:3eee9435dd17 544 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
EricLew 0:3eee9435dd17 545
EricLew 0:3eee9435dd17 546 /* SCB System Control Register Definitions */
EricLew 0:3eee9435dd17 547 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
EricLew 0:3eee9435dd17 548 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
EricLew 0:3eee9435dd17 549
EricLew 0:3eee9435dd17 550 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
EricLew 0:3eee9435dd17 551 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
EricLew 0:3eee9435dd17 552
EricLew 0:3eee9435dd17 553 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
EricLew 0:3eee9435dd17 554 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
EricLew 0:3eee9435dd17 555
EricLew 0:3eee9435dd17 556 /* SCB Configuration Control Register Definitions */
EricLew 0:3eee9435dd17 557 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
EricLew 0:3eee9435dd17 558 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
EricLew 0:3eee9435dd17 559
EricLew 0:3eee9435dd17 560 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
EricLew 0:3eee9435dd17 561 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
EricLew 0:3eee9435dd17 562
EricLew 0:3eee9435dd17 563 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
EricLew 0:3eee9435dd17 564 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
EricLew 0:3eee9435dd17 565
EricLew 0:3eee9435dd17 566 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
EricLew 0:3eee9435dd17 567 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
EricLew 0:3eee9435dd17 568
EricLew 0:3eee9435dd17 569 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
EricLew 0:3eee9435dd17 570 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
EricLew 0:3eee9435dd17 571
EricLew 0:3eee9435dd17 572 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
EricLew 0:3eee9435dd17 573 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
EricLew 0:3eee9435dd17 574
EricLew 0:3eee9435dd17 575 /* SCB System Handler Control and State Register Definitions */
EricLew 0:3eee9435dd17 576 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
EricLew 0:3eee9435dd17 577 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
EricLew 0:3eee9435dd17 578
EricLew 0:3eee9435dd17 579 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
EricLew 0:3eee9435dd17 580 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
EricLew 0:3eee9435dd17 581
EricLew 0:3eee9435dd17 582 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
EricLew 0:3eee9435dd17 583 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
EricLew 0:3eee9435dd17 584
EricLew 0:3eee9435dd17 585 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
EricLew 0:3eee9435dd17 586 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
EricLew 0:3eee9435dd17 587
EricLew 0:3eee9435dd17 588 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
EricLew 0:3eee9435dd17 589 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
EricLew 0:3eee9435dd17 590
EricLew 0:3eee9435dd17 591 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
EricLew 0:3eee9435dd17 592 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
EricLew 0:3eee9435dd17 593
EricLew 0:3eee9435dd17 594 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
EricLew 0:3eee9435dd17 595 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
EricLew 0:3eee9435dd17 596
EricLew 0:3eee9435dd17 597 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
EricLew 0:3eee9435dd17 598 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
EricLew 0:3eee9435dd17 599
EricLew 0:3eee9435dd17 600 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
EricLew 0:3eee9435dd17 601 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
EricLew 0:3eee9435dd17 602
EricLew 0:3eee9435dd17 603 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
EricLew 0:3eee9435dd17 604 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
EricLew 0:3eee9435dd17 605
EricLew 0:3eee9435dd17 606 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
EricLew 0:3eee9435dd17 607 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
EricLew 0:3eee9435dd17 608
EricLew 0:3eee9435dd17 609 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
EricLew 0:3eee9435dd17 610 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
EricLew 0:3eee9435dd17 611
EricLew 0:3eee9435dd17 612 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
EricLew 0:3eee9435dd17 613 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
EricLew 0:3eee9435dd17 614
EricLew 0:3eee9435dd17 615 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
EricLew 0:3eee9435dd17 616 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
EricLew 0:3eee9435dd17 617
EricLew 0:3eee9435dd17 618 /* SCB Configurable Fault Status Registers Definitions */
EricLew 0:3eee9435dd17 619 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
EricLew 0:3eee9435dd17 620 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
EricLew 0:3eee9435dd17 621
EricLew 0:3eee9435dd17 622 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
EricLew 0:3eee9435dd17 623 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
EricLew 0:3eee9435dd17 624
EricLew 0:3eee9435dd17 625 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
EricLew 0:3eee9435dd17 626 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
EricLew 0:3eee9435dd17 627
EricLew 0:3eee9435dd17 628 /* SCB Hard Fault Status Registers Definitions */
EricLew 0:3eee9435dd17 629 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
EricLew 0:3eee9435dd17 630 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
EricLew 0:3eee9435dd17 631
EricLew 0:3eee9435dd17 632 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
EricLew 0:3eee9435dd17 633 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
EricLew 0:3eee9435dd17 634
EricLew 0:3eee9435dd17 635 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
EricLew 0:3eee9435dd17 636 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
EricLew 0:3eee9435dd17 637
EricLew 0:3eee9435dd17 638 /* SCB Debug Fault Status Register Definitions */
EricLew 0:3eee9435dd17 639 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
EricLew 0:3eee9435dd17 640 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
EricLew 0:3eee9435dd17 641
EricLew 0:3eee9435dd17 642 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
EricLew 0:3eee9435dd17 643 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
EricLew 0:3eee9435dd17 644
EricLew 0:3eee9435dd17 645 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
EricLew 0:3eee9435dd17 646 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
EricLew 0:3eee9435dd17 647
EricLew 0:3eee9435dd17 648 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
EricLew 0:3eee9435dd17 649 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
EricLew 0:3eee9435dd17 650
EricLew 0:3eee9435dd17 651 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
EricLew 0:3eee9435dd17 652 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
EricLew 0:3eee9435dd17 653
EricLew 0:3eee9435dd17 654 /*@} end of group CMSIS_SCB */
EricLew 0:3eee9435dd17 655
EricLew 0:3eee9435dd17 656
EricLew 0:3eee9435dd17 657 /** \ingroup CMSIS_core_register
EricLew 0:3eee9435dd17 658 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
EricLew 0:3eee9435dd17 659 \brief Type definitions for the System Control and ID Register not in the SCB
EricLew 0:3eee9435dd17 660 @{
EricLew 0:3eee9435dd17 661 */
EricLew 0:3eee9435dd17 662
EricLew 0:3eee9435dd17 663 /** \brief Structure type to access the System Control and ID Register not in the SCB.
EricLew 0:3eee9435dd17 664 */
EricLew 0:3eee9435dd17 665 typedef struct
EricLew 0:3eee9435dd17 666 {
EricLew 0:3eee9435dd17 667 uint32_t RESERVED0[1];
EricLew 0:3eee9435dd17 668 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
EricLew 0:3eee9435dd17 669 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
EricLew 0:3eee9435dd17 670 } SCnSCB_Type;
EricLew 0:3eee9435dd17 671
EricLew 0:3eee9435dd17 672 /* Interrupt Controller Type Register Definitions */
EricLew 0:3eee9435dd17 673 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
EricLew 0:3eee9435dd17 674 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
EricLew 0:3eee9435dd17 675
EricLew 0:3eee9435dd17 676 /* Auxiliary Control Register Definitions */
EricLew 0:3eee9435dd17 677 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
EricLew 0:3eee9435dd17 678 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
EricLew 0:3eee9435dd17 679
EricLew 0:3eee9435dd17 680 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
EricLew 0:3eee9435dd17 681 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
EricLew 0:3eee9435dd17 682
EricLew 0:3eee9435dd17 683 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
EricLew 0:3eee9435dd17 684 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
EricLew 0:3eee9435dd17 685
EricLew 0:3eee9435dd17 686 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
EricLew 0:3eee9435dd17 687 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
EricLew 0:3eee9435dd17 688
EricLew 0:3eee9435dd17 689 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
EricLew 0:3eee9435dd17 690 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
EricLew 0:3eee9435dd17 691
EricLew 0:3eee9435dd17 692 /*@} end of group CMSIS_SCnotSCB */
EricLew 0:3eee9435dd17 693
EricLew 0:3eee9435dd17 694
EricLew 0:3eee9435dd17 695 /** \ingroup CMSIS_core_register
EricLew 0:3eee9435dd17 696 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
EricLew 0:3eee9435dd17 697 \brief Type definitions for the System Timer Registers.
EricLew 0:3eee9435dd17 698 @{
EricLew 0:3eee9435dd17 699 */
EricLew 0:3eee9435dd17 700
EricLew 0:3eee9435dd17 701 /** \brief Structure type to access the System Timer (SysTick).
EricLew 0:3eee9435dd17 702 */
EricLew 0:3eee9435dd17 703 typedef struct
EricLew 0:3eee9435dd17 704 {
EricLew 0:3eee9435dd17 705 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
EricLew 0:3eee9435dd17 706 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
EricLew 0:3eee9435dd17 707 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
EricLew 0:3eee9435dd17 708 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
EricLew 0:3eee9435dd17 709 } SysTick_Type;
EricLew 0:3eee9435dd17 710
EricLew 0:3eee9435dd17 711 /* SysTick Control / Status Register Definitions */
EricLew 0:3eee9435dd17 712 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
EricLew 0:3eee9435dd17 713 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
EricLew 0:3eee9435dd17 714
EricLew 0:3eee9435dd17 715 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
EricLew 0:3eee9435dd17 716 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
EricLew 0:3eee9435dd17 717
EricLew 0:3eee9435dd17 718 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
EricLew 0:3eee9435dd17 719 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
EricLew 0:3eee9435dd17 720
EricLew 0:3eee9435dd17 721 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
EricLew 0:3eee9435dd17 722 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
EricLew 0:3eee9435dd17 723
EricLew 0:3eee9435dd17 724 /* SysTick Reload Register Definitions */
EricLew 0:3eee9435dd17 725 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
EricLew 0:3eee9435dd17 726 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
EricLew 0:3eee9435dd17 727
EricLew 0:3eee9435dd17 728 /* SysTick Current Register Definitions */
EricLew 0:3eee9435dd17 729 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
EricLew 0:3eee9435dd17 730 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
EricLew 0:3eee9435dd17 731
EricLew 0:3eee9435dd17 732 /* SysTick Calibration Register Definitions */
EricLew 0:3eee9435dd17 733 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
EricLew 0:3eee9435dd17 734 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
EricLew 0:3eee9435dd17 735
EricLew 0:3eee9435dd17 736 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
EricLew 0:3eee9435dd17 737 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
EricLew 0:3eee9435dd17 738
EricLew 0:3eee9435dd17 739 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
EricLew 0:3eee9435dd17 740 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
EricLew 0:3eee9435dd17 741
EricLew 0:3eee9435dd17 742 /*@} end of group CMSIS_SysTick */
EricLew 0:3eee9435dd17 743
EricLew 0:3eee9435dd17 744
EricLew 0:3eee9435dd17 745 /** \ingroup CMSIS_core_register
EricLew 0:3eee9435dd17 746 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
EricLew 0:3eee9435dd17 747 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
EricLew 0:3eee9435dd17 748 @{
EricLew 0:3eee9435dd17 749 */
EricLew 0:3eee9435dd17 750
EricLew 0:3eee9435dd17 751 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
EricLew 0:3eee9435dd17 752 */
EricLew 0:3eee9435dd17 753 typedef struct
EricLew 0:3eee9435dd17 754 {
EricLew 0:3eee9435dd17 755 __O union
EricLew 0:3eee9435dd17 756 {
EricLew 0:3eee9435dd17 757 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
EricLew 0:3eee9435dd17 758 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
EricLew 0:3eee9435dd17 759 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
EricLew 0:3eee9435dd17 760 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
EricLew 0:3eee9435dd17 761 uint32_t RESERVED0[864];
EricLew 0:3eee9435dd17 762 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
EricLew 0:3eee9435dd17 763 uint32_t RESERVED1[15];
EricLew 0:3eee9435dd17 764 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
EricLew 0:3eee9435dd17 765 uint32_t RESERVED2[15];
EricLew 0:3eee9435dd17 766 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
EricLew 0:3eee9435dd17 767 uint32_t RESERVED3[29];
EricLew 0:3eee9435dd17 768 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
EricLew 0:3eee9435dd17 769 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
EricLew 0:3eee9435dd17 770 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
EricLew 0:3eee9435dd17 771 uint32_t RESERVED4[43];
EricLew 0:3eee9435dd17 772 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
EricLew 0:3eee9435dd17 773 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
EricLew 0:3eee9435dd17 774 uint32_t RESERVED5[6];
EricLew 0:3eee9435dd17 775 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
EricLew 0:3eee9435dd17 776 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
EricLew 0:3eee9435dd17 777 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
EricLew 0:3eee9435dd17 778 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
EricLew 0:3eee9435dd17 779 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
EricLew 0:3eee9435dd17 780 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
EricLew 0:3eee9435dd17 781 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
EricLew 0:3eee9435dd17 782 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
EricLew 0:3eee9435dd17 783 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
EricLew 0:3eee9435dd17 784 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
EricLew 0:3eee9435dd17 785 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
EricLew 0:3eee9435dd17 786 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
EricLew 0:3eee9435dd17 787 } ITM_Type;
EricLew 0:3eee9435dd17 788
EricLew 0:3eee9435dd17 789 /* ITM Trace Privilege Register Definitions */
EricLew 0:3eee9435dd17 790 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
EricLew 0:3eee9435dd17 791 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
EricLew 0:3eee9435dd17 792
EricLew 0:3eee9435dd17 793 /* ITM Trace Control Register Definitions */
EricLew 0:3eee9435dd17 794 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
EricLew 0:3eee9435dd17 795 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
EricLew 0:3eee9435dd17 796
EricLew 0:3eee9435dd17 797 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
EricLew 0:3eee9435dd17 798 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
EricLew 0:3eee9435dd17 799
EricLew 0:3eee9435dd17 800 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
EricLew 0:3eee9435dd17 801 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
EricLew 0:3eee9435dd17 802
EricLew 0:3eee9435dd17 803 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
EricLew 0:3eee9435dd17 804 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
EricLew 0:3eee9435dd17 805
EricLew 0:3eee9435dd17 806 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
EricLew 0:3eee9435dd17 807 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
EricLew 0:3eee9435dd17 808
EricLew 0:3eee9435dd17 809 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
EricLew 0:3eee9435dd17 810 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
EricLew 0:3eee9435dd17 811
EricLew 0:3eee9435dd17 812 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
EricLew 0:3eee9435dd17 813 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
EricLew 0:3eee9435dd17 814
EricLew 0:3eee9435dd17 815 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
EricLew 0:3eee9435dd17 816 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
EricLew 0:3eee9435dd17 817
EricLew 0:3eee9435dd17 818 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
EricLew 0:3eee9435dd17 819 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
EricLew 0:3eee9435dd17 820
EricLew 0:3eee9435dd17 821 /* ITM Integration Write Register Definitions */
EricLew 0:3eee9435dd17 822 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
EricLew 0:3eee9435dd17 823 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
EricLew 0:3eee9435dd17 824
EricLew 0:3eee9435dd17 825 /* ITM Integration Read Register Definitions */
EricLew 0:3eee9435dd17 826 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
EricLew 0:3eee9435dd17 827 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
EricLew 0:3eee9435dd17 828
EricLew 0:3eee9435dd17 829 /* ITM Integration Mode Control Register Definitions */
EricLew 0:3eee9435dd17 830 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
EricLew 0:3eee9435dd17 831 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
EricLew 0:3eee9435dd17 832
EricLew 0:3eee9435dd17 833 /* ITM Lock Status Register Definitions */
EricLew 0:3eee9435dd17 834 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
EricLew 0:3eee9435dd17 835 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
EricLew 0:3eee9435dd17 836
EricLew 0:3eee9435dd17 837 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
EricLew 0:3eee9435dd17 838 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
EricLew 0:3eee9435dd17 839
EricLew 0:3eee9435dd17 840 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
EricLew 0:3eee9435dd17 841 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
EricLew 0:3eee9435dd17 842
EricLew 0:3eee9435dd17 843 /*@}*/ /* end of group CMSIS_ITM */
EricLew 0:3eee9435dd17 844
EricLew 0:3eee9435dd17 845
EricLew 0:3eee9435dd17 846 /** \ingroup CMSIS_core_register
EricLew 0:3eee9435dd17 847 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
EricLew 0:3eee9435dd17 848 \brief Type definitions for the Data Watchpoint and Trace (DWT)
EricLew 0:3eee9435dd17 849 @{
EricLew 0:3eee9435dd17 850 */
EricLew 0:3eee9435dd17 851
EricLew 0:3eee9435dd17 852 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
EricLew 0:3eee9435dd17 853 */
EricLew 0:3eee9435dd17 854 typedef struct
EricLew 0:3eee9435dd17 855 {
EricLew 0:3eee9435dd17 856 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
EricLew 0:3eee9435dd17 857 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
EricLew 0:3eee9435dd17 858 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
EricLew 0:3eee9435dd17 859 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
EricLew 0:3eee9435dd17 860 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
EricLew 0:3eee9435dd17 861 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
EricLew 0:3eee9435dd17 862 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
EricLew 0:3eee9435dd17 863 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
EricLew 0:3eee9435dd17 864 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
EricLew 0:3eee9435dd17 865 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
EricLew 0:3eee9435dd17 866 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
EricLew 0:3eee9435dd17 867 uint32_t RESERVED0[1];
EricLew 0:3eee9435dd17 868 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
EricLew 0:3eee9435dd17 869 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
EricLew 0:3eee9435dd17 870 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
EricLew 0:3eee9435dd17 871 uint32_t RESERVED1[1];
EricLew 0:3eee9435dd17 872 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
EricLew 0:3eee9435dd17 873 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
EricLew 0:3eee9435dd17 874 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
EricLew 0:3eee9435dd17 875 uint32_t RESERVED2[1];
EricLew 0:3eee9435dd17 876 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
EricLew 0:3eee9435dd17 877 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
EricLew 0:3eee9435dd17 878 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
EricLew 0:3eee9435dd17 879 } DWT_Type;
EricLew 0:3eee9435dd17 880
EricLew 0:3eee9435dd17 881 /* DWT Control Register Definitions */
EricLew 0:3eee9435dd17 882 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
EricLew 0:3eee9435dd17 883 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
EricLew 0:3eee9435dd17 884
EricLew 0:3eee9435dd17 885 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
EricLew 0:3eee9435dd17 886 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
EricLew 0:3eee9435dd17 887
EricLew 0:3eee9435dd17 888 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
EricLew 0:3eee9435dd17 889 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
EricLew 0:3eee9435dd17 890
EricLew 0:3eee9435dd17 891 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
EricLew 0:3eee9435dd17 892 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
EricLew 0:3eee9435dd17 893
EricLew 0:3eee9435dd17 894 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
EricLew 0:3eee9435dd17 895 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
EricLew 0:3eee9435dd17 896
EricLew 0:3eee9435dd17 897 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
EricLew 0:3eee9435dd17 898 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
EricLew 0:3eee9435dd17 899
EricLew 0:3eee9435dd17 900 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
EricLew 0:3eee9435dd17 901 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
EricLew 0:3eee9435dd17 902
EricLew 0:3eee9435dd17 903 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
EricLew 0:3eee9435dd17 904 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
EricLew 0:3eee9435dd17 905
EricLew 0:3eee9435dd17 906 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
EricLew 0:3eee9435dd17 907 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
EricLew 0:3eee9435dd17 908
EricLew 0:3eee9435dd17 909 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
EricLew 0:3eee9435dd17 910 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
EricLew 0:3eee9435dd17 911
EricLew 0:3eee9435dd17 912 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
EricLew 0:3eee9435dd17 913 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
EricLew 0:3eee9435dd17 914
EricLew 0:3eee9435dd17 915 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
EricLew 0:3eee9435dd17 916 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
EricLew 0:3eee9435dd17 917
EricLew 0:3eee9435dd17 918 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
EricLew 0:3eee9435dd17 919 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
EricLew 0:3eee9435dd17 920
EricLew 0:3eee9435dd17 921 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
EricLew 0:3eee9435dd17 922 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
EricLew 0:3eee9435dd17 923
EricLew 0:3eee9435dd17 924 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
EricLew 0:3eee9435dd17 925 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
EricLew 0:3eee9435dd17 926
EricLew 0:3eee9435dd17 927 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
EricLew 0:3eee9435dd17 928 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
EricLew 0:3eee9435dd17 929
EricLew 0:3eee9435dd17 930 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
EricLew 0:3eee9435dd17 931 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
EricLew 0:3eee9435dd17 932
EricLew 0:3eee9435dd17 933 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
EricLew 0:3eee9435dd17 934 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
EricLew 0:3eee9435dd17 935
EricLew 0:3eee9435dd17 936 /* DWT CPI Count Register Definitions */
EricLew 0:3eee9435dd17 937 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
EricLew 0:3eee9435dd17 938 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
EricLew 0:3eee9435dd17 939
EricLew 0:3eee9435dd17 940 /* DWT Exception Overhead Count Register Definitions */
EricLew 0:3eee9435dd17 941 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
EricLew 0:3eee9435dd17 942 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
EricLew 0:3eee9435dd17 943
EricLew 0:3eee9435dd17 944 /* DWT Sleep Count Register Definitions */
EricLew 0:3eee9435dd17 945 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
EricLew 0:3eee9435dd17 946 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
EricLew 0:3eee9435dd17 947
EricLew 0:3eee9435dd17 948 /* DWT LSU Count Register Definitions */
EricLew 0:3eee9435dd17 949 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
EricLew 0:3eee9435dd17 950 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
EricLew 0:3eee9435dd17 951
EricLew 0:3eee9435dd17 952 /* DWT Folded-instruction Count Register Definitions */
EricLew 0:3eee9435dd17 953 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
EricLew 0:3eee9435dd17 954 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
EricLew 0:3eee9435dd17 955
EricLew 0:3eee9435dd17 956 /* DWT Comparator Mask Register Definitions */
EricLew 0:3eee9435dd17 957 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
EricLew 0:3eee9435dd17 958 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
EricLew 0:3eee9435dd17 959
EricLew 0:3eee9435dd17 960 /* DWT Comparator Function Register Definitions */
EricLew 0:3eee9435dd17 961 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
EricLew 0:3eee9435dd17 962 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
EricLew 0:3eee9435dd17 963
EricLew 0:3eee9435dd17 964 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
EricLew 0:3eee9435dd17 965 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
EricLew 0:3eee9435dd17 966
EricLew 0:3eee9435dd17 967 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
EricLew 0:3eee9435dd17 968 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
EricLew 0:3eee9435dd17 969
EricLew 0:3eee9435dd17 970 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
EricLew 0:3eee9435dd17 971 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
EricLew 0:3eee9435dd17 972
EricLew 0:3eee9435dd17 973 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
EricLew 0:3eee9435dd17 974 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
EricLew 0:3eee9435dd17 975
EricLew 0:3eee9435dd17 976 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
EricLew 0:3eee9435dd17 977 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
EricLew 0:3eee9435dd17 978
EricLew 0:3eee9435dd17 979 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
EricLew 0:3eee9435dd17 980 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
EricLew 0:3eee9435dd17 981
EricLew 0:3eee9435dd17 982 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
EricLew 0:3eee9435dd17 983 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
EricLew 0:3eee9435dd17 984
EricLew 0:3eee9435dd17 985 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
EricLew 0:3eee9435dd17 986 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
EricLew 0:3eee9435dd17 987
EricLew 0:3eee9435dd17 988 /*@}*/ /* end of group CMSIS_DWT */
EricLew 0:3eee9435dd17 989
EricLew 0:3eee9435dd17 990
EricLew 0:3eee9435dd17 991 /** \ingroup CMSIS_core_register
EricLew 0:3eee9435dd17 992 \defgroup CMSIS_TPI Trace Port Interface (TPI)
EricLew 0:3eee9435dd17 993 \brief Type definitions for the Trace Port Interface (TPI)
EricLew 0:3eee9435dd17 994 @{
EricLew 0:3eee9435dd17 995 */
EricLew 0:3eee9435dd17 996
EricLew 0:3eee9435dd17 997 /** \brief Structure type to access the Trace Port Interface Register (TPI).
EricLew 0:3eee9435dd17 998 */
EricLew 0:3eee9435dd17 999 typedef struct
EricLew 0:3eee9435dd17 1000 {
EricLew 0:3eee9435dd17 1001 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
EricLew 0:3eee9435dd17 1002 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
EricLew 0:3eee9435dd17 1003 uint32_t RESERVED0[2];
EricLew 0:3eee9435dd17 1004 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
EricLew 0:3eee9435dd17 1005 uint32_t RESERVED1[55];
EricLew 0:3eee9435dd17 1006 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
EricLew 0:3eee9435dd17 1007 uint32_t RESERVED2[131];
EricLew 0:3eee9435dd17 1008 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
EricLew 0:3eee9435dd17 1009 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
EricLew 0:3eee9435dd17 1010 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
EricLew 0:3eee9435dd17 1011 uint32_t RESERVED3[759];
EricLew 0:3eee9435dd17 1012 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
EricLew 0:3eee9435dd17 1013 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
EricLew 0:3eee9435dd17 1014 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
EricLew 0:3eee9435dd17 1015 uint32_t RESERVED4[1];
EricLew 0:3eee9435dd17 1016 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
EricLew 0:3eee9435dd17 1017 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
EricLew 0:3eee9435dd17 1018 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
EricLew 0:3eee9435dd17 1019 uint32_t RESERVED5[39];
EricLew 0:3eee9435dd17 1020 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
EricLew 0:3eee9435dd17 1021 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
EricLew 0:3eee9435dd17 1022 uint32_t RESERVED7[8];
EricLew 0:3eee9435dd17 1023 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
EricLew 0:3eee9435dd17 1024 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
EricLew 0:3eee9435dd17 1025 } TPI_Type;
EricLew 0:3eee9435dd17 1026
EricLew 0:3eee9435dd17 1027 /* TPI Asynchronous Clock Prescaler Register Definitions */
EricLew 0:3eee9435dd17 1028 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
EricLew 0:3eee9435dd17 1029 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
EricLew 0:3eee9435dd17 1030
EricLew 0:3eee9435dd17 1031 /* TPI Selected Pin Protocol Register Definitions */
EricLew 0:3eee9435dd17 1032 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
EricLew 0:3eee9435dd17 1033 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
EricLew 0:3eee9435dd17 1034
EricLew 0:3eee9435dd17 1035 /* TPI Formatter and Flush Status Register Definitions */
EricLew 0:3eee9435dd17 1036 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
EricLew 0:3eee9435dd17 1037 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
EricLew 0:3eee9435dd17 1038
EricLew 0:3eee9435dd17 1039 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
EricLew 0:3eee9435dd17 1040 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
EricLew 0:3eee9435dd17 1041
EricLew 0:3eee9435dd17 1042 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
EricLew 0:3eee9435dd17 1043 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
EricLew 0:3eee9435dd17 1044
EricLew 0:3eee9435dd17 1045 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
EricLew 0:3eee9435dd17 1046 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
EricLew 0:3eee9435dd17 1047
EricLew 0:3eee9435dd17 1048 /* TPI Formatter and Flush Control Register Definitions */
EricLew 0:3eee9435dd17 1049 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
EricLew 0:3eee9435dd17 1050 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
EricLew 0:3eee9435dd17 1051
EricLew 0:3eee9435dd17 1052 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
EricLew 0:3eee9435dd17 1053 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
EricLew 0:3eee9435dd17 1054
EricLew 0:3eee9435dd17 1055 /* TPI TRIGGER Register Definitions */
EricLew 0:3eee9435dd17 1056 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
EricLew 0:3eee9435dd17 1057 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
EricLew 0:3eee9435dd17 1058
EricLew 0:3eee9435dd17 1059 /* TPI Integration ETM Data Register Definitions (FIFO0) */
EricLew 0:3eee9435dd17 1060 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
EricLew 0:3eee9435dd17 1061 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
EricLew 0:3eee9435dd17 1062
EricLew 0:3eee9435dd17 1063 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
EricLew 0:3eee9435dd17 1064 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
EricLew 0:3eee9435dd17 1065
EricLew 0:3eee9435dd17 1066 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
EricLew 0:3eee9435dd17 1067 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
EricLew 0:3eee9435dd17 1068
EricLew 0:3eee9435dd17 1069 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
EricLew 0:3eee9435dd17 1070 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
EricLew 0:3eee9435dd17 1071
EricLew 0:3eee9435dd17 1072 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
EricLew 0:3eee9435dd17 1073 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
EricLew 0:3eee9435dd17 1074
EricLew 0:3eee9435dd17 1075 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
EricLew 0:3eee9435dd17 1076 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
EricLew 0:3eee9435dd17 1077
EricLew 0:3eee9435dd17 1078 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
EricLew 0:3eee9435dd17 1079 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
EricLew 0:3eee9435dd17 1080
EricLew 0:3eee9435dd17 1081 /* TPI ITATBCTR2 Register Definitions */
EricLew 0:3eee9435dd17 1082 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
EricLew 0:3eee9435dd17 1083 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
EricLew 0:3eee9435dd17 1084
EricLew 0:3eee9435dd17 1085 /* TPI Integration ITM Data Register Definitions (FIFO1) */
EricLew 0:3eee9435dd17 1086 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
EricLew 0:3eee9435dd17 1087 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
EricLew 0:3eee9435dd17 1088
EricLew 0:3eee9435dd17 1089 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
EricLew 0:3eee9435dd17 1090 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
EricLew 0:3eee9435dd17 1091
EricLew 0:3eee9435dd17 1092 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
EricLew 0:3eee9435dd17 1093 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
EricLew 0:3eee9435dd17 1094
EricLew 0:3eee9435dd17 1095 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
EricLew 0:3eee9435dd17 1096 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
EricLew 0:3eee9435dd17 1097
EricLew 0:3eee9435dd17 1098 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
EricLew 0:3eee9435dd17 1099 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
EricLew 0:3eee9435dd17 1100
EricLew 0:3eee9435dd17 1101 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
EricLew 0:3eee9435dd17 1102 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
EricLew 0:3eee9435dd17 1103
EricLew 0:3eee9435dd17 1104 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
EricLew 0:3eee9435dd17 1105 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
EricLew 0:3eee9435dd17 1106
EricLew 0:3eee9435dd17 1107 /* TPI ITATBCTR0 Register Definitions */
EricLew 0:3eee9435dd17 1108 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
EricLew 0:3eee9435dd17 1109 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
EricLew 0:3eee9435dd17 1110
EricLew 0:3eee9435dd17 1111 /* TPI Integration Mode Control Register Definitions */
EricLew 0:3eee9435dd17 1112 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
EricLew 0:3eee9435dd17 1113 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
EricLew 0:3eee9435dd17 1114
EricLew 0:3eee9435dd17 1115 /* TPI DEVID Register Definitions */
EricLew 0:3eee9435dd17 1116 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
EricLew 0:3eee9435dd17 1117 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
EricLew 0:3eee9435dd17 1118
EricLew 0:3eee9435dd17 1119 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
EricLew 0:3eee9435dd17 1120 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
EricLew 0:3eee9435dd17 1121
EricLew 0:3eee9435dd17 1122 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
EricLew 0:3eee9435dd17 1123 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
EricLew 0:3eee9435dd17 1124
EricLew 0:3eee9435dd17 1125 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
EricLew 0:3eee9435dd17 1126 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
EricLew 0:3eee9435dd17 1127
EricLew 0:3eee9435dd17 1128 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
EricLew 0:3eee9435dd17 1129 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
EricLew 0:3eee9435dd17 1130
EricLew 0:3eee9435dd17 1131 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
EricLew 0:3eee9435dd17 1132 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
EricLew 0:3eee9435dd17 1133
EricLew 0:3eee9435dd17 1134 /* TPI DEVTYPE Register Definitions */
EricLew 0:3eee9435dd17 1135 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
EricLew 0:3eee9435dd17 1136 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
EricLew 0:3eee9435dd17 1137
EricLew 0:3eee9435dd17 1138 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
EricLew 0:3eee9435dd17 1139 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
EricLew 0:3eee9435dd17 1140
EricLew 0:3eee9435dd17 1141 /*@}*/ /* end of group CMSIS_TPI */
EricLew 0:3eee9435dd17 1142
EricLew 0:3eee9435dd17 1143
EricLew 0:3eee9435dd17 1144 #if (__MPU_PRESENT == 1)
EricLew 0:3eee9435dd17 1145 /** \ingroup CMSIS_core_register
EricLew 0:3eee9435dd17 1146 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
EricLew 0:3eee9435dd17 1147 \brief Type definitions for the Memory Protection Unit (MPU)
EricLew 0:3eee9435dd17 1148 @{
EricLew 0:3eee9435dd17 1149 */
EricLew 0:3eee9435dd17 1150
EricLew 0:3eee9435dd17 1151 /** \brief Structure type to access the Memory Protection Unit (MPU).
EricLew 0:3eee9435dd17 1152 */
EricLew 0:3eee9435dd17 1153 typedef struct
EricLew 0:3eee9435dd17 1154 {
EricLew 0:3eee9435dd17 1155 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
EricLew 0:3eee9435dd17 1156 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
EricLew 0:3eee9435dd17 1157 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
EricLew 0:3eee9435dd17 1158 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
EricLew 0:3eee9435dd17 1159 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
EricLew 0:3eee9435dd17 1160 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
EricLew 0:3eee9435dd17 1161 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
EricLew 0:3eee9435dd17 1162 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
EricLew 0:3eee9435dd17 1163 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
EricLew 0:3eee9435dd17 1164 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
EricLew 0:3eee9435dd17 1165 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
EricLew 0:3eee9435dd17 1166 } MPU_Type;
EricLew 0:3eee9435dd17 1167
EricLew 0:3eee9435dd17 1168 /* MPU Type Register */
EricLew 0:3eee9435dd17 1169 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
EricLew 0:3eee9435dd17 1170 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
EricLew 0:3eee9435dd17 1171
EricLew 0:3eee9435dd17 1172 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
EricLew 0:3eee9435dd17 1173 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
EricLew 0:3eee9435dd17 1174
EricLew 0:3eee9435dd17 1175 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
EricLew 0:3eee9435dd17 1176 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
EricLew 0:3eee9435dd17 1177
EricLew 0:3eee9435dd17 1178 /* MPU Control Register */
EricLew 0:3eee9435dd17 1179 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
EricLew 0:3eee9435dd17 1180 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
EricLew 0:3eee9435dd17 1181
EricLew 0:3eee9435dd17 1182 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
EricLew 0:3eee9435dd17 1183 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
EricLew 0:3eee9435dd17 1184
EricLew 0:3eee9435dd17 1185 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
EricLew 0:3eee9435dd17 1186 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
EricLew 0:3eee9435dd17 1187
EricLew 0:3eee9435dd17 1188 /* MPU Region Number Register */
EricLew 0:3eee9435dd17 1189 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
EricLew 0:3eee9435dd17 1190 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
EricLew 0:3eee9435dd17 1191
EricLew 0:3eee9435dd17 1192 /* MPU Region Base Address Register */
EricLew 0:3eee9435dd17 1193 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
EricLew 0:3eee9435dd17 1194 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
EricLew 0:3eee9435dd17 1195
EricLew 0:3eee9435dd17 1196 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
EricLew 0:3eee9435dd17 1197 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
EricLew 0:3eee9435dd17 1198
EricLew 0:3eee9435dd17 1199 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
EricLew 0:3eee9435dd17 1200 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
EricLew 0:3eee9435dd17 1201
EricLew 0:3eee9435dd17 1202 /* MPU Region Attribute and Size Register */
EricLew 0:3eee9435dd17 1203 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
EricLew 0:3eee9435dd17 1204 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
EricLew 0:3eee9435dd17 1205
EricLew 0:3eee9435dd17 1206 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
EricLew 0:3eee9435dd17 1207 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
EricLew 0:3eee9435dd17 1208
EricLew 0:3eee9435dd17 1209 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
EricLew 0:3eee9435dd17 1210 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
EricLew 0:3eee9435dd17 1211
EricLew 0:3eee9435dd17 1212 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
EricLew 0:3eee9435dd17 1213 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
EricLew 0:3eee9435dd17 1214
EricLew 0:3eee9435dd17 1215 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
EricLew 0:3eee9435dd17 1216 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
EricLew 0:3eee9435dd17 1217
EricLew 0:3eee9435dd17 1218 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
EricLew 0:3eee9435dd17 1219 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
EricLew 0:3eee9435dd17 1220
EricLew 0:3eee9435dd17 1221 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
EricLew 0:3eee9435dd17 1222 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
EricLew 0:3eee9435dd17 1223
EricLew 0:3eee9435dd17 1224 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
EricLew 0:3eee9435dd17 1225 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
EricLew 0:3eee9435dd17 1226
EricLew 0:3eee9435dd17 1227 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
EricLew 0:3eee9435dd17 1228 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
EricLew 0:3eee9435dd17 1229
EricLew 0:3eee9435dd17 1230 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
EricLew 0:3eee9435dd17 1231 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
EricLew 0:3eee9435dd17 1232
EricLew 0:3eee9435dd17 1233 /*@} end of group CMSIS_MPU */
EricLew 0:3eee9435dd17 1234 #endif
EricLew 0:3eee9435dd17 1235
EricLew 0:3eee9435dd17 1236
EricLew 0:3eee9435dd17 1237 #if (__FPU_PRESENT == 1)
EricLew 0:3eee9435dd17 1238 /** \ingroup CMSIS_core_register
EricLew 0:3eee9435dd17 1239 \defgroup CMSIS_FPU Floating Point Unit (FPU)
EricLew 0:3eee9435dd17 1240 \brief Type definitions for the Floating Point Unit (FPU)
EricLew 0:3eee9435dd17 1241 @{
EricLew 0:3eee9435dd17 1242 */
EricLew 0:3eee9435dd17 1243
EricLew 0:3eee9435dd17 1244 /** \brief Structure type to access the Floating Point Unit (FPU).
EricLew 0:3eee9435dd17 1245 */
EricLew 0:3eee9435dd17 1246 typedef struct
EricLew 0:3eee9435dd17 1247 {
EricLew 0:3eee9435dd17 1248 uint32_t RESERVED0[1];
EricLew 0:3eee9435dd17 1249 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
EricLew 0:3eee9435dd17 1250 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
EricLew 0:3eee9435dd17 1251 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
EricLew 0:3eee9435dd17 1252 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
EricLew 0:3eee9435dd17 1253 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
EricLew 0:3eee9435dd17 1254 } FPU_Type;
EricLew 0:3eee9435dd17 1255
EricLew 0:3eee9435dd17 1256 /* Floating-Point Context Control Register */
EricLew 0:3eee9435dd17 1257 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
EricLew 0:3eee9435dd17 1258 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
EricLew 0:3eee9435dd17 1259
EricLew 0:3eee9435dd17 1260 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
EricLew 0:3eee9435dd17 1261 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
EricLew 0:3eee9435dd17 1262
EricLew 0:3eee9435dd17 1263 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
EricLew 0:3eee9435dd17 1264 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
EricLew 0:3eee9435dd17 1265
EricLew 0:3eee9435dd17 1266 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
EricLew 0:3eee9435dd17 1267 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
EricLew 0:3eee9435dd17 1268
EricLew 0:3eee9435dd17 1269 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
EricLew 0:3eee9435dd17 1270 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
EricLew 0:3eee9435dd17 1271
EricLew 0:3eee9435dd17 1272 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
EricLew 0:3eee9435dd17 1273 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
EricLew 0:3eee9435dd17 1274
EricLew 0:3eee9435dd17 1275 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
EricLew 0:3eee9435dd17 1276 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
EricLew 0:3eee9435dd17 1277
EricLew 0:3eee9435dd17 1278 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
EricLew 0:3eee9435dd17 1279 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
EricLew 0:3eee9435dd17 1280
EricLew 0:3eee9435dd17 1281 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
EricLew 0:3eee9435dd17 1282 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
EricLew 0:3eee9435dd17 1283
EricLew 0:3eee9435dd17 1284 /* Floating-Point Context Address Register */
EricLew 0:3eee9435dd17 1285 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
EricLew 0:3eee9435dd17 1286 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
EricLew 0:3eee9435dd17 1287
EricLew 0:3eee9435dd17 1288 /* Floating-Point Default Status Control Register */
EricLew 0:3eee9435dd17 1289 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
EricLew 0:3eee9435dd17 1290 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
EricLew 0:3eee9435dd17 1291
EricLew 0:3eee9435dd17 1292 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
EricLew 0:3eee9435dd17 1293 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
EricLew 0:3eee9435dd17 1294
EricLew 0:3eee9435dd17 1295 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
EricLew 0:3eee9435dd17 1296 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
EricLew 0:3eee9435dd17 1297
EricLew 0:3eee9435dd17 1298 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
EricLew 0:3eee9435dd17 1299 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
EricLew 0:3eee9435dd17 1300
EricLew 0:3eee9435dd17 1301 /* Media and FP Feature Register 0 */
EricLew 0:3eee9435dd17 1302 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
EricLew 0:3eee9435dd17 1303 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
EricLew 0:3eee9435dd17 1304
EricLew 0:3eee9435dd17 1305 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
EricLew 0:3eee9435dd17 1306 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
EricLew 0:3eee9435dd17 1307
EricLew 0:3eee9435dd17 1308 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
EricLew 0:3eee9435dd17 1309 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
EricLew 0:3eee9435dd17 1310
EricLew 0:3eee9435dd17 1311 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
EricLew 0:3eee9435dd17 1312 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
EricLew 0:3eee9435dd17 1313
EricLew 0:3eee9435dd17 1314 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
EricLew 0:3eee9435dd17 1315 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
EricLew 0:3eee9435dd17 1316
EricLew 0:3eee9435dd17 1317 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
EricLew 0:3eee9435dd17 1318 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
EricLew 0:3eee9435dd17 1319
EricLew 0:3eee9435dd17 1320 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
EricLew 0:3eee9435dd17 1321 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
EricLew 0:3eee9435dd17 1322
EricLew 0:3eee9435dd17 1323 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
EricLew 0:3eee9435dd17 1324 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
EricLew 0:3eee9435dd17 1325
EricLew 0:3eee9435dd17 1326 /* Media and FP Feature Register 1 */
EricLew 0:3eee9435dd17 1327 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
EricLew 0:3eee9435dd17 1328 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
EricLew 0:3eee9435dd17 1329
EricLew 0:3eee9435dd17 1330 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
EricLew 0:3eee9435dd17 1331 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
EricLew 0:3eee9435dd17 1332
EricLew 0:3eee9435dd17 1333 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
EricLew 0:3eee9435dd17 1334 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
EricLew 0:3eee9435dd17 1335
EricLew 0:3eee9435dd17 1336 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
EricLew 0:3eee9435dd17 1337 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
EricLew 0:3eee9435dd17 1338
EricLew 0:3eee9435dd17 1339 /*@} end of group CMSIS_FPU */
EricLew 0:3eee9435dd17 1340 #endif
EricLew 0:3eee9435dd17 1341
EricLew 0:3eee9435dd17 1342
EricLew 0:3eee9435dd17 1343 /** \ingroup CMSIS_core_register
EricLew 0:3eee9435dd17 1344 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
EricLew 0:3eee9435dd17 1345 \brief Type definitions for the Core Debug Registers
EricLew 0:3eee9435dd17 1346 @{
EricLew 0:3eee9435dd17 1347 */
EricLew 0:3eee9435dd17 1348
EricLew 0:3eee9435dd17 1349 /** \brief Structure type to access the Core Debug Register (CoreDebug).
EricLew 0:3eee9435dd17 1350 */
EricLew 0:3eee9435dd17 1351 typedef struct
EricLew 0:3eee9435dd17 1352 {
EricLew 0:3eee9435dd17 1353 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
EricLew 0:3eee9435dd17 1354 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
EricLew 0:3eee9435dd17 1355 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
EricLew 0:3eee9435dd17 1356 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
EricLew 0:3eee9435dd17 1357 } CoreDebug_Type;
EricLew 0:3eee9435dd17 1358
EricLew 0:3eee9435dd17 1359 /* Debug Halting Control and Status Register */
EricLew 0:3eee9435dd17 1360 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
EricLew 0:3eee9435dd17 1361 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
EricLew 0:3eee9435dd17 1362
EricLew 0:3eee9435dd17 1363 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
EricLew 0:3eee9435dd17 1364 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
EricLew 0:3eee9435dd17 1365
EricLew 0:3eee9435dd17 1366 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
EricLew 0:3eee9435dd17 1367 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
EricLew 0:3eee9435dd17 1368
EricLew 0:3eee9435dd17 1369 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
EricLew 0:3eee9435dd17 1370 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
EricLew 0:3eee9435dd17 1371
EricLew 0:3eee9435dd17 1372 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
EricLew 0:3eee9435dd17 1373 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
EricLew 0:3eee9435dd17 1374
EricLew 0:3eee9435dd17 1375 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
EricLew 0:3eee9435dd17 1376 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
EricLew 0:3eee9435dd17 1377
EricLew 0:3eee9435dd17 1378 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
EricLew 0:3eee9435dd17 1379 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
EricLew 0:3eee9435dd17 1380
EricLew 0:3eee9435dd17 1381 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
EricLew 0:3eee9435dd17 1382 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
EricLew 0:3eee9435dd17 1383
EricLew 0:3eee9435dd17 1384 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
EricLew 0:3eee9435dd17 1385 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
EricLew 0:3eee9435dd17 1386
EricLew 0:3eee9435dd17 1387 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
EricLew 0:3eee9435dd17 1388 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
EricLew 0:3eee9435dd17 1389
EricLew 0:3eee9435dd17 1390 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
EricLew 0:3eee9435dd17 1391 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
EricLew 0:3eee9435dd17 1392
EricLew 0:3eee9435dd17 1393 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
EricLew 0:3eee9435dd17 1394 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
EricLew 0:3eee9435dd17 1395
EricLew 0:3eee9435dd17 1396 /* Debug Core Register Selector Register */
EricLew 0:3eee9435dd17 1397 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
EricLew 0:3eee9435dd17 1398 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
EricLew 0:3eee9435dd17 1399
EricLew 0:3eee9435dd17 1400 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
EricLew 0:3eee9435dd17 1401 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
EricLew 0:3eee9435dd17 1402
EricLew 0:3eee9435dd17 1403 /* Debug Exception and Monitor Control Register */
EricLew 0:3eee9435dd17 1404 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
EricLew 0:3eee9435dd17 1405 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
EricLew 0:3eee9435dd17 1406
EricLew 0:3eee9435dd17 1407 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
EricLew 0:3eee9435dd17 1408 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
EricLew 0:3eee9435dd17 1409
EricLew 0:3eee9435dd17 1410 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
EricLew 0:3eee9435dd17 1411 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
EricLew 0:3eee9435dd17 1412
EricLew 0:3eee9435dd17 1413 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
EricLew 0:3eee9435dd17 1414 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
EricLew 0:3eee9435dd17 1415
EricLew 0:3eee9435dd17 1416 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
EricLew 0:3eee9435dd17 1417 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
EricLew 0:3eee9435dd17 1418
EricLew 0:3eee9435dd17 1419 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
EricLew 0:3eee9435dd17 1420 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
EricLew 0:3eee9435dd17 1421
EricLew 0:3eee9435dd17 1422 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
EricLew 0:3eee9435dd17 1423 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
EricLew 0:3eee9435dd17 1424
EricLew 0:3eee9435dd17 1425 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
EricLew 0:3eee9435dd17 1426 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
EricLew 0:3eee9435dd17 1427
EricLew 0:3eee9435dd17 1428 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
EricLew 0:3eee9435dd17 1429 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
EricLew 0:3eee9435dd17 1430
EricLew 0:3eee9435dd17 1431 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
EricLew 0:3eee9435dd17 1432 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
EricLew 0:3eee9435dd17 1433
EricLew 0:3eee9435dd17 1434 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
EricLew 0:3eee9435dd17 1435 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
EricLew 0:3eee9435dd17 1436
EricLew 0:3eee9435dd17 1437 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
EricLew 0:3eee9435dd17 1438 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
EricLew 0:3eee9435dd17 1439
EricLew 0:3eee9435dd17 1440 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
EricLew 0:3eee9435dd17 1441 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
EricLew 0:3eee9435dd17 1442
EricLew 0:3eee9435dd17 1443 /*@} end of group CMSIS_CoreDebug */
EricLew 0:3eee9435dd17 1444
EricLew 0:3eee9435dd17 1445
EricLew 0:3eee9435dd17 1446 /** \ingroup CMSIS_core_register
EricLew 0:3eee9435dd17 1447 \defgroup CMSIS_core_base Core Definitions
EricLew 0:3eee9435dd17 1448 \brief Definitions for base addresses, unions, and structures.
EricLew 0:3eee9435dd17 1449 @{
EricLew 0:3eee9435dd17 1450 */
EricLew 0:3eee9435dd17 1451
EricLew 0:3eee9435dd17 1452 /* Memory mapping of Cortex-M4 Hardware */
EricLew 0:3eee9435dd17 1453 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
EricLew 0:3eee9435dd17 1454 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
EricLew 0:3eee9435dd17 1455 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
EricLew 0:3eee9435dd17 1456 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
EricLew 0:3eee9435dd17 1457 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
EricLew 0:3eee9435dd17 1458 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
EricLew 0:3eee9435dd17 1459 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
EricLew 0:3eee9435dd17 1460 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
EricLew 0:3eee9435dd17 1461
EricLew 0:3eee9435dd17 1462 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
EricLew 0:3eee9435dd17 1463 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
EricLew 0:3eee9435dd17 1464 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
EricLew 0:3eee9435dd17 1465 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
EricLew 0:3eee9435dd17 1466 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
EricLew 0:3eee9435dd17 1467 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
EricLew 0:3eee9435dd17 1468 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
EricLew 0:3eee9435dd17 1469 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
EricLew 0:3eee9435dd17 1470
EricLew 0:3eee9435dd17 1471 #if (__MPU_PRESENT == 1)
EricLew 0:3eee9435dd17 1472 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
EricLew 0:3eee9435dd17 1473 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
EricLew 0:3eee9435dd17 1474 #endif
EricLew 0:3eee9435dd17 1475
EricLew 0:3eee9435dd17 1476 #if (__FPU_PRESENT == 1)
EricLew 0:3eee9435dd17 1477 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
EricLew 0:3eee9435dd17 1478 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
EricLew 0:3eee9435dd17 1479 #endif
EricLew 0:3eee9435dd17 1480
EricLew 0:3eee9435dd17 1481 /*@} */
EricLew 0:3eee9435dd17 1482
EricLew 0:3eee9435dd17 1483
EricLew 0:3eee9435dd17 1484
EricLew 0:3eee9435dd17 1485 /*******************************************************************************
EricLew 0:3eee9435dd17 1486 * Hardware Abstraction Layer
EricLew 0:3eee9435dd17 1487 Core Function Interface contains:
EricLew 0:3eee9435dd17 1488 - Core NVIC Functions
EricLew 0:3eee9435dd17 1489 - Core SysTick Functions
EricLew 0:3eee9435dd17 1490 - Core Debug Functions
EricLew 0:3eee9435dd17 1491 - Core Register Access Functions
EricLew 0:3eee9435dd17 1492 ******************************************************************************/
EricLew 0:3eee9435dd17 1493 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
EricLew 0:3eee9435dd17 1494 */
EricLew 0:3eee9435dd17 1495
EricLew 0:3eee9435dd17 1496
EricLew 0:3eee9435dd17 1497
EricLew 0:3eee9435dd17 1498 /* ########################## NVIC functions #################################### */
EricLew 0:3eee9435dd17 1499 /** \ingroup CMSIS_Core_FunctionInterface
EricLew 0:3eee9435dd17 1500 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
EricLew 0:3eee9435dd17 1501 \brief Functions that manage interrupts and exceptions via the NVIC.
EricLew 0:3eee9435dd17 1502 @{
EricLew 0:3eee9435dd17 1503 */
EricLew 0:3eee9435dd17 1504
EricLew 0:3eee9435dd17 1505 /** \brief Set Priority Grouping
EricLew 0:3eee9435dd17 1506
EricLew 0:3eee9435dd17 1507 The function sets the priority grouping field using the required unlock sequence.
EricLew 0:3eee9435dd17 1508 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
EricLew 0:3eee9435dd17 1509 Only values from 0..7 are used.
EricLew 0:3eee9435dd17 1510 In case of a conflict between priority grouping and available
EricLew 0:3eee9435dd17 1511 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
EricLew 0:3eee9435dd17 1512
EricLew 0:3eee9435dd17 1513 \param [in] PriorityGroup Priority grouping field.
EricLew 0:3eee9435dd17 1514 */
EricLew 0:3eee9435dd17 1515 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
EricLew 0:3eee9435dd17 1516 {
EricLew 0:3eee9435dd17 1517 uint32_t reg_value;
EricLew 0:3eee9435dd17 1518 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
EricLew 0:3eee9435dd17 1519
EricLew 0:3eee9435dd17 1520 reg_value = SCB->AIRCR; /* read old register configuration */
EricLew 0:3eee9435dd17 1521 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
EricLew 0:3eee9435dd17 1522 reg_value = (reg_value |
EricLew 0:3eee9435dd17 1523 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
EricLew 0:3eee9435dd17 1524 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
EricLew 0:3eee9435dd17 1525 SCB->AIRCR = reg_value;
EricLew 0:3eee9435dd17 1526 }
EricLew 0:3eee9435dd17 1527
EricLew 0:3eee9435dd17 1528
EricLew 0:3eee9435dd17 1529 /** \brief Get Priority Grouping
EricLew 0:3eee9435dd17 1530
EricLew 0:3eee9435dd17 1531 The function reads the priority grouping field from the NVIC Interrupt Controller.
EricLew 0:3eee9435dd17 1532
EricLew 0:3eee9435dd17 1533 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
EricLew 0:3eee9435dd17 1534 */
EricLew 0:3eee9435dd17 1535 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
EricLew 0:3eee9435dd17 1536 {
EricLew 0:3eee9435dd17 1537 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
EricLew 0:3eee9435dd17 1538 }
EricLew 0:3eee9435dd17 1539
EricLew 0:3eee9435dd17 1540
EricLew 0:3eee9435dd17 1541 /** \brief Enable External Interrupt
EricLew 0:3eee9435dd17 1542
EricLew 0:3eee9435dd17 1543 The function enables a device-specific interrupt in the NVIC interrupt controller.
EricLew 0:3eee9435dd17 1544
EricLew 0:3eee9435dd17 1545 \param [in] IRQn External interrupt number. Value cannot be negative.
EricLew 0:3eee9435dd17 1546 */
EricLew 0:3eee9435dd17 1547 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
EricLew 0:3eee9435dd17 1548 {
EricLew 0:3eee9435dd17 1549 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
EricLew 0:3eee9435dd17 1550 }
EricLew 0:3eee9435dd17 1551
EricLew 0:3eee9435dd17 1552
EricLew 0:3eee9435dd17 1553 /** \brief Disable External Interrupt
EricLew 0:3eee9435dd17 1554
EricLew 0:3eee9435dd17 1555 The function disables a device-specific interrupt in the NVIC interrupt controller.
EricLew 0:3eee9435dd17 1556
EricLew 0:3eee9435dd17 1557 \param [in] IRQn External interrupt number. Value cannot be negative.
EricLew 0:3eee9435dd17 1558 */
EricLew 0:3eee9435dd17 1559 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
EricLew 0:3eee9435dd17 1560 {
EricLew 0:3eee9435dd17 1561 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
EricLew 0:3eee9435dd17 1562 }
EricLew 0:3eee9435dd17 1563
EricLew 0:3eee9435dd17 1564
EricLew 0:3eee9435dd17 1565 /** \brief Get Pending Interrupt
EricLew 0:3eee9435dd17 1566
EricLew 0:3eee9435dd17 1567 The function reads the pending register in the NVIC and returns the pending bit
EricLew 0:3eee9435dd17 1568 for the specified interrupt.
EricLew 0:3eee9435dd17 1569
EricLew 0:3eee9435dd17 1570 \param [in] IRQn Interrupt number.
EricLew 0:3eee9435dd17 1571
EricLew 0:3eee9435dd17 1572 \return 0 Interrupt status is not pending.
EricLew 0:3eee9435dd17 1573 \return 1 Interrupt status is pending.
EricLew 0:3eee9435dd17 1574 */
EricLew 0:3eee9435dd17 1575 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
EricLew 0:3eee9435dd17 1576 {
EricLew 0:3eee9435dd17 1577 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
EricLew 0:3eee9435dd17 1578 }
EricLew 0:3eee9435dd17 1579
EricLew 0:3eee9435dd17 1580
EricLew 0:3eee9435dd17 1581 /** \brief Set Pending Interrupt
EricLew 0:3eee9435dd17 1582
EricLew 0:3eee9435dd17 1583 The function sets the pending bit of an external interrupt.
EricLew 0:3eee9435dd17 1584
EricLew 0:3eee9435dd17 1585 \param [in] IRQn Interrupt number. Value cannot be negative.
EricLew 0:3eee9435dd17 1586 */
EricLew 0:3eee9435dd17 1587 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
EricLew 0:3eee9435dd17 1588 {
EricLew 0:3eee9435dd17 1589 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
EricLew 0:3eee9435dd17 1590 }
EricLew 0:3eee9435dd17 1591
EricLew 0:3eee9435dd17 1592
EricLew 0:3eee9435dd17 1593 /** \brief Clear Pending Interrupt
EricLew 0:3eee9435dd17 1594
EricLew 0:3eee9435dd17 1595 The function clears the pending bit of an external interrupt.
EricLew 0:3eee9435dd17 1596
EricLew 0:3eee9435dd17 1597 \param [in] IRQn External interrupt number. Value cannot be negative.
EricLew 0:3eee9435dd17 1598 */
EricLew 0:3eee9435dd17 1599 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
EricLew 0:3eee9435dd17 1600 {
EricLew 0:3eee9435dd17 1601 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
EricLew 0:3eee9435dd17 1602 }
EricLew 0:3eee9435dd17 1603
EricLew 0:3eee9435dd17 1604
EricLew 0:3eee9435dd17 1605 /** \brief Get Active Interrupt
EricLew 0:3eee9435dd17 1606
EricLew 0:3eee9435dd17 1607 The function reads the active register in NVIC and returns the active bit.
EricLew 0:3eee9435dd17 1608
EricLew 0:3eee9435dd17 1609 \param [in] IRQn Interrupt number.
EricLew 0:3eee9435dd17 1610
EricLew 0:3eee9435dd17 1611 \return 0 Interrupt status is not active.
EricLew 0:3eee9435dd17 1612 \return 1 Interrupt status is active.
EricLew 0:3eee9435dd17 1613 */
EricLew 0:3eee9435dd17 1614 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
EricLew 0:3eee9435dd17 1615 {
EricLew 0:3eee9435dd17 1616 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
EricLew 0:3eee9435dd17 1617 }
EricLew 0:3eee9435dd17 1618
EricLew 0:3eee9435dd17 1619
EricLew 0:3eee9435dd17 1620 /** \brief Set Interrupt Priority
EricLew 0:3eee9435dd17 1621
EricLew 0:3eee9435dd17 1622 The function sets the priority of an interrupt.
EricLew 0:3eee9435dd17 1623
EricLew 0:3eee9435dd17 1624 \note The priority cannot be set for every core interrupt.
EricLew 0:3eee9435dd17 1625
EricLew 0:3eee9435dd17 1626 \param [in] IRQn Interrupt number.
EricLew 0:3eee9435dd17 1627 \param [in] priority Priority to set.
EricLew 0:3eee9435dd17 1628 */
EricLew 0:3eee9435dd17 1629 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
EricLew 0:3eee9435dd17 1630 {
EricLew 0:3eee9435dd17 1631 if((int32_t)IRQn < 0) {
EricLew 0:3eee9435dd17 1632 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
EricLew 0:3eee9435dd17 1633 }
EricLew 0:3eee9435dd17 1634 else {
EricLew 0:3eee9435dd17 1635 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
EricLew 0:3eee9435dd17 1636 }
EricLew 0:3eee9435dd17 1637 }
EricLew 0:3eee9435dd17 1638
EricLew 0:3eee9435dd17 1639
EricLew 0:3eee9435dd17 1640 /** \brief Get Interrupt Priority
EricLew 0:3eee9435dd17 1641
EricLew 0:3eee9435dd17 1642 The function reads the priority of an interrupt. The interrupt
EricLew 0:3eee9435dd17 1643 number can be positive to specify an external (device specific)
EricLew 0:3eee9435dd17 1644 interrupt, or negative to specify an internal (core) interrupt.
EricLew 0:3eee9435dd17 1645
EricLew 0:3eee9435dd17 1646
EricLew 0:3eee9435dd17 1647 \param [in] IRQn Interrupt number.
EricLew 0:3eee9435dd17 1648 \return Interrupt Priority. Value is aligned automatically to the implemented
EricLew 0:3eee9435dd17 1649 priority bits of the microcontroller.
EricLew 0:3eee9435dd17 1650 */
EricLew 0:3eee9435dd17 1651 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
EricLew 0:3eee9435dd17 1652 {
EricLew 0:3eee9435dd17 1653
EricLew 0:3eee9435dd17 1654 if((int32_t)IRQn < 0) {
EricLew 0:3eee9435dd17 1655 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
EricLew 0:3eee9435dd17 1656 }
EricLew 0:3eee9435dd17 1657 else {
EricLew 0:3eee9435dd17 1658 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
EricLew 0:3eee9435dd17 1659 }
EricLew 0:3eee9435dd17 1660 }
EricLew 0:3eee9435dd17 1661
EricLew 0:3eee9435dd17 1662
EricLew 0:3eee9435dd17 1663 /** \brief Encode Priority
EricLew 0:3eee9435dd17 1664
EricLew 0:3eee9435dd17 1665 The function encodes the priority for an interrupt with the given priority group,
EricLew 0:3eee9435dd17 1666 preemptive priority value, and subpriority value.
EricLew 0:3eee9435dd17 1667 In case of a conflict between priority grouping and available
EricLew 0:3eee9435dd17 1668 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
EricLew 0:3eee9435dd17 1669
EricLew 0:3eee9435dd17 1670 \param [in] PriorityGroup Used priority group.
EricLew 0:3eee9435dd17 1671 \param [in] PreemptPriority Preemptive priority value (starting from 0).
EricLew 0:3eee9435dd17 1672 \param [in] SubPriority Subpriority value (starting from 0).
EricLew 0:3eee9435dd17 1673 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
EricLew 0:3eee9435dd17 1674 */
EricLew 0:3eee9435dd17 1675 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
EricLew 0:3eee9435dd17 1676 {
EricLew 0:3eee9435dd17 1677 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
EricLew 0:3eee9435dd17 1678 uint32_t PreemptPriorityBits;
EricLew 0:3eee9435dd17 1679 uint32_t SubPriorityBits;
EricLew 0:3eee9435dd17 1680
EricLew 0:3eee9435dd17 1681 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
EricLew 0:3eee9435dd17 1682 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
EricLew 0:3eee9435dd17 1683
EricLew 0:3eee9435dd17 1684 return (
EricLew 0:3eee9435dd17 1685 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
EricLew 0:3eee9435dd17 1686 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
EricLew 0:3eee9435dd17 1687 );
EricLew 0:3eee9435dd17 1688 }
EricLew 0:3eee9435dd17 1689
EricLew 0:3eee9435dd17 1690
EricLew 0:3eee9435dd17 1691 /** \brief Decode Priority
EricLew 0:3eee9435dd17 1692
EricLew 0:3eee9435dd17 1693 The function decodes an interrupt priority value with a given priority group to
EricLew 0:3eee9435dd17 1694 preemptive priority value and subpriority value.
EricLew 0:3eee9435dd17 1695 In case of a conflict between priority grouping and available
EricLew 0:3eee9435dd17 1696 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
EricLew 0:3eee9435dd17 1697
EricLew 0:3eee9435dd17 1698 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
EricLew 0:3eee9435dd17 1699 \param [in] PriorityGroup Used priority group.
EricLew 0:3eee9435dd17 1700 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
EricLew 0:3eee9435dd17 1701 \param [out] pSubPriority Subpriority value (starting from 0).
EricLew 0:3eee9435dd17 1702 */
EricLew 0:3eee9435dd17 1703 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
EricLew 0:3eee9435dd17 1704 {
EricLew 0:3eee9435dd17 1705 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
EricLew 0:3eee9435dd17 1706 uint32_t PreemptPriorityBits;
EricLew 0:3eee9435dd17 1707 uint32_t SubPriorityBits;
EricLew 0:3eee9435dd17 1708
EricLew 0:3eee9435dd17 1709 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
EricLew 0:3eee9435dd17 1710 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
EricLew 0:3eee9435dd17 1711
EricLew 0:3eee9435dd17 1712 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
EricLew 0:3eee9435dd17 1713 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
EricLew 0:3eee9435dd17 1714 }
EricLew 0:3eee9435dd17 1715
EricLew 0:3eee9435dd17 1716
EricLew 0:3eee9435dd17 1717 /** \brief System Reset
EricLew 0:3eee9435dd17 1718
EricLew 0:3eee9435dd17 1719 The function initiates a system reset request to reset the MCU.
EricLew 0:3eee9435dd17 1720 */
EricLew 0:3eee9435dd17 1721 __STATIC_INLINE void NVIC_SystemReset(void)
EricLew 0:3eee9435dd17 1722 {
EricLew 0:3eee9435dd17 1723 __DSB(); /* Ensure all outstanding memory accesses included
EricLew 0:3eee9435dd17 1724 buffered write are completed before reset */
EricLew 0:3eee9435dd17 1725 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
EricLew 0:3eee9435dd17 1726 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
EricLew 0:3eee9435dd17 1727 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
EricLew 0:3eee9435dd17 1728 __DSB(); /* Ensure completion of memory access */
EricLew 0:3eee9435dd17 1729 while(1) { __NOP(); } /* wait until reset */
EricLew 0:3eee9435dd17 1730 }
EricLew 0:3eee9435dd17 1731
EricLew 0:3eee9435dd17 1732 /*@} end of CMSIS_Core_NVICFunctions */
EricLew 0:3eee9435dd17 1733
EricLew 0:3eee9435dd17 1734
EricLew 0:3eee9435dd17 1735
EricLew 0:3eee9435dd17 1736 /* ################################## SysTick function ############################################ */
EricLew 0:3eee9435dd17 1737 /** \ingroup CMSIS_Core_FunctionInterface
EricLew 0:3eee9435dd17 1738 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
EricLew 0:3eee9435dd17 1739 \brief Functions that configure the System.
EricLew 0:3eee9435dd17 1740 @{
EricLew 0:3eee9435dd17 1741 */
EricLew 0:3eee9435dd17 1742
EricLew 0:3eee9435dd17 1743 #if (__Vendor_SysTickConfig == 0)
EricLew 0:3eee9435dd17 1744
EricLew 0:3eee9435dd17 1745 /** \brief System Tick Configuration
EricLew 0:3eee9435dd17 1746
EricLew 0:3eee9435dd17 1747 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
EricLew 0:3eee9435dd17 1748 Counter is in free running mode to generate periodic interrupts.
EricLew 0:3eee9435dd17 1749
EricLew 0:3eee9435dd17 1750 \param [in] ticks Number of ticks between two interrupts.
EricLew 0:3eee9435dd17 1751
EricLew 0:3eee9435dd17 1752 \return 0 Function succeeded.
EricLew 0:3eee9435dd17 1753 \return 1 Function failed.
EricLew 0:3eee9435dd17 1754
EricLew 0:3eee9435dd17 1755 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
EricLew 0:3eee9435dd17 1756 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
EricLew 0:3eee9435dd17 1757 must contain a vendor-specific implementation of this function.
EricLew 0:3eee9435dd17 1758
EricLew 0:3eee9435dd17 1759 */
EricLew 0:3eee9435dd17 1760 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
EricLew 0:3eee9435dd17 1761 {
EricLew 0:3eee9435dd17 1762 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
EricLew 0:3eee9435dd17 1763
EricLew 0:3eee9435dd17 1764 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
EricLew 0:3eee9435dd17 1765 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
EricLew 0:3eee9435dd17 1766 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
EricLew 0:3eee9435dd17 1767 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
EricLew 0:3eee9435dd17 1768 SysTick_CTRL_TICKINT_Msk |
EricLew 0:3eee9435dd17 1769 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
EricLew 0:3eee9435dd17 1770 return (0UL); /* Function successful */
EricLew 0:3eee9435dd17 1771 }
EricLew 0:3eee9435dd17 1772
EricLew 0:3eee9435dd17 1773 #endif
EricLew 0:3eee9435dd17 1774
EricLew 0:3eee9435dd17 1775 /*@} end of CMSIS_Core_SysTickFunctions */
EricLew 0:3eee9435dd17 1776
EricLew 0:3eee9435dd17 1777
EricLew 0:3eee9435dd17 1778
EricLew 0:3eee9435dd17 1779 /* ##################################### Debug In/Output function ########################################### */
EricLew 0:3eee9435dd17 1780 /** \ingroup CMSIS_Core_FunctionInterface
EricLew 0:3eee9435dd17 1781 \defgroup CMSIS_core_DebugFunctions ITM Functions
EricLew 0:3eee9435dd17 1782 \brief Functions that access the ITM debug interface.
EricLew 0:3eee9435dd17 1783 @{
EricLew 0:3eee9435dd17 1784 */
EricLew 0:3eee9435dd17 1785
EricLew 0:3eee9435dd17 1786 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
EricLew 0:3eee9435dd17 1787 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
EricLew 0:3eee9435dd17 1788
EricLew 0:3eee9435dd17 1789
EricLew 0:3eee9435dd17 1790 /** \brief ITM Send Character
EricLew 0:3eee9435dd17 1791
EricLew 0:3eee9435dd17 1792 The function transmits a character via the ITM channel 0, and
EricLew 0:3eee9435dd17 1793 \li Just returns when no debugger is connected that has booked the output.
EricLew 0:3eee9435dd17 1794 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
EricLew 0:3eee9435dd17 1795
EricLew 0:3eee9435dd17 1796 \param [in] ch Character to transmit.
EricLew 0:3eee9435dd17 1797
EricLew 0:3eee9435dd17 1798 \returns Character to transmit.
EricLew 0:3eee9435dd17 1799 */
EricLew 0:3eee9435dd17 1800 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
EricLew 0:3eee9435dd17 1801 {
EricLew 0:3eee9435dd17 1802 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
EricLew 0:3eee9435dd17 1803 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
EricLew 0:3eee9435dd17 1804 {
EricLew 0:3eee9435dd17 1805 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
EricLew 0:3eee9435dd17 1806 ITM->PORT[0].u8 = (uint8_t)ch;
EricLew 0:3eee9435dd17 1807 }
EricLew 0:3eee9435dd17 1808 return (ch);
EricLew 0:3eee9435dd17 1809 }
EricLew 0:3eee9435dd17 1810
EricLew 0:3eee9435dd17 1811
EricLew 0:3eee9435dd17 1812 /** \brief ITM Receive Character
EricLew 0:3eee9435dd17 1813
EricLew 0:3eee9435dd17 1814 The function inputs a character via the external variable \ref ITM_RxBuffer.
EricLew 0:3eee9435dd17 1815
EricLew 0:3eee9435dd17 1816 \return Received character.
EricLew 0:3eee9435dd17 1817 \return -1 No character pending.
EricLew 0:3eee9435dd17 1818 */
EricLew 0:3eee9435dd17 1819 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
EricLew 0:3eee9435dd17 1820 int32_t ch = -1; /* no character available */
EricLew 0:3eee9435dd17 1821
EricLew 0:3eee9435dd17 1822 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
EricLew 0:3eee9435dd17 1823 ch = ITM_RxBuffer;
EricLew 0:3eee9435dd17 1824 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
EricLew 0:3eee9435dd17 1825 }
EricLew 0:3eee9435dd17 1826
EricLew 0:3eee9435dd17 1827 return (ch);
EricLew 0:3eee9435dd17 1828 }
EricLew 0:3eee9435dd17 1829
EricLew 0:3eee9435dd17 1830
EricLew 0:3eee9435dd17 1831 /** \brief ITM Check Character
EricLew 0:3eee9435dd17 1832
EricLew 0:3eee9435dd17 1833 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
EricLew 0:3eee9435dd17 1834
EricLew 0:3eee9435dd17 1835 \return 0 No character available.
EricLew 0:3eee9435dd17 1836 \return 1 Character available.
EricLew 0:3eee9435dd17 1837 */
EricLew 0:3eee9435dd17 1838 __STATIC_INLINE int32_t ITM_CheckChar (void) {
EricLew 0:3eee9435dd17 1839
EricLew 0:3eee9435dd17 1840 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
EricLew 0:3eee9435dd17 1841 return (0); /* no character available */
EricLew 0:3eee9435dd17 1842 } else {
EricLew 0:3eee9435dd17 1843 return (1); /* character available */
EricLew 0:3eee9435dd17 1844 }
EricLew 0:3eee9435dd17 1845 }
EricLew 0:3eee9435dd17 1846
EricLew 0:3eee9435dd17 1847 /*@} end of CMSIS_core_DebugFunctions */
EricLew 0:3eee9435dd17 1848
EricLew 0:3eee9435dd17 1849
EricLew 0:3eee9435dd17 1850
EricLew 0:3eee9435dd17 1851
EricLew 0:3eee9435dd17 1852 #ifdef __cplusplus
EricLew 0:3eee9435dd17 1853 }
EricLew 0:3eee9435dd17 1854 #endif
EricLew 0:3eee9435dd17 1855
EricLew 0:3eee9435dd17 1856 #endif /* __CORE_CM4_H_DEPENDANT */
EricLew 0:3eee9435dd17 1857
EricLew 0:3eee9435dd17 1858 #endif /* __CMSIS_GENERIC */
EricLew 0:3eee9435dd17 1859
EricLew 0:3eee9435dd17 1860