Semtech / SX126xLib

SX1261 and sx1262 common library

Dependents:   SX126xDevKit SX1262PingPong SX126X_TXonly SX126X_PingPong_Demo ... more

Fork of SX126xLib by Gregory Cristian

sx126x-hal.cpp@3:7e3595a9ebe0, 2016-10-12 (annotated)

Committer:
GregCr
Date:
Wed Oct 12 08:49:58 2016 +0000
Revision:
3:7e3595a9ebe0
Parent:
2:4ff11ea92fbe
Child:
4:c6ef863d0b07
updated version with patch RAM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:deaafdfde3bb 1 /*
GregCr 0:deaafdfde3bb 2 / _____) _ | |
GregCr 0:deaafdfde3bb 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:deaafdfde3bb 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:deaafdfde3bb 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:deaafdfde3bb 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
GregCr 0:deaafdfde3bb 7 (C)2016 Semtech
GregCr 0:deaafdfde3bb 8
GregCr 0:deaafdfde3bb 9 Description: Handling of the node configuration protocol
GregCr 0:deaafdfde3bb 10
GregCr 0:deaafdfde3bb 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:deaafdfde3bb 12
GregCr 0:deaafdfde3bb 13 Maintainer: Miguel Luis, Gregory Cristian and Matthieu Verdy
GregCr 0:deaafdfde3bb 14 */
GregCr 1:35d34672a089 15 #include "sx126x-hal.h"
GregCr 0:deaafdfde3bb 16
GregCr 0:deaafdfde3bb 17 #define V1A_WORKAROUNDS
GregCr 0:deaafdfde3bb 18
GregCr 0:deaafdfde3bb 19 /*!
GregCr 0:deaafdfde3bb 20 * \brief Used to block execution waiting for low state on radio busy pin.
GregCr 0:deaafdfde3bb 21 * Essentially used in SPI communications
GregCr 0:deaafdfde3bb 22 */
GregCr 0:deaafdfde3bb 23 #define WaitBusy( ) while( BUSY == 1 ){ }
GregCr 0:deaafdfde3bb 24
GregCr 0:deaafdfde3bb 25
GregCr 0:deaafdfde3bb 26
GregCr 0:deaafdfde3bb 27 /*!
GregCr 0:deaafdfde3bb 28 * \brief Blocking routine for waiting the UART to be writeable
GregCr 0:deaafdfde3bb 29 *
GregCr 0:deaafdfde3bb 30 */
GregCr 0:deaafdfde3bb 31 #define WaitUartWritable( ) while( RadioUart->writeable( ) == false ){ }
GregCr 0:deaafdfde3bb 32
GregCr 0:deaafdfde3bb 33 /*!
GregCr 0:deaafdfde3bb 34 * \brief Blocking routine for waiting the UART to be readable
GregCr 0:deaafdfde3bb 35 *
GregCr 0:deaafdfde3bb 36 */
GregCr 0:deaafdfde3bb 37 #define WaitUartReadable( ) while( RadioUart->readable( ) == false ){ }
GregCr 0:deaafdfde3bb 38
GregCr 2:4ff11ea92fbe 39 SX126xHal::SX126xHal( PinName mosi, PinName miso, PinName sclk, PinName nss, PinName busy, PinName dio1, PinName dio2, PinName dio3, PinName rst,
GregCr 0:deaafdfde3bb 40 void ( *txDone )( ), void ( *rxDone )( ), void ( *rxPblSyncWordHeader )( IrqPblSyncHeaderCode_t val ),
GregCr 3:7e3595a9ebe0 41 void ( *rxTxTimeout )( IrqTimeoutCode_t timeoutCode ), void ( *rxError )( IrqErrorCode_t errorCode ), void ( *cadDone )( bool channelActivityDetected ),
GregCr 0:deaafdfde3bb 42 void ( *onDioIrq )( ) )
GregCr 3:7e3595a9ebe0 43 : SX126x( txDone, rxDone, rxPblSyncWordHeader, rxTxTimeout, rxError, cadDone, onDioIrq ),
GregCr 0:deaafdfde3bb 44 RadioNss( nss ),
GregCr 0:deaafdfde3bb 45 RadioReset( rst ),
GregCr 0:deaafdfde3bb 46 BUSY( busy ),
GregCr 0:deaafdfde3bb 47 DIO1( dio1 ),
GregCr 0:deaafdfde3bb 48 DIO2( dio2 ),
GregCr 0:deaafdfde3bb 49 DIO3( dio3 )
GregCr 0:deaafdfde3bb 50 {
GregCr 0:deaafdfde3bb 51 RadioSpi = new SPI( mosi, miso, sclk );
GregCr 0:deaafdfde3bb 52 RadioUart = NULL;
GregCr 0:deaafdfde3bb 53
GregCr 0:deaafdfde3bb 54 RadioNss = 1;
GregCr 0:deaafdfde3bb 55 RadioReset = 1;
GregCr 0:deaafdfde3bb 56 }
GregCr 0:deaafdfde3bb 57
GregCr 2:4ff11ea92fbe 58 SX126xHal::SX126xHal( PinName tx, PinName rx, PinName busy, PinName dio1, PinName dio2, PinName dio3, PinName rst,
GregCr 0:deaafdfde3bb 59 void ( *txDone )( ), void ( *rxDone )( ), void ( *rxPblSyncWordHeader )( IrqPblSyncHeaderCode_t val ),
GregCr 3:7e3595a9ebe0 60 void ( *rxTxTimeout )( IrqTimeoutCode_t timeoutCode ), void ( *rxError )( IrqErrorCode_t errorCode ), void ( *cadDone )( bool channelActivityDetected ),
GregCr 0:deaafdfde3bb 61 void ( *onDioIrq )( ) )
GregCr 3:7e3595a9ebe0 62 : SX126x( txDone, rxDone, rxPblSyncWordHeader, rxTxTimeout, rxError, cadDone, onDioIrq ),
GregCr 0:deaafdfde3bb 63 RadioNss( NC ),
GregCr 0:deaafdfde3bb 64 RadioReset( rst ),
GregCr 0:deaafdfde3bb 65 BUSY( busy ),
GregCr 0:deaafdfde3bb 66 DIO1( dio1 ),
GregCr 0:deaafdfde3bb 67 DIO2( dio2 ),
GregCr 0:deaafdfde3bb 68 DIO3( dio3 )
GregCr 0:deaafdfde3bb 69 {
GregCr 0:deaafdfde3bb 70 RadioSpi = NULL;
GregCr 0:deaafdfde3bb 71 RadioUart = new Serial( tx, rx );
GregCr 0:deaafdfde3bb 72 RadioReset = 1;
GregCr 0:deaafdfde3bb 73 }
GregCr 0:deaafdfde3bb 74
GregCr 2:4ff11ea92fbe 75 void SX126xHal::SpiInit( void )
GregCr 0:deaafdfde3bb 76 {
GregCr 0:deaafdfde3bb 77 RadioNss = 1;
GregCr 0:deaafdfde3bb 78 RadioSpi->format( 8, 0 );
GregCr 2:4ff11ea92fbe 79 RadioSpi->frequency( SX126x_SPI_FREQ_DEFAULT );
GregCr 0:deaafdfde3bb 80
GregCr 0:deaafdfde3bb 81 wait( 0.1 );
GregCr 0:deaafdfde3bb 82 }
GregCr 0:deaafdfde3bb 83
GregCr 2:4ff11ea92fbe 84 void SX126xHal::UartInit( void )
GregCr 0:deaafdfde3bb 85 {
GregCr 0:deaafdfde3bb 86 RadioUart->format( 9, SerialBase::Even, 1 ); // 8 data bits + 1 even parity bit + 1 stop bit
GregCr 0:deaafdfde3bb 87 RadioUart->baud( 115200 );
GregCr 0:deaafdfde3bb 88
GregCr 2:4ff11ea92fbe 89 // By default the SX126x UART is setup to handle bytes MSB first.
GregCr 0:deaafdfde3bb 90 // In order to setup the radio to use the UART standard way we first send
GregCr 0:deaafdfde3bb 91 // the equivalent of a WriteRegister with reversed bit order in order to
GregCr 0:deaafdfde3bb 92 // change the endianness.
GregCr 0:deaafdfde3bb 93 //@todo
GregCr 0:deaafdfde3bb 94 /*uint8_t regVal = 0;
GregCr 0:deaafdfde3bb 95 RadioUart->putc( 0x98 ); // Reversed opcode for read register (0x19)
GregCr 0:deaafdfde3bb 96 RadioUart->putc( 0x10 ); // Reversed MSB register address (0x08)
GregCr 0:deaafdfde3bb 97 RadioUart->putc( 0x18 ); // Reversed LSB register address (0x18)
GregCr 0:deaafdfde3bb 98 RadioUart->putc( 0x80 ); // Reversed value for reading only 1 byte (0x01)
GregCr 0:deaafdfde3bb 99 regVal = RadioUart->getc( )& 0xF3; // Read reversed value and mask it
GregCr 0:deaafdfde3bb 100
GregCr 0:deaafdfde3bb 101 RadioUart->putc( 0x18 ); // Reversed opcode for read register (0x18)
GregCr 0:deaafdfde3bb 102 RadioUart->putc( 0x10 ); // Reversed MSB register address (0x08)
GregCr 0:deaafdfde3bb 103 RadioUart->putc( 0x18 ); // Reversed LSB register address (0x18)
GregCr 0:deaafdfde3bb 104 RadioUart->putc( 0x80 ); // Reversed value for writing only 1 byte (0x01)
GregCr 0:deaafdfde3bb 105 RadioUart->putc( regVal ); // The new value of the register*/
GregCr 0:deaafdfde3bb 106
GregCr 0:deaafdfde3bb 107 // After this point, the UART is running standard mode: 8 data bit, 1 even
GregCr 0:deaafdfde3bb 108 // parity bit, 1 stop bit, 115200 baud, LSB first
GregCr 0:deaafdfde3bb 109 wait_us( 10 );
GregCr 0:deaafdfde3bb 110 }
GregCr 0:deaafdfde3bb 111
GregCr 2:4ff11ea92fbe 112 void SX126xHal::IoIrqInit( DioIrqHandler irqHandler )
GregCr 0:deaafdfde3bb 113 {
GregCr 0:deaafdfde3bb 114 assert_param( RadioSpi != 0 || RadioUart != 0 );
GregCr 0:deaafdfde3bb 115 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 116 {
GregCr 0:deaafdfde3bb 117 SpiInit( );
GregCr 0:deaafdfde3bb 118 }
GregCr 0:deaafdfde3bb 119 if( RadioUart != NULL )
GregCr 0:deaafdfde3bb 120 {
GregCr 0:deaafdfde3bb 121 UartInit( );
GregCr 0:deaafdfde3bb 122 }
GregCr 0:deaafdfde3bb 123
GregCr 0:deaafdfde3bb 124 BUSY.mode( PullDown );
GregCr 0:deaafdfde3bb 125 DIO1.mode( PullDown );
GregCr 0:deaafdfde3bb 126 DIO2.mode( PullDown );
GregCr 0:deaafdfde3bb 127 DIO3.mode( PullDown );
GregCr 0:deaafdfde3bb 128
GregCr 0:deaafdfde3bb 129 DIO1.rise( this, static_cast <Trigger>( irqHandler ) );
GregCr 0:deaafdfde3bb 130 DIO2.rise( this, static_cast <Trigger>( irqHandler ) );
GregCr 0:deaafdfde3bb 131 DIO3.rise( this, static_cast <Trigger>( irqHandler ) );
GregCr 0:deaafdfde3bb 132 }
GregCr 0:deaafdfde3bb 133
GregCr 2:4ff11ea92fbe 134 void SX126xHal::Reset( void )
GregCr 0:deaafdfde3bb 135 {
GregCr 0:deaafdfde3bb 136 __disable_irq( );
GregCr 0:deaafdfde3bb 137 wait( 0.05 );
GregCr 0:deaafdfde3bb 138 RadioReset = 0;
GregCr 0:deaafdfde3bb 139 wait( 0.1 );
GregCr 0:deaafdfde3bb 140 RadioReset = 1;
GregCr 0:deaafdfde3bb 141 wait( 0.05 );
GregCr 0:deaafdfde3bb 142 __enable_irq( );
GregCr 0:deaafdfde3bb 143 }
GregCr 0:deaafdfde3bb 144
GregCr 2:4ff11ea92fbe 145 void SX126xHal::ClearInstructionRam( void )
GregCr 0:deaafdfde3bb 146 {
GregCr 0:deaafdfde3bb 147 // Clearing the instruction RAM is writing 0x00s on every bytes of the
GregCr 0:deaafdfde3bb 148 // instruction RAM
GregCr 0:deaafdfde3bb 149 WaitBusy( );
GregCr 0:deaafdfde3bb 150
GregCr 0:deaafdfde3bb 151 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 152 {
GregCr 0:deaafdfde3bb 153 RadioNss = 0;
GregCr 0:deaafdfde3bb 154 RadioSpi->write( RADIO_WRITE_REGISTER ); // Send write register opcode
GregCr 0:deaafdfde3bb 155 RadioSpi->write( ( IRAM_START_ADDRESS >> 8 ) & 0x00FF ); // Send MSB of the first byte address
GregCr 0:deaafdfde3bb 156 RadioSpi->write( IRAM_START_ADDRESS & 0x00FF ); // Send LSB of the first byte address
GregCr 0:deaafdfde3bb 157
GregCr 0:deaafdfde3bb 158 for( uint16_t address = IRAM_START_ADDRESS; address < ( IRAM_START_ADDRESS + IRAM_SIZE ); address++ )
GregCr 0:deaafdfde3bb 159 {
GregCr 0:deaafdfde3bb 160 RadioSpi->write( 0x00 );
GregCr 0:deaafdfde3bb 161 }
GregCr 0:deaafdfde3bb 162 RadioNss = 1;
GregCr 0:deaafdfde3bb 163 }
GregCr 0:deaafdfde3bb 164 if( RadioUart != NULL )
GregCr 0:deaafdfde3bb 165 {
GregCr 0:deaafdfde3bb 166 // We can't erase the whole instruction RAM in one shot with UART
GregCr 0:deaafdfde3bb 167 // because we need to send the length of register to erase
GregCr 0:deaafdfde3bb 168 // and this length is coded on 1 byte.
GregCr 0:deaafdfde3bb 169 for( uint16_t address = IRAM_START_ADDRESS; address < ( IRAM_START_ADDRESS + IRAM_SIZE ); address++ )
GregCr 0:deaafdfde3bb 170 {
GregCr 0:deaafdfde3bb 171 WriteRegister( address, 0 );
GregCr 0:deaafdfde3bb 172 }
GregCr 0:deaafdfde3bb 173 }
GregCr 0:deaafdfde3bb 174
GregCr 0:deaafdfde3bb 175 WaitBusy( );
GregCr 0:deaafdfde3bb 176 }
GregCr 0:deaafdfde3bb 177
GregCr 2:4ff11ea92fbe 178 void SX126xHal::Wakeup( void )
GregCr 0:deaafdfde3bb 179 {
GregCr 0:deaafdfde3bb 180 __disable_irq( );
GregCr 0:deaafdfde3bb 181
GregCr 0:deaafdfde3bb 182 //Don't wait for DIO0 here
GregCr 0:deaafdfde3bb 183
GregCr 0:deaafdfde3bb 184 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 185 {
GregCr 0:deaafdfde3bb 186 RadioNss = 0;
GregCr 0:deaafdfde3bb 187 RadioSpi->write( RADIO_GET_STATUS );
GregCr 0:deaafdfde3bb 188 RadioSpi->write( 0 );
GregCr 0:deaafdfde3bb 189 RadioNss = 1;
GregCr 0:deaafdfde3bb 190 }
GregCr 0:deaafdfde3bb 191 if( RadioUart != NULL )
GregCr 0:deaafdfde3bb 192 {
GregCr 0:deaafdfde3bb 193 RadioUart->putc( RADIO_GET_STATUS );
GregCr 0:deaafdfde3bb 194 WaitUartReadable( );
GregCr 0:deaafdfde3bb 195 RadioUart->getc( );
GregCr 0:deaafdfde3bb 196 }
GregCr 0:deaafdfde3bb 197
GregCr 0:deaafdfde3bb 198 // Wait for chip to be ready.
GregCr 0:deaafdfde3bb 199 WaitBusy( );
GregCr 0:deaafdfde3bb 200
GregCr 0:deaafdfde3bb 201 #ifdef V1A_WORKAROUNDS
GregCr 0:deaafdfde3bb 202 //V1a workaround: rc64k not enabled after warm_start, rtc_wake_up=0
GregCr 0:deaafdfde3bb 203 WriteRegister(0x91e, ReadRegister(0x91e) | 0x40);
GregCr 0:deaafdfde3bb 204 //rc13m enable bug
GregCr 0:deaafdfde3bb 205 uint8_t txFallbackFunc[2];
GregCr 0:deaafdfde3bb 206 //set to ModeTx2Rc addr = 0fce, so rc is not enabled before ramp down
GregCr 0:deaafdfde3bb 207 txFallbackFunc[0] = 0x0f;
GregCr 0:deaafdfde3bb 208 txFallbackFunc[1] = 0xce;
GregCr 0:deaafdfde3bb 209 WriteRegister(0x00CC, txFallbackFunc, 2);
GregCr 0:deaafdfde3bb 210 #endif
GregCr 0:deaafdfde3bb 211
GregCr 0:deaafdfde3bb 212 __enable_irq( );
GregCr 0:deaafdfde3bb 213 }
GregCr 0:deaafdfde3bb 214
GregCr 2:4ff11ea92fbe 215 void SX126xHal::WriteCommand( RadioCommands_t command, uint8_t *buffer, uint16_t size )
GregCr 0:deaafdfde3bb 216 {
GregCr 0:deaafdfde3bb 217 WaitBusy( );
GregCr 0:deaafdfde3bb 218
GregCr 0:deaafdfde3bb 219 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 220 {
GregCr 0:deaafdfde3bb 221 RadioNss = 0;
GregCr 0:deaafdfde3bb 222 RadioSpi->write( ( uint8_t )command );
GregCr 0:deaafdfde3bb 223 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 224 {
GregCr 0:deaafdfde3bb 225 RadioSpi->write( buffer[i] );
GregCr 0:deaafdfde3bb 226 }
GregCr 0:deaafdfde3bb 227 RadioNss = 1;
GregCr 0:deaafdfde3bb 228 }
GregCr 0:deaafdfde3bb 229 if( RadioUart != NULL )
GregCr 0:deaafdfde3bb 230 {
GregCr 0:deaafdfde3bb 231 RadioUart->putc( command );
GregCr 0:deaafdfde3bb 232 if( size > 0 )
GregCr 0:deaafdfde3bb 233 {
GregCr 0:deaafdfde3bb 234 RadioUart->putc( size );
GregCr 0:deaafdfde3bb 235 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 236 {
GregCr 0:deaafdfde3bb 237 RadioUart->putc( buffer[i] );
GregCr 0:deaafdfde3bb 238 }
GregCr 0:deaafdfde3bb 239 }
GregCr 0:deaafdfde3bb 240 }
GregCr 0:deaafdfde3bb 241
GregCr 0:deaafdfde3bb 242 if( command != RADIO_SET_SLEEP )
GregCr 0:deaafdfde3bb 243 {
GregCr 0:deaafdfde3bb 244 WaitBusy( );
GregCr 0:deaafdfde3bb 245 }
GregCr 0:deaafdfde3bb 246 }
GregCr 0:deaafdfde3bb 247
GregCr 2:4ff11ea92fbe 248 void SX126xHal::ReadCommand( RadioCommands_t command, uint8_t *buffer, uint16_t size )
GregCr 0:deaafdfde3bb 249 {
GregCr 0:deaafdfde3bb 250 WaitBusy( );
GregCr 0:deaafdfde3bb 251
GregCr 0:deaafdfde3bb 252 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 253 {
GregCr 0:deaafdfde3bb 254 RadioNss = 0;
GregCr 0:deaafdfde3bb 255 RadioSpi->write( ( uint8_t )command );
GregCr 0:deaafdfde3bb 256 RadioSpi->write( 0 );
GregCr 0:deaafdfde3bb 257 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 258 {
GregCr 0:deaafdfde3bb 259 buffer[i] = RadioSpi->write( 0 );
GregCr 0:deaafdfde3bb 260 }
GregCr 0:deaafdfde3bb 261 RadioNss = 1;
GregCr 0:deaafdfde3bb 262 }
GregCr 0:deaafdfde3bb 263 else if( RadioUart != NULL )
GregCr 0:deaafdfde3bb 264 {
GregCr 0:deaafdfde3bb 265 RadioUart->putc( command );
GregCr 0:deaafdfde3bb 266
GregCr 0:deaafdfde3bb 267 // Behavior on the UART is different depending of the opcode command
GregCr 0:deaafdfde3bb 268 if( ( command == RADIO_GET_PACKETTYPE ) ||
GregCr 0:deaafdfde3bb 269 ( command == RADIO_GET_RXBUFFERSTATUS ) ||
GregCr 0:deaafdfde3bb 270 ( command == RADIO_GET_RSSIINST ) ||
GregCr 0:deaafdfde3bb 271 ( command == RADIO_GET_PACKETSTATUS ) ||
GregCr 0:deaafdfde3bb 272 ( command == RADIO_GET_IRQSTATUS ) )
GregCr 0:deaafdfde3bb 273 {
GregCr 0:deaafdfde3bb 274 RadioUart->putc( size );
GregCr 0:deaafdfde3bb 275 }
GregCr 0:deaafdfde3bb 276
GregCr 0:deaafdfde3bb 277 WaitUartReadable( );
GregCr 0:deaafdfde3bb 278 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 279 {
GregCr 0:deaafdfde3bb 280 buffer[i] = RadioUart->getc( );
GregCr 0:deaafdfde3bb 281 }
GregCr 0:deaafdfde3bb 282 }
GregCr 0:deaafdfde3bb 283 else
GregCr 0:deaafdfde3bb 284 {
GregCr 0:deaafdfde3bb 285 buffer[0] = 0xFF;
GregCr 0:deaafdfde3bb 286 }
GregCr 0:deaafdfde3bb 287
GregCr 0:deaafdfde3bb 288 WaitBusy( );
GregCr 0:deaafdfde3bb 289 }
GregCr 0:deaafdfde3bb 290
GregCr 2:4ff11ea92fbe 291 void SX126xHal::WriteRegister( uint16_t address, uint8_t *buffer, uint16_t size )
GregCr 0:deaafdfde3bb 292 {
GregCr 0:deaafdfde3bb 293 WaitBusy( );
GregCr 0:deaafdfde3bb 294
GregCr 0:deaafdfde3bb 295 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 296 {
GregCr 0:deaafdfde3bb 297 RadioNss = 0;
GregCr 0:deaafdfde3bb 298 RadioSpi->write( RADIO_WRITE_REGISTER );
GregCr 0:deaafdfde3bb 299 RadioSpi->write( ( address & 0xFF00 ) >> 8 );
GregCr 0:deaafdfde3bb 300 RadioSpi->write( address & 0x00FF );
GregCr 0:deaafdfde3bb 301 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 302 {
GregCr 0:deaafdfde3bb 303 RadioSpi->write( buffer[i] );
GregCr 0:deaafdfde3bb 304 }
GregCr 0:deaafdfde3bb 305 RadioNss = 1;
GregCr 0:deaafdfde3bb 306 }
GregCr 0:deaafdfde3bb 307 if( RadioUart != NULL )
GregCr 0:deaafdfde3bb 308 {
GregCr 0:deaafdfde3bb 309 RadioUart->putc( RADIO_WRITE_REGISTER );
GregCr 0:deaafdfde3bb 310 RadioUart->putc( ( address & 0xFF00 ) >> 8 );
GregCr 0:deaafdfde3bb 311 RadioUart->putc( address & 0x00FF );
GregCr 0:deaafdfde3bb 312 RadioUart->putc( size );
GregCr 0:deaafdfde3bb 313 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 314 {
GregCr 0:deaafdfde3bb 315 RadioUart->putc( buffer[i] );
GregCr 0:deaafdfde3bb 316 }
GregCr 0:deaafdfde3bb 317 }
GregCr 0:deaafdfde3bb 318
GregCr 0:deaafdfde3bb 319 WaitBusy( );
GregCr 0:deaafdfde3bb 320 }
GregCr 0:deaafdfde3bb 321
GregCr 2:4ff11ea92fbe 322 void SX126xHal::WriteRegisterNoBusy( uint16_t address, uint8_t *buffer, uint16_t size )
GregCr 0:deaafdfde3bb 323 {
GregCr 0:deaafdfde3bb 324 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 325 {
GregCr 0:deaafdfde3bb 326 RadioNss = 0;
GregCr 0:deaafdfde3bb 327 RadioSpi->write( RADIO_WRITE_REGISTER );
GregCr 0:deaafdfde3bb 328 RadioSpi->write( ( address & 0xFF00 ) >> 8 );
GregCr 0:deaafdfde3bb 329 RadioSpi->write( address & 0x00FF );
GregCr 0:deaafdfde3bb 330 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 331 {
GregCr 0:deaafdfde3bb 332 RadioSpi->write( buffer[i] );
GregCr 0:deaafdfde3bb 333 }
GregCr 0:deaafdfde3bb 334 RadioNss = 1;
GregCr 0:deaafdfde3bb 335 }
GregCr 0:deaafdfde3bb 336 if( RadioUart != NULL )
GregCr 0:deaafdfde3bb 337 {
GregCr 0:deaafdfde3bb 338 RadioUart->putc( RADIO_WRITE_REGISTER );
GregCr 0:deaafdfde3bb 339 RadioUart->putc( ( address & 0xFF00 ) >> 8 );
GregCr 0:deaafdfde3bb 340 RadioUart->putc( address & 0x00FF );
GregCr 0:deaafdfde3bb 341 RadioUart->putc( size );
GregCr 0:deaafdfde3bb 342 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 343 {
GregCr 0:deaafdfde3bb 344 RadioUart->putc( buffer[i] );
GregCr 0:deaafdfde3bb 345 }
GregCr 0:deaafdfde3bb 346 }
GregCr 0:deaafdfde3bb 347 }
GregCr 0:deaafdfde3bb 348
GregCr 2:4ff11ea92fbe 349 void SX126xHal::WriteRegister( uint16_t address, uint8_t value )
GregCr 0:deaafdfde3bb 350 {
GregCr 0:deaafdfde3bb 351 WriteRegister( address, &value, 1 );
GregCr 0:deaafdfde3bb 352 }
GregCr 0:deaafdfde3bb 353
GregCr 2:4ff11ea92fbe 354 void SX126xHal::WriteRegisterNoBusy( uint16_t address, uint8_t value )
GregCr 0:deaafdfde3bb 355 {
GregCr 0:deaafdfde3bb 356 WriteRegisterNoBusy( address, &value, 1 );
GregCr 0:deaafdfde3bb 357 }
GregCr 0:deaafdfde3bb 358
GregCr 2:4ff11ea92fbe 359 void SX126xHal::ReadRegister( uint16_t address, uint8_t *buffer, uint16_t size )
GregCr 0:deaafdfde3bb 360 {
GregCr 0:deaafdfde3bb 361 WaitBusy( );
GregCr 0:deaafdfde3bb 362
GregCr 0:deaafdfde3bb 363 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 364 {
GregCr 0:deaafdfde3bb 365 RadioNss = 0;
GregCr 0:deaafdfde3bb 366 RadioSpi->write( RADIO_READ_REGISTER );
GregCr 0:deaafdfde3bb 367 RadioSpi->write( ( address & 0xFF00 ) >> 8 );
GregCr 0:deaafdfde3bb 368 RadioSpi->write( address & 0x00FF );
GregCr 0:deaafdfde3bb 369 RadioSpi->write( 0 );
GregCr 0:deaafdfde3bb 370 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 371 {
GregCr 0:deaafdfde3bb 372 buffer[i] = RadioSpi->write( 0 );
GregCr 0:deaafdfde3bb 373 }
GregCr 0:deaafdfde3bb 374 RadioNss = 1;
GregCr 0:deaafdfde3bb 375 }
GregCr 0:deaafdfde3bb 376 if( RadioUart != NULL )
GregCr 0:deaafdfde3bb 377 {
GregCr 0:deaafdfde3bb 378 RadioUart->putc( RADIO_READ_REGISTER );
GregCr 0:deaafdfde3bb 379 RadioUart->putc( ( address & 0xFF00 ) >> 8 );
GregCr 0:deaafdfde3bb 380 RadioUart->putc( address & 0x00FF );
GregCr 0:deaafdfde3bb 381 RadioUart->putc( size );
GregCr 0:deaafdfde3bb 382 WaitUartReadable( );
GregCr 0:deaafdfde3bb 383 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 384 {
GregCr 0:deaafdfde3bb 385 buffer[i] = RadioUart->getc( );
GregCr 0:deaafdfde3bb 386 }
GregCr 0:deaafdfde3bb 387 }
GregCr 0:deaafdfde3bb 388
GregCr 0:deaafdfde3bb 389 WaitBusy( );
GregCr 0:deaafdfde3bb 390 }
GregCr 0:deaafdfde3bb 391
GregCr 2:4ff11ea92fbe 392 void SX126xHal::ReadRegisterNoBusy( uint16_t address, uint8_t *buffer, uint16_t size )
GregCr 0:deaafdfde3bb 393 {
GregCr 0:deaafdfde3bb 394
GregCr 0:deaafdfde3bb 395 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 396 {
GregCr 0:deaafdfde3bb 397 RadioNss = 0;
GregCr 0:deaafdfde3bb 398 RadioSpi->write( RADIO_READ_REGISTER );
GregCr 0:deaafdfde3bb 399 RadioSpi->write( ( address & 0xFF00 ) >> 8 );
GregCr 0:deaafdfde3bb 400 RadioSpi->write( address & 0x00FF );
GregCr 0:deaafdfde3bb 401 RadioSpi->write( 0 );
GregCr 0:deaafdfde3bb 402 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 403 {
GregCr 0:deaafdfde3bb 404 buffer[i] = RadioSpi->write( 0 );
GregCr 0:deaafdfde3bb 405 }
GregCr 0:deaafdfde3bb 406 RadioNss = 1;
GregCr 0:deaafdfde3bb 407 }
GregCr 0:deaafdfde3bb 408 if( RadioUart != NULL )
GregCr 0:deaafdfde3bb 409 {
GregCr 0:deaafdfde3bb 410 RadioUart->putc( RADIO_READ_REGISTER );
GregCr 0:deaafdfde3bb 411 RadioUart->putc( ( address & 0xFF00 ) >> 8 );
GregCr 0:deaafdfde3bb 412 RadioUart->putc( address & 0x00FF );
GregCr 0:deaafdfde3bb 413 RadioUart->putc( size );
GregCr 0:deaafdfde3bb 414 WaitUartReadable( );
GregCr 0:deaafdfde3bb 415 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 416 {
GregCr 0:deaafdfde3bb 417 buffer[i] = RadioUart->getc( );
GregCr 0:deaafdfde3bb 418 }
GregCr 0:deaafdfde3bb 419 }
GregCr 0:deaafdfde3bb 420
GregCr 0:deaafdfde3bb 421 }
GregCr 0:deaafdfde3bb 422
GregCr 2:4ff11ea92fbe 423 uint8_t SX126xHal::ReadRegister( uint16_t address )
GregCr 0:deaafdfde3bb 424 {
GregCr 0:deaafdfde3bb 425 uint8_t data;
GregCr 0:deaafdfde3bb 426
GregCr 0:deaafdfde3bb 427 ReadRegister( address, &data, 1 );
GregCr 0:deaafdfde3bb 428 return data;
GregCr 0:deaafdfde3bb 429 }
GregCr 0:deaafdfde3bb 430
GregCr 2:4ff11ea92fbe 431 uint8_t SX126xHal::ReadRegisterNoBusy( uint16_t address )
GregCr 0:deaafdfde3bb 432 {
GregCr 0:deaafdfde3bb 433 uint8_t data;
GregCr 0:deaafdfde3bb 434
GregCr 0:deaafdfde3bb 435 ReadRegisterNoBusy( address, &data, 1 );
GregCr 0:deaafdfde3bb 436 return data;
GregCr 0:deaafdfde3bb 437 }
GregCr 0:deaafdfde3bb 438
GregCr 2:4ff11ea92fbe 439 void SX126xHal::WriteBuffer( uint8_t offset, uint8_t *buffer, uint8_t size )
GregCr 0:deaafdfde3bb 440 {
GregCr 0:deaafdfde3bb 441 WaitBusy( );
GregCr 0:deaafdfde3bb 442
GregCr 0:deaafdfde3bb 443 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 444 {
GregCr 0:deaafdfde3bb 445 RadioNss = 0;
GregCr 0:deaafdfde3bb 446 RadioSpi->write( RADIO_WRITE_BUFFER );
GregCr 0:deaafdfde3bb 447 RadioSpi->write( offset );
GregCr 0:deaafdfde3bb 448 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 449 {
GregCr 0:deaafdfde3bb 450 RadioSpi->write( buffer[i] );
GregCr 0:deaafdfde3bb 451 }
GregCr 0:deaafdfde3bb 452 RadioNss = 1;
GregCr 0:deaafdfde3bb 453 }
GregCr 0:deaafdfde3bb 454 if( RadioUart != NULL )
GregCr 0:deaafdfde3bb 455 {
GregCr 0:deaafdfde3bb 456 RadioUart->putc( RADIO_WRITE_BUFFER );
GregCr 0:deaafdfde3bb 457 RadioUart->putc( offset );
GregCr 0:deaafdfde3bb 458 RadioUart->putc( size );
GregCr 0:deaafdfde3bb 459 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 460 {
GregCr 0:deaafdfde3bb 461 RadioUart->putc( buffer[i] );
GregCr 0:deaafdfde3bb 462 }
GregCr 0:deaafdfde3bb 463 }
GregCr 0:deaafdfde3bb 464
GregCr 0:deaafdfde3bb 465 WaitBusy( );
GregCr 0:deaafdfde3bb 466 }
GregCr 0:deaafdfde3bb 467
GregCr 2:4ff11ea92fbe 468 void SX126xHal::ReadBuffer( uint8_t offset, uint8_t *buffer, uint8_t size )
GregCr 0:deaafdfde3bb 469 {
GregCr 0:deaafdfde3bb 470 WaitBusy( );
GregCr 0:deaafdfde3bb 471
GregCr 0:deaafdfde3bb 472 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 473 {
GregCr 0:deaafdfde3bb 474 RadioNss = 0;
GregCr 0:deaafdfde3bb 475 RadioSpi->write( RADIO_READ_BUFFER );
GregCr 0:deaafdfde3bb 476 RadioSpi->write( offset );
GregCr 0:deaafdfde3bb 477 RadioSpi->write( 0 );
GregCr 0:deaafdfde3bb 478 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 479 {
GregCr 0:deaafdfde3bb 480 buffer[i] = RadioSpi->write( 0 );
GregCr 0:deaafdfde3bb 481 }
GregCr 0:deaafdfde3bb 482 RadioNss = 1;
GregCr 0:deaafdfde3bb 483 }
GregCr 0:deaafdfde3bb 484 if( RadioUart != NULL )
GregCr 0:deaafdfde3bb 485 {
GregCr 0:deaafdfde3bb 486 RadioUart->putc( RADIO_READ_BUFFER );
GregCr 0:deaafdfde3bb 487 RadioUart->putc( offset );
GregCr 0:deaafdfde3bb 488 RadioUart->putc( size );
GregCr 0:deaafdfde3bb 489 WaitUartReadable( );
GregCr 0:deaafdfde3bb 490 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 491 {
GregCr 0:deaafdfde3bb 492 buffer[i] = RadioUart->getc( );
GregCr 0:deaafdfde3bb 493 }
GregCr 0:deaafdfde3bb 494 }
GregCr 0:deaafdfde3bb 495
GregCr 0:deaafdfde3bb 496 WaitBusy( );
GregCr 0:deaafdfde3bb 497 }
GregCr 0:deaafdfde3bb 498
GregCr 2:4ff11ea92fbe 499 uint8_t SX126xHal::GetDioStatus( void )
GregCr 0:deaafdfde3bb 500 {
GregCr 0:deaafdfde3bb 501 return ( DIO3 << 3 ) | ( DIO2 << 2 ) | ( DIO1 << 1 ) | ( BUSY << 0 );
GregCr 0:deaafdfde3bb 502 }
GregCr 0:deaafdfde3bb 503
GregCr 0:deaafdfde3bb 504