Seeed / Mbed 2 deprecated Seeed_Tiny_BLE_Get_Started

To get started with Seeed Tiny BLE, include detecting motion, button and battery level.

Dependencies:   BLE_API eMPL_MPU6050 mbed nRF51822

nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf51_bitfields.h@1:fc2f9d636751, 2015-04-22 (annotated)

Committer:
yihui
Date:
Wed Apr 22 07:47:17 2015 +0000
Revision:
1:fc2f9d636751
update libraries; ; delete nRF51822/nordic-sdk/components/gpiote/app_gpiote.c to solve GPIOTE_IRQHandler multiply defined issue. temperarily change nRF51822 library to folder

Who changed what in which revision?

UserRevisionLine numberNew contents of line
yihui 1:fc2f9d636751 1 /* Copyright (c) 2013, Nordic Semiconductor ASA
yihui 1:fc2f9d636751 2 * All rights reserved.
yihui 1:fc2f9d636751 3 *
yihui 1:fc2f9d636751 4 * Redistribution and use in source and binary forms, with or without
yihui 1:fc2f9d636751 5 * modification, are permitted provided that the following conditions are met:
yihui 1:fc2f9d636751 6 *
yihui 1:fc2f9d636751 7 * * Redistributions of source code must retain the above copyright notice, this
yihui 1:fc2f9d636751 8 * list of conditions and the following disclaimer.
yihui 1:fc2f9d636751 9 *
yihui 1:fc2f9d636751 10 * * Redistributions in binary form must reproduce the above copyright notice,
yihui 1:fc2f9d636751 11 * this list of conditions and the following disclaimer in the documentation
yihui 1:fc2f9d636751 12 * and/or other materials provided with the distribution.
yihui 1:fc2f9d636751 13 *
yihui 1:fc2f9d636751 14 * * Neither the name of Nordic Semiconductor ASA nor the names of its
yihui 1:fc2f9d636751 15 * contributors may be used to endorse or promote products derived from
yihui 1:fc2f9d636751 16 * this software without specific prior written permission.
yihui 1:fc2f9d636751 17 *
yihui 1:fc2f9d636751 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
yihui 1:fc2f9d636751 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
yihui 1:fc2f9d636751 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
yihui 1:fc2f9d636751 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
yihui 1:fc2f9d636751 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
yihui 1:fc2f9d636751 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
yihui 1:fc2f9d636751 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
yihui 1:fc2f9d636751 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
yihui 1:fc2f9d636751 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
yihui 1:fc2f9d636751 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
yihui 1:fc2f9d636751 28 *
yihui 1:fc2f9d636751 29 */
yihui 1:fc2f9d636751 30 #ifndef __NRF51_BITS_H
yihui 1:fc2f9d636751 31 #define __NRF51_BITS_H
yihui 1:fc2f9d636751 32
yihui 1:fc2f9d636751 33 /*lint ++flb "Enter library region */
yihui 1:fc2f9d636751 34
yihui 1:fc2f9d636751 35 #include <core_cm0.h>
yihui 1:fc2f9d636751 36
yihui 1:fc2f9d636751 37 /* Peripheral: AAR */
yihui 1:fc2f9d636751 38 /* Description: Accelerated Address Resolver. */
yihui 1:fc2f9d636751 39
yihui 1:fc2f9d636751 40 /* Register: AAR_INTENSET */
yihui 1:fc2f9d636751 41 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 42
yihui 1:fc2f9d636751 43 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */
yihui 1:fc2f9d636751 44 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
yihui 1:fc2f9d636751 45 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
yihui 1:fc2f9d636751 46 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 47 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 48 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 49
yihui 1:fc2f9d636751 50 /* Bit 1 : Enable interrupt on RESOLVED event. */
yihui 1:fc2f9d636751 51 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
yihui 1:fc2f9d636751 52 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
yihui 1:fc2f9d636751 53 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 54 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 55 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 56
yihui 1:fc2f9d636751 57 /* Bit 0 : Enable interrupt on END event. */
yihui 1:fc2f9d636751 58 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
yihui 1:fc2f9d636751 59 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
yihui 1:fc2f9d636751 60 #define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 61 #define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 62 #define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 63
yihui 1:fc2f9d636751 64 /* Register: AAR_INTENCLR */
yihui 1:fc2f9d636751 65 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 66
yihui 1:fc2f9d636751 67 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */
yihui 1:fc2f9d636751 68 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
yihui 1:fc2f9d636751 69 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
yihui 1:fc2f9d636751 70 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 71 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 72 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 73
yihui 1:fc2f9d636751 74 /* Bit 1 : Disable interrupt on RESOLVED event. */
yihui 1:fc2f9d636751 75 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
yihui 1:fc2f9d636751 76 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
yihui 1:fc2f9d636751 77 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 78 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 79 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 80
yihui 1:fc2f9d636751 81 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
yihui 1:fc2f9d636751 82 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
yihui 1:fc2f9d636751 83 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
yihui 1:fc2f9d636751 84 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 85 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 86 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 87
yihui 1:fc2f9d636751 88 /* Register: AAR_STATUS */
yihui 1:fc2f9d636751 89 /* Description: Resolution status. */
yihui 1:fc2f9d636751 90
yihui 1:fc2f9d636751 91 /* Bits 3..0 : The IRK used last time an address was resolved. */
yihui 1:fc2f9d636751 92 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
yihui 1:fc2f9d636751 93 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
yihui 1:fc2f9d636751 94
yihui 1:fc2f9d636751 95 /* Register: AAR_ENABLE */
yihui 1:fc2f9d636751 96 /* Description: Enable AAR. */
yihui 1:fc2f9d636751 97
yihui 1:fc2f9d636751 98 /* Bits 1..0 : Enable AAR. */
yihui 1:fc2f9d636751 99 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
yihui 1:fc2f9d636751 100 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
yihui 1:fc2f9d636751 101 #define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
yihui 1:fc2f9d636751 102 #define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
yihui 1:fc2f9d636751 103
yihui 1:fc2f9d636751 104 /* Register: AAR_NIRK */
yihui 1:fc2f9d636751 105 /* Description: Number of Identity root Keys in the IRK data structure. */
yihui 1:fc2f9d636751 106
yihui 1:fc2f9d636751 107 /* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
yihui 1:fc2f9d636751 108 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
yihui 1:fc2f9d636751 109 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
yihui 1:fc2f9d636751 110
yihui 1:fc2f9d636751 111 /* Register: AAR_POWER */
yihui 1:fc2f9d636751 112 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 113
yihui 1:fc2f9d636751 114 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 115 #define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 116 #define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 117 #define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 118 #define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 119
yihui 1:fc2f9d636751 120
yihui 1:fc2f9d636751 121 /* Peripheral: ADC */
yihui 1:fc2f9d636751 122 /* Description: Analog to digital converter. */
yihui 1:fc2f9d636751 123
yihui 1:fc2f9d636751 124 /* Register: ADC_INTENSET */
yihui 1:fc2f9d636751 125 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 126
yihui 1:fc2f9d636751 127 /* Bit 0 : Enable interrupt on END event. */
yihui 1:fc2f9d636751 128 #define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
yihui 1:fc2f9d636751 129 #define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
yihui 1:fc2f9d636751 130 #define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 131 #define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 132 #define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 133
yihui 1:fc2f9d636751 134 /* Register: ADC_INTENCLR */
yihui 1:fc2f9d636751 135 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 136
yihui 1:fc2f9d636751 137 /* Bit 0 : Disable interrupt on END event. */
yihui 1:fc2f9d636751 138 #define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
yihui 1:fc2f9d636751 139 #define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
yihui 1:fc2f9d636751 140 #define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 141 #define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 142 #define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 143
yihui 1:fc2f9d636751 144 /* Register: ADC_BUSY */
yihui 1:fc2f9d636751 145 /* Description: ADC busy register. */
yihui 1:fc2f9d636751 146
yihui 1:fc2f9d636751 147 /* Bit 0 : ADC busy register. */
yihui 1:fc2f9d636751 148 #define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
yihui 1:fc2f9d636751 149 #define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
yihui 1:fc2f9d636751 150 #define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
yihui 1:fc2f9d636751 151 #define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
yihui 1:fc2f9d636751 152
yihui 1:fc2f9d636751 153 /* Register: ADC_ENABLE */
yihui 1:fc2f9d636751 154 /* Description: ADC enable. */
yihui 1:fc2f9d636751 155
yihui 1:fc2f9d636751 156 /* Bits 1..0 : ADC enable. */
yihui 1:fc2f9d636751 157 #define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
yihui 1:fc2f9d636751 158 #define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
yihui 1:fc2f9d636751 159 #define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
yihui 1:fc2f9d636751 160 #define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
yihui 1:fc2f9d636751 161
yihui 1:fc2f9d636751 162 /* Register: ADC_CONFIG */
yihui 1:fc2f9d636751 163 /* Description: ADC configuration register. */
yihui 1:fc2f9d636751 164
yihui 1:fc2f9d636751 165 /* Bits 17..16 : ADC external reference pin selection. */
yihui 1:fc2f9d636751 166 #define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
yihui 1:fc2f9d636751 167 #define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
yihui 1:fc2f9d636751 168 #define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
yihui 1:fc2f9d636751 169 #define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
yihui 1:fc2f9d636751 170 #define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
yihui 1:fc2f9d636751 171
yihui 1:fc2f9d636751 172 /* Bits 15..8 : ADC analog pin selection. */
yihui 1:fc2f9d636751 173 #define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
yihui 1:fc2f9d636751 174 #define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
yihui 1:fc2f9d636751 175 #define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
yihui 1:fc2f9d636751 176 #define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
yihui 1:fc2f9d636751 177 #define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
yihui 1:fc2f9d636751 178 #define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
yihui 1:fc2f9d636751 179 #define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
yihui 1:fc2f9d636751 180 #define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
yihui 1:fc2f9d636751 181 #define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
yihui 1:fc2f9d636751 182 #define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
yihui 1:fc2f9d636751 183 #define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
yihui 1:fc2f9d636751 184
yihui 1:fc2f9d636751 185 /* Bits 6..5 : ADC reference selection. */
yihui 1:fc2f9d636751 186 #define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
yihui 1:fc2f9d636751 187 #define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
yihui 1:fc2f9d636751 188 #define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
yihui 1:fc2f9d636751 189 #define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
yihui 1:fc2f9d636751 190 #define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
yihui 1:fc2f9d636751 191 #define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
yihui 1:fc2f9d636751 192
yihui 1:fc2f9d636751 193 /* Bits 4..2 : ADC input selection. */
yihui 1:fc2f9d636751 194 #define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
yihui 1:fc2f9d636751 195 #define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
yihui 1:fc2f9d636751 196 #define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
yihui 1:fc2f9d636751 197 #define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
yihui 1:fc2f9d636751 198 #define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
yihui 1:fc2f9d636751 199 #define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
yihui 1:fc2f9d636751 200 #define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
yihui 1:fc2f9d636751 201
yihui 1:fc2f9d636751 202 /* Bits 1..0 : ADC resolution. */
yihui 1:fc2f9d636751 203 #define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
yihui 1:fc2f9d636751 204 #define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
yihui 1:fc2f9d636751 205 #define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
yihui 1:fc2f9d636751 206 #define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
yihui 1:fc2f9d636751 207 #define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
yihui 1:fc2f9d636751 208
yihui 1:fc2f9d636751 209 /* Register: ADC_RESULT */
yihui 1:fc2f9d636751 210 /* Description: Result of ADC conversion. */
yihui 1:fc2f9d636751 211
yihui 1:fc2f9d636751 212 /* Bits 9..0 : Result of ADC conversion. */
yihui 1:fc2f9d636751 213 #define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
yihui 1:fc2f9d636751 214 #define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
yihui 1:fc2f9d636751 215
yihui 1:fc2f9d636751 216 /* Register: ADC_POWER */
yihui 1:fc2f9d636751 217 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 218
yihui 1:fc2f9d636751 219 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 220 #define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 221 #define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 222 #define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 223 #define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 224
yihui 1:fc2f9d636751 225
yihui 1:fc2f9d636751 226 /* Peripheral: AMLI */
yihui 1:fc2f9d636751 227 /* Description: AHB Multi-Layer Interface. */
yihui 1:fc2f9d636751 228
yihui 1:fc2f9d636751 229 /* Register: AMLI_RAMPRI_CPU0 */
yihui 1:fc2f9d636751 230 /* Description: Configurable priority configuration register for CPU0. */
yihui 1:fc2f9d636751 231
yihui 1:fc2f9d636751 232 /* Bits 31..28 : Configuration field for RAM block 7. */
yihui 1:fc2f9d636751 233 #define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
yihui 1:fc2f9d636751 234 #define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
yihui 1:fc2f9d636751 235 #define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 236 #define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 237 #define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 238 #define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 239 #define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 240 #define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 241 #define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 242 #define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 243
yihui 1:fc2f9d636751 244 /* Bits 27..24 : Configuration field for RAM block 6. */
yihui 1:fc2f9d636751 245 #define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
yihui 1:fc2f9d636751 246 #define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
yihui 1:fc2f9d636751 247 #define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 248 #define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 249 #define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 250 #define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 251 #define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 252 #define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 253 #define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 254 #define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 255
yihui 1:fc2f9d636751 256 /* Bits 23..20 : Configuration field for RAM block 5. */
yihui 1:fc2f9d636751 257 #define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
yihui 1:fc2f9d636751 258 #define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
yihui 1:fc2f9d636751 259 #define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 260 #define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 261 #define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 262 #define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 263 #define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 264 #define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 265 #define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 266 #define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 267
yihui 1:fc2f9d636751 268 /* Bits 19..16 : Configuration field for RAM block 4. */
yihui 1:fc2f9d636751 269 #define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
yihui 1:fc2f9d636751 270 #define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
yihui 1:fc2f9d636751 271 #define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 272 #define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 273 #define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 274 #define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 275 #define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 276 #define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 277 #define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 278 #define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 279
yihui 1:fc2f9d636751 280 /* Bits 15..12 : Configuration field for RAM block 3. */
yihui 1:fc2f9d636751 281 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
yihui 1:fc2f9d636751 282 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
yihui 1:fc2f9d636751 283 #define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 284 #define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 285 #define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 286 #define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 287 #define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 288 #define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 289 #define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 290 #define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 291
yihui 1:fc2f9d636751 292 /* Bits 11..8 : Configuration field for RAM block 2. */
yihui 1:fc2f9d636751 293 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
yihui 1:fc2f9d636751 294 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
yihui 1:fc2f9d636751 295 #define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 296 #define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 297 #define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 298 #define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 299 #define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 300 #define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 301 #define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 302 #define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 303
yihui 1:fc2f9d636751 304 /* Bits 7..4 : Configuration field for RAM block 1. */
yihui 1:fc2f9d636751 305 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
yihui 1:fc2f9d636751 306 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
yihui 1:fc2f9d636751 307 #define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 308 #define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 309 #define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 310 #define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 311 #define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 312 #define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 313 #define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 314 #define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 315
yihui 1:fc2f9d636751 316 /* Bits 3..0 : Configuration field for RAM block 0. */
yihui 1:fc2f9d636751 317 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
yihui 1:fc2f9d636751 318 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
yihui 1:fc2f9d636751 319 #define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 320 #define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 321 #define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 322 #define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 323 #define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 324 #define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 325 #define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 326 #define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 327
yihui 1:fc2f9d636751 328 /* Register: AMLI_RAMPRI_SPIS1 */
yihui 1:fc2f9d636751 329 /* Description: Configurable priority configuration register for SPIS1. */
yihui 1:fc2f9d636751 330
yihui 1:fc2f9d636751 331 /* Bits 31..28 : Configuration field for RAM block 7. */
yihui 1:fc2f9d636751 332 #define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
yihui 1:fc2f9d636751 333 #define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */
yihui 1:fc2f9d636751 334 #define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 335 #define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 336 #define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 337 #define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 338 #define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 339 #define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 340 #define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 341 #define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 342
yihui 1:fc2f9d636751 343 /* Bits 27..24 : Configuration field for RAM block 6. */
yihui 1:fc2f9d636751 344 #define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
yihui 1:fc2f9d636751 345 #define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */
yihui 1:fc2f9d636751 346 #define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 347 #define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 348 #define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 349 #define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 350 #define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 351 #define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 352 #define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 353 #define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 354
yihui 1:fc2f9d636751 355 /* Bits 23..20 : Configuration field for RAM block 5. */
yihui 1:fc2f9d636751 356 #define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
yihui 1:fc2f9d636751 357 #define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */
yihui 1:fc2f9d636751 358 #define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 359 #define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 360 #define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 361 #define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 362 #define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 363 #define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 364 #define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 365 #define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 366
yihui 1:fc2f9d636751 367 /* Bits 19..16 : Configuration field for RAM block 4. */
yihui 1:fc2f9d636751 368 #define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
yihui 1:fc2f9d636751 369 #define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */
yihui 1:fc2f9d636751 370 #define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 371 #define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 372 #define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 373 #define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 374 #define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 375 #define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 376 #define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 377 #define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 378
yihui 1:fc2f9d636751 379 /* Bits 15..12 : Configuration field for RAM block 3. */
yihui 1:fc2f9d636751 380 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
yihui 1:fc2f9d636751 381 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
yihui 1:fc2f9d636751 382 #define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 383 #define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 384 #define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 385 #define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 386 #define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 387 #define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 388 #define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 389 #define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 390
yihui 1:fc2f9d636751 391 /* Bits 11..8 : Configuration field for RAM block 2. */
yihui 1:fc2f9d636751 392 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
yihui 1:fc2f9d636751 393 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
yihui 1:fc2f9d636751 394 #define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 395 #define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 396 #define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 397 #define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 398 #define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 399 #define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 400 #define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 401 #define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 402
yihui 1:fc2f9d636751 403 /* Bits 7..4 : Configuration field for RAM block 1. */
yihui 1:fc2f9d636751 404 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
yihui 1:fc2f9d636751 405 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
yihui 1:fc2f9d636751 406 #define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 407 #define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 408 #define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 409 #define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 410 #define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 411 #define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 412 #define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 413 #define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 414
yihui 1:fc2f9d636751 415 /* Bits 3..0 : Configuration field for RAM block 0. */
yihui 1:fc2f9d636751 416 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
yihui 1:fc2f9d636751 417 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
yihui 1:fc2f9d636751 418 #define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 419 #define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 420 #define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 421 #define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 422 #define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 423 #define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 424 #define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 425 #define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 426
yihui 1:fc2f9d636751 427 /* Register: AMLI_RAMPRI_RADIO */
yihui 1:fc2f9d636751 428 /* Description: Configurable priority configuration register for RADIO. */
yihui 1:fc2f9d636751 429
yihui 1:fc2f9d636751 430 /* Bits 31..28 : Configuration field for RAM block 7. */
yihui 1:fc2f9d636751 431 #define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
yihui 1:fc2f9d636751 432 #define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */
yihui 1:fc2f9d636751 433 #define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 434 #define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 435 #define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 436 #define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 437 #define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 438 #define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 439 #define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 440 #define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 441
yihui 1:fc2f9d636751 442 /* Bits 27..24 : Configuration field for RAM block 6. */
yihui 1:fc2f9d636751 443 #define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
yihui 1:fc2f9d636751 444 #define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */
yihui 1:fc2f9d636751 445 #define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 446 #define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 447 #define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 448 #define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 449 #define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 450 #define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 451 #define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 452 #define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 453
yihui 1:fc2f9d636751 454 /* Bits 23..20 : Configuration field for RAM block 5. */
yihui 1:fc2f9d636751 455 #define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
yihui 1:fc2f9d636751 456 #define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */
yihui 1:fc2f9d636751 457 #define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 458 #define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 459 #define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 460 #define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 461 #define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 462 #define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 463 #define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 464 #define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 465
yihui 1:fc2f9d636751 466 /* Bits 19..16 : Configuration field for RAM block 4. */
yihui 1:fc2f9d636751 467 #define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
yihui 1:fc2f9d636751 468 #define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */
yihui 1:fc2f9d636751 469 #define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 470 #define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 471 #define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 472 #define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 473 #define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 474 #define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 475 #define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 476 #define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 477
yihui 1:fc2f9d636751 478 /* Bits 15..12 : Configuration field for RAM block 3. */
yihui 1:fc2f9d636751 479 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
yihui 1:fc2f9d636751 480 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
yihui 1:fc2f9d636751 481 #define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 482 #define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 483 #define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 484 #define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 485 #define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 486 #define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 487 #define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 488 #define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 489
yihui 1:fc2f9d636751 490 /* Bits 11..8 : Configuration field for RAM block 2. */
yihui 1:fc2f9d636751 491 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
yihui 1:fc2f9d636751 492 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
yihui 1:fc2f9d636751 493 #define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 494 #define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 495 #define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 496 #define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 497 #define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 498 #define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 499 #define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 500 #define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 501
yihui 1:fc2f9d636751 502 /* Bits 7..4 : Configuration field for RAM block 1. */
yihui 1:fc2f9d636751 503 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
yihui 1:fc2f9d636751 504 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
yihui 1:fc2f9d636751 505 #define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 506 #define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 507 #define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 508 #define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 509 #define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 510 #define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 511 #define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 512 #define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 513
yihui 1:fc2f9d636751 514 /* Bits 3..0 : Configuration field for RAM block 0. */
yihui 1:fc2f9d636751 515 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
yihui 1:fc2f9d636751 516 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
yihui 1:fc2f9d636751 517 #define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 518 #define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 519 #define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 520 #define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 521 #define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 522 #define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 523 #define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 524 #define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 525
yihui 1:fc2f9d636751 526 /* Register: AMLI_RAMPRI_ECB */
yihui 1:fc2f9d636751 527 /* Description: Configurable priority configuration register for ECB. */
yihui 1:fc2f9d636751 528
yihui 1:fc2f9d636751 529 /* Bits 31..28 : Configuration field for RAM block 7. */
yihui 1:fc2f9d636751 530 #define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
yihui 1:fc2f9d636751 531 #define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */
yihui 1:fc2f9d636751 532 #define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 533 #define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 534 #define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 535 #define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 536 #define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 537 #define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 538 #define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 539 #define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 540
yihui 1:fc2f9d636751 541 /* Bits 27..24 : Configuration field for RAM block 6. */
yihui 1:fc2f9d636751 542 #define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
yihui 1:fc2f9d636751 543 #define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */
yihui 1:fc2f9d636751 544 #define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 545 #define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 546 #define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 547 #define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 548 #define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 549 #define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 550 #define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 551 #define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 552
yihui 1:fc2f9d636751 553 /* Bits 23..20 : Configuration field for RAM block 5. */
yihui 1:fc2f9d636751 554 #define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
yihui 1:fc2f9d636751 555 #define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */
yihui 1:fc2f9d636751 556 #define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 557 #define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 558 #define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 559 #define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 560 #define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 561 #define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 562 #define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 563 #define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 564
yihui 1:fc2f9d636751 565 /* Bits 19..16 : Configuration field for RAM block 4. */
yihui 1:fc2f9d636751 566 #define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
yihui 1:fc2f9d636751 567 #define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */
yihui 1:fc2f9d636751 568 #define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 569 #define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 570 #define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 571 #define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 572 #define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 573 #define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 574 #define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 575 #define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 576
yihui 1:fc2f9d636751 577 /* Bits 15..12 : Configuration field for RAM block 3. */
yihui 1:fc2f9d636751 578 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
yihui 1:fc2f9d636751 579 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
yihui 1:fc2f9d636751 580 #define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 581 #define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 582 #define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 583 #define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 584 #define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 585 #define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 586 #define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 587 #define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 588
yihui 1:fc2f9d636751 589 /* Bits 11..8 : Configuration field for RAM block 2. */
yihui 1:fc2f9d636751 590 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
yihui 1:fc2f9d636751 591 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
yihui 1:fc2f9d636751 592 #define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 593 #define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 594 #define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 595 #define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 596 #define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 597 #define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 598 #define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 599 #define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 600
yihui 1:fc2f9d636751 601 /* Bits 7..4 : Configuration field for RAM block 1. */
yihui 1:fc2f9d636751 602 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
yihui 1:fc2f9d636751 603 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
yihui 1:fc2f9d636751 604 #define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 605 #define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 606 #define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 607 #define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 608 #define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 609 #define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 610 #define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 611 #define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 612
yihui 1:fc2f9d636751 613 /* Bits 3..0 : Configuration field for RAM block 0. */
yihui 1:fc2f9d636751 614 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
yihui 1:fc2f9d636751 615 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
yihui 1:fc2f9d636751 616 #define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 617 #define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 618 #define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 619 #define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 620 #define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 621 #define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 622 #define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 623 #define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 624
yihui 1:fc2f9d636751 625 /* Register: AMLI_RAMPRI_CCM */
yihui 1:fc2f9d636751 626 /* Description: Configurable priority configuration register for CCM. */
yihui 1:fc2f9d636751 627
yihui 1:fc2f9d636751 628 /* Bits 31..28 : Configuration field for RAM block 7. */
yihui 1:fc2f9d636751 629 #define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
yihui 1:fc2f9d636751 630 #define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
yihui 1:fc2f9d636751 631 #define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 632 #define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 633 #define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 634 #define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 635 #define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 636 #define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 637 #define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 638 #define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 639
yihui 1:fc2f9d636751 640 /* Bits 27..24 : Configuration field for RAM block 6. */
yihui 1:fc2f9d636751 641 #define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
yihui 1:fc2f9d636751 642 #define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
yihui 1:fc2f9d636751 643 #define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 644 #define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 645 #define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 646 #define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 647 #define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 648 #define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 649 #define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 650 #define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 651
yihui 1:fc2f9d636751 652 /* Bits 23..20 : Configuration field for RAM block 5. */
yihui 1:fc2f9d636751 653 #define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
yihui 1:fc2f9d636751 654 #define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
yihui 1:fc2f9d636751 655 #define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 656 #define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 657 #define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 658 #define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 659 #define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 660 #define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 661 #define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 662 #define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 663
yihui 1:fc2f9d636751 664 /* Bits 19..16 : Configuration field for RAM block 4. */
yihui 1:fc2f9d636751 665 #define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
yihui 1:fc2f9d636751 666 #define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
yihui 1:fc2f9d636751 667 #define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 668 #define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 669 #define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 670 #define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 671 #define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 672 #define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 673 #define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 674 #define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 675
yihui 1:fc2f9d636751 676 /* Bits 15..12 : Configuration field for RAM block 3. */
yihui 1:fc2f9d636751 677 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
yihui 1:fc2f9d636751 678 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
yihui 1:fc2f9d636751 679 #define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 680 #define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 681 #define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 682 #define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 683 #define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 684 #define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 685 #define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 686 #define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 687
yihui 1:fc2f9d636751 688 /* Bits 11..8 : Configuration field for RAM block 2. */
yihui 1:fc2f9d636751 689 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
yihui 1:fc2f9d636751 690 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
yihui 1:fc2f9d636751 691 #define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 692 #define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 693 #define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 694 #define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 695 #define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 696 #define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 697 #define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 698 #define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 699
yihui 1:fc2f9d636751 700 /* Bits 7..4 : Configuration field for RAM block 1. */
yihui 1:fc2f9d636751 701 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
yihui 1:fc2f9d636751 702 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
yihui 1:fc2f9d636751 703 #define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 704 #define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 705 #define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 706 #define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 707 #define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 708 #define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 709 #define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 710 #define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 711
yihui 1:fc2f9d636751 712 /* Bits 3..0 : Configuration field for RAM block 0. */
yihui 1:fc2f9d636751 713 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
yihui 1:fc2f9d636751 714 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
yihui 1:fc2f9d636751 715 #define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 716 #define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 717 #define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 718 #define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 719 #define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 720 #define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 721 #define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 722 #define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 723
yihui 1:fc2f9d636751 724 /* Register: AMLI_RAMPRI_AAR */
yihui 1:fc2f9d636751 725 /* Description: Configurable priority configuration register for AAR. */
yihui 1:fc2f9d636751 726
yihui 1:fc2f9d636751 727 /* Bits 31..28 : Configuration field for RAM block 7. */
yihui 1:fc2f9d636751 728 #define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
yihui 1:fc2f9d636751 729 #define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */
yihui 1:fc2f9d636751 730 #define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 731 #define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 732 #define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 733 #define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 734 #define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 735 #define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 736 #define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 737 #define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 738
yihui 1:fc2f9d636751 739 /* Bits 27..24 : Configuration field for RAM block 6. */
yihui 1:fc2f9d636751 740 #define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
yihui 1:fc2f9d636751 741 #define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */
yihui 1:fc2f9d636751 742 #define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 743 #define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 744 #define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 745 #define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 746 #define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 747 #define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 748 #define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 749 #define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 750
yihui 1:fc2f9d636751 751 /* Bits 23..20 : Configuration field for RAM block 5. */
yihui 1:fc2f9d636751 752 #define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
yihui 1:fc2f9d636751 753 #define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */
yihui 1:fc2f9d636751 754 #define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 755 #define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 756 #define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 757 #define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 758 #define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 759 #define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 760 #define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 761 #define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 762
yihui 1:fc2f9d636751 763 /* Bits 19..16 : Configuration field for RAM block 4. */
yihui 1:fc2f9d636751 764 #define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
yihui 1:fc2f9d636751 765 #define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */
yihui 1:fc2f9d636751 766 #define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 767 #define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 768 #define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 769 #define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 770 #define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 771 #define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 772 #define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 773 #define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 774
yihui 1:fc2f9d636751 775 /* Bits 15..12 : Configuration field for RAM block 3. */
yihui 1:fc2f9d636751 776 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
yihui 1:fc2f9d636751 777 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
yihui 1:fc2f9d636751 778 #define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 779 #define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 780 #define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 781 #define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 782 #define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 783 #define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 784 #define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 785 #define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 786
yihui 1:fc2f9d636751 787 /* Bits 11..8 : Configuration field for RAM block 2. */
yihui 1:fc2f9d636751 788 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
yihui 1:fc2f9d636751 789 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
yihui 1:fc2f9d636751 790 #define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 791 #define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 792 #define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 793 #define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 794 #define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 795 #define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 796 #define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 797 #define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 798
yihui 1:fc2f9d636751 799 /* Bits 7..4 : Configuration field for RAM block 1. */
yihui 1:fc2f9d636751 800 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
yihui 1:fc2f9d636751 801 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
yihui 1:fc2f9d636751 802 #define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 803 #define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 804 #define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 805 #define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 806 #define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 807 #define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 808 #define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 809 #define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 810
yihui 1:fc2f9d636751 811 /* Bits 3..0 : Configuration field for RAM block 0. */
yihui 1:fc2f9d636751 812 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
yihui 1:fc2f9d636751 813 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
yihui 1:fc2f9d636751 814 #define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
yihui 1:fc2f9d636751 815 #define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
yihui 1:fc2f9d636751 816 #define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
yihui 1:fc2f9d636751 817 #define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
yihui 1:fc2f9d636751 818 #define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
yihui 1:fc2f9d636751 819 #define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
yihui 1:fc2f9d636751 820 #define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
yihui 1:fc2f9d636751 821 #define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
yihui 1:fc2f9d636751 822
yihui 1:fc2f9d636751 823 /* Peripheral: CCM */
yihui 1:fc2f9d636751 824 /* Description: AES CCM Mode Encryption. */
yihui 1:fc2f9d636751 825
yihui 1:fc2f9d636751 826 /* Register: CCM_SHORTS */
yihui 1:fc2f9d636751 827 /* Description: Shortcuts for the CCM. */
yihui 1:fc2f9d636751 828
yihui 1:fc2f9d636751 829 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
yihui 1:fc2f9d636751 830 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
yihui 1:fc2f9d636751 831 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
yihui 1:fc2f9d636751 832 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 833 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 834
yihui 1:fc2f9d636751 835 /* Register: CCM_INTENSET */
yihui 1:fc2f9d636751 836 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 837
yihui 1:fc2f9d636751 838 /* Bit 2 : Enable interrupt on ERROR event. */
yihui 1:fc2f9d636751 839 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
yihui 1:fc2f9d636751 840 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
yihui 1:fc2f9d636751 841 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 842 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 843 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 844
yihui 1:fc2f9d636751 845 /* Bit 1 : Enable interrupt on ENDCRYPT event. */
yihui 1:fc2f9d636751 846 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
yihui 1:fc2f9d636751 847 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
yihui 1:fc2f9d636751 848 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 849 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 850 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 851
yihui 1:fc2f9d636751 852 /* Bit 0 : Enable interrupt on ENDKSGEN event. */
yihui 1:fc2f9d636751 853 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
yihui 1:fc2f9d636751 854 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
yihui 1:fc2f9d636751 855 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 856 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 857 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 858
yihui 1:fc2f9d636751 859 /* Register: CCM_INTENCLR */
yihui 1:fc2f9d636751 860 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 861
yihui 1:fc2f9d636751 862 /* Bit 2 : Disable interrupt on ERROR event. */
yihui 1:fc2f9d636751 863 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
yihui 1:fc2f9d636751 864 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
yihui 1:fc2f9d636751 865 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 866 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 867 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 868
yihui 1:fc2f9d636751 869 /* Bit 1 : Disable interrupt on ENDCRYPT event. */
yihui 1:fc2f9d636751 870 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
yihui 1:fc2f9d636751 871 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
yihui 1:fc2f9d636751 872 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 873 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 874 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 875
yihui 1:fc2f9d636751 876 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
yihui 1:fc2f9d636751 877 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
yihui 1:fc2f9d636751 878 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
yihui 1:fc2f9d636751 879 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 880 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 881 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 882
yihui 1:fc2f9d636751 883 /* Register: CCM_MICSTATUS */
yihui 1:fc2f9d636751 884 /* Description: CCM RX MIC check result. */
yihui 1:fc2f9d636751 885
yihui 1:fc2f9d636751 886 /* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
yihui 1:fc2f9d636751 887 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
yihui 1:fc2f9d636751 888 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
yihui 1:fc2f9d636751 889 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
yihui 1:fc2f9d636751 890 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
yihui 1:fc2f9d636751 891
yihui 1:fc2f9d636751 892 /* Register: CCM_ENABLE */
yihui 1:fc2f9d636751 893 /* Description: CCM enable. */
yihui 1:fc2f9d636751 894
yihui 1:fc2f9d636751 895 /* Bits 1..0 : CCM enable. */
yihui 1:fc2f9d636751 896 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
yihui 1:fc2f9d636751 897 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
yihui 1:fc2f9d636751 898 #define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
yihui 1:fc2f9d636751 899 #define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
yihui 1:fc2f9d636751 900
yihui 1:fc2f9d636751 901 /* Register: CCM_MODE */
yihui 1:fc2f9d636751 902 /* Description: Operation mode. */
yihui 1:fc2f9d636751 903
yihui 1:fc2f9d636751 904 /* Bit 0 : CCM mode operation. */
yihui 1:fc2f9d636751 905 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
yihui 1:fc2f9d636751 906 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
yihui 1:fc2f9d636751 907 #define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
yihui 1:fc2f9d636751 908 #define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
yihui 1:fc2f9d636751 909
yihui 1:fc2f9d636751 910 /* Register: CCM_POWER */
yihui 1:fc2f9d636751 911 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 912
yihui 1:fc2f9d636751 913 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 914 #define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 915 #define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 916 #define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 917 #define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 918
yihui 1:fc2f9d636751 919
yihui 1:fc2f9d636751 920 /* Peripheral: CLOCK */
yihui 1:fc2f9d636751 921 /* Description: Clock control. */
yihui 1:fc2f9d636751 922
yihui 1:fc2f9d636751 923 /* Register: CLOCK_INTENSET */
yihui 1:fc2f9d636751 924 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 925
yihui 1:fc2f9d636751 926 /* Bit 4 : Enable interrupt on CTTO event. */
yihui 1:fc2f9d636751 927 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
yihui 1:fc2f9d636751 928 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
yihui 1:fc2f9d636751 929 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 930 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 931 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 932
yihui 1:fc2f9d636751 933 /* Bit 3 : Enable interrupt on DONE event. */
yihui 1:fc2f9d636751 934 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
yihui 1:fc2f9d636751 935 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
yihui 1:fc2f9d636751 936 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 937 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 938 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 939
yihui 1:fc2f9d636751 940 /* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
yihui 1:fc2f9d636751 941 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
yihui 1:fc2f9d636751 942 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
yihui 1:fc2f9d636751 943 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 944 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 945 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 946
yihui 1:fc2f9d636751 947 /* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
yihui 1:fc2f9d636751 948 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
yihui 1:fc2f9d636751 949 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
yihui 1:fc2f9d636751 950 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 951 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 952 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 953
yihui 1:fc2f9d636751 954 /* Register: CLOCK_INTENCLR */
yihui 1:fc2f9d636751 955 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 956
yihui 1:fc2f9d636751 957 /* Bit 4 : Disable interrupt on CTTO event. */
yihui 1:fc2f9d636751 958 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
yihui 1:fc2f9d636751 959 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
yihui 1:fc2f9d636751 960 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 961 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 962 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 963
yihui 1:fc2f9d636751 964 /* Bit 3 : Disable interrupt on DONE event. */
yihui 1:fc2f9d636751 965 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
yihui 1:fc2f9d636751 966 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
yihui 1:fc2f9d636751 967 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 968 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 969 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 970
yihui 1:fc2f9d636751 971 /* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
yihui 1:fc2f9d636751 972 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
yihui 1:fc2f9d636751 973 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
yihui 1:fc2f9d636751 974 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 975 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 976 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 977
yihui 1:fc2f9d636751 978 /* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
yihui 1:fc2f9d636751 979 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
yihui 1:fc2f9d636751 980 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
yihui 1:fc2f9d636751 981 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 982 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 983 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 984
yihui 1:fc2f9d636751 985 /* Register: CLOCK_HFCLKRUN */
yihui 1:fc2f9d636751 986 /* Description: Task HFCLKSTART trigger status. */
yihui 1:fc2f9d636751 987
yihui 1:fc2f9d636751 988 /* Bit 0 : Task HFCLKSTART trigger status. */
yihui 1:fc2f9d636751 989 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
yihui 1:fc2f9d636751 990 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
yihui 1:fc2f9d636751 991 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */
yihui 1:fc2f9d636751 992 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */
yihui 1:fc2f9d636751 993
yihui 1:fc2f9d636751 994 /* Register: CLOCK_HFCLKSTAT */
yihui 1:fc2f9d636751 995 /* Description: High frequency clock status. */
yihui 1:fc2f9d636751 996
yihui 1:fc2f9d636751 997 /* Bit 16 : State for the HFCLK. */
yihui 1:fc2f9d636751 998 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
yihui 1:fc2f9d636751 999 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
yihui 1:fc2f9d636751 1000 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
yihui 1:fc2f9d636751 1001 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
yihui 1:fc2f9d636751 1002
yihui 1:fc2f9d636751 1003 /* Bit 0 : Active clock source for the HF clock. */
yihui 1:fc2f9d636751 1004 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
yihui 1:fc2f9d636751 1005 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
yihui 1:fc2f9d636751 1006 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
yihui 1:fc2f9d636751 1007 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
yihui 1:fc2f9d636751 1008
yihui 1:fc2f9d636751 1009 /* Register: CLOCK_LFCLKRUN */
yihui 1:fc2f9d636751 1010 /* Description: Task LFCLKSTART triggered status. */
yihui 1:fc2f9d636751 1011
yihui 1:fc2f9d636751 1012 /* Bit 0 : Task LFCLKSTART triggered status. */
yihui 1:fc2f9d636751 1013 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
yihui 1:fc2f9d636751 1014 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
yihui 1:fc2f9d636751 1015 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */
yihui 1:fc2f9d636751 1016 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */
yihui 1:fc2f9d636751 1017
yihui 1:fc2f9d636751 1018 /* Register: CLOCK_LFCLKSTAT */
yihui 1:fc2f9d636751 1019 /* Description: Low frequency clock status. */
yihui 1:fc2f9d636751 1020
yihui 1:fc2f9d636751 1021 /* Bit 16 : State for the LF clock. */
yihui 1:fc2f9d636751 1022 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
yihui 1:fc2f9d636751 1023 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
yihui 1:fc2f9d636751 1024 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
yihui 1:fc2f9d636751 1025 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
yihui 1:fc2f9d636751 1026
yihui 1:fc2f9d636751 1027 /* Bits 1..0 : Active clock source for the LF clock. */
yihui 1:fc2f9d636751 1028 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
yihui 1:fc2f9d636751 1029 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
yihui 1:fc2f9d636751 1030 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
yihui 1:fc2f9d636751 1031 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
yihui 1:fc2f9d636751 1032 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
yihui 1:fc2f9d636751 1033
yihui 1:fc2f9d636751 1034 /* Register: CLOCK_LFCLKSRCCOPY */
yihui 1:fc2f9d636751 1035 /* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
yihui 1:fc2f9d636751 1036
yihui 1:fc2f9d636751 1037 /* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
yihui 1:fc2f9d636751 1038 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
yihui 1:fc2f9d636751 1039 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
yihui 1:fc2f9d636751 1040 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
yihui 1:fc2f9d636751 1041 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
yihui 1:fc2f9d636751 1042 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
yihui 1:fc2f9d636751 1043
yihui 1:fc2f9d636751 1044 /* Register: CLOCK_LFCLKSRC */
yihui 1:fc2f9d636751 1045 /* Description: Clock source for the LFCLK clock. */
yihui 1:fc2f9d636751 1046
yihui 1:fc2f9d636751 1047 /* Bits 1..0 : Clock source. */
yihui 1:fc2f9d636751 1048 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
yihui 1:fc2f9d636751 1049 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
yihui 1:fc2f9d636751 1050 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
yihui 1:fc2f9d636751 1051 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
yihui 1:fc2f9d636751 1052 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
yihui 1:fc2f9d636751 1053
yihui 1:fc2f9d636751 1054 /* Register: CLOCK_CTIV */
yihui 1:fc2f9d636751 1055 /* Description: Calibration timer interval. */
yihui 1:fc2f9d636751 1056
yihui 1:fc2f9d636751 1057 /* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
yihui 1:fc2f9d636751 1058 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
yihui 1:fc2f9d636751 1059 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
yihui 1:fc2f9d636751 1060
yihui 1:fc2f9d636751 1061 /* Register: CLOCK_XTALFREQ */
yihui 1:fc2f9d636751 1062 /* Description: Crystal frequency. */
yihui 1:fc2f9d636751 1063
yihui 1:fc2f9d636751 1064 /* Bits 7..0 : External Xtal frequency selection. */
yihui 1:fc2f9d636751 1065 #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
yihui 1:fc2f9d636751 1066 #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
yihui 1:fc2f9d636751 1067 #define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */
yihui 1:fc2f9d636751 1068 #define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */
yihui 1:fc2f9d636751 1069
yihui 1:fc2f9d636751 1070
yihui 1:fc2f9d636751 1071 /* Peripheral: ECB */
yihui 1:fc2f9d636751 1072 /* Description: AES ECB Mode Encryption. */
yihui 1:fc2f9d636751 1073
yihui 1:fc2f9d636751 1074 /* Register: ECB_INTENSET */
yihui 1:fc2f9d636751 1075 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 1076
yihui 1:fc2f9d636751 1077 /* Bit 1 : Enable interrupt on ERRORECB event. */
yihui 1:fc2f9d636751 1078 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
yihui 1:fc2f9d636751 1079 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
yihui 1:fc2f9d636751 1080 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 1081 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 1082 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 1083
yihui 1:fc2f9d636751 1084 /* Bit 0 : Enable interrupt on ENDECB event. */
yihui 1:fc2f9d636751 1085 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
yihui 1:fc2f9d636751 1086 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
yihui 1:fc2f9d636751 1087 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 1088 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 1089 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 1090
yihui 1:fc2f9d636751 1091 /* Register: ECB_INTENCLR */
yihui 1:fc2f9d636751 1092 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 1093
yihui 1:fc2f9d636751 1094 /* Bit 1 : Disable interrupt on ERRORECB event. */
yihui 1:fc2f9d636751 1095 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
yihui 1:fc2f9d636751 1096 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
yihui 1:fc2f9d636751 1097 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 1098 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 1099 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 1100
yihui 1:fc2f9d636751 1101 /* Bit 0 : Disable interrupt on ENDECB event. */
yihui 1:fc2f9d636751 1102 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
yihui 1:fc2f9d636751 1103 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
yihui 1:fc2f9d636751 1104 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 1105 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 1106 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 1107
yihui 1:fc2f9d636751 1108 /* Register: ECB_POWER */
yihui 1:fc2f9d636751 1109 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 1110
yihui 1:fc2f9d636751 1111 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 1112 #define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 1113 #define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 1114 #define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 1115 #define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 1116
yihui 1:fc2f9d636751 1117
yihui 1:fc2f9d636751 1118 /* Peripheral: FICR */
yihui 1:fc2f9d636751 1119 /* Description: Factory Information Configuration. */
yihui 1:fc2f9d636751 1120
yihui 1:fc2f9d636751 1121 /* Register: FICR_PPFC */
yihui 1:fc2f9d636751 1122 /* Description: Pre-programmed factory code present. */
yihui 1:fc2f9d636751 1123
yihui 1:fc2f9d636751 1124 /* Bits 7..0 : Pre-programmed factory code present. */
yihui 1:fc2f9d636751 1125 #define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
yihui 1:fc2f9d636751 1126 #define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
yihui 1:fc2f9d636751 1127 #define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
yihui 1:fc2f9d636751 1128 #define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
yihui 1:fc2f9d636751 1129
yihui 1:fc2f9d636751 1130 /* Register: FICR_CONFIGID */
yihui 1:fc2f9d636751 1131 /* Description: Configuration identifier. */
yihui 1:fc2f9d636751 1132
yihui 1:fc2f9d636751 1133 /* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
yihui 1:fc2f9d636751 1134 #define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
yihui 1:fc2f9d636751 1135 #define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
yihui 1:fc2f9d636751 1136
yihui 1:fc2f9d636751 1137 /* Bits 15..0 : Hardware Identification Number. */
yihui 1:fc2f9d636751 1138 #define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
yihui 1:fc2f9d636751 1139 #define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
yihui 1:fc2f9d636751 1140
yihui 1:fc2f9d636751 1141 /* Register: FICR_DEVICEADDRTYPE */
yihui 1:fc2f9d636751 1142 /* Description: Device address type. */
yihui 1:fc2f9d636751 1143
yihui 1:fc2f9d636751 1144 /* Bit 0 : Device address type. */
yihui 1:fc2f9d636751 1145 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
yihui 1:fc2f9d636751 1146 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
yihui 1:fc2f9d636751 1147 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
yihui 1:fc2f9d636751 1148 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
yihui 1:fc2f9d636751 1149
yihui 1:fc2f9d636751 1150 /* Register: FICR_OVERRIDEEN */
yihui 1:fc2f9d636751 1151 /* Description: Radio calibration override enable. */
yihui 1:fc2f9d636751 1152
yihui 1:fc2f9d636751 1153 /* Bit 3 : Override default values for BLE_1Mbit mode. */
yihui 1:fc2f9d636751 1154 #define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
yihui 1:fc2f9d636751 1155 #define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
yihui 1:fc2f9d636751 1156 #define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
yihui 1:fc2f9d636751 1157 #define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
yihui 1:fc2f9d636751 1158
yihui 1:fc2f9d636751 1159 /* Bit 0 : Override default values for NRF_1Mbit mode. */
yihui 1:fc2f9d636751 1160 #define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */
yihui 1:fc2f9d636751 1161 #define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */
yihui 1:fc2f9d636751 1162 #define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */
yihui 1:fc2f9d636751 1163 #define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */
yihui 1:fc2f9d636751 1164
yihui 1:fc2f9d636751 1165 /* Register: FICR_INFO_PART */
yihui 1:fc2f9d636751 1166 /* Description: Part code */
yihui 1:fc2f9d636751 1167
yihui 1:fc2f9d636751 1168 /* Bits 31..0 : Part code */
yihui 1:fc2f9d636751 1169 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
yihui 1:fc2f9d636751 1170 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
yihui 1:fc2f9d636751 1171 #define FICR_INFO_PART_PART_N51822 (0x51822UL) /*!< nRF51822 */
yihui 1:fc2f9d636751 1172 #define FICR_INFO_PART_PART_N51422 (0x51422UL) /*!< nRF51422 */
yihui 1:fc2f9d636751 1173 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
yihui 1:fc2f9d636751 1174
yihui 1:fc2f9d636751 1175 /* Register: FICR_INFO_VARIANT */
yihui 1:fc2f9d636751 1176 /* Description: Part variant */
yihui 1:fc2f9d636751 1177
yihui 1:fc2f9d636751 1178 /* Bits 31..0 : Part variant */
yihui 1:fc2f9d636751 1179 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
yihui 1:fc2f9d636751 1180 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
yihui 1:fc2f9d636751 1181 #define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /*!< nRF51-C (XLR3) */
yihui 1:fc2f9d636751 1182 #define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /*!< nRF51-D (L3) */
yihui 1:fc2f9d636751 1183 #define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /*!< nRF51-E (XLR3P) */
yihui 1:fc2f9d636751 1184 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
yihui 1:fc2f9d636751 1185
yihui 1:fc2f9d636751 1186 /* Register: FICR_INFO_PACKAGE */
yihui 1:fc2f9d636751 1187 /* Description: Package option */
yihui 1:fc2f9d636751 1188
yihui 1:fc2f9d636751 1189 /* Bits 31..0 : Package option */
yihui 1:fc2f9d636751 1190 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
yihui 1:fc2f9d636751 1191 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
yihui 1:fc2f9d636751 1192 #define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /*!< 48-pin QFN with 31 GPIO */
yihui 1:fc2f9d636751 1193 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /*!< nRF51x22 CDxx - WLCSP 56 balls */
yihui 1:fc2f9d636751 1194 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /*!< nRF51x22 CExx - WLCSP 62 balls */
yihui 1:fc2f9d636751 1195 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /*!< nRF51x22 CFxx - WLCSP 62 balls */
yihui 1:fc2f9d636751 1196 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /*!< nRF51x22 CTxx - WLCSP 62 balls */
yihui 1:fc2f9d636751 1197 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
yihui 1:fc2f9d636751 1198
yihui 1:fc2f9d636751 1199 /* Register: FICR_INFO_RAM */
yihui 1:fc2f9d636751 1200 /* Description: RAM variant */
yihui 1:fc2f9d636751 1201
yihui 1:fc2f9d636751 1202 /* Bits 31..0 : RAM variant */
yihui 1:fc2f9d636751 1203 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
yihui 1:fc2f9d636751 1204 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
yihui 1:fc2f9d636751 1205 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
yihui 1:fc2f9d636751 1206 #define FICR_INFO_RAM_RAM_K16 (16UL) /*!< 16 kByte RAM. */
yihui 1:fc2f9d636751 1207 #define FICR_INFO_RAM_RAM_K32 (32UL) /*!< 32 kByte RAM. */
yihui 1:fc2f9d636751 1208
yihui 1:fc2f9d636751 1209 /* Register: FICR_INFO_FLASH */
yihui 1:fc2f9d636751 1210 /* Description: Flash variant */
yihui 1:fc2f9d636751 1211
yihui 1:fc2f9d636751 1212 /* Bits 31..0 : Flash variant */
yihui 1:fc2f9d636751 1213 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
yihui 1:fc2f9d636751 1214 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
yihui 1:fc2f9d636751 1215 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
yihui 1:fc2f9d636751 1216 #define FICR_INFO_FLASH_FLASH_K128 (128UL) /*!< 128 kByte FLASH. */
yihui 1:fc2f9d636751 1217 #define FICR_INFO_FLASH_FLASH_K256 (256UL) /*!< 256 kByte FLASH. */
yihui 1:fc2f9d636751 1218
yihui 1:fc2f9d636751 1219
yihui 1:fc2f9d636751 1220 /* Peripheral: GPIO */
yihui 1:fc2f9d636751 1221 /* Description: General purpose input and output. */
yihui 1:fc2f9d636751 1222
yihui 1:fc2f9d636751 1223 /* Register: GPIO_OUT */
yihui 1:fc2f9d636751 1224 /* Description: Write GPIO port. */
yihui 1:fc2f9d636751 1225
yihui 1:fc2f9d636751 1226 /* Bit 31 : Pin 31. */
yihui 1:fc2f9d636751 1227 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
yihui 1:fc2f9d636751 1228 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
yihui 1:fc2f9d636751 1229 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1230 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1231
yihui 1:fc2f9d636751 1232 /* Bit 30 : Pin 30. */
yihui 1:fc2f9d636751 1233 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
yihui 1:fc2f9d636751 1234 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
yihui 1:fc2f9d636751 1235 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1236 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1237
yihui 1:fc2f9d636751 1238 /* Bit 29 : Pin 29. */
yihui 1:fc2f9d636751 1239 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
yihui 1:fc2f9d636751 1240 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
yihui 1:fc2f9d636751 1241 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1242 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1243
yihui 1:fc2f9d636751 1244 /* Bit 28 : Pin 28. */
yihui 1:fc2f9d636751 1245 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
yihui 1:fc2f9d636751 1246 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
yihui 1:fc2f9d636751 1247 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1248 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1249
yihui 1:fc2f9d636751 1250 /* Bit 27 : Pin 27. */
yihui 1:fc2f9d636751 1251 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
yihui 1:fc2f9d636751 1252 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
yihui 1:fc2f9d636751 1253 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1254 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1255
yihui 1:fc2f9d636751 1256 /* Bit 26 : Pin 26. */
yihui 1:fc2f9d636751 1257 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
yihui 1:fc2f9d636751 1258 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
yihui 1:fc2f9d636751 1259 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1260 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1261
yihui 1:fc2f9d636751 1262 /* Bit 25 : Pin 25. */
yihui 1:fc2f9d636751 1263 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
yihui 1:fc2f9d636751 1264 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
yihui 1:fc2f9d636751 1265 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1266 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1267
yihui 1:fc2f9d636751 1268 /* Bit 24 : Pin 24. */
yihui 1:fc2f9d636751 1269 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
yihui 1:fc2f9d636751 1270 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
yihui 1:fc2f9d636751 1271 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1272 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1273
yihui 1:fc2f9d636751 1274 /* Bit 23 : Pin 23. */
yihui 1:fc2f9d636751 1275 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
yihui 1:fc2f9d636751 1276 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
yihui 1:fc2f9d636751 1277 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1278 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1279
yihui 1:fc2f9d636751 1280 /* Bit 22 : Pin 22. */
yihui 1:fc2f9d636751 1281 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
yihui 1:fc2f9d636751 1282 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
yihui 1:fc2f9d636751 1283 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1284 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1285
yihui 1:fc2f9d636751 1286 /* Bit 21 : Pin 21. */
yihui 1:fc2f9d636751 1287 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
yihui 1:fc2f9d636751 1288 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
yihui 1:fc2f9d636751 1289 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1290 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1291
yihui 1:fc2f9d636751 1292 /* Bit 20 : Pin 20. */
yihui 1:fc2f9d636751 1293 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
yihui 1:fc2f9d636751 1294 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
yihui 1:fc2f9d636751 1295 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1296 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1297
yihui 1:fc2f9d636751 1298 /* Bit 19 : Pin 19. */
yihui 1:fc2f9d636751 1299 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
yihui 1:fc2f9d636751 1300 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
yihui 1:fc2f9d636751 1301 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1302 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1303
yihui 1:fc2f9d636751 1304 /* Bit 18 : Pin 18. */
yihui 1:fc2f9d636751 1305 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
yihui 1:fc2f9d636751 1306 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
yihui 1:fc2f9d636751 1307 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1308 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1309
yihui 1:fc2f9d636751 1310 /* Bit 17 : Pin 17. */
yihui 1:fc2f9d636751 1311 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
yihui 1:fc2f9d636751 1312 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
yihui 1:fc2f9d636751 1313 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1314 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1315
yihui 1:fc2f9d636751 1316 /* Bit 16 : Pin 16. */
yihui 1:fc2f9d636751 1317 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
yihui 1:fc2f9d636751 1318 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
yihui 1:fc2f9d636751 1319 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1320 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1321
yihui 1:fc2f9d636751 1322 /* Bit 15 : Pin 15. */
yihui 1:fc2f9d636751 1323 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
yihui 1:fc2f9d636751 1324 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
yihui 1:fc2f9d636751 1325 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1326 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1327
yihui 1:fc2f9d636751 1328 /* Bit 14 : Pin 14. */
yihui 1:fc2f9d636751 1329 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
yihui 1:fc2f9d636751 1330 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
yihui 1:fc2f9d636751 1331 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1332 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1333
yihui 1:fc2f9d636751 1334 /* Bit 13 : Pin 13. */
yihui 1:fc2f9d636751 1335 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
yihui 1:fc2f9d636751 1336 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
yihui 1:fc2f9d636751 1337 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1338 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1339
yihui 1:fc2f9d636751 1340 /* Bit 12 : Pin 12. */
yihui 1:fc2f9d636751 1341 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
yihui 1:fc2f9d636751 1342 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
yihui 1:fc2f9d636751 1343 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1344 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1345
yihui 1:fc2f9d636751 1346 /* Bit 11 : Pin 11. */
yihui 1:fc2f9d636751 1347 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
yihui 1:fc2f9d636751 1348 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
yihui 1:fc2f9d636751 1349 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1350 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1351
yihui 1:fc2f9d636751 1352 /* Bit 10 : Pin 10. */
yihui 1:fc2f9d636751 1353 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
yihui 1:fc2f9d636751 1354 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
yihui 1:fc2f9d636751 1355 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1356 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1357
yihui 1:fc2f9d636751 1358 /* Bit 9 : Pin 9. */
yihui 1:fc2f9d636751 1359 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
yihui 1:fc2f9d636751 1360 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
yihui 1:fc2f9d636751 1361 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1362 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1363
yihui 1:fc2f9d636751 1364 /* Bit 8 : Pin 8. */
yihui 1:fc2f9d636751 1365 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
yihui 1:fc2f9d636751 1366 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
yihui 1:fc2f9d636751 1367 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1368 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1369
yihui 1:fc2f9d636751 1370 /* Bit 7 : Pin 7. */
yihui 1:fc2f9d636751 1371 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
yihui 1:fc2f9d636751 1372 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
yihui 1:fc2f9d636751 1373 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1374 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1375
yihui 1:fc2f9d636751 1376 /* Bit 6 : Pin 6. */
yihui 1:fc2f9d636751 1377 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
yihui 1:fc2f9d636751 1378 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
yihui 1:fc2f9d636751 1379 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1380 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1381
yihui 1:fc2f9d636751 1382 /* Bit 5 : Pin 5. */
yihui 1:fc2f9d636751 1383 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
yihui 1:fc2f9d636751 1384 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
yihui 1:fc2f9d636751 1385 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1386 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1387
yihui 1:fc2f9d636751 1388 /* Bit 4 : Pin 4. */
yihui 1:fc2f9d636751 1389 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
yihui 1:fc2f9d636751 1390 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
yihui 1:fc2f9d636751 1391 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1392 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1393
yihui 1:fc2f9d636751 1394 /* Bit 3 : Pin 3. */
yihui 1:fc2f9d636751 1395 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
yihui 1:fc2f9d636751 1396 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
yihui 1:fc2f9d636751 1397 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1398 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1399
yihui 1:fc2f9d636751 1400 /* Bit 2 : Pin 2. */
yihui 1:fc2f9d636751 1401 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
yihui 1:fc2f9d636751 1402 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
yihui 1:fc2f9d636751 1403 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1404 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1405
yihui 1:fc2f9d636751 1406 /* Bit 1 : Pin 1. */
yihui 1:fc2f9d636751 1407 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
yihui 1:fc2f9d636751 1408 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
yihui 1:fc2f9d636751 1409 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1410 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1411
yihui 1:fc2f9d636751 1412 /* Bit 0 : Pin 0. */
yihui 1:fc2f9d636751 1413 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
yihui 1:fc2f9d636751 1414 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
yihui 1:fc2f9d636751 1415 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1416 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1417
yihui 1:fc2f9d636751 1418 /* Register: GPIO_OUTSET */
yihui 1:fc2f9d636751 1419 /* Description: Set individual bits in GPIO port. */
yihui 1:fc2f9d636751 1420
yihui 1:fc2f9d636751 1421 /* Bit 31 : Pin 31. */
yihui 1:fc2f9d636751 1422 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
yihui 1:fc2f9d636751 1423 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
yihui 1:fc2f9d636751 1424 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1425 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1426 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1427
yihui 1:fc2f9d636751 1428 /* Bit 30 : Pin 30. */
yihui 1:fc2f9d636751 1429 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
yihui 1:fc2f9d636751 1430 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
yihui 1:fc2f9d636751 1431 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1432 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1433 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1434
yihui 1:fc2f9d636751 1435 /* Bit 29 : Pin 29. */
yihui 1:fc2f9d636751 1436 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
yihui 1:fc2f9d636751 1437 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
yihui 1:fc2f9d636751 1438 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1439 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1440 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1441
yihui 1:fc2f9d636751 1442 /* Bit 28 : Pin 28. */
yihui 1:fc2f9d636751 1443 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
yihui 1:fc2f9d636751 1444 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
yihui 1:fc2f9d636751 1445 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1446 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1447 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1448
yihui 1:fc2f9d636751 1449 /* Bit 27 : Pin 27. */
yihui 1:fc2f9d636751 1450 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
yihui 1:fc2f9d636751 1451 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
yihui 1:fc2f9d636751 1452 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1453 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1454 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1455
yihui 1:fc2f9d636751 1456 /* Bit 26 : Pin 26. */
yihui 1:fc2f9d636751 1457 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
yihui 1:fc2f9d636751 1458 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
yihui 1:fc2f9d636751 1459 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1460 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1461 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1462
yihui 1:fc2f9d636751 1463 /* Bit 25 : Pin 25. */
yihui 1:fc2f9d636751 1464 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
yihui 1:fc2f9d636751 1465 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
yihui 1:fc2f9d636751 1466 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1467 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1468 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1469
yihui 1:fc2f9d636751 1470 /* Bit 24 : Pin 24. */
yihui 1:fc2f9d636751 1471 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
yihui 1:fc2f9d636751 1472 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
yihui 1:fc2f9d636751 1473 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1474 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1475 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1476
yihui 1:fc2f9d636751 1477 /* Bit 23 : Pin 23. */
yihui 1:fc2f9d636751 1478 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
yihui 1:fc2f9d636751 1479 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
yihui 1:fc2f9d636751 1480 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1481 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1482 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1483
yihui 1:fc2f9d636751 1484 /* Bit 22 : Pin 22. */
yihui 1:fc2f9d636751 1485 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
yihui 1:fc2f9d636751 1486 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
yihui 1:fc2f9d636751 1487 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1488 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1489 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1490
yihui 1:fc2f9d636751 1491 /* Bit 21 : Pin 21. */
yihui 1:fc2f9d636751 1492 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
yihui 1:fc2f9d636751 1493 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
yihui 1:fc2f9d636751 1494 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1495 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1496 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1497
yihui 1:fc2f9d636751 1498 /* Bit 20 : Pin 20. */
yihui 1:fc2f9d636751 1499 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
yihui 1:fc2f9d636751 1500 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
yihui 1:fc2f9d636751 1501 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1502 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1503 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1504
yihui 1:fc2f9d636751 1505 /* Bit 19 : Pin 19. */
yihui 1:fc2f9d636751 1506 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
yihui 1:fc2f9d636751 1507 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
yihui 1:fc2f9d636751 1508 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1509 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1510 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1511
yihui 1:fc2f9d636751 1512 /* Bit 18 : Pin 18. */
yihui 1:fc2f9d636751 1513 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
yihui 1:fc2f9d636751 1514 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
yihui 1:fc2f9d636751 1515 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1516 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1517 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1518
yihui 1:fc2f9d636751 1519 /* Bit 17 : Pin 17. */
yihui 1:fc2f9d636751 1520 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
yihui 1:fc2f9d636751 1521 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
yihui 1:fc2f9d636751 1522 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1523 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1524 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1525
yihui 1:fc2f9d636751 1526 /* Bit 16 : Pin 16. */
yihui 1:fc2f9d636751 1527 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
yihui 1:fc2f9d636751 1528 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
yihui 1:fc2f9d636751 1529 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1530 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1531 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1532
yihui 1:fc2f9d636751 1533 /* Bit 15 : Pin 15. */
yihui 1:fc2f9d636751 1534 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
yihui 1:fc2f9d636751 1535 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
yihui 1:fc2f9d636751 1536 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1537 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1538 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1539
yihui 1:fc2f9d636751 1540 /* Bit 14 : Pin 14. */
yihui 1:fc2f9d636751 1541 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
yihui 1:fc2f9d636751 1542 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
yihui 1:fc2f9d636751 1543 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1544 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1545 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1546
yihui 1:fc2f9d636751 1547 /* Bit 13 : Pin 13. */
yihui 1:fc2f9d636751 1548 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
yihui 1:fc2f9d636751 1549 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
yihui 1:fc2f9d636751 1550 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1551 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1552 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1553
yihui 1:fc2f9d636751 1554 /* Bit 12 : Pin 12. */
yihui 1:fc2f9d636751 1555 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
yihui 1:fc2f9d636751 1556 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
yihui 1:fc2f9d636751 1557 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1558 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1559 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1560
yihui 1:fc2f9d636751 1561 /* Bit 11 : Pin 11. */
yihui 1:fc2f9d636751 1562 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
yihui 1:fc2f9d636751 1563 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
yihui 1:fc2f9d636751 1564 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1565 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1566 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1567
yihui 1:fc2f9d636751 1568 /* Bit 10 : Pin 10. */
yihui 1:fc2f9d636751 1569 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
yihui 1:fc2f9d636751 1570 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
yihui 1:fc2f9d636751 1571 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1572 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1573 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1574
yihui 1:fc2f9d636751 1575 /* Bit 9 : Pin 9. */
yihui 1:fc2f9d636751 1576 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
yihui 1:fc2f9d636751 1577 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
yihui 1:fc2f9d636751 1578 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1579 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1580 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1581
yihui 1:fc2f9d636751 1582 /* Bit 8 : Pin 8. */
yihui 1:fc2f9d636751 1583 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
yihui 1:fc2f9d636751 1584 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
yihui 1:fc2f9d636751 1585 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1586 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1587 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1588
yihui 1:fc2f9d636751 1589 /* Bit 7 : Pin 7. */
yihui 1:fc2f9d636751 1590 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
yihui 1:fc2f9d636751 1591 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
yihui 1:fc2f9d636751 1592 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1593 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1594 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1595
yihui 1:fc2f9d636751 1596 /* Bit 6 : Pin 6. */
yihui 1:fc2f9d636751 1597 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
yihui 1:fc2f9d636751 1598 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
yihui 1:fc2f9d636751 1599 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1600 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1601 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1602
yihui 1:fc2f9d636751 1603 /* Bit 5 : Pin 5. */
yihui 1:fc2f9d636751 1604 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
yihui 1:fc2f9d636751 1605 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
yihui 1:fc2f9d636751 1606 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1607 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1608 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1609
yihui 1:fc2f9d636751 1610 /* Bit 4 : Pin 4. */
yihui 1:fc2f9d636751 1611 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
yihui 1:fc2f9d636751 1612 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
yihui 1:fc2f9d636751 1613 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1614 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1615 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1616
yihui 1:fc2f9d636751 1617 /* Bit 3 : Pin 3. */
yihui 1:fc2f9d636751 1618 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
yihui 1:fc2f9d636751 1619 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
yihui 1:fc2f9d636751 1620 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1621 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1622 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1623
yihui 1:fc2f9d636751 1624 /* Bit 2 : Pin 2. */
yihui 1:fc2f9d636751 1625 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
yihui 1:fc2f9d636751 1626 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
yihui 1:fc2f9d636751 1627 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1628 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1629 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1630
yihui 1:fc2f9d636751 1631 /* Bit 1 : Pin 1. */
yihui 1:fc2f9d636751 1632 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
yihui 1:fc2f9d636751 1633 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
yihui 1:fc2f9d636751 1634 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1635 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1636 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1637
yihui 1:fc2f9d636751 1638 /* Bit 0 : Pin 0. */
yihui 1:fc2f9d636751 1639 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
yihui 1:fc2f9d636751 1640 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
yihui 1:fc2f9d636751 1641 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1642 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1643 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
yihui 1:fc2f9d636751 1644
yihui 1:fc2f9d636751 1645 /* Register: GPIO_OUTCLR */
yihui 1:fc2f9d636751 1646 /* Description: Clear individual bits in GPIO port. */
yihui 1:fc2f9d636751 1647
yihui 1:fc2f9d636751 1648 /* Bit 31 : Pin 31. */
yihui 1:fc2f9d636751 1649 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
yihui 1:fc2f9d636751 1650 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
yihui 1:fc2f9d636751 1651 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1652 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1653 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1654
yihui 1:fc2f9d636751 1655 /* Bit 30 : Pin 30. */
yihui 1:fc2f9d636751 1656 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
yihui 1:fc2f9d636751 1657 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
yihui 1:fc2f9d636751 1658 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1659 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1660 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1661
yihui 1:fc2f9d636751 1662 /* Bit 29 : Pin 29. */
yihui 1:fc2f9d636751 1663 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
yihui 1:fc2f9d636751 1664 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
yihui 1:fc2f9d636751 1665 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1666 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1667 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1668
yihui 1:fc2f9d636751 1669 /* Bit 28 : Pin 28. */
yihui 1:fc2f9d636751 1670 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
yihui 1:fc2f9d636751 1671 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
yihui 1:fc2f9d636751 1672 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1673 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1674 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1675
yihui 1:fc2f9d636751 1676 /* Bit 27 : Pin 27. */
yihui 1:fc2f9d636751 1677 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
yihui 1:fc2f9d636751 1678 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
yihui 1:fc2f9d636751 1679 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1680 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1681 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1682
yihui 1:fc2f9d636751 1683 /* Bit 26 : Pin 26. */
yihui 1:fc2f9d636751 1684 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
yihui 1:fc2f9d636751 1685 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
yihui 1:fc2f9d636751 1686 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1687 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1688 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1689
yihui 1:fc2f9d636751 1690 /* Bit 25 : Pin 25. */
yihui 1:fc2f9d636751 1691 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
yihui 1:fc2f9d636751 1692 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
yihui 1:fc2f9d636751 1693 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1694 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1695 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1696
yihui 1:fc2f9d636751 1697 /* Bit 24 : Pin 24. */
yihui 1:fc2f9d636751 1698 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
yihui 1:fc2f9d636751 1699 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
yihui 1:fc2f9d636751 1700 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1701 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1702 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1703
yihui 1:fc2f9d636751 1704 /* Bit 23 : Pin 23. */
yihui 1:fc2f9d636751 1705 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
yihui 1:fc2f9d636751 1706 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
yihui 1:fc2f9d636751 1707 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1708 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1709 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1710
yihui 1:fc2f9d636751 1711 /* Bit 22 : Pin 22. */
yihui 1:fc2f9d636751 1712 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
yihui 1:fc2f9d636751 1713 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
yihui 1:fc2f9d636751 1714 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1715 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1716 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1717
yihui 1:fc2f9d636751 1718 /* Bit 21 : Pin 21. */
yihui 1:fc2f9d636751 1719 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
yihui 1:fc2f9d636751 1720 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
yihui 1:fc2f9d636751 1721 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1722 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1723 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1724
yihui 1:fc2f9d636751 1725 /* Bit 20 : Pin 20. */
yihui 1:fc2f9d636751 1726 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
yihui 1:fc2f9d636751 1727 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
yihui 1:fc2f9d636751 1728 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1729 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1730 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1731
yihui 1:fc2f9d636751 1732 /* Bit 19 : Pin 19. */
yihui 1:fc2f9d636751 1733 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
yihui 1:fc2f9d636751 1734 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
yihui 1:fc2f9d636751 1735 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1736 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1737 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1738
yihui 1:fc2f9d636751 1739 /* Bit 18 : Pin 18. */
yihui 1:fc2f9d636751 1740 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
yihui 1:fc2f9d636751 1741 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
yihui 1:fc2f9d636751 1742 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1743 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1744 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1745
yihui 1:fc2f9d636751 1746 /* Bit 17 : Pin 17. */
yihui 1:fc2f9d636751 1747 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
yihui 1:fc2f9d636751 1748 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
yihui 1:fc2f9d636751 1749 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1750 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1751 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1752
yihui 1:fc2f9d636751 1753 /* Bit 16 : Pin 16. */
yihui 1:fc2f9d636751 1754 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
yihui 1:fc2f9d636751 1755 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
yihui 1:fc2f9d636751 1756 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1757 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1758 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1759
yihui 1:fc2f9d636751 1760 /* Bit 15 : Pin 15. */
yihui 1:fc2f9d636751 1761 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
yihui 1:fc2f9d636751 1762 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
yihui 1:fc2f9d636751 1763 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1764 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1765 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1766
yihui 1:fc2f9d636751 1767 /* Bit 14 : Pin 14. */
yihui 1:fc2f9d636751 1768 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
yihui 1:fc2f9d636751 1769 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
yihui 1:fc2f9d636751 1770 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1771 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1772 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1773
yihui 1:fc2f9d636751 1774 /* Bit 13 : Pin 13. */
yihui 1:fc2f9d636751 1775 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
yihui 1:fc2f9d636751 1776 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
yihui 1:fc2f9d636751 1777 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1778 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1779 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1780
yihui 1:fc2f9d636751 1781 /* Bit 12 : Pin 12. */
yihui 1:fc2f9d636751 1782 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
yihui 1:fc2f9d636751 1783 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
yihui 1:fc2f9d636751 1784 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1785 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1786 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1787
yihui 1:fc2f9d636751 1788 /* Bit 11 : Pin 11. */
yihui 1:fc2f9d636751 1789 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
yihui 1:fc2f9d636751 1790 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
yihui 1:fc2f9d636751 1791 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1792 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1793 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1794
yihui 1:fc2f9d636751 1795 /* Bit 10 : Pin 10. */
yihui 1:fc2f9d636751 1796 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
yihui 1:fc2f9d636751 1797 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
yihui 1:fc2f9d636751 1798 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1799 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1800 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1801
yihui 1:fc2f9d636751 1802 /* Bit 9 : Pin 9. */
yihui 1:fc2f9d636751 1803 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
yihui 1:fc2f9d636751 1804 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
yihui 1:fc2f9d636751 1805 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1806 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1807 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1808
yihui 1:fc2f9d636751 1809 /* Bit 8 : Pin 8. */
yihui 1:fc2f9d636751 1810 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
yihui 1:fc2f9d636751 1811 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
yihui 1:fc2f9d636751 1812 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1813 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1814 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1815
yihui 1:fc2f9d636751 1816 /* Bit 7 : Pin 7. */
yihui 1:fc2f9d636751 1817 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
yihui 1:fc2f9d636751 1818 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
yihui 1:fc2f9d636751 1819 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1820 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1821 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1822
yihui 1:fc2f9d636751 1823 /* Bit 6 : Pin 6. */
yihui 1:fc2f9d636751 1824 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
yihui 1:fc2f9d636751 1825 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
yihui 1:fc2f9d636751 1826 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1827 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1828 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1829
yihui 1:fc2f9d636751 1830 /* Bit 5 : Pin 5. */
yihui 1:fc2f9d636751 1831 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
yihui 1:fc2f9d636751 1832 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
yihui 1:fc2f9d636751 1833 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1834 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1835 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1836
yihui 1:fc2f9d636751 1837 /* Bit 4 : Pin 4. */
yihui 1:fc2f9d636751 1838 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
yihui 1:fc2f9d636751 1839 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
yihui 1:fc2f9d636751 1840 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1841 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1842 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1843
yihui 1:fc2f9d636751 1844 /* Bit 3 : Pin 3. */
yihui 1:fc2f9d636751 1845 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
yihui 1:fc2f9d636751 1846 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
yihui 1:fc2f9d636751 1847 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1848 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1849 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1850
yihui 1:fc2f9d636751 1851 /* Bit 2 : Pin 2. */
yihui 1:fc2f9d636751 1852 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
yihui 1:fc2f9d636751 1853 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
yihui 1:fc2f9d636751 1854 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1855 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1856 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1857
yihui 1:fc2f9d636751 1858 /* Bit 1 : Pin 1. */
yihui 1:fc2f9d636751 1859 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
yihui 1:fc2f9d636751 1860 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
yihui 1:fc2f9d636751 1861 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1862 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1863 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1864
yihui 1:fc2f9d636751 1865 /* Bit 0 : Pin 0. */
yihui 1:fc2f9d636751 1866 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
yihui 1:fc2f9d636751 1867 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
yihui 1:fc2f9d636751 1868 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
yihui 1:fc2f9d636751 1869 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
yihui 1:fc2f9d636751 1870 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
yihui 1:fc2f9d636751 1871
yihui 1:fc2f9d636751 1872 /* Register: GPIO_IN */
yihui 1:fc2f9d636751 1873 /* Description: Read GPIO port. */
yihui 1:fc2f9d636751 1874
yihui 1:fc2f9d636751 1875 /* Bit 31 : Pin 31. */
yihui 1:fc2f9d636751 1876 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
yihui 1:fc2f9d636751 1877 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
yihui 1:fc2f9d636751 1878 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1879 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1880
yihui 1:fc2f9d636751 1881 /* Bit 30 : Pin 30. */
yihui 1:fc2f9d636751 1882 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
yihui 1:fc2f9d636751 1883 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
yihui 1:fc2f9d636751 1884 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1885 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1886
yihui 1:fc2f9d636751 1887 /* Bit 29 : Pin 29. */
yihui 1:fc2f9d636751 1888 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
yihui 1:fc2f9d636751 1889 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
yihui 1:fc2f9d636751 1890 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1891 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1892
yihui 1:fc2f9d636751 1893 /* Bit 28 : Pin 28. */
yihui 1:fc2f9d636751 1894 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
yihui 1:fc2f9d636751 1895 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
yihui 1:fc2f9d636751 1896 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1897 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1898
yihui 1:fc2f9d636751 1899 /* Bit 27 : Pin 27. */
yihui 1:fc2f9d636751 1900 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
yihui 1:fc2f9d636751 1901 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
yihui 1:fc2f9d636751 1902 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1903 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1904
yihui 1:fc2f9d636751 1905 /* Bit 26 : Pin 26. */
yihui 1:fc2f9d636751 1906 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
yihui 1:fc2f9d636751 1907 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
yihui 1:fc2f9d636751 1908 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1909 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1910
yihui 1:fc2f9d636751 1911 /* Bit 25 : Pin 25. */
yihui 1:fc2f9d636751 1912 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
yihui 1:fc2f9d636751 1913 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
yihui 1:fc2f9d636751 1914 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1915 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1916
yihui 1:fc2f9d636751 1917 /* Bit 24 : Pin 24. */
yihui 1:fc2f9d636751 1918 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
yihui 1:fc2f9d636751 1919 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
yihui 1:fc2f9d636751 1920 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1921 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1922
yihui 1:fc2f9d636751 1923 /* Bit 23 : Pin 23. */
yihui 1:fc2f9d636751 1924 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
yihui 1:fc2f9d636751 1925 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
yihui 1:fc2f9d636751 1926 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1927 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1928
yihui 1:fc2f9d636751 1929 /* Bit 22 : Pin 22. */
yihui 1:fc2f9d636751 1930 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
yihui 1:fc2f9d636751 1931 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
yihui 1:fc2f9d636751 1932 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1933 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1934
yihui 1:fc2f9d636751 1935 /* Bit 21 : Pin 21. */
yihui 1:fc2f9d636751 1936 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
yihui 1:fc2f9d636751 1937 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
yihui 1:fc2f9d636751 1938 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1939 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1940
yihui 1:fc2f9d636751 1941 /* Bit 20 : Pin 20. */
yihui 1:fc2f9d636751 1942 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
yihui 1:fc2f9d636751 1943 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
yihui 1:fc2f9d636751 1944 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1945 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1946
yihui 1:fc2f9d636751 1947 /* Bit 19 : Pin 19. */
yihui 1:fc2f9d636751 1948 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
yihui 1:fc2f9d636751 1949 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
yihui 1:fc2f9d636751 1950 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1951 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1952
yihui 1:fc2f9d636751 1953 /* Bit 18 : Pin 18. */
yihui 1:fc2f9d636751 1954 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
yihui 1:fc2f9d636751 1955 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
yihui 1:fc2f9d636751 1956 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1957 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1958
yihui 1:fc2f9d636751 1959 /* Bit 17 : Pin 17. */
yihui 1:fc2f9d636751 1960 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
yihui 1:fc2f9d636751 1961 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
yihui 1:fc2f9d636751 1962 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1963 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1964
yihui 1:fc2f9d636751 1965 /* Bit 16 : Pin 16. */
yihui 1:fc2f9d636751 1966 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
yihui 1:fc2f9d636751 1967 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
yihui 1:fc2f9d636751 1968 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1969 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1970
yihui 1:fc2f9d636751 1971 /* Bit 15 : Pin 15. */
yihui 1:fc2f9d636751 1972 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
yihui 1:fc2f9d636751 1973 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
yihui 1:fc2f9d636751 1974 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1975 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1976
yihui 1:fc2f9d636751 1977 /* Bit 14 : Pin 14. */
yihui 1:fc2f9d636751 1978 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
yihui 1:fc2f9d636751 1979 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
yihui 1:fc2f9d636751 1980 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1981 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1982
yihui 1:fc2f9d636751 1983 /* Bit 13 : Pin 13. */
yihui 1:fc2f9d636751 1984 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
yihui 1:fc2f9d636751 1985 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
yihui 1:fc2f9d636751 1986 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1987 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1988
yihui 1:fc2f9d636751 1989 /* Bit 12 : Pin 12. */
yihui 1:fc2f9d636751 1990 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
yihui 1:fc2f9d636751 1991 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
yihui 1:fc2f9d636751 1992 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1993 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 1994
yihui 1:fc2f9d636751 1995 /* Bit 11 : Pin 11. */
yihui 1:fc2f9d636751 1996 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
yihui 1:fc2f9d636751 1997 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
yihui 1:fc2f9d636751 1998 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 1999 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 2000
yihui 1:fc2f9d636751 2001 /* Bit 10 : Pin 10. */
yihui 1:fc2f9d636751 2002 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
yihui 1:fc2f9d636751 2003 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
yihui 1:fc2f9d636751 2004 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 2005 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 2006
yihui 1:fc2f9d636751 2007 /* Bit 9 : Pin 9. */
yihui 1:fc2f9d636751 2008 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
yihui 1:fc2f9d636751 2009 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
yihui 1:fc2f9d636751 2010 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 2011 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 2012
yihui 1:fc2f9d636751 2013 /* Bit 8 : Pin 8. */
yihui 1:fc2f9d636751 2014 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
yihui 1:fc2f9d636751 2015 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
yihui 1:fc2f9d636751 2016 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 2017 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 2018
yihui 1:fc2f9d636751 2019 /* Bit 7 : Pin 7. */
yihui 1:fc2f9d636751 2020 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
yihui 1:fc2f9d636751 2021 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
yihui 1:fc2f9d636751 2022 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 2023 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 2024
yihui 1:fc2f9d636751 2025 /* Bit 6 : Pin 6. */
yihui 1:fc2f9d636751 2026 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
yihui 1:fc2f9d636751 2027 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
yihui 1:fc2f9d636751 2028 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 2029 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 2030
yihui 1:fc2f9d636751 2031 /* Bit 5 : Pin 5. */
yihui 1:fc2f9d636751 2032 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
yihui 1:fc2f9d636751 2033 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
yihui 1:fc2f9d636751 2034 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 2035 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 2036
yihui 1:fc2f9d636751 2037 /* Bit 4 : Pin 4. */
yihui 1:fc2f9d636751 2038 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
yihui 1:fc2f9d636751 2039 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
yihui 1:fc2f9d636751 2040 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 2041 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 2042
yihui 1:fc2f9d636751 2043 /* Bit 3 : Pin 3. */
yihui 1:fc2f9d636751 2044 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
yihui 1:fc2f9d636751 2045 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
yihui 1:fc2f9d636751 2046 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 2047 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 2048
yihui 1:fc2f9d636751 2049 /* Bit 2 : Pin 2. */
yihui 1:fc2f9d636751 2050 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
yihui 1:fc2f9d636751 2051 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
yihui 1:fc2f9d636751 2052 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 2053 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 2054
yihui 1:fc2f9d636751 2055 /* Bit 1 : Pin 1. */
yihui 1:fc2f9d636751 2056 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
yihui 1:fc2f9d636751 2057 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
yihui 1:fc2f9d636751 2058 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 2059 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 2060
yihui 1:fc2f9d636751 2061 /* Bit 0 : Pin 0. */
yihui 1:fc2f9d636751 2062 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
yihui 1:fc2f9d636751 2063 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
yihui 1:fc2f9d636751 2064 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
yihui 1:fc2f9d636751 2065 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
yihui 1:fc2f9d636751 2066
yihui 1:fc2f9d636751 2067 /* Register: GPIO_DIR */
yihui 1:fc2f9d636751 2068 /* Description: Direction of GPIO pins. */
yihui 1:fc2f9d636751 2069
yihui 1:fc2f9d636751 2070 /* Bit 31 : Pin 31. */
yihui 1:fc2f9d636751 2071 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
yihui 1:fc2f9d636751 2072 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
yihui 1:fc2f9d636751 2073 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2074 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2075
yihui 1:fc2f9d636751 2076 /* Bit 30 : Pin 30. */
yihui 1:fc2f9d636751 2077 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
yihui 1:fc2f9d636751 2078 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
yihui 1:fc2f9d636751 2079 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2080 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2081
yihui 1:fc2f9d636751 2082 /* Bit 29 : Pin 29. */
yihui 1:fc2f9d636751 2083 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
yihui 1:fc2f9d636751 2084 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
yihui 1:fc2f9d636751 2085 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2086 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2087
yihui 1:fc2f9d636751 2088 /* Bit 28 : Pin 28. */
yihui 1:fc2f9d636751 2089 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
yihui 1:fc2f9d636751 2090 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
yihui 1:fc2f9d636751 2091 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2092 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2093
yihui 1:fc2f9d636751 2094 /* Bit 27 : Pin 27. */
yihui 1:fc2f9d636751 2095 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
yihui 1:fc2f9d636751 2096 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
yihui 1:fc2f9d636751 2097 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2098 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2099
yihui 1:fc2f9d636751 2100 /* Bit 26 : Pin 26. */
yihui 1:fc2f9d636751 2101 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
yihui 1:fc2f9d636751 2102 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
yihui 1:fc2f9d636751 2103 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2104 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2105
yihui 1:fc2f9d636751 2106 /* Bit 25 : Pin 25. */
yihui 1:fc2f9d636751 2107 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
yihui 1:fc2f9d636751 2108 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
yihui 1:fc2f9d636751 2109 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2110 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2111
yihui 1:fc2f9d636751 2112 /* Bit 24 : Pin 24. */
yihui 1:fc2f9d636751 2113 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
yihui 1:fc2f9d636751 2114 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
yihui 1:fc2f9d636751 2115 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2116 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2117
yihui 1:fc2f9d636751 2118 /* Bit 23 : Pin 23. */
yihui 1:fc2f9d636751 2119 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
yihui 1:fc2f9d636751 2120 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
yihui 1:fc2f9d636751 2121 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2122 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2123
yihui 1:fc2f9d636751 2124 /* Bit 22 : Pin 22. */
yihui 1:fc2f9d636751 2125 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
yihui 1:fc2f9d636751 2126 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
yihui 1:fc2f9d636751 2127 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2128 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2129
yihui 1:fc2f9d636751 2130 /* Bit 21 : Pin 21. */
yihui 1:fc2f9d636751 2131 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
yihui 1:fc2f9d636751 2132 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
yihui 1:fc2f9d636751 2133 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2134 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2135
yihui 1:fc2f9d636751 2136 /* Bit 20 : Pin 20. */
yihui 1:fc2f9d636751 2137 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
yihui 1:fc2f9d636751 2138 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
yihui 1:fc2f9d636751 2139 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2140 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2141
yihui 1:fc2f9d636751 2142 /* Bit 19 : Pin 19. */
yihui 1:fc2f9d636751 2143 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
yihui 1:fc2f9d636751 2144 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
yihui 1:fc2f9d636751 2145 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2146 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2147
yihui 1:fc2f9d636751 2148 /* Bit 18 : Pin 18. */
yihui 1:fc2f9d636751 2149 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
yihui 1:fc2f9d636751 2150 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
yihui 1:fc2f9d636751 2151 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2152 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2153
yihui 1:fc2f9d636751 2154 /* Bit 17 : Pin 17. */
yihui 1:fc2f9d636751 2155 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
yihui 1:fc2f9d636751 2156 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
yihui 1:fc2f9d636751 2157 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2158 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2159
yihui 1:fc2f9d636751 2160 /* Bit 16 : Pin 16. */
yihui 1:fc2f9d636751 2161 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
yihui 1:fc2f9d636751 2162 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
yihui 1:fc2f9d636751 2163 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2164 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2165
yihui 1:fc2f9d636751 2166 /* Bit 15 : Pin 15. */
yihui 1:fc2f9d636751 2167 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
yihui 1:fc2f9d636751 2168 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
yihui 1:fc2f9d636751 2169 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2170 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2171
yihui 1:fc2f9d636751 2172 /* Bit 14 : Pin 14. */
yihui 1:fc2f9d636751 2173 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
yihui 1:fc2f9d636751 2174 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
yihui 1:fc2f9d636751 2175 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2176 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2177
yihui 1:fc2f9d636751 2178 /* Bit 13 : Pin 13. */
yihui 1:fc2f9d636751 2179 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
yihui 1:fc2f9d636751 2180 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
yihui 1:fc2f9d636751 2181 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2182 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2183
yihui 1:fc2f9d636751 2184 /* Bit 12 : Pin 12. */
yihui 1:fc2f9d636751 2185 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
yihui 1:fc2f9d636751 2186 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
yihui 1:fc2f9d636751 2187 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2188 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2189
yihui 1:fc2f9d636751 2190 /* Bit 11 : Pin 11. */
yihui 1:fc2f9d636751 2191 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
yihui 1:fc2f9d636751 2192 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
yihui 1:fc2f9d636751 2193 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2194 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2195
yihui 1:fc2f9d636751 2196 /* Bit 10 : Pin 10. */
yihui 1:fc2f9d636751 2197 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
yihui 1:fc2f9d636751 2198 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
yihui 1:fc2f9d636751 2199 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2200 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2201
yihui 1:fc2f9d636751 2202 /* Bit 9 : Pin 9. */
yihui 1:fc2f9d636751 2203 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
yihui 1:fc2f9d636751 2204 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
yihui 1:fc2f9d636751 2205 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2206 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2207
yihui 1:fc2f9d636751 2208 /* Bit 8 : Pin 8. */
yihui 1:fc2f9d636751 2209 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
yihui 1:fc2f9d636751 2210 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
yihui 1:fc2f9d636751 2211 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2212 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2213
yihui 1:fc2f9d636751 2214 /* Bit 7 : Pin 7. */
yihui 1:fc2f9d636751 2215 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
yihui 1:fc2f9d636751 2216 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
yihui 1:fc2f9d636751 2217 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2218 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2219
yihui 1:fc2f9d636751 2220 /* Bit 6 : Pin 6. */
yihui 1:fc2f9d636751 2221 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
yihui 1:fc2f9d636751 2222 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
yihui 1:fc2f9d636751 2223 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2224 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2225
yihui 1:fc2f9d636751 2226 /* Bit 5 : Pin 5. */
yihui 1:fc2f9d636751 2227 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
yihui 1:fc2f9d636751 2228 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
yihui 1:fc2f9d636751 2229 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2230 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2231
yihui 1:fc2f9d636751 2232 /* Bit 4 : Pin 4. */
yihui 1:fc2f9d636751 2233 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
yihui 1:fc2f9d636751 2234 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
yihui 1:fc2f9d636751 2235 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2236 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2237
yihui 1:fc2f9d636751 2238 /* Bit 3 : Pin 3. */
yihui 1:fc2f9d636751 2239 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
yihui 1:fc2f9d636751 2240 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
yihui 1:fc2f9d636751 2241 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2242 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2243
yihui 1:fc2f9d636751 2244 /* Bit 2 : Pin 2. */
yihui 1:fc2f9d636751 2245 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
yihui 1:fc2f9d636751 2246 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
yihui 1:fc2f9d636751 2247 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2248 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2249
yihui 1:fc2f9d636751 2250 /* Bit 1 : Pin 1. */
yihui 1:fc2f9d636751 2251 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
yihui 1:fc2f9d636751 2252 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
yihui 1:fc2f9d636751 2253 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2254 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2255
yihui 1:fc2f9d636751 2256 /* Bit 0 : Pin 0. */
yihui 1:fc2f9d636751 2257 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
yihui 1:fc2f9d636751 2258 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
yihui 1:fc2f9d636751 2259 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2260 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2261
yihui 1:fc2f9d636751 2262 /* Register: GPIO_DIRSET */
yihui 1:fc2f9d636751 2263 /* Description: DIR set register. */
yihui 1:fc2f9d636751 2264
yihui 1:fc2f9d636751 2265 /* Bit 31 : Set as output pin 31. */
yihui 1:fc2f9d636751 2266 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
yihui 1:fc2f9d636751 2267 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
yihui 1:fc2f9d636751 2268 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2269 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2270 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2271
yihui 1:fc2f9d636751 2272 /* Bit 30 : Set as output pin 30. */
yihui 1:fc2f9d636751 2273 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
yihui 1:fc2f9d636751 2274 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
yihui 1:fc2f9d636751 2275 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2276 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2277 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2278
yihui 1:fc2f9d636751 2279 /* Bit 29 : Set as output pin 29. */
yihui 1:fc2f9d636751 2280 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
yihui 1:fc2f9d636751 2281 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
yihui 1:fc2f9d636751 2282 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2283 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2284 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2285
yihui 1:fc2f9d636751 2286 /* Bit 28 : Set as output pin 28. */
yihui 1:fc2f9d636751 2287 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
yihui 1:fc2f9d636751 2288 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
yihui 1:fc2f9d636751 2289 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2290 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2291 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2292
yihui 1:fc2f9d636751 2293 /* Bit 27 : Set as output pin 27. */
yihui 1:fc2f9d636751 2294 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
yihui 1:fc2f9d636751 2295 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
yihui 1:fc2f9d636751 2296 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2297 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2298 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2299
yihui 1:fc2f9d636751 2300 /* Bit 26 : Set as output pin 26. */
yihui 1:fc2f9d636751 2301 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
yihui 1:fc2f9d636751 2302 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
yihui 1:fc2f9d636751 2303 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2304 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2305 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2306
yihui 1:fc2f9d636751 2307 /* Bit 25 : Set as output pin 25. */
yihui 1:fc2f9d636751 2308 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
yihui 1:fc2f9d636751 2309 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
yihui 1:fc2f9d636751 2310 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2311 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2312 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2313
yihui 1:fc2f9d636751 2314 /* Bit 24 : Set as output pin 24. */
yihui 1:fc2f9d636751 2315 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
yihui 1:fc2f9d636751 2316 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
yihui 1:fc2f9d636751 2317 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2318 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2319 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2320
yihui 1:fc2f9d636751 2321 /* Bit 23 : Set as output pin 23. */
yihui 1:fc2f9d636751 2322 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
yihui 1:fc2f9d636751 2323 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
yihui 1:fc2f9d636751 2324 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2325 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2326 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2327
yihui 1:fc2f9d636751 2328 /* Bit 22 : Set as output pin 22. */
yihui 1:fc2f9d636751 2329 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
yihui 1:fc2f9d636751 2330 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
yihui 1:fc2f9d636751 2331 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2332 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2333 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2334
yihui 1:fc2f9d636751 2335 /* Bit 21 : Set as output pin 21. */
yihui 1:fc2f9d636751 2336 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
yihui 1:fc2f9d636751 2337 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
yihui 1:fc2f9d636751 2338 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2339 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2340 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2341
yihui 1:fc2f9d636751 2342 /* Bit 20 : Set as output pin 20. */
yihui 1:fc2f9d636751 2343 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
yihui 1:fc2f9d636751 2344 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
yihui 1:fc2f9d636751 2345 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2346 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2347 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2348
yihui 1:fc2f9d636751 2349 /* Bit 19 : Set as output pin 19. */
yihui 1:fc2f9d636751 2350 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
yihui 1:fc2f9d636751 2351 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
yihui 1:fc2f9d636751 2352 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2353 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2354 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2355
yihui 1:fc2f9d636751 2356 /* Bit 18 : Set as output pin 18. */
yihui 1:fc2f9d636751 2357 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
yihui 1:fc2f9d636751 2358 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
yihui 1:fc2f9d636751 2359 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2360 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2361 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2362
yihui 1:fc2f9d636751 2363 /* Bit 17 : Set as output pin 17. */
yihui 1:fc2f9d636751 2364 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
yihui 1:fc2f9d636751 2365 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
yihui 1:fc2f9d636751 2366 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2367 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2368 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2369
yihui 1:fc2f9d636751 2370 /* Bit 16 : Set as output pin 16. */
yihui 1:fc2f9d636751 2371 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
yihui 1:fc2f9d636751 2372 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
yihui 1:fc2f9d636751 2373 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2374 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2375 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2376
yihui 1:fc2f9d636751 2377 /* Bit 15 : Set as output pin 15. */
yihui 1:fc2f9d636751 2378 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
yihui 1:fc2f9d636751 2379 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
yihui 1:fc2f9d636751 2380 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2381 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2382 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2383
yihui 1:fc2f9d636751 2384 /* Bit 14 : Set as output pin 14. */
yihui 1:fc2f9d636751 2385 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
yihui 1:fc2f9d636751 2386 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
yihui 1:fc2f9d636751 2387 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2388 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2389 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2390
yihui 1:fc2f9d636751 2391 /* Bit 13 : Set as output pin 13. */
yihui 1:fc2f9d636751 2392 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
yihui 1:fc2f9d636751 2393 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
yihui 1:fc2f9d636751 2394 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2395 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2396 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2397
yihui 1:fc2f9d636751 2398 /* Bit 12 : Set as output pin 12. */
yihui 1:fc2f9d636751 2399 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
yihui 1:fc2f9d636751 2400 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
yihui 1:fc2f9d636751 2401 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2402 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2403 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2404
yihui 1:fc2f9d636751 2405 /* Bit 11 : Set as output pin 11. */
yihui 1:fc2f9d636751 2406 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
yihui 1:fc2f9d636751 2407 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
yihui 1:fc2f9d636751 2408 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2409 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2410 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2411
yihui 1:fc2f9d636751 2412 /* Bit 10 : Set as output pin 10. */
yihui 1:fc2f9d636751 2413 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
yihui 1:fc2f9d636751 2414 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
yihui 1:fc2f9d636751 2415 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2416 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2417 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2418
yihui 1:fc2f9d636751 2419 /* Bit 9 : Set as output pin 9. */
yihui 1:fc2f9d636751 2420 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
yihui 1:fc2f9d636751 2421 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
yihui 1:fc2f9d636751 2422 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2423 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2424 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2425
yihui 1:fc2f9d636751 2426 /* Bit 8 : Set as output pin 8. */
yihui 1:fc2f9d636751 2427 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
yihui 1:fc2f9d636751 2428 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
yihui 1:fc2f9d636751 2429 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2430 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2431 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2432
yihui 1:fc2f9d636751 2433 /* Bit 7 : Set as output pin 7. */
yihui 1:fc2f9d636751 2434 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
yihui 1:fc2f9d636751 2435 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
yihui 1:fc2f9d636751 2436 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2437 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2438 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2439
yihui 1:fc2f9d636751 2440 /* Bit 6 : Set as output pin 6. */
yihui 1:fc2f9d636751 2441 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
yihui 1:fc2f9d636751 2442 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
yihui 1:fc2f9d636751 2443 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2444 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2445 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2446
yihui 1:fc2f9d636751 2447 /* Bit 5 : Set as output pin 5. */
yihui 1:fc2f9d636751 2448 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
yihui 1:fc2f9d636751 2449 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
yihui 1:fc2f9d636751 2450 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2451 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2452 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2453
yihui 1:fc2f9d636751 2454 /* Bit 4 : Set as output pin 4. */
yihui 1:fc2f9d636751 2455 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
yihui 1:fc2f9d636751 2456 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
yihui 1:fc2f9d636751 2457 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2458 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2459 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2460
yihui 1:fc2f9d636751 2461 /* Bit 3 : Set as output pin 3. */
yihui 1:fc2f9d636751 2462 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
yihui 1:fc2f9d636751 2463 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
yihui 1:fc2f9d636751 2464 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2465 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2466 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2467
yihui 1:fc2f9d636751 2468 /* Bit 2 : Set as output pin 2. */
yihui 1:fc2f9d636751 2469 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
yihui 1:fc2f9d636751 2470 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
yihui 1:fc2f9d636751 2471 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2472 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2473 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2474
yihui 1:fc2f9d636751 2475 /* Bit 1 : Set as output pin 1. */
yihui 1:fc2f9d636751 2476 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
yihui 1:fc2f9d636751 2477 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
yihui 1:fc2f9d636751 2478 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2479 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2480 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2481
yihui 1:fc2f9d636751 2482 /* Bit 0 : Set as output pin 0. */
yihui 1:fc2f9d636751 2483 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
yihui 1:fc2f9d636751 2484 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
yihui 1:fc2f9d636751 2485 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2486 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2487 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
yihui 1:fc2f9d636751 2488
yihui 1:fc2f9d636751 2489 /* Register: GPIO_DIRCLR */
yihui 1:fc2f9d636751 2490 /* Description: DIR clear register. */
yihui 1:fc2f9d636751 2491
yihui 1:fc2f9d636751 2492 /* Bit 31 : Set as input pin 31. */
yihui 1:fc2f9d636751 2493 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
yihui 1:fc2f9d636751 2494 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
yihui 1:fc2f9d636751 2495 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2496 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2497 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2498
yihui 1:fc2f9d636751 2499 /* Bit 30 : Set as input pin 30. */
yihui 1:fc2f9d636751 2500 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
yihui 1:fc2f9d636751 2501 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
yihui 1:fc2f9d636751 2502 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2503 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2504 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2505
yihui 1:fc2f9d636751 2506 /* Bit 29 : Set as input pin 29. */
yihui 1:fc2f9d636751 2507 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
yihui 1:fc2f9d636751 2508 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
yihui 1:fc2f9d636751 2509 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2510 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2511 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2512
yihui 1:fc2f9d636751 2513 /* Bit 28 : Set as input pin 28. */
yihui 1:fc2f9d636751 2514 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
yihui 1:fc2f9d636751 2515 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
yihui 1:fc2f9d636751 2516 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2517 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2518 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2519
yihui 1:fc2f9d636751 2520 /* Bit 27 : Set as input pin 27. */
yihui 1:fc2f9d636751 2521 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
yihui 1:fc2f9d636751 2522 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
yihui 1:fc2f9d636751 2523 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2524 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2525 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2526
yihui 1:fc2f9d636751 2527 /* Bit 26 : Set as input pin 26. */
yihui 1:fc2f9d636751 2528 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
yihui 1:fc2f9d636751 2529 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
yihui 1:fc2f9d636751 2530 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2531 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2532 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2533
yihui 1:fc2f9d636751 2534 /* Bit 25 : Set as input pin 25. */
yihui 1:fc2f9d636751 2535 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
yihui 1:fc2f9d636751 2536 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
yihui 1:fc2f9d636751 2537 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2538 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2539 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2540
yihui 1:fc2f9d636751 2541 /* Bit 24 : Set as input pin 24. */
yihui 1:fc2f9d636751 2542 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
yihui 1:fc2f9d636751 2543 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
yihui 1:fc2f9d636751 2544 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2545 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2546 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2547
yihui 1:fc2f9d636751 2548 /* Bit 23 : Set as input pin 23. */
yihui 1:fc2f9d636751 2549 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
yihui 1:fc2f9d636751 2550 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
yihui 1:fc2f9d636751 2551 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2552 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2553 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2554
yihui 1:fc2f9d636751 2555 /* Bit 22 : Set as input pin 22. */
yihui 1:fc2f9d636751 2556 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
yihui 1:fc2f9d636751 2557 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
yihui 1:fc2f9d636751 2558 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2559 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2560 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2561
yihui 1:fc2f9d636751 2562 /* Bit 21 : Set as input pin 21. */
yihui 1:fc2f9d636751 2563 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
yihui 1:fc2f9d636751 2564 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
yihui 1:fc2f9d636751 2565 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2566 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2567 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2568
yihui 1:fc2f9d636751 2569 /* Bit 20 : Set as input pin 20. */
yihui 1:fc2f9d636751 2570 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
yihui 1:fc2f9d636751 2571 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
yihui 1:fc2f9d636751 2572 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2573 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2574 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2575
yihui 1:fc2f9d636751 2576 /* Bit 19 : Set as input pin 19. */
yihui 1:fc2f9d636751 2577 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
yihui 1:fc2f9d636751 2578 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
yihui 1:fc2f9d636751 2579 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2580 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2581 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2582
yihui 1:fc2f9d636751 2583 /* Bit 18 : Set as input pin 18. */
yihui 1:fc2f9d636751 2584 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
yihui 1:fc2f9d636751 2585 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
yihui 1:fc2f9d636751 2586 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2587 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2588 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2589
yihui 1:fc2f9d636751 2590 /* Bit 17 : Set as input pin 17. */
yihui 1:fc2f9d636751 2591 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
yihui 1:fc2f9d636751 2592 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
yihui 1:fc2f9d636751 2593 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2594 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2595 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2596
yihui 1:fc2f9d636751 2597 /* Bit 16 : Set as input pin 16. */
yihui 1:fc2f9d636751 2598 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
yihui 1:fc2f9d636751 2599 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
yihui 1:fc2f9d636751 2600 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2601 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2602 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2603
yihui 1:fc2f9d636751 2604 /* Bit 15 : Set as input pin 15. */
yihui 1:fc2f9d636751 2605 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
yihui 1:fc2f9d636751 2606 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
yihui 1:fc2f9d636751 2607 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2608 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2609 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2610
yihui 1:fc2f9d636751 2611 /* Bit 14 : Set as input pin 14. */
yihui 1:fc2f9d636751 2612 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
yihui 1:fc2f9d636751 2613 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
yihui 1:fc2f9d636751 2614 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2615 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2616 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2617
yihui 1:fc2f9d636751 2618 /* Bit 13 : Set as input pin 13. */
yihui 1:fc2f9d636751 2619 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
yihui 1:fc2f9d636751 2620 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
yihui 1:fc2f9d636751 2621 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2622 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2623 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2624
yihui 1:fc2f9d636751 2625 /* Bit 12 : Set as input pin 12. */
yihui 1:fc2f9d636751 2626 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
yihui 1:fc2f9d636751 2627 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
yihui 1:fc2f9d636751 2628 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2629 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2630 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2631
yihui 1:fc2f9d636751 2632 /* Bit 11 : Set as input pin 11. */
yihui 1:fc2f9d636751 2633 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
yihui 1:fc2f9d636751 2634 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
yihui 1:fc2f9d636751 2635 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2636 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2637 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2638
yihui 1:fc2f9d636751 2639 /* Bit 10 : Set as input pin 10. */
yihui 1:fc2f9d636751 2640 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
yihui 1:fc2f9d636751 2641 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
yihui 1:fc2f9d636751 2642 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2643 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2644 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2645
yihui 1:fc2f9d636751 2646 /* Bit 9 : Set as input pin 9. */
yihui 1:fc2f9d636751 2647 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
yihui 1:fc2f9d636751 2648 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
yihui 1:fc2f9d636751 2649 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2650 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2651 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2652
yihui 1:fc2f9d636751 2653 /* Bit 8 : Set as input pin 8. */
yihui 1:fc2f9d636751 2654 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
yihui 1:fc2f9d636751 2655 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
yihui 1:fc2f9d636751 2656 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2657 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2658 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2659
yihui 1:fc2f9d636751 2660 /* Bit 7 : Set as input pin 7. */
yihui 1:fc2f9d636751 2661 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
yihui 1:fc2f9d636751 2662 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
yihui 1:fc2f9d636751 2663 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2664 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2665 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2666
yihui 1:fc2f9d636751 2667 /* Bit 6 : Set as input pin 6. */
yihui 1:fc2f9d636751 2668 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
yihui 1:fc2f9d636751 2669 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
yihui 1:fc2f9d636751 2670 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2671 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2672 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2673
yihui 1:fc2f9d636751 2674 /* Bit 5 : Set as input pin 5. */
yihui 1:fc2f9d636751 2675 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
yihui 1:fc2f9d636751 2676 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
yihui 1:fc2f9d636751 2677 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2678 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2679 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2680
yihui 1:fc2f9d636751 2681 /* Bit 4 : Set as input pin 4. */
yihui 1:fc2f9d636751 2682 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
yihui 1:fc2f9d636751 2683 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
yihui 1:fc2f9d636751 2684 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2685 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2686 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2687
yihui 1:fc2f9d636751 2688 /* Bit 3 : Set as input pin 3. */
yihui 1:fc2f9d636751 2689 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
yihui 1:fc2f9d636751 2690 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
yihui 1:fc2f9d636751 2691 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2692 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2693 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2694
yihui 1:fc2f9d636751 2695 /* Bit 2 : Set as input pin 2. */
yihui 1:fc2f9d636751 2696 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
yihui 1:fc2f9d636751 2697 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
yihui 1:fc2f9d636751 2698 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2699 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2700 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2701
yihui 1:fc2f9d636751 2702 /* Bit 1 : Set as input pin 1. */
yihui 1:fc2f9d636751 2703 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
yihui 1:fc2f9d636751 2704 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
yihui 1:fc2f9d636751 2705 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2706 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2707 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2708
yihui 1:fc2f9d636751 2709 /* Bit 0 : Set as input pin 0. */
yihui 1:fc2f9d636751 2710 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
yihui 1:fc2f9d636751 2711 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
yihui 1:fc2f9d636751 2712 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
yihui 1:fc2f9d636751 2713 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
yihui 1:fc2f9d636751 2714 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
yihui 1:fc2f9d636751 2715
yihui 1:fc2f9d636751 2716 /* Register: GPIO_PIN_CNF */
yihui 1:fc2f9d636751 2717 /* Description: Configuration of GPIO pins. */
yihui 1:fc2f9d636751 2718
yihui 1:fc2f9d636751 2719 /* Bits 17..16 : Pin sensing mechanism. */
yihui 1:fc2f9d636751 2720 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
yihui 1:fc2f9d636751 2721 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
yihui 1:fc2f9d636751 2722 #define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
yihui 1:fc2f9d636751 2723 #define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
yihui 1:fc2f9d636751 2724 #define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
yihui 1:fc2f9d636751 2725
yihui 1:fc2f9d636751 2726 /* Bits 10..8 : Drive configuration. */
yihui 1:fc2f9d636751 2727 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
yihui 1:fc2f9d636751 2728 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
yihui 1:fc2f9d636751 2729 #define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
yihui 1:fc2f9d636751 2730 #define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
yihui 1:fc2f9d636751 2731 #define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
yihui 1:fc2f9d636751 2732 #define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
yihui 1:fc2f9d636751 2733 #define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
yihui 1:fc2f9d636751 2734 #define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
yihui 1:fc2f9d636751 2735 #define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
yihui 1:fc2f9d636751 2736 #define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
yihui 1:fc2f9d636751 2737
yihui 1:fc2f9d636751 2738 /* Bits 3..2 : Pull-up or -down configuration. */
yihui 1:fc2f9d636751 2739 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
yihui 1:fc2f9d636751 2740 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
yihui 1:fc2f9d636751 2741 #define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
yihui 1:fc2f9d636751 2742 #define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
yihui 1:fc2f9d636751 2743 #define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
yihui 1:fc2f9d636751 2744
yihui 1:fc2f9d636751 2745 /* Bit 1 : Connect or disconnect input path. */
yihui 1:fc2f9d636751 2746 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
yihui 1:fc2f9d636751 2747 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
yihui 1:fc2f9d636751 2748 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
yihui 1:fc2f9d636751 2749 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
yihui 1:fc2f9d636751 2750
yihui 1:fc2f9d636751 2751 /* Bit 0 : Pin direction. */
yihui 1:fc2f9d636751 2752 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
yihui 1:fc2f9d636751 2753 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
yihui 1:fc2f9d636751 2754 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
yihui 1:fc2f9d636751 2755 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
yihui 1:fc2f9d636751 2756
yihui 1:fc2f9d636751 2757
yihui 1:fc2f9d636751 2758 /* Peripheral: GPIOTE */
yihui 1:fc2f9d636751 2759 /* Description: GPIO tasks and events. */
yihui 1:fc2f9d636751 2760
yihui 1:fc2f9d636751 2761 /* Register: GPIOTE_INTENSET */
yihui 1:fc2f9d636751 2762 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 2763
yihui 1:fc2f9d636751 2764 /* Bit 31 : Enable interrupt on PORT event. */
yihui 1:fc2f9d636751 2765 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
yihui 1:fc2f9d636751 2766 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
yihui 1:fc2f9d636751 2767 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2768 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2769 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 2770
yihui 1:fc2f9d636751 2771 /* Bit 3 : Enable interrupt on IN[3] event. */
yihui 1:fc2f9d636751 2772 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
yihui 1:fc2f9d636751 2773 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
yihui 1:fc2f9d636751 2774 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2775 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2776 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 2777
yihui 1:fc2f9d636751 2778 /* Bit 2 : Enable interrupt on IN[2] event. */
yihui 1:fc2f9d636751 2779 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
yihui 1:fc2f9d636751 2780 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
yihui 1:fc2f9d636751 2781 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2782 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2783 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 2784
yihui 1:fc2f9d636751 2785 /* Bit 1 : Enable interrupt on IN[1] event. */
yihui 1:fc2f9d636751 2786 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
yihui 1:fc2f9d636751 2787 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
yihui 1:fc2f9d636751 2788 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2789 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2790 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 2791
yihui 1:fc2f9d636751 2792 /* Bit 0 : Enable interrupt on IN[0] event. */
yihui 1:fc2f9d636751 2793 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
yihui 1:fc2f9d636751 2794 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
yihui 1:fc2f9d636751 2795 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2796 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2797 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 2798
yihui 1:fc2f9d636751 2799 /* Register: GPIOTE_INTENCLR */
yihui 1:fc2f9d636751 2800 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 2801
yihui 1:fc2f9d636751 2802 /* Bit 31 : Disable interrupt on PORT event. */
yihui 1:fc2f9d636751 2803 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
yihui 1:fc2f9d636751 2804 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
yihui 1:fc2f9d636751 2805 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2806 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2807 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 2808
yihui 1:fc2f9d636751 2809 /* Bit 3 : Disable interrupt on IN[3] event. */
yihui 1:fc2f9d636751 2810 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
yihui 1:fc2f9d636751 2811 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
yihui 1:fc2f9d636751 2812 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2813 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2814 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 2815
yihui 1:fc2f9d636751 2816 /* Bit 2 : Disable interrupt on IN[2] event. */
yihui 1:fc2f9d636751 2817 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
yihui 1:fc2f9d636751 2818 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
yihui 1:fc2f9d636751 2819 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2820 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2821 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 2822
yihui 1:fc2f9d636751 2823 /* Bit 1 : Disable interrupt on IN[1] event. */
yihui 1:fc2f9d636751 2824 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
yihui 1:fc2f9d636751 2825 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
yihui 1:fc2f9d636751 2826 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2827 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2828 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 2829
yihui 1:fc2f9d636751 2830 /* Bit 0 : Disable interrupt on IN[0] event. */
yihui 1:fc2f9d636751 2831 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
yihui 1:fc2f9d636751 2832 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
yihui 1:fc2f9d636751 2833 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2834 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2835 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 2836
yihui 1:fc2f9d636751 2837 /* Register: GPIOTE_CONFIG */
yihui 1:fc2f9d636751 2838 /* Description: Channel configuration registers. */
yihui 1:fc2f9d636751 2839
yihui 1:fc2f9d636751 2840 /* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
yihui 1:fc2f9d636751 2841 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
yihui 1:fc2f9d636751 2842 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
yihui 1:fc2f9d636751 2843 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
yihui 1:fc2f9d636751 2844 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
yihui 1:fc2f9d636751 2845
yihui 1:fc2f9d636751 2846 /* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
yihui 1:fc2f9d636751 2847 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
yihui 1:fc2f9d636751 2848 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
yihui 1:fc2f9d636751 2849 #define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
yihui 1:fc2f9d636751 2850 #define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
yihui 1:fc2f9d636751 2851 #define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
yihui 1:fc2f9d636751 2852
yihui 1:fc2f9d636751 2853 /* Bits 12..8 : Pin select. */
yihui 1:fc2f9d636751 2854 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
yihui 1:fc2f9d636751 2855 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
yihui 1:fc2f9d636751 2856
yihui 1:fc2f9d636751 2857 /* Bits 1..0 : Mode */
yihui 1:fc2f9d636751 2858 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
yihui 1:fc2f9d636751 2859 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
yihui 1:fc2f9d636751 2860 #define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
yihui 1:fc2f9d636751 2861 #define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
yihui 1:fc2f9d636751 2862 #define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
yihui 1:fc2f9d636751 2863
yihui 1:fc2f9d636751 2864 /* Register: GPIOTE_POWER */
yihui 1:fc2f9d636751 2865 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 2866
yihui 1:fc2f9d636751 2867 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 2868 #define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 2869 #define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 2870 #define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 2871 #define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 2872
yihui 1:fc2f9d636751 2873
yihui 1:fc2f9d636751 2874 /* Peripheral: LPCOMP */
yihui 1:fc2f9d636751 2875 /* Description: Low power comparator. */
yihui 1:fc2f9d636751 2876
yihui 1:fc2f9d636751 2877 /* Register: LPCOMP_SHORTS */
yihui 1:fc2f9d636751 2878 /* Description: Shortcuts for the LPCOMP. */
yihui 1:fc2f9d636751 2879
yihui 1:fc2f9d636751 2880 /* Bit 4 : Shortcut between CROSS event and STOP task. */
yihui 1:fc2f9d636751 2881 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
yihui 1:fc2f9d636751 2882 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
yihui 1:fc2f9d636751 2883 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 2884 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 2885
yihui 1:fc2f9d636751 2886 /* Bit 3 : Shortcut between UP event and STOP task. */
yihui 1:fc2f9d636751 2887 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
yihui 1:fc2f9d636751 2888 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
yihui 1:fc2f9d636751 2889 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 2890 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 2891
yihui 1:fc2f9d636751 2892 /* Bit 2 : Shortcut between DOWN event and STOP task. */
yihui 1:fc2f9d636751 2893 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
yihui 1:fc2f9d636751 2894 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
yihui 1:fc2f9d636751 2895 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 2896 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 2897
yihui 1:fc2f9d636751 2898 /* Bit 1 : Shortcut between RADY event and STOP task. */
yihui 1:fc2f9d636751 2899 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
yihui 1:fc2f9d636751 2900 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
yihui 1:fc2f9d636751 2901 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 2902 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 2903
yihui 1:fc2f9d636751 2904 /* Bit 0 : Shortcut between READY event and SAMPLE task. */
yihui 1:fc2f9d636751 2905 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
yihui 1:fc2f9d636751 2906 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
yihui 1:fc2f9d636751 2907 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 2908 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 2909
yihui 1:fc2f9d636751 2910 /* Register: LPCOMP_INTENSET */
yihui 1:fc2f9d636751 2911 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 2912
yihui 1:fc2f9d636751 2913 /* Bit 3 : Enable interrupt on CROSS event. */
yihui 1:fc2f9d636751 2914 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
yihui 1:fc2f9d636751 2915 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
yihui 1:fc2f9d636751 2916 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2917 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2918 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 2919
yihui 1:fc2f9d636751 2920 /* Bit 2 : Enable interrupt on UP event. */
yihui 1:fc2f9d636751 2921 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
yihui 1:fc2f9d636751 2922 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
yihui 1:fc2f9d636751 2923 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2924 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2925 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 2926
yihui 1:fc2f9d636751 2927 /* Bit 1 : Enable interrupt on DOWN event. */
yihui 1:fc2f9d636751 2928 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
yihui 1:fc2f9d636751 2929 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
yihui 1:fc2f9d636751 2930 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2931 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2932 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 2933
yihui 1:fc2f9d636751 2934 /* Bit 0 : Enable interrupt on READY event. */
yihui 1:fc2f9d636751 2935 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
yihui 1:fc2f9d636751 2936 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
yihui 1:fc2f9d636751 2937 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2938 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2939 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 2940
yihui 1:fc2f9d636751 2941 /* Register: LPCOMP_INTENCLR */
yihui 1:fc2f9d636751 2942 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 2943
yihui 1:fc2f9d636751 2944 /* Bit 3 : Disable interrupt on CROSS event. */
yihui 1:fc2f9d636751 2945 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
yihui 1:fc2f9d636751 2946 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
yihui 1:fc2f9d636751 2947 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2948 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2949 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 2950
yihui 1:fc2f9d636751 2951 /* Bit 2 : Disable interrupt on UP event. */
yihui 1:fc2f9d636751 2952 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
yihui 1:fc2f9d636751 2953 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
yihui 1:fc2f9d636751 2954 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2955 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2956 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 2957
yihui 1:fc2f9d636751 2958 /* Bit 1 : Disable interrupt on DOWN event. */
yihui 1:fc2f9d636751 2959 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
yihui 1:fc2f9d636751 2960 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
yihui 1:fc2f9d636751 2961 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2962 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2963 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 2964
yihui 1:fc2f9d636751 2965 /* Bit 0 : Disable interrupt on READY event. */
yihui 1:fc2f9d636751 2966 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
yihui 1:fc2f9d636751 2967 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
yihui 1:fc2f9d636751 2968 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 2969 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 2970 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 2971
yihui 1:fc2f9d636751 2972 /* Register: LPCOMP_RESULT */
yihui 1:fc2f9d636751 2973 /* Description: Result of last compare. */
yihui 1:fc2f9d636751 2974
yihui 1:fc2f9d636751 2975 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
yihui 1:fc2f9d636751 2976 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
yihui 1:fc2f9d636751 2977 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
yihui 1:fc2f9d636751 2978 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
yihui 1:fc2f9d636751 2979 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
yihui 1:fc2f9d636751 2980
yihui 1:fc2f9d636751 2981 /* Register: LPCOMP_ENABLE */
yihui 1:fc2f9d636751 2982 /* Description: Enable the LPCOMP. */
yihui 1:fc2f9d636751 2983
yihui 1:fc2f9d636751 2984 /* Bits 1..0 : Enable or disable LPCOMP. */
yihui 1:fc2f9d636751 2985 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
yihui 1:fc2f9d636751 2986 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
yihui 1:fc2f9d636751 2987 #define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
yihui 1:fc2f9d636751 2988 #define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
yihui 1:fc2f9d636751 2989
yihui 1:fc2f9d636751 2990 /* Register: LPCOMP_PSEL */
yihui 1:fc2f9d636751 2991 /* Description: Input pin select. */
yihui 1:fc2f9d636751 2992
yihui 1:fc2f9d636751 2993 /* Bits 2..0 : Analog input pin select. */
yihui 1:fc2f9d636751 2994 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
yihui 1:fc2f9d636751 2995 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
yihui 1:fc2f9d636751 2996 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
yihui 1:fc2f9d636751 2997 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
yihui 1:fc2f9d636751 2998 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
yihui 1:fc2f9d636751 2999 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
yihui 1:fc2f9d636751 3000 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
yihui 1:fc2f9d636751 3001 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
yihui 1:fc2f9d636751 3002 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
yihui 1:fc2f9d636751 3003 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
yihui 1:fc2f9d636751 3004
yihui 1:fc2f9d636751 3005 /* Register: LPCOMP_REFSEL */
yihui 1:fc2f9d636751 3006 /* Description: Reference select. */
yihui 1:fc2f9d636751 3007
yihui 1:fc2f9d636751 3008 /* Bits 2..0 : Reference select. */
yihui 1:fc2f9d636751 3009 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
yihui 1:fc2f9d636751 3010 #define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
yihui 1:fc2f9d636751 3011 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */
yihui 1:fc2f9d636751 3012 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */
yihui 1:fc2f9d636751 3013 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */
yihui 1:fc2f9d636751 3014 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */
yihui 1:fc2f9d636751 3015 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */
yihui 1:fc2f9d636751 3016 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */
yihui 1:fc2f9d636751 3017 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */
yihui 1:fc2f9d636751 3018 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
yihui 1:fc2f9d636751 3019
yihui 1:fc2f9d636751 3020 /* Register: LPCOMP_EXTREFSEL */
yihui 1:fc2f9d636751 3021 /* Description: External reference select. */
yihui 1:fc2f9d636751 3022
yihui 1:fc2f9d636751 3023 /* Bit 0 : External analog reference pin selection. */
yihui 1:fc2f9d636751 3024 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
yihui 1:fc2f9d636751 3025 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
yihui 1:fc2f9d636751 3026 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
yihui 1:fc2f9d636751 3027 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
yihui 1:fc2f9d636751 3028
yihui 1:fc2f9d636751 3029 /* Register: LPCOMP_ANADETECT */
yihui 1:fc2f9d636751 3030 /* Description: Analog detect configuration. */
yihui 1:fc2f9d636751 3031
yihui 1:fc2f9d636751 3032 /* Bits 1..0 : Analog detect configuration. */
yihui 1:fc2f9d636751 3033 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
yihui 1:fc2f9d636751 3034 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
yihui 1:fc2f9d636751 3035 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
yihui 1:fc2f9d636751 3036 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
yihui 1:fc2f9d636751 3037 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
yihui 1:fc2f9d636751 3038
yihui 1:fc2f9d636751 3039 /* Register: LPCOMP_POWER */
yihui 1:fc2f9d636751 3040 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 3041
yihui 1:fc2f9d636751 3042 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 3043 #define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 3044 #define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 3045 #define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 3046 #define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 3047
yihui 1:fc2f9d636751 3048
yihui 1:fc2f9d636751 3049 /* Peripheral: MPU */
yihui 1:fc2f9d636751 3050 /* Description: Memory Protection Unit. */
yihui 1:fc2f9d636751 3051
yihui 1:fc2f9d636751 3052 /* Register: MPU_PERR0 */
yihui 1:fc2f9d636751 3053 /* Description: Configuration of peripherals in mpu regions. */
yihui 1:fc2f9d636751 3054
yihui 1:fc2f9d636751 3055 /* Bit 31 : PPI region configuration. */
yihui 1:fc2f9d636751 3056 #define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
yihui 1:fc2f9d636751 3057 #define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
yihui 1:fc2f9d636751 3058 #define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3059 #define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3060
yihui 1:fc2f9d636751 3061 /* Bit 30 : NVMC region configuration. */
yihui 1:fc2f9d636751 3062 #define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
yihui 1:fc2f9d636751 3063 #define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
yihui 1:fc2f9d636751 3064 #define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3065 #define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3066
yihui 1:fc2f9d636751 3067 /* Bit 19 : LPCOMP region configuration. */
yihui 1:fc2f9d636751 3068 #define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */
yihui 1:fc2f9d636751 3069 #define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
yihui 1:fc2f9d636751 3070 #define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3071 #define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3072
yihui 1:fc2f9d636751 3073 /* Bit 18 : QDEC region configuration. */
yihui 1:fc2f9d636751 3074 #define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
yihui 1:fc2f9d636751 3075 #define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
yihui 1:fc2f9d636751 3076 #define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3077 #define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3078
yihui 1:fc2f9d636751 3079 /* Bit 17 : RTC1 region configuration. */
yihui 1:fc2f9d636751 3080 #define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
yihui 1:fc2f9d636751 3081 #define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
yihui 1:fc2f9d636751 3082 #define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3083 #define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3084
yihui 1:fc2f9d636751 3085 /* Bit 16 : WDT region configuration. */
yihui 1:fc2f9d636751 3086 #define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
yihui 1:fc2f9d636751 3087 #define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
yihui 1:fc2f9d636751 3088 #define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3089 #define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3090
yihui 1:fc2f9d636751 3091 /* Bit 15 : CCM and AAR region configuration. */
yihui 1:fc2f9d636751 3092 #define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
yihui 1:fc2f9d636751 3093 #define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
yihui 1:fc2f9d636751 3094 #define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3095 #define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3096
yihui 1:fc2f9d636751 3097 /* Bit 14 : ECB region configuration. */
yihui 1:fc2f9d636751 3098 #define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
yihui 1:fc2f9d636751 3099 #define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
yihui 1:fc2f9d636751 3100 #define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3101 #define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3102
yihui 1:fc2f9d636751 3103 /* Bit 13 : RNG region configuration. */
yihui 1:fc2f9d636751 3104 #define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
yihui 1:fc2f9d636751 3105 #define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
yihui 1:fc2f9d636751 3106 #define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3107 #define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3108
yihui 1:fc2f9d636751 3109 /* Bit 12 : TEMP region configuration. */
yihui 1:fc2f9d636751 3110 #define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
yihui 1:fc2f9d636751 3111 #define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
yihui 1:fc2f9d636751 3112 #define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3113 #define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3114
yihui 1:fc2f9d636751 3115 /* Bit 11 : RTC0 region configuration. */
yihui 1:fc2f9d636751 3116 #define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
yihui 1:fc2f9d636751 3117 #define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
yihui 1:fc2f9d636751 3118 #define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3119 #define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3120
yihui 1:fc2f9d636751 3121 /* Bit 10 : TIMER2 region configuration. */
yihui 1:fc2f9d636751 3122 #define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
yihui 1:fc2f9d636751 3123 #define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
yihui 1:fc2f9d636751 3124 #define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3125 #define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3126
yihui 1:fc2f9d636751 3127 /* Bit 9 : TIMER1 region configuration. */
yihui 1:fc2f9d636751 3128 #define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
yihui 1:fc2f9d636751 3129 #define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
yihui 1:fc2f9d636751 3130 #define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3131 #define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3132
yihui 1:fc2f9d636751 3133 /* Bit 8 : TIMER0 region configuration. */
yihui 1:fc2f9d636751 3134 #define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
yihui 1:fc2f9d636751 3135 #define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
yihui 1:fc2f9d636751 3136 #define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3137 #define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3138
yihui 1:fc2f9d636751 3139 /* Bit 7 : ADC region configuration. */
yihui 1:fc2f9d636751 3140 #define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
yihui 1:fc2f9d636751 3141 #define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
yihui 1:fc2f9d636751 3142 #define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3143 #define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3144
yihui 1:fc2f9d636751 3145 /* Bit 6 : GPIOTE region configuration. */
yihui 1:fc2f9d636751 3146 #define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
yihui 1:fc2f9d636751 3147 #define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
yihui 1:fc2f9d636751 3148 #define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3149 #define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3150
yihui 1:fc2f9d636751 3151 /* Bit 4 : SPI1 and TWI1 region configuration. */
yihui 1:fc2f9d636751 3152 #define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
yihui 1:fc2f9d636751 3153 #define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
yihui 1:fc2f9d636751 3154 #define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3155 #define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3156
yihui 1:fc2f9d636751 3157 /* Bit 3 : SPI0 and TWI0 region configuration. */
yihui 1:fc2f9d636751 3158 #define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
yihui 1:fc2f9d636751 3159 #define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
yihui 1:fc2f9d636751 3160 #define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3161 #define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3162
yihui 1:fc2f9d636751 3163 /* Bit 2 : UART0 region configuration. */
yihui 1:fc2f9d636751 3164 #define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
yihui 1:fc2f9d636751 3165 #define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
yihui 1:fc2f9d636751 3166 #define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3167 #define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3168
yihui 1:fc2f9d636751 3169 /* Bit 1 : RADIO region configuration. */
yihui 1:fc2f9d636751 3170 #define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
yihui 1:fc2f9d636751 3171 #define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
yihui 1:fc2f9d636751 3172 #define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3173 #define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3174
yihui 1:fc2f9d636751 3175 /* Bit 0 : POWER_CLOCK region configuration. */
yihui 1:fc2f9d636751 3176 #define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
yihui 1:fc2f9d636751 3177 #define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
yihui 1:fc2f9d636751 3178 #define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
yihui 1:fc2f9d636751 3179 #define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
yihui 1:fc2f9d636751 3180
yihui 1:fc2f9d636751 3181 /* Register: MPU_PROTENSET0 */
yihui 1:fc2f9d636751 3182 /* Description: Erase and write protection bit enable set register. */
yihui 1:fc2f9d636751 3183
yihui 1:fc2f9d636751 3184 /* Bit 31 : Protection enable for region 31. */
yihui 1:fc2f9d636751 3185 #define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
yihui 1:fc2f9d636751 3186 #define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
yihui 1:fc2f9d636751 3187 #define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3188 #define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3189 #define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3190
yihui 1:fc2f9d636751 3191 /* Bit 30 : Protection enable for region 30. */
yihui 1:fc2f9d636751 3192 #define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
yihui 1:fc2f9d636751 3193 #define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
yihui 1:fc2f9d636751 3194 #define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3195 #define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3196 #define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3197
yihui 1:fc2f9d636751 3198 /* Bit 29 : Protection enable for region 29. */
yihui 1:fc2f9d636751 3199 #define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
yihui 1:fc2f9d636751 3200 #define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
yihui 1:fc2f9d636751 3201 #define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3202 #define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3203 #define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3204
yihui 1:fc2f9d636751 3205 /* Bit 28 : Protection enable for region 28. */
yihui 1:fc2f9d636751 3206 #define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
yihui 1:fc2f9d636751 3207 #define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
yihui 1:fc2f9d636751 3208 #define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3209 #define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3210 #define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3211
yihui 1:fc2f9d636751 3212 /* Bit 27 : Protection enable for region 27. */
yihui 1:fc2f9d636751 3213 #define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
yihui 1:fc2f9d636751 3214 #define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
yihui 1:fc2f9d636751 3215 #define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3216 #define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3217 #define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3218
yihui 1:fc2f9d636751 3219 /* Bit 26 : Protection enable for region 26. */
yihui 1:fc2f9d636751 3220 #define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
yihui 1:fc2f9d636751 3221 #define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
yihui 1:fc2f9d636751 3222 #define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3223 #define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3224 #define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3225
yihui 1:fc2f9d636751 3226 /* Bit 25 : Protection enable for region 25. */
yihui 1:fc2f9d636751 3227 #define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
yihui 1:fc2f9d636751 3228 #define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
yihui 1:fc2f9d636751 3229 #define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3230 #define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3231 #define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3232
yihui 1:fc2f9d636751 3233 /* Bit 24 : Protection enable for region 24. */
yihui 1:fc2f9d636751 3234 #define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
yihui 1:fc2f9d636751 3235 #define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
yihui 1:fc2f9d636751 3236 #define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3237 #define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3238 #define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3239
yihui 1:fc2f9d636751 3240 /* Bit 23 : Protection enable for region 23. */
yihui 1:fc2f9d636751 3241 #define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
yihui 1:fc2f9d636751 3242 #define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
yihui 1:fc2f9d636751 3243 #define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3244 #define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3245 #define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3246
yihui 1:fc2f9d636751 3247 /* Bit 22 : Protection enable for region 22. */
yihui 1:fc2f9d636751 3248 #define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
yihui 1:fc2f9d636751 3249 #define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
yihui 1:fc2f9d636751 3250 #define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3251 #define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3252 #define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3253
yihui 1:fc2f9d636751 3254 /* Bit 21 : Protection enable for region 21. */
yihui 1:fc2f9d636751 3255 #define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
yihui 1:fc2f9d636751 3256 #define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
yihui 1:fc2f9d636751 3257 #define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3258 #define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3259 #define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3260
yihui 1:fc2f9d636751 3261 /* Bit 20 : Protection enable for region 20. */
yihui 1:fc2f9d636751 3262 #define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
yihui 1:fc2f9d636751 3263 #define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
yihui 1:fc2f9d636751 3264 #define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3265 #define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3266 #define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3267
yihui 1:fc2f9d636751 3268 /* Bit 19 : Protection enable for region 19. */
yihui 1:fc2f9d636751 3269 #define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
yihui 1:fc2f9d636751 3270 #define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
yihui 1:fc2f9d636751 3271 #define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3272 #define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3273 #define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3274
yihui 1:fc2f9d636751 3275 /* Bit 18 : Protection enable for region 18. */
yihui 1:fc2f9d636751 3276 #define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
yihui 1:fc2f9d636751 3277 #define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
yihui 1:fc2f9d636751 3278 #define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3279 #define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3280 #define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3281
yihui 1:fc2f9d636751 3282 /* Bit 17 : Protection enable for region 17. */
yihui 1:fc2f9d636751 3283 #define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
yihui 1:fc2f9d636751 3284 #define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
yihui 1:fc2f9d636751 3285 #define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3286 #define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3287 #define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3288
yihui 1:fc2f9d636751 3289 /* Bit 16 : Protection enable for region 16. */
yihui 1:fc2f9d636751 3290 #define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
yihui 1:fc2f9d636751 3291 #define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
yihui 1:fc2f9d636751 3292 #define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3293 #define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3294 #define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3295
yihui 1:fc2f9d636751 3296 /* Bit 15 : Protection enable for region 15. */
yihui 1:fc2f9d636751 3297 #define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
yihui 1:fc2f9d636751 3298 #define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
yihui 1:fc2f9d636751 3299 #define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3300 #define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3301 #define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3302
yihui 1:fc2f9d636751 3303 /* Bit 14 : Protection enable for region 14. */
yihui 1:fc2f9d636751 3304 #define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
yihui 1:fc2f9d636751 3305 #define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
yihui 1:fc2f9d636751 3306 #define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3307 #define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3308 #define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3309
yihui 1:fc2f9d636751 3310 /* Bit 13 : Protection enable for region 13. */
yihui 1:fc2f9d636751 3311 #define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
yihui 1:fc2f9d636751 3312 #define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
yihui 1:fc2f9d636751 3313 #define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3314 #define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3315 #define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3316
yihui 1:fc2f9d636751 3317 /* Bit 12 : Protection enable for region 12. */
yihui 1:fc2f9d636751 3318 #define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
yihui 1:fc2f9d636751 3319 #define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
yihui 1:fc2f9d636751 3320 #define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3321 #define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3322 #define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3323
yihui 1:fc2f9d636751 3324 /* Bit 11 : Protection enable for region 11. */
yihui 1:fc2f9d636751 3325 #define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
yihui 1:fc2f9d636751 3326 #define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
yihui 1:fc2f9d636751 3327 #define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3328 #define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3329 #define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3330
yihui 1:fc2f9d636751 3331 /* Bit 10 : Protection enable for region 10. */
yihui 1:fc2f9d636751 3332 #define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
yihui 1:fc2f9d636751 3333 #define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
yihui 1:fc2f9d636751 3334 #define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3335 #define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3336 #define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3337
yihui 1:fc2f9d636751 3338 /* Bit 9 : Protection enable for region 9. */
yihui 1:fc2f9d636751 3339 #define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
yihui 1:fc2f9d636751 3340 #define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
yihui 1:fc2f9d636751 3341 #define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3342 #define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3343 #define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3344
yihui 1:fc2f9d636751 3345 /* Bit 8 : Protection enable for region 8. */
yihui 1:fc2f9d636751 3346 #define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
yihui 1:fc2f9d636751 3347 #define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
yihui 1:fc2f9d636751 3348 #define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3349 #define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3350 #define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3351
yihui 1:fc2f9d636751 3352 /* Bit 7 : Protection enable for region 7. */
yihui 1:fc2f9d636751 3353 #define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
yihui 1:fc2f9d636751 3354 #define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
yihui 1:fc2f9d636751 3355 #define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3356 #define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3357 #define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3358
yihui 1:fc2f9d636751 3359 /* Bit 6 : Protection enable for region 6. */
yihui 1:fc2f9d636751 3360 #define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
yihui 1:fc2f9d636751 3361 #define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
yihui 1:fc2f9d636751 3362 #define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3363 #define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3364 #define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3365
yihui 1:fc2f9d636751 3366 /* Bit 5 : Protection enable for region 5. */
yihui 1:fc2f9d636751 3367 #define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
yihui 1:fc2f9d636751 3368 #define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
yihui 1:fc2f9d636751 3369 #define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3370 #define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3371 #define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3372
yihui 1:fc2f9d636751 3373 /* Bit 4 : Protection enable for region 4. */
yihui 1:fc2f9d636751 3374 #define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
yihui 1:fc2f9d636751 3375 #define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
yihui 1:fc2f9d636751 3376 #define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3377 #define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3378 #define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3379
yihui 1:fc2f9d636751 3380 /* Bit 3 : Protection enable for region 3. */
yihui 1:fc2f9d636751 3381 #define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
yihui 1:fc2f9d636751 3382 #define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
yihui 1:fc2f9d636751 3383 #define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3384 #define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3385 #define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3386
yihui 1:fc2f9d636751 3387 /* Bit 2 : Protection enable for region 2. */
yihui 1:fc2f9d636751 3388 #define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
yihui 1:fc2f9d636751 3389 #define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
yihui 1:fc2f9d636751 3390 #define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3391 #define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3392 #define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3393
yihui 1:fc2f9d636751 3394 /* Bit 1 : Protection enable for region 1. */
yihui 1:fc2f9d636751 3395 #define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
yihui 1:fc2f9d636751 3396 #define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
yihui 1:fc2f9d636751 3397 #define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3398 #define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3399 #define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3400
yihui 1:fc2f9d636751 3401 /* Bit 0 : Protection enable for region 0. */
yihui 1:fc2f9d636751 3402 #define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
yihui 1:fc2f9d636751 3403 #define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
yihui 1:fc2f9d636751 3404 #define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3405 #define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3406 #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3407
yihui 1:fc2f9d636751 3408 /* Register: MPU_PROTENSET1 */
yihui 1:fc2f9d636751 3409 /* Description: Erase and write protection bit enable set register. */
yihui 1:fc2f9d636751 3410
yihui 1:fc2f9d636751 3411 /* Bit 31 : Protection enable for region 63. */
yihui 1:fc2f9d636751 3412 #define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
yihui 1:fc2f9d636751 3413 #define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
yihui 1:fc2f9d636751 3414 #define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3415 #define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3416 #define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3417
yihui 1:fc2f9d636751 3418 /* Bit 30 : Protection enable for region 62. */
yihui 1:fc2f9d636751 3419 #define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
yihui 1:fc2f9d636751 3420 #define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
yihui 1:fc2f9d636751 3421 #define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3422 #define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3423 #define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3424
yihui 1:fc2f9d636751 3425 /* Bit 29 : Protection enable for region 61. */
yihui 1:fc2f9d636751 3426 #define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
yihui 1:fc2f9d636751 3427 #define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
yihui 1:fc2f9d636751 3428 #define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3429 #define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3430 #define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3431
yihui 1:fc2f9d636751 3432 /* Bit 28 : Protection enable for region 60. */
yihui 1:fc2f9d636751 3433 #define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
yihui 1:fc2f9d636751 3434 #define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
yihui 1:fc2f9d636751 3435 #define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3436 #define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3437 #define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3438
yihui 1:fc2f9d636751 3439 /* Bit 27 : Protection enable for region 59. */
yihui 1:fc2f9d636751 3440 #define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
yihui 1:fc2f9d636751 3441 #define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
yihui 1:fc2f9d636751 3442 #define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3443 #define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3444 #define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3445
yihui 1:fc2f9d636751 3446 /* Bit 26 : Protection enable for region 58. */
yihui 1:fc2f9d636751 3447 #define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
yihui 1:fc2f9d636751 3448 #define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
yihui 1:fc2f9d636751 3449 #define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3450 #define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3451 #define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3452
yihui 1:fc2f9d636751 3453 /* Bit 25 : Protection enable for region 57. */
yihui 1:fc2f9d636751 3454 #define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
yihui 1:fc2f9d636751 3455 #define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
yihui 1:fc2f9d636751 3456 #define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3457 #define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3458 #define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3459
yihui 1:fc2f9d636751 3460 /* Bit 24 : Protection enable for region 56. */
yihui 1:fc2f9d636751 3461 #define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
yihui 1:fc2f9d636751 3462 #define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
yihui 1:fc2f9d636751 3463 #define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3464 #define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3465 #define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3466
yihui 1:fc2f9d636751 3467 /* Bit 23 : Protection enable for region 55. */
yihui 1:fc2f9d636751 3468 #define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
yihui 1:fc2f9d636751 3469 #define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
yihui 1:fc2f9d636751 3470 #define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3471 #define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3472 #define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3473
yihui 1:fc2f9d636751 3474 /* Bit 22 : Protection enable for region 54. */
yihui 1:fc2f9d636751 3475 #define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
yihui 1:fc2f9d636751 3476 #define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
yihui 1:fc2f9d636751 3477 #define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3478 #define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3479 #define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3480
yihui 1:fc2f9d636751 3481 /* Bit 21 : Protection enable for region 53. */
yihui 1:fc2f9d636751 3482 #define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
yihui 1:fc2f9d636751 3483 #define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
yihui 1:fc2f9d636751 3484 #define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3485 #define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3486 #define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3487
yihui 1:fc2f9d636751 3488 /* Bit 20 : Protection enable for region 52. */
yihui 1:fc2f9d636751 3489 #define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
yihui 1:fc2f9d636751 3490 #define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
yihui 1:fc2f9d636751 3491 #define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3492 #define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3493 #define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3494
yihui 1:fc2f9d636751 3495 /* Bit 19 : Protection enable for region 51. */
yihui 1:fc2f9d636751 3496 #define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
yihui 1:fc2f9d636751 3497 #define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
yihui 1:fc2f9d636751 3498 #define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3499 #define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3500 #define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3501
yihui 1:fc2f9d636751 3502 /* Bit 18 : Protection enable for region 50. */
yihui 1:fc2f9d636751 3503 #define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
yihui 1:fc2f9d636751 3504 #define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
yihui 1:fc2f9d636751 3505 #define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3506 #define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3507 #define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3508
yihui 1:fc2f9d636751 3509 /* Bit 17 : Protection enable for region 49. */
yihui 1:fc2f9d636751 3510 #define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
yihui 1:fc2f9d636751 3511 #define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
yihui 1:fc2f9d636751 3512 #define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3513 #define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3514 #define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3515
yihui 1:fc2f9d636751 3516 /* Bit 16 : Protection enable for region 48. */
yihui 1:fc2f9d636751 3517 #define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
yihui 1:fc2f9d636751 3518 #define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
yihui 1:fc2f9d636751 3519 #define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3520 #define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3521 #define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3522
yihui 1:fc2f9d636751 3523 /* Bit 15 : Protection enable for region 47. */
yihui 1:fc2f9d636751 3524 #define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
yihui 1:fc2f9d636751 3525 #define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
yihui 1:fc2f9d636751 3526 #define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3527 #define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3528 #define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3529
yihui 1:fc2f9d636751 3530 /* Bit 14 : Protection enable for region 46. */
yihui 1:fc2f9d636751 3531 #define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
yihui 1:fc2f9d636751 3532 #define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
yihui 1:fc2f9d636751 3533 #define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3534 #define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3535 #define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3536
yihui 1:fc2f9d636751 3537 /* Bit 13 : Protection enable for region 45. */
yihui 1:fc2f9d636751 3538 #define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
yihui 1:fc2f9d636751 3539 #define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
yihui 1:fc2f9d636751 3540 #define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3541 #define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3542 #define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3543
yihui 1:fc2f9d636751 3544 /* Bit 12 : Protection enable for region 44. */
yihui 1:fc2f9d636751 3545 #define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
yihui 1:fc2f9d636751 3546 #define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
yihui 1:fc2f9d636751 3547 #define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3548 #define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3549 #define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3550
yihui 1:fc2f9d636751 3551 /* Bit 11 : Protection enable for region 43. */
yihui 1:fc2f9d636751 3552 #define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
yihui 1:fc2f9d636751 3553 #define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
yihui 1:fc2f9d636751 3554 #define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3555 #define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3556 #define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3557
yihui 1:fc2f9d636751 3558 /* Bit 10 : Protection enable for region 42. */
yihui 1:fc2f9d636751 3559 #define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
yihui 1:fc2f9d636751 3560 #define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
yihui 1:fc2f9d636751 3561 #define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3562 #define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3563 #define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3564
yihui 1:fc2f9d636751 3565 /* Bit 9 : Protection enable for region 41. */
yihui 1:fc2f9d636751 3566 #define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
yihui 1:fc2f9d636751 3567 #define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
yihui 1:fc2f9d636751 3568 #define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3569 #define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3570 #define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3571
yihui 1:fc2f9d636751 3572 /* Bit 8 : Protection enable for region 40. */
yihui 1:fc2f9d636751 3573 #define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
yihui 1:fc2f9d636751 3574 #define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
yihui 1:fc2f9d636751 3575 #define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3576 #define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3577 #define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3578
yihui 1:fc2f9d636751 3579 /* Bit 7 : Protection enable for region 39. */
yihui 1:fc2f9d636751 3580 #define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
yihui 1:fc2f9d636751 3581 #define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
yihui 1:fc2f9d636751 3582 #define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3583 #define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3584 #define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3585
yihui 1:fc2f9d636751 3586 /* Bit 6 : Protection enable for region 38. */
yihui 1:fc2f9d636751 3587 #define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
yihui 1:fc2f9d636751 3588 #define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
yihui 1:fc2f9d636751 3589 #define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3590 #define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3591 #define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3592
yihui 1:fc2f9d636751 3593 /* Bit 5 : Protection enable for region 37. */
yihui 1:fc2f9d636751 3594 #define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
yihui 1:fc2f9d636751 3595 #define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
yihui 1:fc2f9d636751 3596 #define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3597 #define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3598 #define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3599
yihui 1:fc2f9d636751 3600 /* Bit 4 : Protection enable for region 36. */
yihui 1:fc2f9d636751 3601 #define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
yihui 1:fc2f9d636751 3602 #define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
yihui 1:fc2f9d636751 3603 #define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3604 #define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3605 #define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3606
yihui 1:fc2f9d636751 3607 /* Bit 3 : Protection enable for region 35. */
yihui 1:fc2f9d636751 3608 #define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
yihui 1:fc2f9d636751 3609 #define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
yihui 1:fc2f9d636751 3610 #define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3611 #define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3612 #define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3613
yihui 1:fc2f9d636751 3614 /* Bit 2 : Protection enable for region 34. */
yihui 1:fc2f9d636751 3615 #define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
yihui 1:fc2f9d636751 3616 #define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
yihui 1:fc2f9d636751 3617 #define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3618 #define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3619 #define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3620
yihui 1:fc2f9d636751 3621 /* Bit 1 : Protection enable for region 33. */
yihui 1:fc2f9d636751 3622 #define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
yihui 1:fc2f9d636751 3623 #define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
yihui 1:fc2f9d636751 3624 #define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3625 #define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3626 #define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3627
yihui 1:fc2f9d636751 3628 /* Bit 0 : Protection enable for region 32. */
yihui 1:fc2f9d636751 3629 #define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
yihui 1:fc2f9d636751 3630 #define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
yihui 1:fc2f9d636751 3631 #define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3632 #define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3633 #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
yihui 1:fc2f9d636751 3634
yihui 1:fc2f9d636751 3635 /* Register: MPU_DISABLEINDEBUG */
yihui 1:fc2f9d636751 3636 /* Description: Disable erase and write protection mechanism in debug mode. */
yihui 1:fc2f9d636751 3637
yihui 1:fc2f9d636751 3638 /* Bit 0 : Disable protection mechanism in debug mode. */
yihui 1:fc2f9d636751 3639 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
yihui 1:fc2f9d636751 3640 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
yihui 1:fc2f9d636751 3641 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
yihui 1:fc2f9d636751 3642 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
yihui 1:fc2f9d636751 3643
yihui 1:fc2f9d636751 3644 /* Register: MPU_PROTBLOCKSIZE */
yihui 1:fc2f9d636751 3645 /* Description: Erase and write protection block size. */
yihui 1:fc2f9d636751 3646
yihui 1:fc2f9d636751 3647 /* Bits 1..0 : Erase and write protection block size. */
yihui 1:fc2f9d636751 3648 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */
yihui 1:fc2f9d636751 3649 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */
yihui 1:fc2f9d636751 3650 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */
yihui 1:fc2f9d636751 3651
yihui 1:fc2f9d636751 3652
yihui 1:fc2f9d636751 3653 /* Peripheral: NVMC */
yihui 1:fc2f9d636751 3654 /* Description: Non Volatile Memory Controller. */
yihui 1:fc2f9d636751 3655
yihui 1:fc2f9d636751 3656 /* Register: NVMC_READY */
yihui 1:fc2f9d636751 3657 /* Description: Ready flag. */
yihui 1:fc2f9d636751 3658
yihui 1:fc2f9d636751 3659 /* Bit 0 : NVMC ready. */
yihui 1:fc2f9d636751 3660 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
yihui 1:fc2f9d636751 3661 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
yihui 1:fc2f9d636751 3662 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
yihui 1:fc2f9d636751 3663 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
yihui 1:fc2f9d636751 3664
yihui 1:fc2f9d636751 3665 /* Register: NVMC_CONFIG */
yihui 1:fc2f9d636751 3666 /* Description: Configuration register. */
yihui 1:fc2f9d636751 3667
yihui 1:fc2f9d636751 3668 /* Bits 1..0 : Program write enable. */
yihui 1:fc2f9d636751 3669 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
yihui 1:fc2f9d636751 3670 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
yihui 1:fc2f9d636751 3671 #define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
yihui 1:fc2f9d636751 3672 #define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
yihui 1:fc2f9d636751 3673 #define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
yihui 1:fc2f9d636751 3674
yihui 1:fc2f9d636751 3675 /* Register: NVMC_ERASEALL */
yihui 1:fc2f9d636751 3676 /* Description: Register for erasing all non-volatile user memory. */
yihui 1:fc2f9d636751 3677
yihui 1:fc2f9d636751 3678 /* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
yihui 1:fc2f9d636751 3679 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
yihui 1:fc2f9d636751 3680 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
yihui 1:fc2f9d636751 3681 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
yihui 1:fc2f9d636751 3682 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
yihui 1:fc2f9d636751 3683
yihui 1:fc2f9d636751 3684 /* Register: NVMC_ERASEUICR */
yihui 1:fc2f9d636751 3685 /* Description: Register for start erasing User Information Congfiguration Registers. */
yihui 1:fc2f9d636751 3686
yihui 1:fc2f9d636751 3687 /* Bit 0 : It can only be used when all contents of code region 1 are erased. */
yihui 1:fc2f9d636751 3688 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
yihui 1:fc2f9d636751 3689 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
yihui 1:fc2f9d636751 3690 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
yihui 1:fc2f9d636751 3691 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
yihui 1:fc2f9d636751 3692
yihui 1:fc2f9d636751 3693
yihui 1:fc2f9d636751 3694 /* Peripheral: POWER */
yihui 1:fc2f9d636751 3695 /* Description: Power Control. */
yihui 1:fc2f9d636751 3696
yihui 1:fc2f9d636751 3697 /* Register: POWER_INTENSET */
yihui 1:fc2f9d636751 3698 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 3699
yihui 1:fc2f9d636751 3700 /* Bit 2 : Enable interrupt on POFWARN event. */
yihui 1:fc2f9d636751 3701 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
yihui 1:fc2f9d636751 3702 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
yihui 1:fc2f9d636751 3703 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 3704 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 3705 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 3706
yihui 1:fc2f9d636751 3707 /* Register: POWER_INTENCLR */
yihui 1:fc2f9d636751 3708 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 3709
yihui 1:fc2f9d636751 3710 /* Bit 2 : Disable interrupt on POFWARN event. */
yihui 1:fc2f9d636751 3711 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
yihui 1:fc2f9d636751 3712 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
yihui 1:fc2f9d636751 3713 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 3714 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 3715 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 3716
yihui 1:fc2f9d636751 3717 /* Register: POWER_RESETREAS */
yihui 1:fc2f9d636751 3718 /* Description: Reset reason. */
yihui 1:fc2f9d636751 3719
yihui 1:fc2f9d636751 3720 /* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
yihui 1:fc2f9d636751 3721 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
yihui 1:fc2f9d636751 3722 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
yihui 1:fc2f9d636751 3723
yihui 1:fc2f9d636751 3724 /* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
yihui 1:fc2f9d636751 3725 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
yihui 1:fc2f9d636751 3726 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
yihui 1:fc2f9d636751 3727
yihui 1:fc2f9d636751 3728 /* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
yihui 1:fc2f9d636751 3729 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
yihui 1:fc2f9d636751 3730 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
yihui 1:fc2f9d636751 3731
yihui 1:fc2f9d636751 3732 /* Bit 3 : Reset from CPU lock-up detected. */
yihui 1:fc2f9d636751 3733 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
yihui 1:fc2f9d636751 3734 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
yihui 1:fc2f9d636751 3735
yihui 1:fc2f9d636751 3736 /* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
yihui 1:fc2f9d636751 3737 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
yihui 1:fc2f9d636751 3738 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
yihui 1:fc2f9d636751 3739
yihui 1:fc2f9d636751 3740 /* Bit 1 : Reset from watchdog detected. */
yihui 1:fc2f9d636751 3741 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
yihui 1:fc2f9d636751 3742 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
yihui 1:fc2f9d636751 3743
yihui 1:fc2f9d636751 3744 /* Bit 0 : Reset from pin-reset detected. */
yihui 1:fc2f9d636751 3745 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
yihui 1:fc2f9d636751 3746 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
yihui 1:fc2f9d636751 3747
yihui 1:fc2f9d636751 3748 /* Register: POWER_RAMSTATUS */
yihui 1:fc2f9d636751 3749 /* Description: Ram status register. */
yihui 1:fc2f9d636751 3750
yihui 1:fc2f9d636751 3751 /* Bit 3 : RAM block 3 status. */
yihui 1:fc2f9d636751 3752 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
yihui 1:fc2f9d636751 3753 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
yihui 1:fc2f9d636751 3754 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */
yihui 1:fc2f9d636751 3755 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */
yihui 1:fc2f9d636751 3756
yihui 1:fc2f9d636751 3757 /* Bit 2 : RAM block 2 status. */
yihui 1:fc2f9d636751 3758 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
yihui 1:fc2f9d636751 3759 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
yihui 1:fc2f9d636751 3760 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */
yihui 1:fc2f9d636751 3761 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */
yihui 1:fc2f9d636751 3762
yihui 1:fc2f9d636751 3763 /* Bit 1 : RAM block 1 status. */
yihui 1:fc2f9d636751 3764 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
yihui 1:fc2f9d636751 3765 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
yihui 1:fc2f9d636751 3766 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */
yihui 1:fc2f9d636751 3767 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */
yihui 1:fc2f9d636751 3768
yihui 1:fc2f9d636751 3769 /* Bit 0 : RAM block 0 status. */
yihui 1:fc2f9d636751 3770 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
yihui 1:fc2f9d636751 3771 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
yihui 1:fc2f9d636751 3772 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */
yihui 1:fc2f9d636751 3773 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */
yihui 1:fc2f9d636751 3774
yihui 1:fc2f9d636751 3775 /* Register: POWER_SYSTEMOFF */
yihui 1:fc2f9d636751 3776 /* Description: System off register. */
yihui 1:fc2f9d636751 3777
yihui 1:fc2f9d636751 3778 /* Bit 0 : Enter system off mode. */
yihui 1:fc2f9d636751 3779 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
yihui 1:fc2f9d636751 3780 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
yihui 1:fc2f9d636751 3781 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
yihui 1:fc2f9d636751 3782
yihui 1:fc2f9d636751 3783 /* Register: POWER_POFCON */
yihui 1:fc2f9d636751 3784 /* Description: Power failure configuration. */
yihui 1:fc2f9d636751 3785
yihui 1:fc2f9d636751 3786 /* Bits 2..1 : Set threshold level. */
yihui 1:fc2f9d636751 3787 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
yihui 1:fc2f9d636751 3788 #define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
yihui 1:fc2f9d636751 3789 #define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
yihui 1:fc2f9d636751 3790 #define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
yihui 1:fc2f9d636751 3791 #define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
yihui 1:fc2f9d636751 3792 #define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
yihui 1:fc2f9d636751 3793
yihui 1:fc2f9d636751 3794 /* Bit 0 : Power failure comparator enable. */
yihui 1:fc2f9d636751 3795 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
yihui 1:fc2f9d636751 3796 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
yihui 1:fc2f9d636751 3797 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
yihui 1:fc2f9d636751 3798 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
yihui 1:fc2f9d636751 3799
yihui 1:fc2f9d636751 3800 /* Register: POWER_GPREGRET */
yihui 1:fc2f9d636751 3801 /* Description: General purpose retention register. This register is a retained register. */
yihui 1:fc2f9d636751 3802
yihui 1:fc2f9d636751 3803 /* Bits 7..0 : General purpose retention register. */
yihui 1:fc2f9d636751 3804 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
yihui 1:fc2f9d636751 3805 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
yihui 1:fc2f9d636751 3806
yihui 1:fc2f9d636751 3807 /* Register: POWER_RAMON */
yihui 1:fc2f9d636751 3808 /* Description: Ram on/off. */
yihui 1:fc2f9d636751 3809
yihui 1:fc2f9d636751 3810 /* Bit 17 : RAM block 1 behaviour in OFF mode. */
yihui 1:fc2f9d636751 3811 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
yihui 1:fc2f9d636751 3812 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
yihui 1:fc2f9d636751 3813 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
yihui 1:fc2f9d636751 3814 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
yihui 1:fc2f9d636751 3815
yihui 1:fc2f9d636751 3816 /* Bit 16 : RAM block 0 behaviour in OFF mode. */
yihui 1:fc2f9d636751 3817 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
yihui 1:fc2f9d636751 3818 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
yihui 1:fc2f9d636751 3819 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
yihui 1:fc2f9d636751 3820 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
yihui 1:fc2f9d636751 3821
yihui 1:fc2f9d636751 3822 /* Bit 1 : RAM block 1 behaviour in ON mode. */
yihui 1:fc2f9d636751 3823 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
yihui 1:fc2f9d636751 3824 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
yihui 1:fc2f9d636751 3825 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
yihui 1:fc2f9d636751 3826 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
yihui 1:fc2f9d636751 3827
yihui 1:fc2f9d636751 3828 /* Bit 0 : RAM block 0 behaviour in ON mode. */
yihui 1:fc2f9d636751 3829 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
yihui 1:fc2f9d636751 3830 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
yihui 1:fc2f9d636751 3831 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
yihui 1:fc2f9d636751 3832 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
yihui 1:fc2f9d636751 3833
yihui 1:fc2f9d636751 3834 /* Register: POWER_RESET */
yihui 1:fc2f9d636751 3835 /* Description: Pin reset functionality configuration register. This register is a retained register. */
yihui 1:fc2f9d636751 3836
yihui 1:fc2f9d636751 3837 /* Bit 0 : Enable or disable pin reset in debug interface mode. */
yihui 1:fc2f9d636751 3838 #define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
yihui 1:fc2f9d636751 3839 #define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
yihui 1:fc2f9d636751 3840 #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
yihui 1:fc2f9d636751 3841 #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
yihui 1:fc2f9d636751 3842
yihui 1:fc2f9d636751 3843 /* Register: POWER_RAMONB */
yihui 1:fc2f9d636751 3844 /* Description: Ram on/off. */
yihui 1:fc2f9d636751 3845
yihui 1:fc2f9d636751 3846 /* Bit 17 : RAM block 3 behaviour in OFF mode. */
yihui 1:fc2f9d636751 3847 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
yihui 1:fc2f9d636751 3848 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
yihui 1:fc2f9d636751 3849 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
yihui 1:fc2f9d636751 3850 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
yihui 1:fc2f9d636751 3851
yihui 1:fc2f9d636751 3852 /* Bit 16 : RAM block 2 behaviour in OFF mode. */
yihui 1:fc2f9d636751 3853 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
yihui 1:fc2f9d636751 3854 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
yihui 1:fc2f9d636751 3855 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
yihui 1:fc2f9d636751 3856 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
yihui 1:fc2f9d636751 3857
yihui 1:fc2f9d636751 3858 /* Bit 1 : RAM block 3 behaviour in ON mode. */
yihui 1:fc2f9d636751 3859 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
yihui 1:fc2f9d636751 3860 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
yihui 1:fc2f9d636751 3861 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */
yihui 1:fc2f9d636751 3862 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
yihui 1:fc2f9d636751 3863
yihui 1:fc2f9d636751 3864 /* Bit 0 : RAM block 2 behaviour in ON mode. */
yihui 1:fc2f9d636751 3865 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
yihui 1:fc2f9d636751 3866 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
yihui 1:fc2f9d636751 3867 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
yihui 1:fc2f9d636751 3868 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
yihui 1:fc2f9d636751 3869
yihui 1:fc2f9d636751 3870 /* Register: POWER_DCDCEN */
yihui 1:fc2f9d636751 3871 /* Description: DCDC converter enable configuration register. */
yihui 1:fc2f9d636751 3872
yihui 1:fc2f9d636751 3873 /* Bit 0 : Enable DCDC converter. */
yihui 1:fc2f9d636751 3874 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
yihui 1:fc2f9d636751 3875 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
yihui 1:fc2f9d636751 3876 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
yihui 1:fc2f9d636751 3877 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
yihui 1:fc2f9d636751 3878
yihui 1:fc2f9d636751 3879 /* Register: POWER_DCDCFORCE */
yihui 1:fc2f9d636751 3880 /* Description: DCDC power-up force register. */
yihui 1:fc2f9d636751 3881
yihui 1:fc2f9d636751 3882 /* Bit 1 : DCDC power-up force on. */
yihui 1:fc2f9d636751 3883 #define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */
yihui 1:fc2f9d636751 3884 #define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */
yihui 1:fc2f9d636751 3885 #define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */
yihui 1:fc2f9d636751 3886 #define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */
yihui 1:fc2f9d636751 3887
yihui 1:fc2f9d636751 3888 /* Bit 0 : DCDC power-up force off. */
yihui 1:fc2f9d636751 3889 #define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
yihui 1:fc2f9d636751 3890 #define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
yihui 1:fc2f9d636751 3891 #define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */
yihui 1:fc2f9d636751 3892 #define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */
yihui 1:fc2f9d636751 3893
yihui 1:fc2f9d636751 3894
yihui 1:fc2f9d636751 3895 /* Peripheral: PPI */
yihui 1:fc2f9d636751 3896 /* Description: PPI controller. */
yihui 1:fc2f9d636751 3897
yihui 1:fc2f9d636751 3898 /* Register: PPI_CHEN */
yihui 1:fc2f9d636751 3899 /* Description: Channel enable. */
yihui 1:fc2f9d636751 3900
yihui 1:fc2f9d636751 3901 /* Bit 31 : Enable PPI channel 31. */
yihui 1:fc2f9d636751 3902 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
yihui 1:fc2f9d636751 3903 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
yihui 1:fc2f9d636751 3904 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 3905 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 3906
yihui 1:fc2f9d636751 3907 /* Bit 30 : Enable PPI channel 30. */
yihui 1:fc2f9d636751 3908 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
yihui 1:fc2f9d636751 3909 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
yihui 1:fc2f9d636751 3910 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 3911 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 3912
yihui 1:fc2f9d636751 3913 /* Bit 29 : Enable PPI channel 29. */
yihui 1:fc2f9d636751 3914 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
yihui 1:fc2f9d636751 3915 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
yihui 1:fc2f9d636751 3916 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 3917 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 3918
yihui 1:fc2f9d636751 3919 /* Bit 28 : Enable PPI channel 28. */
yihui 1:fc2f9d636751 3920 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
yihui 1:fc2f9d636751 3921 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
yihui 1:fc2f9d636751 3922 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 3923 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 3924
yihui 1:fc2f9d636751 3925 /* Bit 27 : Enable PPI channel 27. */
yihui 1:fc2f9d636751 3926 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
yihui 1:fc2f9d636751 3927 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
yihui 1:fc2f9d636751 3928 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 3929 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 3930
yihui 1:fc2f9d636751 3931 /* Bit 26 : Enable PPI channel 26. */
yihui 1:fc2f9d636751 3932 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
yihui 1:fc2f9d636751 3933 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
yihui 1:fc2f9d636751 3934 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 3935 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 3936
yihui 1:fc2f9d636751 3937 /* Bit 25 : Enable PPI channel 25. */
yihui 1:fc2f9d636751 3938 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
yihui 1:fc2f9d636751 3939 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
yihui 1:fc2f9d636751 3940 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 3941 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 3942
yihui 1:fc2f9d636751 3943 /* Bit 24 : Enable PPI channel 24. */
yihui 1:fc2f9d636751 3944 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
yihui 1:fc2f9d636751 3945 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
yihui 1:fc2f9d636751 3946 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 3947 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 3948
yihui 1:fc2f9d636751 3949 /* Bit 23 : Enable PPI channel 23. */
yihui 1:fc2f9d636751 3950 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
yihui 1:fc2f9d636751 3951 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
yihui 1:fc2f9d636751 3952 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 3953 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 3954
yihui 1:fc2f9d636751 3955 /* Bit 22 : Enable PPI channel 22. */
yihui 1:fc2f9d636751 3956 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
yihui 1:fc2f9d636751 3957 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
yihui 1:fc2f9d636751 3958 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 3959 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 3960
yihui 1:fc2f9d636751 3961 /* Bit 21 : Enable PPI channel 21. */
yihui 1:fc2f9d636751 3962 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
yihui 1:fc2f9d636751 3963 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
yihui 1:fc2f9d636751 3964 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 3965 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 3966
yihui 1:fc2f9d636751 3967 /* Bit 20 : Enable PPI channel 20. */
yihui 1:fc2f9d636751 3968 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
yihui 1:fc2f9d636751 3969 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
yihui 1:fc2f9d636751 3970 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 3971 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 3972
yihui 1:fc2f9d636751 3973 /* Bit 15 : Enable PPI channel 15. */
yihui 1:fc2f9d636751 3974 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
yihui 1:fc2f9d636751 3975 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
yihui 1:fc2f9d636751 3976 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 3977 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 3978
yihui 1:fc2f9d636751 3979 /* Bit 14 : Enable PPI channel 14. */
yihui 1:fc2f9d636751 3980 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
yihui 1:fc2f9d636751 3981 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
yihui 1:fc2f9d636751 3982 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 3983 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 3984
yihui 1:fc2f9d636751 3985 /* Bit 13 : Enable PPI channel 13. */
yihui 1:fc2f9d636751 3986 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
yihui 1:fc2f9d636751 3987 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
yihui 1:fc2f9d636751 3988 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 3989 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 3990
yihui 1:fc2f9d636751 3991 /* Bit 12 : Enable PPI channel 12. */
yihui 1:fc2f9d636751 3992 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
yihui 1:fc2f9d636751 3993 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
yihui 1:fc2f9d636751 3994 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 3995 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 3996
yihui 1:fc2f9d636751 3997 /* Bit 11 : Enable PPI channel 11. */
yihui 1:fc2f9d636751 3998 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
yihui 1:fc2f9d636751 3999 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
yihui 1:fc2f9d636751 4000 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4001 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4002
yihui 1:fc2f9d636751 4003 /* Bit 10 : Enable PPI channel 10. */
yihui 1:fc2f9d636751 4004 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
yihui 1:fc2f9d636751 4005 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
yihui 1:fc2f9d636751 4006 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4007 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4008
yihui 1:fc2f9d636751 4009 /* Bit 9 : Enable PPI channel 9. */
yihui 1:fc2f9d636751 4010 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
yihui 1:fc2f9d636751 4011 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
yihui 1:fc2f9d636751 4012 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4013 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4014
yihui 1:fc2f9d636751 4015 /* Bit 8 : Enable PPI channel 8. */
yihui 1:fc2f9d636751 4016 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
yihui 1:fc2f9d636751 4017 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
yihui 1:fc2f9d636751 4018 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4019 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4020
yihui 1:fc2f9d636751 4021 /* Bit 7 : Enable PPI channel 7. */
yihui 1:fc2f9d636751 4022 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
yihui 1:fc2f9d636751 4023 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
yihui 1:fc2f9d636751 4024 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4025 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4026
yihui 1:fc2f9d636751 4027 /* Bit 6 : Enable PPI channel 6. */
yihui 1:fc2f9d636751 4028 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
yihui 1:fc2f9d636751 4029 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
yihui 1:fc2f9d636751 4030 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4031 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4032
yihui 1:fc2f9d636751 4033 /* Bit 5 : Enable PPI channel 5. */
yihui 1:fc2f9d636751 4034 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
yihui 1:fc2f9d636751 4035 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
yihui 1:fc2f9d636751 4036 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4037 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4038
yihui 1:fc2f9d636751 4039 /* Bit 4 : Enable PPI channel 4. */
yihui 1:fc2f9d636751 4040 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
yihui 1:fc2f9d636751 4041 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
yihui 1:fc2f9d636751 4042 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4043 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4044
yihui 1:fc2f9d636751 4045 /* Bit 3 : Enable PPI channel 3. */
yihui 1:fc2f9d636751 4046 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
yihui 1:fc2f9d636751 4047 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
yihui 1:fc2f9d636751 4048 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
yihui 1:fc2f9d636751 4049 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
yihui 1:fc2f9d636751 4050
yihui 1:fc2f9d636751 4051 /* Bit 2 : Enable PPI channel 2. */
yihui 1:fc2f9d636751 4052 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
yihui 1:fc2f9d636751 4053 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
yihui 1:fc2f9d636751 4054 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4055 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4056
yihui 1:fc2f9d636751 4057 /* Bit 1 : Enable PPI channel 1. */
yihui 1:fc2f9d636751 4058 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
yihui 1:fc2f9d636751 4059 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
yihui 1:fc2f9d636751 4060 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4061 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4062
yihui 1:fc2f9d636751 4063 /* Bit 0 : Enable PPI channel 0. */
yihui 1:fc2f9d636751 4064 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
yihui 1:fc2f9d636751 4065 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
yihui 1:fc2f9d636751 4066 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4067 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4068
yihui 1:fc2f9d636751 4069 /* Register: PPI_CHENSET */
yihui 1:fc2f9d636751 4070 /* Description: Channel enable set. */
yihui 1:fc2f9d636751 4071
yihui 1:fc2f9d636751 4072 /* Bit 31 : Enable PPI channel 31. */
yihui 1:fc2f9d636751 4073 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
yihui 1:fc2f9d636751 4074 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
yihui 1:fc2f9d636751 4075 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4076 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4077 #define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4078
yihui 1:fc2f9d636751 4079 /* Bit 30 : Enable PPI channel 30. */
yihui 1:fc2f9d636751 4080 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
yihui 1:fc2f9d636751 4081 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
yihui 1:fc2f9d636751 4082 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4083 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4084 #define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4085
yihui 1:fc2f9d636751 4086 /* Bit 29 : Enable PPI channel 29. */
yihui 1:fc2f9d636751 4087 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
yihui 1:fc2f9d636751 4088 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
yihui 1:fc2f9d636751 4089 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4090 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4091 #define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4092
yihui 1:fc2f9d636751 4093 /* Bit 28 : Enable PPI channel 28. */
yihui 1:fc2f9d636751 4094 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
yihui 1:fc2f9d636751 4095 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
yihui 1:fc2f9d636751 4096 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4097 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4098 #define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4099
yihui 1:fc2f9d636751 4100 /* Bit 27 : Enable PPI channel 27. */
yihui 1:fc2f9d636751 4101 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
yihui 1:fc2f9d636751 4102 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
yihui 1:fc2f9d636751 4103 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4104 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4105 #define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4106
yihui 1:fc2f9d636751 4107 /* Bit 26 : Enable PPI channel 26. */
yihui 1:fc2f9d636751 4108 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
yihui 1:fc2f9d636751 4109 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
yihui 1:fc2f9d636751 4110 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4111 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4112 #define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4113
yihui 1:fc2f9d636751 4114 /* Bit 25 : Enable PPI channel 25. */
yihui 1:fc2f9d636751 4115 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
yihui 1:fc2f9d636751 4116 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
yihui 1:fc2f9d636751 4117 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4118 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4119 #define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4120
yihui 1:fc2f9d636751 4121 /* Bit 24 : Enable PPI channel 24. */
yihui 1:fc2f9d636751 4122 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
yihui 1:fc2f9d636751 4123 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
yihui 1:fc2f9d636751 4124 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4125 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4126 #define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4127
yihui 1:fc2f9d636751 4128 /* Bit 23 : Enable PPI channel 23. */
yihui 1:fc2f9d636751 4129 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
yihui 1:fc2f9d636751 4130 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
yihui 1:fc2f9d636751 4131 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4132 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4133 #define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4134
yihui 1:fc2f9d636751 4135 /* Bit 22 : Enable PPI channel 22. */
yihui 1:fc2f9d636751 4136 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
yihui 1:fc2f9d636751 4137 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
yihui 1:fc2f9d636751 4138 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4139 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4140 #define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4141
yihui 1:fc2f9d636751 4142 /* Bit 21 : Enable PPI channel 21. */
yihui 1:fc2f9d636751 4143 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
yihui 1:fc2f9d636751 4144 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
yihui 1:fc2f9d636751 4145 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4146 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4147 #define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4148
yihui 1:fc2f9d636751 4149 /* Bit 20 : Enable PPI channel 20. */
yihui 1:fc2f9d636751 4150 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
yihui 1:fc2f9d636751 4151 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
yihui 1:fc2f9d636751 4152 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4153 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4154 #define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4155
yihui 1:fc2f9d636751 4156 /* Bit 15 : Enable PPI channel 15. */
yihui 1:fc2f9d636751 4157 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
yihui 1:fc2f9d636751 4158 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
yihui 1:fc2f9d636751 4159 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4160 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4161 #define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4162
yihui 1:fc2f9d636751 4163 /* Bit 14 : Enable PPI channel 14. */
yihui 1:fc2f9d636751 4164 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
yihui 1:fc2f9d636751 4165 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
yihui 1:fc2f9d636751 4166 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4167 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4168 #define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4169
yihui 1:fc2f9d636751 4170 /* Bit 13 : Enable PPI channel 13. */
yihui 1:fc2f9d636751 4171 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
yihui 1:fc2f9d636751 4172 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
yihui 1:fc2f9d636751 4173 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4174 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4175 #define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4176
yihui 1:fc2f9d636751 4177 /* Bit 12 : Enable PPI channel 12. */
yihui 1:fc2f9d636751 4178 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
yihui 1:fc2f9d636751 4179 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
yihui 1:fc2f9d636751 4180 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4181 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4182 #define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4183
yihui 1:fc2f9d636751 4184 /* Bit 11 : Enable PPI channel 11. */
yihui 1:fc2f9d636751 4185 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
yihui 1:fc2f9d636751 4186 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
yihui 1:fc2f9d636751 4187 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4188 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4189 #define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4190
yihui 1:fc2f9d636751 4191 /* Bit 10 : Enable PPI channel 10. */
yihui 1:fc2f9d636751 4192 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
yihui 1:fc2f9d636751 4193 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
yihui 1:fc2f9d636751 4194 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4195 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4196 #define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4197
yihui 1:fc2f9d636751 4198 /* Bit 9 : Enable PPI channel 9. */
yihui 1:fc2f9d636751 4199 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
yihui 1:fc2f9d636751 4200 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
yihui 1:fc2f9d636751 4201 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4202 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4203 #define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4204
yihui 1:fc2f9d636751 4205 /* Bit 8 : Enable PPI channel 8. */
yihui 1:fc2f9d636751 4206 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
yihui 1:fc2f9d636751 4207 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
yihui 1:fc2f9d636751 4208 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4209 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4210 #define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4211
yihui 1:fc2f9d636751 4212 /* Bit 7 : Enable PPI channel 7. */
yihui 1:fc2f9d636751 4213 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
yihui 1:fc2f9d636751 4214 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
yihui 1:fc2f9d636751 4215 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4216 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4217 #define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4218
yihui 1:fc2f9d636751 4219 /* Bit 6 : Enable PPI channel 6. */
yihui 1:fc2f9d636751 4220 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
yihui 1:fc2f9d636751 4221 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
yihui 1:fc2f9d636751 4222 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4223 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4224 #define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4225
yihui 1:fc2f9d636751 4226 /* Bit 5 : Enable PPI channel 5. */
yihui 1:fc2f9d636751 4227 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
yihui 1:fc2f9d636751 4228 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
yihui 1:fc2f9d636751 4229 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4230 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4231 #define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4232
yihui 1:fc2f9d636751 4233 /* Bit 4 : Enable PPI channel 4. */
yihui 1:fc2f9d636751 4234 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
yihui 1:fc2f9d636751 4235 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
yihui 1:fc2f9d636751 4236 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4237 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4238 #define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4239
yihui 1:fc2f9d636751 4240 /* Bit 3 : Enable PPI channel 3. */
yihui 1:fc2f9d636751 4241 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
yihui 1:fc2f9d636751 4242 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
yihui 1:fc2f9d636751 4243 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4244 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4245 #define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4246
yihui 1:fc2f9d636751 4247 /* Bit 2 : Enable PPI channel 2. */
yihui 1:fc2f9d636751 4248 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
yihui 1:fc2f9d636751 4249 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
yihui 1:fc2f9d636751 4250 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4251 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4252 #define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4253
yihui 1:fc2f9d636751 4254 /* Bit 1 : Enable PPI channel 1. */
yihui 1:fc2f9d636751 4255 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
yihui 1:fc2f9d636751 4256 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
yihui 1:fc2f9d636751 4257 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4258 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4259 #define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4260
yihui 1:fc2f9d636751 4261 /* Bit 0 : Enable PPI channel 0. */
yihui 1:fc2f9d636751 4262 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
yihui 1:fc2f9d636751 4263 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
yihui 1:fc2f9d636751 4264 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4265 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4266 #define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
yihui 1:fc2f9d636751 4267
yihui 1:fc2f9d636751 4268 /* Register: PPI_CHENCLR */
yihui 1:fc2f9d636751 4269 /* Description: Channel enable clear. */
yihui 1:fc2f9d636751 4270
yihui 1:fc2f9d636751 4271 /* Bit 31 : Disable PPI channel 31. */
yihui 1:fc2f9d636751 4272 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
yihui 1:fc2f9d636751 4273 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
yihui 1:fc2f9d636751 4274 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4275 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4276 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4277
yihui 1:fc2f9d636751 4278 /* Bit 30 : Disable PPI channel 30. */
yihui 1:fc2f9d636751 4279 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
yihui 1:fc2f9d636751 4280 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
yihui 1:fc2f9d636751 4281 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4282 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4283 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4284
yihui 1:fc2f9d636751 4285 /* Bit 29 : Disable PPI channel 29. */
yihui 1:fc2f9d636751 4286 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
yihui 1:fc2f9d636751 4287 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
yihui 1:fc2f9d636751 4288 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4289 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4290 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4291
yihui 1:fc2f9d636751 4292 /* Bit 28 : Disable PPI channel 28. */
yihui 1:fc2f9d636751 4293 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
yihui 1:fc2f9d636751 4294 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
yihui 1:fc2f9d636751 4295 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4296 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4297 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4298
yihui 1:fc2f9d636751 4299 /* Bit 27 : Disable PPI channel 27. */
yihui 1:fc2f9d636751 4300 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
yihui 1:fc2f9d636751 4301 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
yihui 1:fc2f9d636751 4302 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4303 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4304 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4305
yihui 1:fc2f9d636751 4306 /* Bit 26 : Disable PPI channel 26. */
yihui 1:fc2f9d636751 4307 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
yihui 1:fc2f9d636751 4308 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
yihui 1:fc2f9d636751 4309 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4310 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4311 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4312
yihui 1:fc2f9d636751 4313 /* Bit 25 : Disable PPI channel 25. */
yihui 1:fc2f9d636751 4314 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
yihui 1:fc2f9d636751 4315 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
yihui 1:fc2f9d636751 4316 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4317 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4318 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4319
yihui 1:fc2f9d636751 4320 /* Bit 24 : Disable PPI channel 24. */
yihui 1:fc2f9d636751 4321 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
yihui 1:fc2f9d636751 4322 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
yihui 1:fc2f9d636751 4323 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4324 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4325 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4326
yihui 1:fc2f9d636751 4327 /* Bit 23 : Disable PPI channel 23. */
yihui 1:fc2f9d636751 4328 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
yihui 1:fc2f9d636751 4329 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
yihui 1:fc2f9d636751 4330 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4331 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4332 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4333
yihui 1:fc2f9d636751 4334 /* Bit 22 : Disable PPI channel 22. */
yihui 1:fc2f9d636751 4335 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
yihui 1:fc2f9d636751 4336 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
yihui 1:fc2f9d636751 4337 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4338 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4339 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4340
yihui 1:fc2f9d636751 4341 /* Bit 21 : Disable PPI channel 21. */
yihui 1:fc2f9d636751 4342 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
yihui 1:fc2f9d636751 4343 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
yihui 1:fc2f9d636751 4344 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4345 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4346 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4347
yihui 1:fc2f9d636751 4348 /* Bit 20 : Disable PPI channel 20. */
yihui 1:fc2f9d636751 4349 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
yihui 1:fc2f9d636751 4350 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
yihui 1:fc2f9d636751 4351 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4352 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4353 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4354
yihui 1:fc2f9d636751 4355 /* Bit 15 : Disable PPI channel 15. */
yihui 1:fc2f9d636751 4356 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
yihui 1:fc2f9d636751 4357 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
yihui 1:fc2f9d636751 4358 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4359 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4360 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4361
yihui 1:fc2f9d636751 4362 /* Bit 14 : Disable PPI channel 14. */
yihui 1:fc2f9d636751 4363 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
yihui 1:fc2f9d636751 4364 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
yihui 1:fc2f9d636751 4365 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4366 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4367 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4368
yihui 1:fc2f9d636751 4369 /* Bit 13 : Disable PPI channel 13. */
yihui 1:fc2f9d636751 4370 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
yihui 1:fc2f9d636751 4371 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
yihui 1:fc2f9d636751 4372 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4373 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4374 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4375
yihui 1:fc2f9d636751 4376 /* Bit 12 : Disable PPI channel 12. */
yihui 1:fc2f9d636751 4377 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
yihui 1:fc2f9d636751 4378 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
yihui 1:fc2f9d636751 4379 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4380 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4381 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4382
yihui 1:fc2f9d636751 4383 /* Bit 11 : Disable PPI channel 11. */
yihui 1:fc2f9d636751 4384 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
yihui 1:fc2f9d636751 4385 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
yihui 1:fc2f9d636751 4386 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4387 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4388 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4389
yihui 1:fc2f9d636751 4390 /* Bit 10 : Disable PPI channel 10. */
yihui 1:fc2f9d636751 4391 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
yihui 1:fc2f9d636751 4392 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
yihui 1:fc2f9d636751 4393 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4394 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4395 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4396
yihui 1:fc2f9d636751 4397 /* Bit 9 : Disable PPI channel 9. */
yihui 1:fc2f9d636751 4398 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
yihui 1:fc2f9d636751 4399 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
yihui 1:fc2f9d636751 4400 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4401 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4402 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4403
yihui 1:fc2f9d636751 4404 /* Bit 8 : Disable PPI channel 8. */
yihui 1:fc2f9d636751 4405 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
yihui 1:fc2f9d636751 4406 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
yihui 1:fc2f9d636751 4407 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4408 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4409 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4410
yihui 1:fc2f9d636751 4411 /* Bit 7 : Disable PPI channel 7. */
yihui 1:fc2f9d636751 4412 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
yihui 1:fc2f9d636751 4413 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
yihui 1:fc2f9d636751 4414 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4415 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4416 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4417
yihui 1:fc2f9d636751 4418 /* Bit 6 : Disable PPI channel 6. */
yihui 1:fc2f9d636751 4419 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
yihui 1:fc2f9d636751 4420 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
yihui 1:fc2f9d636751 4421 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4422 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4423 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4424
yihui 1:fc2f9d636751 4425 /* Bit 5 : Disable PPI channel 5. */
yihui 1:fc2f9d636751 4426 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
yihui 1:fc2f9d636751 4427 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
yihui 1:fc2f9d636751 4428 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4429 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4430 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4431
yihui 1:fc2f9d636751 4432 /* Bit 4 : Disable PPI channel 4. */
yihui 1:fc2f9d636751 4433 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
yihui 1:fc2f9d636751 4434 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
yihui 1:fc2f9d636751 4435 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4436 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4437 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4438
yihui 1:fc2f9d636751 4439 /* Bit 3 : Disable PPI channel 3. */
yihui 1:fc2f9d636751 4440 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
yihui 1:fc2f9d636751 4441 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
yihui 1:fc2f9d636751 4442 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4443 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4444 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4445
yihui 1:fc2f9d636751 4446 /* Bit 2 : Disable PPI channel 2. */
yihui 1:fc2f9d636751 4447 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
yihui 1:fc2f9d636751 4448 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
yihui 1:fc2f9d636751 4449 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4450 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4451 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4452
yihui 1:fc2f9d636751 4453 /* Bit 1 : Disable PPI channel 1. */
yihui 1:fc2f9d636751 4454 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
yihui 1:fc2f9d636751 4455 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
yihui 1:fc2f9d636751 4456 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4457 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4458 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4459
yihui 1:fc2f9d636751 4460 /* Bit 0 : Disable PPI channel 0. */
yihui 1:fc2f9d636751 4461 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
yihui 1:fc2f9d636751 4462 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
yihui 1:fc2f9d636751 4463 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
yihui 1:fc2f9d636751 4464 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
yihui 1:fc2f9d636751 4465 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
yihui 1:fc2f9d636751 4466
yihui 1:fc2f9d636751 4467 /* Register: PPI_CHG */
yihui 1:fc2f9d636751 4468 /* Description: Channel group configuration. */
yihui 1:fc2f9d636751 4469
yihui 1:fc2f9d636751 4470 /* Bit 31 : Include CH31 in channel group. */
yihui 1:fc2f9d636751 4471 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
yihui 1:fc2f9d636751 4472 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
yihui 1:fc2f9d636751 4473 #define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4474 #define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4475
yihui 1:fc2f9d636751 4476 /* Bit 30 : Include CH30 in channel group. */
yihui 1:fc2f9d636751 4477 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
yihui 1:fc2f9d636751 4478 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
yihui 1:fc2f9d636751 4479 #define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4480 #define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4481
yihui 1:fc2f9d636751 4482 /* Bit 29 : Include CH29 in channel group. */
yihui 1:fc2f9d636751 4483 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
yihui 1:fc2f9d636751 4484 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
yihui 1:fc2f9d636751 4485 #define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4486 #define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4487
yihui 1:fc2f9d636751 4488 /* Bit 28 : Include CH28 in channel group. */
yihui 1:fc2f9d636751 4489 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
yihui 1:fc2f9d636751 4490 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
yihui 1:fc2f9d636751 4491 #define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4492 #define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4493
yihui 1:fc2f9d636751 4494 /* Bit 27 : Include CH27 in channel group. */
yihui 1:fc2f9d636751 4495 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
yihui 1:fc2f9d636751 4496 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
yihui 1:fc2f9d636751 4497 #define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4498 #define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4499
yihui 1:fc2f9d636751 4500 /* Bit 26 : Include CH26 in channel group. */
yihui 1:fc2f9d636751 4501 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
yihui 1:fc2f9d636751 4502 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
yihui 1:fc2f9d636751 4503 #define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4504 #define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4505
yihui 1:fc2f9d636751 4506 /* Bit 25 : Include CH25 in channel group. */
yihui 1:fc2f9d636751 4507 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
yihui 1:fc2f9d636751 4508 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
yihui 1:fc2f9d636751 4509 #define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4510 #define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4511
yihui 1:fc2f9d636751 4512 /* Bit 24 : Include CH24 in channel group. */
yihui 1:fc2f9d636751 4513 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
yihui 1:fc2f9d636751 4514 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
yihui 1:fc2f9d636751 4515 #define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4516 #define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4517
yihui 1:fc2f9d636751 4518 /* Bit 23 : Include CH23 in channel group. */
yihui 1:fc2f9d636751 4519 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
yihui 1:fc2f9d636751 4520 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
yihui 1:fc2f9d636751 4521 #define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4522 #define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4523
yihui 1:fc2f9d636751 4524 /* Bit 22 : Include CH22 in channel group. */
yihui 1:fc2f9d636751 4525 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
yihui 1:fc2f9d636751 4526 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
yihui 1:fc2f9d636751 4527 #define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4528 #define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4529
yihui 1:fc2f9d636751 4530 /* Bit 21 : Include CH21 in channel group. */
yihui 1:fc2f9d636751 4531 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
yihui 1:fc2f9d636751 4532 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
yihui 1:fc2f9d636751 4533 #define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4534 #define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4535
yihui 1:fc2f9d636751 4536 /* Bit 20 : Include CH20 in channel group. */
yihui 1:fc2f9d636751 4537 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
yihui 1:fc2f9d636751 4538 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
yihui 1:fc2f9d636751 4539 #define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4540 #define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4541
yihui 1:fc2f9d636751 4542 /* Bit 15 : Include CH15 in channel group. */
yihui 1:fc2f9d636751 4543 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
yihui 1:fc2f9d636751 4544 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
yihui 1:fc2f9d636751 4545 #define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4546 #define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4547
yihui 1:fc2f9d636751 4548 /* Bit 14 : Include CH14 in channel group. */
yihui 1:fc2f9d636751 4549 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
yihui 1:fc2f9d636751 4550 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
yihui 1:fc2f9d636751 4551 #define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4552 #define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4553
yihui 1:fc2f9d636751 4554 /* Bit 13 : Include CH13 in channel group. */
yihui 1:fc2f9d636751 4555 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
yihui 1:fc2f9d636751 4556 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
yihui 1:fc2f9d636751 4557 #define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4558 #define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4559
yihui 1:fc2f9d636751 4560 /* Bit 12 : Include CH12 in channel group. */
yihui 1:fc2f9d636751 4561 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
yihui 1:fc2f9d636751 4562 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
yihui 1:fc2f9d636751 4563 #define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4564 #define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4565
yihui 1:fc2f9d636751 4566 /* Bit 11 : Include CH11 in channel group. */
yihui 1:fc2f9d636751 4567 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
yihui 1:fc2f9d636751 4568 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
yihui 1:fc2f9d636751 4569 #define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4570 #define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4571
yihui 1:fc2f9d636751 4572 /* Bit 10 : Include CH10 in channel group. */
yihui 1:fc2f9d636751 4573 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
yihui 1:fc2f9d636751 4574 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
yihui 1:fc2f9d636751 4575 #define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4576 #define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4577
yihui 1:fc2f9d636751 4578 /* Bit 9 : Include CH9 in channel group. */
yihui 1:fc2f9d636751 4579 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
yihui 1:fc2f9d636751 4580 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
yihui 1:fc2f9d636751 4581 #define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4582 #define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4583
yihui 1:fc2f9d636751 4584 /* Bit 8 : Include CH8 in channel group. */
yihui 1:fc2f9d636751 4585 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
yihui 1:fc2f9d636751 4586 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
yihui 1:fc2f9d636751 4587 #define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4588 #define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4589
yihui 1:fc2f9d636751 4590 /* Bit 7 : Include CH7 in channel group. */
yihui 1:fc2f9d636751 4591 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
yihui 1:fc2f9d636751 4592 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
yihui 1:fc2f9d636751 4593 #define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4594 #define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4595
yihui 1:fc2f9d636751 4596 /* Bit 6 : Include CH6 in channel group. */
yihui 1:fc2f9d636751 4597 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
yihui 1:fc2f9d636751 4598 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
yihui 1:fc2f9d636751 4599 #define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4600 #define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4601
yihui 1:fc2f9d636751 4602 /* Bit 5 : Include CH5 in channel group. */
yihui 1:fc2f9d636751 4603 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
yihui 1:fc2f9d636751 4604 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
yihui 1:fc2f9d636751 4605 #define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4606 #define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4607
yihui 1:fc2f9d636751 4608 /* Bit 4 : Include CH4 in channel group. */
yihui 1:fc2f9d636751 4609 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
yihui 1:fc2f9d636751 4610 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
yihui 1:fc2f9d636751 4611 #define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4612 #define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4613
yihui 1:fc2f9d636751 4614 /* Bit 3 : Include CH3 in channel group. */
yihui 1:fc2f9d636751 4615 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
yihui 1:fc2f9d636751 4616 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
yihui 1:fc2f9d636751 4617 #define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4618 #define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4619
yihui 1:fc2f9d636751 4620 /* Bit 2 : Include CH2 in channel group. */
yihui 1:fc2f9d636751 4621 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
yihui 1:fc2f9d636751 4622 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
yihui 1:fc2f9d636751 4623 #define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4624 #define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4625
yihui 1:fc2f9d636751 4626 /* Bit 1 : Include CH1 in channel group. */
yihui 1:fc2f9d636751 4627 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
yihui 1:fc2f9d636751 4628 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
yihui 1:fc2f9d636751 4629 #define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4630 #define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4631
yihui 1:fc2f9d636751 4632 /* Bit 0 : Include CH0 in channel group. */
yihui 1:fc2f9d636751 4633 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
yihui 1:fc2f9d636751 4634 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
yihui 1:fc2f9d636751 4635 #define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
yihui 1:fc2f9d636751 4636 #define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
yihui 1:fc2f9d636751 4637
yihui 1:fc2f9d636751 4638
yihui 1:fc2f9d636751 4639 /* Peripheral: PU */
yihui 1:fc2f9d636751 4640 /* Description: Patch unit. */
yihui 1:fc2f9d636751 4641
yihui 1:fc2f9d636751 4642 /* Register: PU_PATCHADDR */
yihui 1:fc2f9d636751 4643 /* Description: Relative address of patch instructions. */
yihui 1:fc2f9d636751 4644
yihui 1:fc2f9d636751 4645 /* Bits 24..0 : Relative address of patch instructions. */
yihui 1:fc2f9d636751 4646 #define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */
yihui 1:fc2f9d636751 4647 #define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */
yihui 1:fc2f9d636751 4648
yihui 1:fc2f9d636751 4649 /* Register: PU_PATCHEN */
yihui 1:fc2f9d636751 4650 /* Description: Patch enable register. */
yihui 1:fc2f9d636751 4651
yihui 1:fc2f9d636751 4652 /* Bit 7 : Patch 7 enabled. */
yihui 1:fc2f9d636751 4653 #define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
yihui 1:fc2f9d636751 4654 #define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
yihui 1:fc2f9d636751 4655 #define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4656 #define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4657
yihui 1:fc2f9d636751 4658 /* Bit 6 : Patch 6 enabled. */
yihui 1:fc2f9d636751 4659 #define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
yihui 1:fc2f9d636751 4660 #define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
yihui 1:fc2f9d636751 4661 #define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4662 #define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4663
yihui 1:fc2f9d636751 4664 /* Bit 5 : Patch 5 enabled. */
yihui 1:fc2f9d636751 4665 #define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
yihui 1:fc2f9d636751 4666 #define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
yihui 1:fc2f9d636751 4667 #define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4668 #define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4669
yihui 1:fc2f9d636751 4670 /* Bit 4 : Patch 4 enabled. */
yihui 1:fc2f9d636751 4671 #define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
yihui 1:fc2f9d636751 4672 #define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
yihui 1:fc2f9d636751 4673 #define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4674 #define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4675
yihui 1:fc2f9d636751 4676 /* Bit 3 : Patch 3 enabled. */
yihui 1:fc2f9d636751 4677 #define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
yihui 1:fc2f9d636751 4678 #define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
yihui 1:fc2f9d636751 4679 #define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4680 #define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4681
yihui 1:fc2f9d636751 4682 /* Bit 2 : Patch 2 enabled. */
yihui 1:fc2f9d636751 4683 #define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
yihui 1:fc2f9d636751 4684 #define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
yihui 1:fc2f9d636751 4685 #define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4686 #define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4687
yihui 1:fc2f9d636751 4688 /* Bit 1 : Patch 1 enabled. */
yihui 1:fc2f9d636751 4689 #define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
yihui 1:fc2f9d636751 4690 #define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
yihui 1:fc2f9d636751 4691 #define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4692 #define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4693
yihui 1:fc2f9d636751 4694 /* Bit 0 : Patch 0 enabled. */
yihui 1:fc2f9d636751 4695 #define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
yihui 1:fc2f9d636751 4696 #define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
yihui 1:fc2f9d636751 4697 #define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4698 #define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4699
yihui 1:fc2f9d636751 4700 /* Register: PU_PATCHENSET */
yihui 1:fc2f9d636751 4701 /* Description: Patch enable register. */
yihui 1:fc2f9d636751 4702
yihui 1:fc2f9d636751 4703 /* Bit 7 : Patch 7 enabled. */
yihui 1:fc2f9d636751 4704 #define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
yihui 1:fc2f9d636751 4705 #define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
yihui 1:fc2f9d636751 4706 #define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4707 #define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4708 #define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */
yihui 1:fc2f9d636751 4709
yihui 1:fc2f9d636751 4710 /* Bit 6 : Patch 6 enabled. */
yihui 1:fc2f9d636751 4711 #define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
yihui 1:fc2f9d636751 4712 #define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
yihui 1:fc2f9d636751 4713 #define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4714 #define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4715 #define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */
yihui 1:fc2f9d636751 4716
yihui 1:fc2f9d636751 4717 /* Bit 5 : Patch 5 enabled. */
yihui 1:fc2f9d636751 4718 #define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
yihui 1:fc2f9d636751 4719 #define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
yihui 1:fc2f9d636751 4720 #define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4721 #define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4722 #define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */
yihui 1:fc2f9d636751 4723
yihui 1:fc2f9d636751 4724 /* Bit 4 : Patch 4 enabled. */
yihui 1:fc2f9d636751 4725 #define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
yihui 1:fc2f9d636751 4726 #define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
yihui 1:fc2f9d636751 4727 #define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4728 #define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4729 #define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */
yihui 1:fc2f9d636751 4730
yihui 1:fc2f9d636751 4731 /* Bit 3 : Patch 3 enabled. */
yihui 1:fc2f9d636751 4732 #define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
yihui 1:fc2f9d636751 4733 #define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
yihui 1:fc2f9d636751 4734 #define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4735 #define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4736 #define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */
yihui 1:fc2f9d636751 4737
yihui 1:fc2f9d636751 4738 /* Bit 2 : Patch 2 enabled. */
yihui 1:fc2f9d636751 4739 #define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
yihui 1:fc2f9d636751 4740 #define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
yihui 1:fc2f9d636751 4741 #define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4742 #define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4743 #define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */
yihui 1:fc2f9d636751 4744
yihui 1:fc2f9d636751 4745 /* Bit 1 : Patch 1 enabled. */
yihui 1:fc2f9d636751 4746 #define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
yihui 1:fc2f9d636751 4747 #define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
yihui 1:fc2f9d636751 4748 #define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4749 #define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4750 #define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */
yihui 1:fc2f9d636751 4751
yihui 1:fc2f9d636751 4752 /* Bit 0 : Patch 0 enabled. */
yihui 1:fc2f9d636751 4753 #define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
yihui 1:fc2f9d636751 4754 #define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
yihui 1:fc2f9d636751 4755 #define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4756 #define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4757 #define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */
yihui 1:fc2f9d636751 4758
yihui 1:fc2f9d636751 4759 /* Register: PU_PATCHENCLR */
yihui 1:fc2f9d636751 4760 /* Description: Patch disable register. */
yihui 1:fc2f9d636751 4761
yihui 1:fc2f9d636751 4762 /* Bit 7 : Patch 7 enabled. */
yihui 1:fc2f9d636751 4763 #define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
yihui 1:fc2f9d636751 4764 #define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
yihui 1:fc2f9d636751 4765 #define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4766 #define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4767 #define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */
yihui 1:fc2f9d636751 4768
yihui 1:fc2f9d636751 4769 /* Bit 6 : Patch 6 enabled. */
yihui 1:fc2f9d636751 4770 #define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
yihui 1:fc2f9d636751 4771 #define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
yihui 1:fc2f9d636751 4772 #define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4773 #define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4774 #define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */
yihui 1:fc2f9d636751 4775
yihui 1:fc2f9d636751 4776 /* Bit 5 : Patch 5 enabled. */
yihui 1:fc2f9d636751 4777 #define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
yihui 1:fc2f9d636751 4778 #define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
yihui 1:fc2f9d636751 4779 #define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4780 #define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4781 #define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */
yihui 1:fc2f9d636751 4782
yihui 1:fc2f9d636751 4783 /* Bit 4 : Patch 4 enabled. */
yihui 1:fc2f9d636751 4784 #define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
yihui 1:fc2f9d636751 4785 #define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
yihui 1:fc2f9d636751 4786 #define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4787 #define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4788 #define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */
yihui 1:fc2f9d636751 4789
yihui 1:fc2f9d636751 4790 /* Bit 3 : Patch 3 enabled. */
yihui 1:fc2f9d636751 4791 #define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
yihui 1:fc2f9d636751 4792 #define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
yihui 1:fc2f9d636751 4793 #define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4794 #define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4795 #define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */
yihui 1:fc2f9d636751 4796
yihui 1:fc2f9d636751 4797 /* Bit 2 : Patch 2 enabled. */
yihui 1:fc2f9d636751 4798 #define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
yihui 1:fc2f9d636751 4799 #define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
yihui 1:fc2f9d636751 4800 #define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4801 #define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4802 #define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */
yihui 1:fc2f9d636751 4803
yihui 1:fc2f9d636751 4804 /* Bit 1 : Patch 1 enabled. */
yihui 1:fc2f9d636751 4805 #define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
yihui 1:fc2f9d636751 4806 #define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
yihui 1:fc2f9d636751 4807 #define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4808 #define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4809 #define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */
yihui 1:fc2f9d636751 4810
yihui 1:fc2f9d636751 4811 /* Bit 0 : Patch 0 enabled. */
yihui 1:fc2f9d636751 4812 #define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
yihui 1:fc2f9d636751 4813 #define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
yihui 1:fc2f9d636751 4814 #define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */
yihui 1:fc2f9d636751 4815 #define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */
yihui 1:fc2f9d636751 4816 #define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */
yihui 1:fc2f9d636751 4817
yihui 1:fc2f9d636751 4818
yihui 1:fc2f9d636751 4819 /* Peripheral: QDEC */
yihui 1:fc2f9d636751 4820 /* Description: Rotary decoder. */
yihui 1:fc2f9d636751 4821
yihui 1:fc2f9d636751 4822 /* Register: QDEC_SHORTS */
yihui 1:fc2f9d636751 4823 /* Description: Shortcuts for the QDEC. */
yihui 1:fc2f9d636751 4824
yihui 1:fc2f9d636751 4825 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
yihui 1:fc2f9d636751 4826 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
yihui 1:fc2f9d636751 4827 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
yihui 1:fc2f9d636751 4828 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 4829 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 4830
yihui 1:fc2f9d636751 4831 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
yihui 1:fc2f9d636751 4832 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
yihui 1:fc2f9d636751 4833 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
yihui 1:fc2f9d636751 4834 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 4835 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 4836
yihui 1:fc2f9d636751 4837 /* Register: QDEC_INTENSET */
yihui 1:fc2f9d636751 4838 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 4839
yihui 1:fc2f9d636751 4840 /* Bit 2 : Enable interrupt on ACCOF event. */
yihui 1:fc2f9d636751 4841 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
yihui 1:fc2f9d636751 4842 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
yihui 1:fc2f9d636751 4843 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 4844 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 4845 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 4846
yihui 1:fc2f9d636751 4847 /* Bit 1 : Enable interrupt on REPORTRDY event. */
yihui 1:fc2f9d636751 4848 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
yihui 1:fc2f9d636751 4849 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
yihui 1:fc2f9d636751 4850 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 4851 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 4852 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 4853
yihui 1:fc2f9d636751 4854 /* Bit 0 : Enable interrupt on SAMPLERDY event. */
yihui 1:fc2f9d636751 4855 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
yihui 1:fc2f9d636751 4856 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
yihui 1:fc2f9d636751 4857 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 4858 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 4859 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 4860
yihui 1:fc2f9d636751 4861 /* Register: QDEC_INTENCLR */
yihui 1:fc2f9d636751 4862 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 4863
yihui 1:fc2f9d636751 4864 /* Bit 2 : Disable interrupt on ACCOF event. */
yihui 1:fc2f9d636751 4865 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
yihui 1:fc2f9d636751 4866 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
yihui 1:fc2f9d636751 4867 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 4868 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 4869 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 4870
yihui 1:fc2f9d636751 4871 /* Bit 1 : Disable interrupt on REPORTRDY event. */
yihui 1:fc2f9d636751 4872 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
yihui 1:fc2f9d636751 4873 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
yihui 1:fc2f9d636751 4874 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 4875 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 4876 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 4877
yihui 1:fc2f9d636751 4878 /* Bit 0 : Disable interrupt on SAMPLERDY event. */
yihui 1:fc2f9d636751 4879 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
yihui 1:fc2f9d636751 4880 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
yihui 1:fc2f9d636751 4881 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 4882 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 4883 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 4884
yihui 1:fc2f9d636751 4885 /* Register: QDEC_ENABLE */
yihui 1:fc2f9d636751 4886 /* Description: Enable the QDEC. */
yihui 1:fc2f9d636751 4887
yihui 1:fc2f9d636751 4888 /* Bit 0 : Enable or disable QDEC. */
yihui 1:fc2f9d636751 4889 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
yihui 1:fc2f9d636751 4890 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
yihui 1:fc2f9d636751 4891 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
yihui 1:fc2f9d636751 4892 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
yihui 1:fc2f9d636751 4893
yihui 1:fc2f9d636751 4894 /* Register: QDEC_LEDPOL */
yihui 1:fc2f9d636751 4895 /* Description: LED output pin polarity. */
yihui 1:fc2f9d636751 4896
yihui 1:fc2f9d636751 4897 /* Bit 0 : LED output pin polarity. */
yihui 1:fc2f9d636751 4898 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
yihui 1:fc2f9d636751 4899 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
yihui 1:fc2f9d636751 4900 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
yihui 1:fc2f9d636751 4901 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
yihui 1:fc2f9d636751 4902
yihui 1:fc2f9d636751 4903 /* Register: QDEC_SAMPLEPER */
yihui 1:fc2f9d636751 4904 /* Description: Sample period. */
yihui 1:fc2f9d636751 4905
yihui 1:fc2f9d636751 4906 /* Bits 2..0 : Sample period. */
yihui 1:fc2f9d636751 4907 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
yihui 1:fc2f9d636751 4908 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
yihui 1:fc2f9d636751 4909 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
yihui 1:fc2f9d636751 4910 #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
yihui 1:fc2f9d636751 4911 #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
yihui 1:fc2f9d636751 4912 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
yihui 1:fc2f9d636751 4913 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
yihui 1:fc2f9d636751 4914 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
yihui 1:fc2f9d636751 4915 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
yihui 1:fc2f9d636751 4916 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
yihui 1:fc2f9d636751 4917
yihui 1:fc2f9d636751 4918 /* Register: QDEC_SAMPLE */
yihui 1:fc2f9d636751 4919 /* Description: Motion sample value. */
yihui 1:fc2f9d636751 4920
yihui 1:fc2f9d636751 4921 /* Bits 31..0 : Last sample taken in compliment to 2. */
yihui 1:fc2f9d636751 4922 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
yihui 1:fc2f9d636751 4923 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
yihui 1:fc2f9d636751 4924
yihui 1:fc2f9d636751 4925 /* Register: QDEC_REPORTPER */
yihui 1:fc2f9d636751 4926 /* Description: Number of samples to generate an EVENT_REPORTRDY. */
yihui 1:fc2f9d636751 4927
yihui 1:fc2f9d636751 4928 /* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
yihui 1:fc2f9d636751 4929 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
yihui 1:fc2f9d636751 4930 #define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
yihui 1:fc2f9d636751 4931 #define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
yihui 1:fc2f9d636751 4932 #define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
yihui 1:fc2f9d636751 4933 #define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
yihui 1:fc2f9d636751 4934 #define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
yihui 1:fc2f9d636751 4935 #define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
yihui 1:fc2f9d636751 4936 #define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
yihui 1:fc2f9d636751 4937 #define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
yihui 1:fc2f9d636751 4938 #define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
yihui 1:fc2f9d636751 4939
yihui 1:fc2f9d636751 4940 /* Register: QDEC_DBFEN */
yihui 1:fc2f9d636751 4941 /* Description: Enable debouncer input filters. */
yihui 1:fc2f9d636751 4942
yihui 1:fc2f9d636751 4943 /* Bit 0 : Enable debounce input filters. */
yihui 1:fc2f9d636751 4944 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
yihui 1:fc2f9d636751 4945 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
yihui 1:fc2f9d636751 4946 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
yihui 1:fc2f9d636751 4947 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
yihui 1:fc2f9d636751 4948
yihui 1:fc2f9d636751 4949 /* Register: QDEC_LEDPRE */
yihui 1:fc2f9d636751 4950 /* Description: Time LED is switched ON before the sample. */
yihui 1:fc2f9d636751 4951
yihui 1:fc2f9d636751 4952 /* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
yihui 1:fc2f9d636751 4953 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
yihui 1:fc2f9d636751 4954 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
yihui 1:fc2f9d636751 4955
yihui 1:fc2f9d636751 4956 /* Register: QDEC_ACCDBL */
yihui 1:fc2f9d636751 4957 /* Description: Accumulated double (error) transitions register. */
yihui 1:fc2f9d636751 4958
yihui 1:fc2f9d636751 4959 /* Bits 3..0 : Accumulated double (error) transitions. */
yihui 1:fc2f9d636751 4960 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
yihui 1:fc2f9d636751 4961 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
yihui 1:fc2f9d636751 4962
yihui 1:fc2f9d636751 4963 /* Register: QDEC_ACCDBLREAD */
yihui 1:fc2f9d636751 4964 /* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
yihui 1:fc2f9d636751 4965
yihui 1:fc2f9d636751 4966 /* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
yihui 1:fc2f9d636751 4967 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
yihui 1:fc2f9d636751 4968 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
yihui 1:fc2f9d636751 4969
yihui 1:fc2f9d636751 4970 /* Register: QDEC_POWER */
yihui 1:fc2f9d636751 4971 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 4972
yihui 1:fc2f9d636751 4973 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 4974 #define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 4975 #define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 4976 #define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 4977 #define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 4978
yihui 1:fc2f9d636751 4979
yihui 1:fc2f9d636751 4980 /* Peripheral: RADIO */
yihui 1:fc2f9d636751 4981 /* Description: The radio. */
yihui 1:fc2f9d636751 4982
yihui 1:fc2f9d636751 4983 /* Register: RADIO_SHORTS */
yihui 1:fc2f9d636751 4984 /* Description: Shortcuts for the radio. */
yihui 1:fc2f9d636751 4985
yihui 1:fc2f9d636751 4986 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
yihui 1:fc2f9d636751 4987 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
yihui 1:fc2f9d636751 4988 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
yihui 1:fc2f9d636751 4989 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 4990 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 4991
yihui 1:fc2f9d636751 4992 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
yihui 1:fc2f9d636751 4993 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
yihui 1:fc2f9d636751 4994 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
yihui 1:fc2f9d636751 4995 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 4996 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 4997
yihui 1:fc2f9d636751 4998 /* Bit 5 : Shortcut between END event and START task. */
yihui 1:fc2f9d636751 4999 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
yihui 1:fc2f9d636751 5000 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
yihui 1:fc2f9d636751 5001 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 5002 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 5003
yihui 1:fc2f9d636751 5004 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
yihui 1:fc2f9d636751 5005 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
yihui 1:fc2f9d636751 5006 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
yihui 1:fc2f9d636751 5007 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 5008 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 5009
yihui 1:fc2f9d636751 5010 /* Bit 3 : Shortcut between DISABLED event and RXEN task. */
yihui 1:fc2f9d636751 5011 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
yihui 1:fc2f9d636751 5012 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
yihui 1:fc2f9d636751 5013 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 5014 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 5015
yihui 1:fc2f9d636751 5016 /* Bit 2 : Shortcut between DISABLED event and TXEN task. */
yihui 1:fc2f9d636751 5017 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
yihui 1:fc2f9d636751 5018 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
yihui 1:fc2f9d636751 5019 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 5020 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 5021
yihui 1:fc2f9d636751 5022 /* Bit 1 : Shortcut between END event and DISABLE task. */
yihui 1:fc2f9d636751 5023 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
yihui 1:fc2f9d636751 5024 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
yihui 1:fc2f9d636751 5025 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 5026 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 5027
yihui 1:fc2f9d636751 5028 /* Bit 0 : Shortcut between READY event and START task. */
yihui 1:fc2f9d636751 5029 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
yihui 1:fc2f9d636751 5030 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
yihui 1:fc2f9d636751 5031 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 5032 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 5033
yihui 1:fc2f9d636751 5034 /* Register: RADIO_INTENSET */
yihui 1:fc2f9d636751 5035 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 5036
yihui 1:fc2f9d636751 5037 /* Bit 10 : Enable interrupt on BCMATCH event. */
yihui 1:fc2f9d636751 5038 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
yihui 1:fc2f9d636751 5039 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
yihui 1:fc2f9d636751 5040 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5041 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5042 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5043
yihui 1:fc2f9d636751 5044 /* Bit 7 : Enable interrupt on RSSIEND event. */
yihui 1:fc2f9d636751 5045 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
yihui 1:fc2f9d636751 5046 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
yihui 1:fc2f9d636751 5047 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5048 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5049 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5050
yihui 1:fc2f9d636751 5051 /* Bit 6 : Enable interrupt on DEVMISS event. */
yihui 1:fc2f9d636751 5052 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
yihui 1:fc2f9d636751 5053 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
yihui 1:fc2f9d636751 5054 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5055 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5056 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5057
yihui 1:fc2f9d636751 5058 /* Bit 5 : Enable interrupt on DEVMATCH event. */
yihui 1:fc2f9d636751 5059 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
yihui 1:fc2f9d636751 5060 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
yihui 1:fc2f9d636751 5061 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5062 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5063 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5064
yihui 1:fc2f9d636751 5065 /* Bit 4 : Enable interrupt on DISABLED event. */
yihui 1:fc2f9d636751 5066 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
yihui 1:fc2f9d636751 5067 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
yihui 1:fc2f9d636751 5068 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5069 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5070 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5071
yihui 1:fc2f9d636751 5072 /* Bit 3 : Enable interrupt on END event. */
yihui 1:fc2f9d636751 5073 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
yihui 1:fc2f9d636751 5074 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
yihui 1:fc2f9d636751 5075 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5076 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5077 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5078
yihui 1:fc2f9d636751 5079 /* Bit 2 : Enable interrupt on PAYLOAD event. */
yihui 1:fc2f9d636751 5080 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
yihui 1:fc2f9d636751 5081 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
yihui 1:fc2f9d636751 5082 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5083 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5084 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5085
yihui 1:fc2f9d636751 5086 /* Bit 1 : Enable interrupt on ADDRESS event. */
yihui 1:fc2f9d636751 5087 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
yihui 1:fc2f9d636751 5088 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
yihui 1:fc2f9d636751 5089 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5090 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5091 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5092
yihui 1:fc2f9d636751 5093 /* Bit 0 : Enable interrupt on READY event. */
yihui 1:fc2f9d636751 5094 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
yihui 1:fc2f9d636751 5095 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
yihui 1:fc2f9d636751 5096 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5097 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5098 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5099
yihui 1:fc2f9d636751 5100 /* Register: RADIO_INTENCLR */
yihui 1:fc2f9d636751 5101 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 5102
yihui 1:fc2f9d636751 5103 /* Bit 10 : Disable interrupt on BCMATCH event. */
yihui 1:fc2f9d636751 5104 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
yihui 1:fc2f9d636751 5105 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
yihui 1:fc2f9d636751 5106 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5107 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5108 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5109
yihui 1:fc2f9d636751 5110 /* Bit 7 : Disable interrupt on RSSIEND event. */
yihui 1:fc2f9d636751 5111 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
yihui 1:fc2f9d636751 5112 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
yihui 1:fc2f9d636751 5113 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5114 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5115 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5116
yihui 1:fc2f9d636751 5117 /* Bit 6 : Disable interrupt on DEVMISS event. */
yihui 1:fc2f9d636751 5118 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
yihui 1:fc2f9d636751 5119 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
yihui 1:fc2f9d636751 5120 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5121 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5122 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5123
yihui 1:fc2f9d636751 5124 /* Bit 5 : Disable interrupt on DEVMATCH event. */
yihui 1:fc2f9d636751 5125 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
yihui 1:fc2f9d636751 5126 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
yihui 1:fc2f9d636751 5127 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5128 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5129 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5130
yihui 1:fc2f9d636751 5131 /* Bit 4 : Disable interrupt on DISABLED event. */
yihui 1:fc2f9d636751 5132 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
yihui 1:fc2f9d636751 5133 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
yihui 1:fc2f9d636751 5134 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5135 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5136 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5137
yihui 1:fc2f9d636751 5138 /* Bit 3 : Disable interrupt on END event. */
yihui 1:fc2f9d636751 5139 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
yihui 1:fc2f9d636751 5140 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
yihui 1:fc2f9d636751 5141 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5142 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5143 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5144
yihui 1:fc2f9d636751 5145 /* Bit 2 : Disable interrupt on PAYLOAD event. */
yihui 1:fc2f9d636751 5146 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
yihui 1:fc2f9d636751 5147 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
yihui 1:fc2f9d636751 5148 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5149 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5150 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5151
yihui 1:fc2f9d636751 5152 /* Bit 1 : Disable interrupt on ADDRESS event. */
yihui 1:fc2f9d636751 5153 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
yihui 1:fc2f9d636751 5154 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
yihui 1:fc2f9d636751 5155 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5156 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5157 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5158
yihui 1:fc2f9d636751 5159 /* Bit 0 : Disable interrupt on READY event. */
yihui 1:fc2f9d636751 5160 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
yihui 1:fc2f9d636751 5161 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
yihui 1:fc2f9d636751 5162 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5163 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5164 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5165
yihui 1:fc2f9d636751 5166 /* Register: RADIO_CRCSTATUS */
yihui 1:fc2f9d636751 5167 /* Description: CRC status of received packet. */
yihui 1:fc2f9d636751 5168
yihui 1:fc2f9d636751 5169 /* Bit 0 : CRC status of received packet. */
yihui 1:fc2f9d636751 5170 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
yihui 1:fc2f9d636751 5171 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
yihui 1:fc2f9d636751 5172 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
yihui 1:fc2f9d636751 5173 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
yihui 1:fc2f9d636751 5174
yihui 1:fc2f9d636751 5175 /* Register: RADIO_CD */
yihui 1:fc2f9d636751 5176 /* Description: Carrier detect. */
yihui 1:fc2f9d636751 5177
yihui 1:fc2f9d636751 5178 /* Bit 0 : Carrier detect. */
yihui 1:fc2f9d636751 5179 #define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */
yihui 1:fc2f9d636751 5180 #define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */
yihui 1:fc2f9d636751 5181
yihui 1:fc2f9d636751 5182 /* Register: RADIO_RXMATCH */
yihui 1:fc2f9d636751 5183 /* Description: Received address. */
yihui 1:fc2f9d636751 5184
yihui 1:fc2f9d636751 5185 /* Bits 2..0 : Logical address in which previous packet was received. */
yihui 1:fc2f9d636751 5186 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
yihui 1:fc2f9d636751 5187 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
yihui 1:fc2f9d636751 5188
yihui 1:fc2f9d636751 5189 /* Register: RADIO_RXCRC */
yihui 1:fc2f9d636751 5190 /* Description: Received CRC. */
yihui 1:fc2f9d636751 5191
yihui 1:fc2f9d636751 5192 /* Bits 23..0 : CRC field of previously received packet. */
yihui 1:fc2f9d636751 5193 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
yihui 1:fc2f9d636751 5194 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
yihui 1:fc2f9d636751 5195
yihui 1:fc2f9d636751 5196 /* Register: RADIO_DAI */
yihui 1:fc2f9d636751 5197 /* Description: Device address match index. */
yihui 1:fc2f9d636751 5198
yihui 1:fc2f9d636751 5199 /* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
yihui 1:fc2f9d636751 5200 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
yihui 1:fc2f9d636751 5201 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
yihui 1:fc2f9d636751 5202
yihui 1:fc2f9d636751 5203 /* Register: RADIO_FREQUENCY */
yihui 1:fc2f9d636751 5204 /* Description: Frequency. */
yihui 1:fc2f9d636751 5205
yihui 1:fc2f9d636751 5206 /* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
yihui 1:fc2f9d636751 5207 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
yihui 1:fc2f9d636751 5208 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
yihui 1:fc2f9d636751 5209
yihui 1:fc2f9d636751 5210 /* Register: RADIO_TXPOWER */
yihui 1:fc2f9d636751 5211 /* Description: Output power. */
yihui 1:fc2f9d636751 5212
yihui 1:fc2f9d636751 5213 /* Bits 7..0 : Radio output power. Decision point: TXEN task. */
yihui 1:fc2f9d636751 5214 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
yihui 1:fc2f9d636751 5215 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
yihui 1:fc2f9d636751 5216 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
yihui 1:fc2f9d636751 5217 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
yihui 1:fc2f9d636751 5218 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
yihui 1:fc2f9d636751 5219 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
yihui 1:fc2f9d636751 5220 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
yihui 1:fc2f9d636751 5221 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
yihui 1:fc2f9d636751 5222 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
yihui 1:fc2f9d636751 5223 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
yihui 1:fc2f9d636751 5224
yihui 1:fc2f9d636751 5225 /* Register: RADIO_MODE */
yihui 1:fc2f9d636751 5226 /* Description: Data rate and modulation. */
yihui 1:fc2f9d636751 5227
yihui 1:fc2f9d636751 5228 /* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
yihui 1:fc2f9d636751 5229 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
yihui 1:fc2f9d636751 5230 #define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
yihui 1:fc2f9d636751 5231 #define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
yihui 1:fc2f9d636751 5232 #define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
yihui 1:fc2f9d636751 5233 #define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
yihui 1:fc2f9d636751 5234 #define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
yihui 1:fc2f9d636751 5235
yihui 1:fc2f9d636751 5236 /* Register: RADIO_PCNF0 */
yihui 1:fc2f9d636751 5237 /* Description: Packet configuration 0. */
yihui 1:fc2f9d636751 5238
yihui 1:fc2f9d636751 5239 /* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
yihui 1:fc2f9d636751 5240 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
yihui 1:fc2f9d636751 5241 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
yihui 1:fc2f9d636751 5242
yihui 1:fc2f9d636751 5243 /* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
yihui 1:fc2f9d636751 5244 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
yihui 1:fc2f9d636751 5245 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
yihui 1:fc2f9d636751 5246
yihui 1:fc2f9d636751 5247 /* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
yihui 1:fc2f9d636751 5248 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
yihui 1:fc2f9d636751 5249 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
yihui 1:fc2f9d636751 5250
yihui 1:fc2f9d636751 5251 /* Register: RADIO_PCNF1 */
yihui 1:fc2f9d636751 5252 /* Description: Packet configuration 1. */
yihui 1:fc2f9d636751 5253
yihui 1:fc2f9d636751 5254 /* Bit 25 : Packet whitening enable. */
yihui 1:fc2f9d636751 5255 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
yihui 1:fc2f9d636751 5256 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
yihui 1:fc2f9d636751 5257 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
yihui 1:fc2f9d636751 5258 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
yihui 1:fc2f9d636751 5259
yihui 1:fc2f9d636751 5260 /* Bit 24 : On air endianness of packet length field. Decision point: START task. */
yihui 1:fc2f9d636751 5261 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
yihui 1:fc2f9d636751 5262 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
yihui 1:fc2f9d636751 5263 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
yihui 1:fc2f9d636751 5264 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
yihui 1:fc2f9d636751 5265
yihui 1:fc2f9d636751 5266 /* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
yihui 1:fc2f9d636751 5267 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
yihui 1:fc2f9d636751 5268 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
yihui 1:fc2f9d636751 5269
yihui 1:fc2f9d636751 5270 /* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
yihui 1:fc2f9d636751 5271 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
yihui 1:fc2f9d636751 5272 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
yihui 1:fc2f9d636751 5273
yihui 1:fc2f9d636751 5274 /* Bits 7..0 : Maximum length of packet payload in number of bytes. */
yihui 1:fc2f9d636751 5275 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
yihui 1:fc2f9d636751 5276 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
yihui 1:fc2f9d636751 5277
yihui 1:fc2f9d636751 5278 /* Register: RADIO_PREFIX0 */
yihui 1:fc2f9d636751 5279 /* Description: Prefixes bytes for logical addresses 0 to 3. */
yihui 1:fc2f9d636751 5280
yihui 1:fc2f9d636751 5281 /* Bits 31..24 : Address prefix 3. Decision point: START task. */
yihui 1:fc2f9d636751 5282 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
yihui 1:fc2f9d636751 5283 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
yihui 1:fc2f9d636751 5284
yihui 1:fc2f9d636751 5285 /* Bits 23..16 : Address prefix 2. Decision point: START task. */
yihui 1:fc2f9d636751 5286 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
yihui 1:fc2f9d636751 5287 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
yihui 1:fc2f9d636751 5288
yihui 1:fc2f9d636751 5289 /* Bits 15..8 : Address prefix 1. Decision point: START task. */
yihui 1:fc2f9d636751 5290 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
yihui 1:fc2f9d636751 5291 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
yihui 1:fc2f9d636751 5292
yihui 1:fc2f9d636751 5293 /* Bits 7..0 : Address prefix 0. Decision point: START task. */
yihui 1:fc2f9d636751 5294 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
yihui 1:fc2f9d636751 5295 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
yihui 1:fc2f9d636751 5296
yihui 1:fc2f9d636751 5297 /* Register: RADIO_PREFIX1 */
yihui 1:fc2f9d636751 5298 /* Description: Prefixes bytes for logical addresses 4 to 7. */
yihui 1:fc2f9d636751 5299
yihui 1:fc2f9d636751 5300 /* Bits 31..24 : Address prefix 7. Decision point: START task. */
yihui 1:fc2f9d636751 5301 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
yihui 1:fc2f9d636751 5302 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
yihui 1:fc2f9d636751 5303
yihui 1:fc2f9d636751 5304 /* Bits 23..16 : Address prefix 6. Decision point: START task. */
yihui 1:fc2f9d636751 5305 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
yihui 1:fc2f9d636751 5306 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
yihui 1:fc2f9d636751 5307
yihui 1:fc2f9d636751 5308 /* Bits 15..8 : Address prefix 5. Decision point: START task. */
yihui 1:fc2f9d636751 5309 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
yihui 1:fc2f9d636751 5310 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
yihui 1:fc2f9d636751 5311
yihui 1:fc2f9d636751 5312 /* Bits 7..0 : Address prefix 4. Decision point: START task. */
yihui 1:fc2f9d636751 5313 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
yihui 1:fc2f9d636751 5314 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
yihui 1:fc2f9d636751 5315
yihui 1:fc2f9d636751 5316 /* Register: RADIO_TXADDRESS */
yihui 1:fc2f9d636751 5317 /* Description: Transmit address select. */
yihui 1:fc2f9d636751 5318
yihui 1:fc2f9d636751 5319 /* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
yihui 1:fc2f9d636751 5320 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
yihui 1:fc2f9d636751 5321 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
yihui 1:fc2f9d636751 5322
yihui 1:fc2f9d636751 5323 /* Register: RADIO_RXADDRESSES */
yihui 1:fc2f9d636751 5324 /* Description: Receive address select. */
yihui 1:fc2f9d636751 5325
yihui 1:fc2f9d636751 5326 /* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
yihui 1:fc2f9d636751 5327 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
yihui 1:fc2f9d636751 5328 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
yihui 1:fc2f9d636751 5329 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
yihui 1:fc2f9d636751 5330 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
yihui 1:fc2f9d636751 5331
yihui 1:fc2f9d636751 5332 /* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
yihui 1:fc2f9d636751 5333 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
yihui 1:fc2f9d636751 5334 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
yihui 1:fc2f9d636751 5335 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
yihui 1:fc2f9d636751 5336 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
yihui 1:fc2f9d636751 5337
yihui 1:fc2f9d636751 5338 /* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
yihui 1:fc2f9d636751 5339 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
yihui 1:fc2f9d636751 5340 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
yihui 1:fc2f9d636751 5341 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
yihui 1:fc2f9d636751 5342 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
yihui 1:fc2f9d636751 5343
yihui 1:fc2f9d636751 5344 /* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
yihui 1:fc2f9d636751 5345 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
yihui 1:fc2f9d636751 5346 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
yihui 1:fc2f9d636751 5347 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
yihui 1:fc2f9d636751 5348 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
yihui 1:fc2f9d636751 5349
yihui 1:fc2f9d636751 5350 /* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
yihui 1:fc2f9d636751 5351 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
yihui 1:fc2f9d636751 5352 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
yihui 1:fc2f9d636751 5353 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
yihui 1:fc2f9d636751 5354 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
yihui 1:fc2f9d636751 5355
yihui 1:fc2f9d636751 5356 /* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
yihui 1:fc2f9d636751 5357 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
yihui 1:fc2f9d636751 5358 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
yihui 1:fc2f9d636751 5359 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
yihui 1:fc2f9d636751 5360 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
yihui 1:fc2f9d636751 5361
yihui 1:fc2f9d636751 5362 /* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
yihui 1:fc2f9d636751 5363 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
yihui 1:fc2f9d636751 5364 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
yihui 1:fc2f9d636751 5365 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
yihui 1:fc2f9d636751 5366 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
yihui 1:fc2f9d636751 5367
yihui 1:fc2f9d636751 5368 /* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
yihui 1:fc2f9d636751 5369 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
yihui 1:fc2f9d636751 5370 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
yihui 1:fc2f9d636751 5371 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
yihui 1:fc2f9d636751 5372 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
yihui 1:fc2f9d636751 5373
yihui 1:fc2f9d636751 5374 /* Register: RADIO_CRCCNF */
yihui 1:fc2f9d636751 5375 /* Description: CRC configuration. */
yihui 1:fc2f9d636751 5376
yihui 1:fc2f9d636751 5377 /* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
yihui 1:fc2f9d636751 5378 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
yihui 1:fc2f9d636751 5379 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
yihui 1:fc2f9d636751 5380 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
yihui 1:fc2f9d636751 5381 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
yihui 1:fc2f9d636751 5382
yihui 1:fc2f9d636751 5383 /* Bits 1..0 : CRC length. Decision point: START task. */
yihui 1:fc2f9d636751 5384 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
yihui 1:fc2f9d636751 5385 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
yihui 1:fc2f9d636751 5386 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
yihui 1:fc2f9d636751 5387 #define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
yihui 1:fc2f9d636751 5388 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
yihui 1:fc2f9d636751 5389 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
yihui 1:fc2f9d636751 5390
yihui 1:fc2f9d636751 5391 /* Register: RADIO_CRCPOLY */
yihui 1:fc2f9d636751 5392 /* Description: CRC polynomial. */
yihui 1:fc2f9d636751 5393
yihui 1:fc2f9d636751 5394 /* Bits 23..0 : CRC polynomial. Decision point: START task. */
yihui 1:fc2f9d636751 5395 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
yihui 1:fc2f9d636751 5396 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
yihui 1:fc2f9d636751 5397
yihui 1:fc2f9d636751 5398 /* Register: RADIO_CRCINIT */
yihui 1:fc2f9d636751 5399 /* Description: CRC initial value. */
yihui 1:fc2f9d636751 5400
yihui 1:fc2f9d636751 5401 /* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
yihui 1:fc2f9d636751 5402 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
yihui 1:fc2f9d636751 5403 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
yihui 1:fc2f9d636751 5404
yihui 1:fc2f9d636751 5405 /* Register: RADIO_TEST */
yihui 1:fc2f9d636751 5406 /* Description: Test features enable register. */
yihui 1:fc2f9d636751 5407
yihui 1:fc2f9d636751 5408 /* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
yihui 1:fc2f9d636751 5409 #define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */
yihui 1:fc2f9d636751 5410 #define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */
yihui 1:fc2f9d636751 5411 #define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */
yihui 1:fc2f9d636751 5412 #define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */
yihui 1:fc2f9d636751 5413
yihui 1:fc2f9d636751 5414 /* Bit 0 : Constant carrier. Decision point: TXEN task. */
yihui 1:fc2f9d636751 5415 #define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */
yihui 1:fc2f9d636751 5416 #define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */
yihui 1:fc2f9d636751 5417 #define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
yihui 1:fc2f9d636751 5418 #define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
yihui 1:fc2f9d636751 5419
yihui 1:fc2f9d636751 5420 /* Register: RADIO_TIFS */
yihui 1:fc2f9d636751 5421 /* Description: Inter Frame Spacing in microseconds. */
yihui 1:fc2f9d636751 5422
yihui 1:fc2f9d636751 5423 /* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
yihui 1:fc2f9d636751 5424 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
yihui 1:fc2f9d636751 5425 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
yihui 1:fc2f9d636751 5426
yihui 1:fc2f9d636751 5427 /* Register: RADIO_RSSISAMPLE */
yihui 1:fc2f9d636751 5428 /* Description: RSSI sample. */
yihui 1:fc2f9d636751 5429
yihui 1:fc2f9d636751 5430 /* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
yihui 1:fc2f9d636751 5431 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
yihui 1:fc2f9d636751 5432 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
yihui 1:fc2f9d636751 5433
yihui 1:fc2f9d636751 5434 /* Register: RADIO_STATE */
yihui 1:fc2f9d636751 5435 /* Description: Current radio state. */
yihui 1:fc2f9d636751 5436
yihui 1:fc2f9d636751 5437 /* Bits 3..0 : Current radio state. */
yihui 1:fc2f9d636751 5438 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
yihui 1:fc2f9d636751 5439 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
yihui 1:fc2f9d636751 5440 #define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
yihui 1:fc2f9d636751 5441 #define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
yihui 1:fc2f9d636751 5442 #define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
yihui 1:fc2f9d636751 5443 #define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
yihui 1:fc2f9d636751 5444 #define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
yihui 1:fc2f9d636751 5445 #define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
yihui 1:fc2f9d636751 5446 #define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
yihui 1:fc2f9d636751 5447 #define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
yihui 1:fc2f9d636751 5448 #define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
yihui 1:fc2f9d636751 5449
yihui 1:fc2f9d636751 5450 /* Register: RADIO_DATAWHITEIV */
yihui 1:fc2f9d636751 5451 /* Description: Data whitening initial value. */
yihui 1:fc2f9d636751 5452
yihui 1:fc2f9d636751 5453 /* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
yihui 1:fc2f9d636751 5454 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
yihui 1:fc2f9d636751 5455 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
yihui 1:fc2f9d636751 5456
yihui 1:fc2f9d636751 5457 /* Register: RADIO_DAP */
yihui 1:fc2f9d636751 5458 /* Description: Device address prefix. */
yihui 1:fc2f9d636751 5459
yihui 1:fc2f9d636751 5460 /* Bits 15..0 : Device address prefix. */
yihui 1:fc2f9d636751 5461 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
yihui 1:fc2f9d636751 5462 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
yihui 1:fc2f9d636751 5463
yihui 1:fc2f9d636751 5464 /* Register: RADIO_DACNF */
yihui 1:fc2f9d636751 5465 /* Description: Device address match configuration. */
yihui 1:fc2f9d636751 5466
yihui 1:fc2f9d636751 5467 /* Bit 15 : TxAdd for device address 7. */
yihui 1:fc2f9d636751 5468 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
yihui 1:fc2f9d636751 5469 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
yihui 1:fc2f9d636751 5470
yihui 1:fc2f9d636751 5471 /* Bit 14 : TxAdd for device address 6. */
yihui 1:fc2f9d636751 5472 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
yihui 1:fc2f9d636751 5473 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
yihui 1:fc2f9d636751 5474
yihui 1:fc2f9d636751 5475 /* Bit 13 : TxAdd for device address 5. */
yihui 1:fc2f9d636751 5476 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
yihui 1:fc2f9d636751 5477 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
yihui 1:fc2f9d636751 5478
yihui 1:fc2f9d636751 5479 /* Bit 12 : TxAdd for device address 4. */
yihui 1:fc2f9d636751 5480 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
yihui 1:fc2f9d636751 5481 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
yihui 1:fc2f9d636751 5482
yihui 1:fc2f9d636751 5483 /* Bit 11 : TxAdd for device address 3. */
yihui 1:fc2f9d636751 5484 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
yihui 1:fc2f9d636751 5485 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
yihui 1:fc2f9d636751 5486
yihui 1:fc2f9d636751 5487 /* Bit 10 : TxAdd for device address 2. */
yihui 1:fc2f9d636751 5488 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
yihui 1:fc2f9d636751 5489 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
yihui 1:fc2f9d636751 5490
yihui 1:fc2f9d636751 5491 /* Bit 9 : TxAdd for device address 1. */
yihui 1:fc2f9d636751 5492 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
yihui 1:fc2f9d636751 5493 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
yihui 1:fc2f9d636751 5494
yihui 1:fc2f9d636751 5495 /* Bit 8 : TxAdd for device address 0. */
yihui 1:fc2f9d636751 5496 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
yihui 1:fc2f9d636751 5497 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
yihui 1:fc2f9d636751 5498
yihui 1:fc2f9d636751 5499 /* Bit 7 : Enable or disable device address matching using device address 7. */
yihui 1:fc2f9d636751 5500 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
yihui 1:fc2f9d636751 5501 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
yihui 1:fc2f9d636751 5502 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
yihui 1:fc2f9d636751 5503 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
yihui 1:fc2f9d636751 5504
yihui 1:fc2f9d636751 5505 /* Bit 6 : Enable or disable device address matching using device address 6. */
yihui 1:fc2f9d636751 5506 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
yihui 1:fc2f9d636751 5507 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
yihui 1:fc2f9d636751 5508 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
yihui 1:fc2f9d636751 5509 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
yihui 1:fc2f9d636751 5510
yihui 1:fc2f9d636751 5511 /* Bit 5 : Enable or disable device address matching using device address 5. */
yihui 1:fc2f9d636751 5512 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
yihui 1:fc2f9d636751 5513 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
yihui 1:fc2f9d636751 5514 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
yihui 1:fc2f9d636751 5515 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
yihui 1:fc2f9d636751 5516
yihui 1:fc2f9d636751 5517 /* Bit 4 : Enable or disable device address matching using device address 4. */
yihui 1:fc2f9d636751 5518 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
yihui 1:fc2f9d636751 5519 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
yihui 1:fc2f9d636751 5520 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
yihui 1:fc2f9d636751 5521 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
yihui 1:fc2f9d636751 5522
yihui 1:fc2f9d636751 5523 /* Bit 3 : Enable or disable device address matching using device address 3. */
yihui 1:fc2f9d636751 5524 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
yihui 1:fc2f9d636751 5525 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
yihui 1:fc2f9d636751 5526 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
yihui 1:fc2f9d636751 5527 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
yihui 1:fc2f9d636751 5528
yihui 1:fc2f9d636751 5529 /* Bit 2 : Enable or disable device address matching using device address 2. */
yihui 1:fc2f9d636751 5530 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
yihui 1:fc2f9d636751 5531 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
yihui 1:fc2f9d636751 5532 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
yihui 1:fc2f9d636751 5533 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
yihui 1:fc2f9d636751 5534
yihui 1:fc2f9d636751 5535 /* Bit 1 : Enable or disable device address matching using device address 1. */
yihui 1:fc2f9d636751 5536 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
yihui 1:fc2f9d636751 5537 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
yihui 1:fc2f9d636751 5538 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
yihui 1:fc2f9d636751 5539 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
yihui 1:fc2f9d636751 5540
yihui 1:fc2f9d636751 5541 /* Bit 0 : Enable or disable device address matching using device address 0. */
yihui 1:fc2f9d636751 5542 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
yihui 1:fc2f9d636751 5543 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
yihui 1:fc2f9d636751 5544 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
yihui 1:fc2f9d636751 5545 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
yihui 1:fc2f9d636751 5546
yihui 1:fc2f9d636751 5547 /* Register: RADIO_OVERRIDE0 */
yihui 1:fc2f9d636751 5548 /* Description: Trim value override register 0. */
yihui 1:fc2f9d636751 5549
yihui 1:fc2f9d636751 5550 /* Bits 31..0 : Trim value override 0. */
yihui 1:fc2f9d636751 5551 #define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
yihui 1:fc2f9d636751 5552 #define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
yihui 1:fc2f9d636751 5553
yihui 1:fc2f9d636751 5554 /* Register: RADIO_OVERRIDE1 */
yihui 1:fc2f9d636751 5555 /* Description: Trim value override register 1. */
yihui 1:fc2f9d636751 5556
yihui 1:fc2f9d636751 5557 /* Bits 31..0 : Trim value override 1. */
yihui 1:fc2f9d636751 5558 #define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
yihui 1:fc2f9d636751 5559 #define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
yihui 1:fc2f9d636751 5560
yihui 1:fc2f9d636751 5561 /* Register: RADIO_OVERRIDE2 */
yihui 1:fc2f9d636751 5562 /* Description: Trim value override register 2. */
yihui 1:fc2f9d636751 5563
yihui 1:fc2f9d636751 5564 /* Bits 31..0 : Trim value override 2. */
yihui 1:fc2f9d636751 5565 #define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
yihui 1:fc2f9d636751 5566 #define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
yihui 1:fc2f9d636751 5567
yihui 1:fc2f9d636751 5568 /* Register: RADIO_OVERRIDE3 */
yihui 1:fc2f9d636751 5569 /* Description: Trim value override register 3. */
yihui 1:fc2f9d636751 5570
yihui 1:fc2f9d636751 5571 /* Bits 31..0 : Trim value override 3. */
yihui 1:fc2f9d636751 5572 #define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
yihui 1:fc2f9d636751 5573 #define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
yihui 1:fc2f9d636751 5574
yihui 1:fc2f9d636751 5575 /* Register: RADIO_OVERRIDE4 */
yihui 1:fc2f9d636751 5576 /* Description: Trim value override register 4. */
yihui 1:fc2f9d636751 5577
yihui 1:fc2f9d636751 5578 /* Bit 31 : Enable or disable override of default trim values. */
yihui 1:fc2f9d636751 5579 #define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
yihui 1:fc2f9d636751 5580 #define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
yihui 1:fc2f9d636751 5581 #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
yihui 1:fc2f9d636751 5582 #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
yihui 1:fc2f9d636751 5583
yihui 1:fc2f9d636751 5584 /* Bits 27..0 : Trim value override 4. */
yihui 1:fc2f9d636751 5585 #define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
yihui 1:fc2f9d636751 5586 #define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
yihui 1:fc2f9d636751 5587
yihui 1:fc2f9d636751 5588 /* Register: RADIO_POWER */
yihui 1:fc2f9d636751 5589 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 5590
yihui 1:fc2f9d636751 5591 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 5592 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 5593 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 5594 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 5595 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 5596
yihui 1:fc2f9d636751 5597
yihui 1:fc2f9d636751 5598 /* Peripheral: RNG */
yihui 1:fc2f9d636751 5599 /* Description: Random Number Generator. */
yihui 1:fc2f9d636751 5600
yihui 1:fc2f9d636751 5601 /* Register: RNG_SHORTS */
yihui 1:fc2f9d636751 5602 /* Description: Shortcuts for the RNG. */
yihui 1:fc2f9d636751 5603
yihui 1:fc2f9d636751 5604 /* Bit 0 : Shortcut between VALRDY event and STOP task. */
yihui 1:fc2f9d636751 5605 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
yihui 1:fc2f9d636751 5606 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
yihui 1:fc2f9d636751 5607 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 5608 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 5609
yihui 1:fc2f9d636751 5610 /* Register: RNG_INTENSET */
yihui 1:fc2f9d636751 5611 /* Description: Interrupt enable set register */
yihui 1:fc2f9d636751 5612
yihui 1:fc2f9d636751 5613 /* Bit 0 : Enable interrupt on VALRDY event. */
yihui 1:fc2f9d636751 5614 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
yihui 1:fc2f9d636751 5615 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
yihui 1:fc2f9d636751 5616 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5617 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5618 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5619
yihui 1:fc2f9d636751 5620 /* Register: RNG_INTENCLR */
yihui 1:fc2f9d636751 5621 /* Description: Interrupt enable clear register */
yihui 1:fc2f9d636751 5622
yihui 1:fc2f9d636751 5623 /* Bit 0 : Disable interrupt on VALRDY event. */
yihui 1:fc2f9d636751 5624 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
yihui 1:fc2f9d636751 5625 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
yihui 1:fc2f9d636751 5626 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5627 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5628 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5629
yihui 1:fc2f9d636751 5630 /* Register: RNG_CONFIG */
yihui 1:fc2f9d636751 5631 /* Description: Configuration register. */
yihui 1:fc2f9d636751 5632
yihui 1:fc2f9d636751 5633 /* Bit 0 : Digital error correction enable. */
yihui 1:fc2f9d636751 5634 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
yihui 1:fc2f9d636751 5635 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
yihui 1:fc2f9d636751 5636 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
yihui 1:fc2f9d636751 5637 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
yihui 1:fc2f9d636751 5638
yihui 1:fc2f9d636751 5639 /* Register: RNG_VALUE */
yihui 1:fc2f9d636751 5640 /* Description: RNG random number. */
yihui 1:fc2f9d636751 5641
yihui 1:fc2f9d636751 5642 /* Bits 7..0 : Generated random number. */
yihui 1:fc2f9d636751 5643 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
yihui 1:fc2f9d636751 5644 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
yihui 1:fc2f9d636751 5645
yihui 1:fc2f9d636751 5646 /* Register: RNG_POWER */
yihui 1:fc2f9d636751 5647 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 5648
yihui 1:fc2f9d636751 5649 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 5650 #define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 5651 #define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 5652 #define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 5653 #define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 5654
yihui 1:fc2f9d636751 5655
yihui 1:fc2f9d636751 5656 /* Peripheral: RTC */
yihui 1:fc2f9d636751 5657 /* Description: Real time counter 0. */
yihui 1:fc2f9d636751 5658
yihui 1:fc2f9d636751 5659 /* Register: RTC_INTENSET */
yihui 1:fc2f9d636751 5660 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 5661
yihui 1:fc2f9d636751 5662 /* Bit 19 : Enable interrupt on COMPARE[3] event. */
yihui 1:fc2f9d636751 5663 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
yihui 1:fc2f9d636751 5664 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
yihui 1:fc2f9d636751 5665 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5666 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5667 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5668
yihui 1:fc2f9d636751 5669 /* Bit 18 : Enable interrupt on COMPARE[2] event. */
yihui 1:fc2f9d636751 5670 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
yihui 1:fc2f9d636751 5671 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
yihui 1:fc2f9d636751 5672 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5673 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5674 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5675
yihui 1:fc2f9d636751 5676 /* Bit 17 : Enable interrupt on COMPARE[1] event. */
yihui 1:fc2f9d636751 5677 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
yihui 1:fc2f9d636751 5678 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
yihui 1:fc2f9d636751 5679 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5680 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5681 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5682
yihui 1:fc2f9d636751 5683 /* Bit 16 : Enable interrupt on COMPARE[0] event. */
yihui 1:fc2f9d636751 5684 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
yihui 1:fc2f9d636751 5685 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
yihui 1:fc2f9d636751 5686 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5687 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5688 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5689
yihui 1:fc2f9d636751 5690 /* Bit 1 : Enable interrupt on OVRFLW event. */
yihui 1:fc2f9d636751 5691 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
yihui 1:fc2f9d636751 5692 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
yihui 1:fc2f9d636751 5693 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5694 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5695 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5696
yihui 1:fc2f9d636751 5697 /* Bit 0 : Enable interrupt on TICK event. */
yihui 1:fc2f9d636751 5698 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
yihui 1:fc2f9d636751 5699 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
yihui 1:fc2f9d636751 5700 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5701 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5702 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5703
yihui 1:fc2f9d636751 5704 /* Register: RTC_INTENCLR */
yihui 1:fc2f9d636751 5705 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 5706
yihui 1:fc2f9d636751 5707 /* Bit 19 : Disable interrupt on COMPARE[3] event. */
yihui 1:fc2f9d636751 5708 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
yihui 1:fc2f9d636751 5709 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
yihui 1:fc2f9d636751 5710 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5711 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5712 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5713
yihui 1:fc2f9d636751 5714 /* Bit 18 : Disable interrupt on COMPARE[2] event. */
yihui 1:fc2f9d636751 5715 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
yihui 1:fc2f9d636751 5716 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
yihui 1:fc2f9d636751 5717 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5718 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5719 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5720
yihui 1:fc2f9d636751 5721 /* Bit 17 : Disable interrupt on COMPARE[1] event. */
yihui 1:fc2f9d636751 5722 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
yihui 1:fc2f9d636751 5723 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
yihui 1:fc2f9d636751 5724 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5725 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5726 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5727
yihui 1:fc2f9d636751 5728 /* Bit 16 : Disable interrupt on COMPARE[0] event. */
yihui 1:fc2f9d636751 5729 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
yihui 1:fc2f9d636751 5730 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
yihui 1:fc2f9d636751 5731 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5732 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5733 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5734
yihui 1:fc2f9d636751 5735 /* Bit 1 : Disable interrupt on OVRFLW event. */
yihui 1:fc2f9d636751 5736 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
yihui 1:fc2f9d636751 5737 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
yihui 1:fc2f9d636751 5738 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5739 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5740 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5741
yihui 1:fc2f9d636751 5742 /* Bit 0 : Disable interrupt on TICK event. */
yihui 1:fc2f9d636751 5743 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
yihui 1:fc2f9d636751 5744 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
yihui 1:fc2f9d636751 5745 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5746 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5747 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5748
yihui 1:fc2f9d636751 5749 /* Register: RTC_EVTEN */
yihui 1:fc2f9d636751 5750 /* Description: Configures event enable routing to PPI for each RTC event. */
yihui 1:fc2f9d636751 5751
yihui 1:fc2f9d636751 5752 /* Bit 19 : COMPARE[3] event enable. */
yihui 1:fc2f9d636751 5753 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
yihui 1:fc2f9d636751 5754 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
yihui 1:fc2f9d636751 5755 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5756 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5757
yihui 1:fc2f9d636751 5758 /* Bit 18 : COMPARE[2] event enable. */
yihui 1:fc2f9d636751 5759 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
yihui 1:fc2f9d636751 5760 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
yihui 1:fc2f9d636751 5761 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5762 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5763
yihui 1:fc2f9d636751 5764 /* Bit 17 : COMPARE[1] event enable. */
yihui 1:fc2f9d636751 5765 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
yihui 1:fc2f9d636751 5766 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
yihui 1:fc2f9d636751 5767 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5768 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5769
yihui 1:fc2f9d636751 5770 /* Bit 16 : COMPARE[0] event enable. */
yihui 1:fc2f9d636751 5771 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
yihui 1:fc2f9d636751 5772 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
yihui 1:fc2f9d636751 5773 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5774 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5775
yihui 1:fc2f9d636751 5776 /* Bit 1 : OVRFLW event enable. */
yihui 1:fc2f9d636751 5777 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
yihui 1:fc2f9d636751 5778 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
yihui 1:fc2f9d636751 5779 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5780 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5781
yihui 1:fc2f9d636751 5782 /* Bit 0 : TICK event enable. */
yihui 1:fc2f9d636751 5783 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
yihui 1:fc2f9d636751 5784 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
yihui 1:fc2f9d636751 5785 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5786 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5787
yihui 1:fc2f9d636751 5788 /* Register: RTC_EVTENSET */
yihui 1:fc2f9d636751 5789 /* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
yihui 1:fc2f9d636751 5790
yihui 1:fc2f9d636751 5791 /* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
yihui 1:fc2f9d636751 5792 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
yihui 1:fc2f9d636751 5793 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
yihui 1:fc2f9d636751 5794 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5795 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5796 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
yihui 1:fc2f9d636751 5797
yihui 1:fc2f9d636751 5798 /* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
yihui 1:fc2f9d636751 5799 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
yihui 1:fc2f9d636751 5800 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
yihui 1:fc2f9d636751 5801 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5802 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5803 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
yihui 1:fc2f9d636751 5804
yihui 1:fc2f9d636751 5805 /* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
yihui 1:fc2f9d636751 5806 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
yihui 1:fc2f9d636751 5807 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
yihui 1:fc2f9d636751 5808 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5809 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5810 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
yihui 1:fc2f9d636751 5811
yihui 1:fc2f9d636751 5812 /* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
yihui 1:fc2f9d636751 5813 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
yihui 1:fc2f9d636751 5814 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
yihui 1:fc2f9d636751 5815 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5816 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5817 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
yihui 1:fc2f9d636751 5818
yihui 1:fc2f9d636751 5819 /* Bit 1 : Enable routing to PPI of OVRFLW event. */
yihui 1:fc2f9d636751 5820 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
yihui 1:fc2f9d636751 5821 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
yihui 1:fc2f9d636751 5822 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5823 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5824 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
yihui 1:fc2f9d636751 5825
yihui 1:fc2f9d636751 5826 /* Bit 0 : Enable routing to PPI of TICK event. */
yihui 1:fc2f9d636751 5827 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
yihui 1:fc2f9d636751 5828 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
yihui 1:fc2f9d636751 5829 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5830 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5831 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
yihui 1:fc2f9d636751 5832
yihui 1:fc2f9d636751 5833 /* Register: RTC_EVTENCLR */
yihui 1:fc2f9d636751 5834 /* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
yihui 1:fc2f9d636751 5835
yihui 1:fc2f9d636751 5836 /* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
yihui 1:fc2f9d636751 5837 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
yihui 1:fc2f9d636751 5838 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
yihui 1:fc2f9d636751 5839 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5840 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5841 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
yihui 1:fc2f9d636751 5842
yihui 1:fc2f9d636751 5843 /* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
yihui 1:fc2f9d636751 5844 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
yihui 1:fc2f9d636751 5845 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
yihui 1:fc2f9d636751 5846 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5847 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5848 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
yihui 1:fc2f9d636751 5849
yihui 1:fc2f9d636751 5850 /* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
yihui 1:fc2f9d636751 5851 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
yihui 1:fc2f9d636751 5852 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
yihui 1:fc2f9d636751 5853 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5854 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5855 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
yihui 1:fc2f9d636751 5856
yihui 1:fc2f9d636751 5857 /* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
yihui 1:fc2f9d636751 5858 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
yihui 1:fc2f9d636751 5859 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
yihui 1:fc2f9d636751 5860 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5861 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5862 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
yihui 1:fc2f9d636751 5863
yihui 1:fc2f9d636751 5864 /* Bit 1 : Disable routing to PPI of OVRFLW event. */
yihui 1:fc2f9d636751 5865 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
yihui 1:fc2f9d636751 5866 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
yihui 1:fc2f9d636751 5867 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5868 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5869 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
yihui 1:fc2f9d636751 5870
yihui 1:fc2f9d636751 5871 /* Bit 0 : Disable routing to PPI of TICK event. */
yihui 1:fc2f9d636751 5872 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
yihui 1:fc2f9d636751 5873 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
yihui 1:fc2f9d636751 5874 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
yihui 1:fc2f9d636751 5875 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
yihui 1:fc2f9d636751 5876 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
yihui 1:fc2f9d636751 5877
yihui 1:fc2f9d636751 5878 /* Register: RTC_COUNTER */
yihui 1:fc2f9d636751 5879 /* Description: Current COUNTER value. */
yihui 1:fc2f9d636751 5880
yihui 1:fc2f9d636751 5881 /* Bits 23..0 : Counter value. */
yihui 1:fc2f9d636751 5882 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
yihui 1:fc2f9d636751 5883 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
yihui 1:fc2f9d636751 5884
yihui 1:fc2f9d636751 5885 /* Register: RTC_PRESCALER */
yihui 1:fc2f9d636751 5886 /* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
yihui 1:fc2f9d636751 5887
yihui 1:fc2f9d636751 5888 /* Bits 11..0 : RTC PRESCALER value. */
yihui 1:fc2f9d636751 5889 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
yihui 1:fc2f9d636751 5890 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
yihui 1:fc2f9d636751 5891
yihui 1:fc2f9d636751 5892 /* Register: RTC_CC */
yihui 1:fc2f9d636751 5893 /* Description: Capture/compare registers. */
yihui 1:fc2f9d636751 5894
yihui 1:fc2f9d636751 5895 /* Bits 23..0 : Compare value. */
yihui 1:fc2f9d636751 5896 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
yihui 1:fc2f9d636751 5897 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
yihui 1:fc2f9d636751 5898
yihui 1:fc2f9d636751 5899 /* Register: RTC_POWER */
yihui 1:fc2f9d636751 5900 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 5901
yihui 1:fc2f9d636751 5902 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 5903 #define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 5904 #define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 5905 #define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 5906 #define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 5907
yihui 1:fc2f9d636751 5908
yihui 1:fc2f9d636751 5909 /* Peripheral: SPI */
yihui 1:fc2f9d636751 5910 /* Description: SPI master 0. */
yihui 1:fc2f9d636751 5911
yihui 1:fc2f9d636751 5912 /* Register: SPI_INTENSET */
yihui 1:fc2f9d636751 5913 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 5914
yihui 1:fc2f9d636751 5915 /* Bit 2 : Enable interrupt on READY event. */
yihui 1:fc2f9d636751 5916 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
yihui 1:fc2f9d636751 5917 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
yihui 1:fc2f9d636751 5918 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5919 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5920 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 5921
yihui 1:fc2f9d636751 5922 /* Register: SPI_INTENCLR */
yihui 1:fc2f9d636751 5923 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 5924
yihui 1:fc2f9d636751 5925 /* Bit 2 : Disable interrupt on READY event. */
yihui 1:fc2f9d636751 5926 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
yihui 1:fc2f9d636751 5927 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
yihui 1:fc2f9d636751 5928 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 5929 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 5930 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 5931
yihui 1:fc2f9d636751 5932 /* Register: SPI_ENABLE */
yihui 1:fc2f9d636751 5933 /* Description: Enable SPI. */
yihui 1:fc2f9d636751 5934
yihui 1:fc2f9d636751 5935 /* Bits 2..0 : Enable or disable SPI. */
yihui 1:fc2f9d636751 5936 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
yihui 1:fc2f9d636751 5937 #define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
yihui 1:fc2f9d636751 5938 #define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
yihui 1:fc2f9d636751 5939 #define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
yihui 1:fc2f9d636751 5940
yihui 1:fc2f9d636751 5941 /* Register: SPI_RXD */
yihui 1:fc2f9d636751 5942 /* Description: RX data. */
yihui 1:fc2f9d636751 5943
yihui 1:fc2f9d636751 5944 /* Bits 7..0 : RX data from last transfer. */
yihui 1:fc2f9d636751 5945 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
yihui 1:fc2f9d636751 5946 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
yihui 1:fc2f9d636751 5947
yihui 1:fc2f9d636751 5948 /* Register: SPI_TXD */
yihui 1:fc2f9d636751 5949 /* Description: TX data. */
yihui 1:fc2f9d636751 5950
yihui 1:fc2f9d636751 5951 /* Bits 7..0 : TX data for next transfer. */
yihui 1:fc2f9d636751 5952 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
yihui 1:fc2f9d636751 5953 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
yihui 1:fc2f9d636751 5954
yihui 1:fc2f9d636751 5955 /* Register: SPI_FREQUENCY */
yihui 1:fc2f9d636751 5956 /* Description: SPI frequency */
yihui 1:fc2f9d636751 5957
yihui 1:fc2f9d636751 5958 /* Bits 31..0 : SPI data rate. */
yihui 1:fc2f9d636751 5959 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
yihui 1:fc2f9d636751 5960 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
yihui 1:fc2f9d636751 5961 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
yihui 1:fc2f9d636751 5962 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
yihui 1:fc2f9d636751 5963 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
yihui 1:fc2f9d636751 5964 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
yihui 1:fc2f9d636751 5965 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
yihui 1:fc2f9d636751 5966 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
yihui 1:fc2f9d636751 5967 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
yihui 1:fc2f9d636751 5968
yihui 1:fc2f9d636751 5969 /* Register: SPI_CONFIG */
yihui 1:fc2f9d636751 5970 /* Description: Configuration register. */
yihui 1:fc2f9d636751 5971
yihui 1:fc2f9d636751 5972 /* Bit 2 : Serial clock (SCK) polarity. */
yihui 1:fc2f9d636751 5973 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
yihui 1:fc2f9d636751 5974 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
yihui 1:fc2f9d636751 5975 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
yihui 1:fc2f9d636751 5976 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
yihui 1:fc2f9d636751 5977
yihui 1:fc2f9d636751 5978 /* Bit 1 : Serial clock (SCK) phase. */
yihui 1:fc2f9d636751 5979 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
yihui 1:fc2f9d636751 5980 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
yihui 1:fc2f9d636751 5981 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
yihui 1:fc2f9d636751 5982 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
yihui 1:fc2f9d636751 5983
yihui 1:fc2f9d636751 5984 /* Bit 0 : Bit order. */
yihui 1:fc2f9d636751 5985 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
yihui 1:fc2f9d636751 5986 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
yihui 1:fc2f9d636751 5987 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
yihui 1:fc2f9d636751 5988 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
yihui 1:fc2f9d636751 5989
yihui 1:fc2f9d636751 5990 /* Register: SPI_POWER */
yihui 1:fc2f9d636751 5991 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 5992
yihui 1:fc2f9d636751 5993 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 5994 #define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 5995 #define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 5996 #define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 5997 #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 5998
yihui 1:fc2f9d636751 5999
yihui 1:fc2f9d636751 6000 /* Peripheral: SPIM */
yihui 1:fc2f9d636751 6001 /* Description: SPI master with easyDMA 1. */
yihui 1:fc2f9d636751 6002
yihui 1:fc2f9d636751 6003 /* Register: SPIM_SHORTS */
yihui 1:fc2f9d636751 6004 /* Description: Shortcuts for SPIM. */
yihui 1:fc2f9d636751 6005
yihui 1:fc2f9d636751 6006 /* Bit 17 : Shortcut between END event and START task. */
yihui 1:fc2f9d636751 6007 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
yihui 1:fc2f9d636751 6008 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
yihui 1:fc2f9d636751 6009 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 6010 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 6011
yihui 1:fc2f9d636751 6012 /* Register: SPIM_INTENSET */
yihui 1:fc2f9d636751 6013 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 6014
yihui 1:fc2f9d636751 6015 /* Bit 19 : Enable interrupt on STARTED event. */
yihui 1:fc2f9d636751 6016 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
yihui 1:fc2f9d636751 6017 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
yihui 1:fc2f9d636751 6018 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6019 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6020 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6021
yihui 1:fc2f9d636751 6022 /* Bit 8 : Enable interrupt on ENDTX event. */
yihui 1:fc2f9d636751 6023 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
yihui 1:fc2f9d636751 6024 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
yihui 1:fc2f9d636751 6025 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6026 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6027 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6028
yihui 1:fc2f9d636751 6029 /* Bit 6 : Enable interrupt on END event. */
yihui 1:fc2f9d636751 6030 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
yihui 1:fc2f9d636751 6031 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
yihui 1:fc2f9d636751 6032 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6033 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6034 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6035
yihui 1:fc2f9d636751 6036 /* Bit 4 : Enable interrupt on ENDRX event. */
yihui 1:fc2f9d636751 6037 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
yihui 1:fc2f9d636751 6038 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
yihui 1:fc2f9d636751 6039 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6040 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6041 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6042
yihui 1:fc2f9d636751 6043 /* Bit 1 : Enable interrupt on STOPPED event. */
yihui 1:fc2f9d636751 6044 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
yihui 1:fc2f9d636751 6045 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
yihui 1:fc2f9d636751 6046 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6047 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6048 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6049
yihui 1:fc2f9d636751 6050 /* Register: SPIM_INTENCLR */
yihui 1:fc2f9d636751 6051 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 6052
yihui 1:fc2f9d636751 6053 /* Bit 19 : Disable interrupt on STARTED event. */
yihui 1:fc2f9d636751 6054 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
yihui 1:fc2f9d636751 6055 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
yihui 1:fc2f9d636751 6056 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6057 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6058 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6059
yihui 1:fc2f9d636751 6060 /* Bit 8 : Disable interrupt on ENDTX event. */
yihui 1:fc2f9d636751 6061 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
yihui 1:fc2f9d636751 6062 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
yihui 1:fc2f9d636751 6063 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6064 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6065 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6066
yihui 1:fc2f9d636751 6067 /* Bit 6 : Disable interrupt on END event. */
yihui 1:fc2f9d636751 6068 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
yihui 1:fc2f9d636751 6069 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
yihui 1:fc2f9d636751 6070 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6071 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6072 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6073
yihui 1:fc2f9d636751 6074 /* Bit 4 : Disable interrupt on ENDRX event. */
yihui 1:fc2f9d636751 6075 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
yihui 1:fc2f9d636751 6076 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
yihui 1:fc2f9d636751 6077 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6078 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6079 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6080
yihui 1:fc2f9d636751 6081 /* Bit 1 : Disable interrupt on STOPPED event. */
yihui 1:fc2f9d636751 6082 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
yihui 1:fc2f9d636751 6083 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
yihui 1:fc2f9d636751 6084 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6085 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6086 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6087
yihui 1:fc2f9d636751 6088 /* Register: SPIM_ENABLE */
yihui 1:fc2f9d636751 6089 /* Description: Enable SPIM. */
yihui 1:fc2f9d636751 6090
yihui 1:fc2f9d636751 6091 /* Bits 3..0 : Enable or disable SPIM. */
yihui 1:fc2f9d636751 6092 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
yihui 1:fc2f9d636751 6093 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
yihui 1:fc2f9d636751 6094 #define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */
yihui 1:fc2f9d636751 6095 #define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */
yihui 1:fc2f9d636751 6096
yihui 1:fc2f9d636751 6097 /* Register: SPIM_RXDDATA */
yihui 1:fc2f9d636751 6098 /* Description: RXD register. */
yihui 1:fc2f9d636751 6099
yihui 1:fc2f9d636751 6100 /* Bits 7..0 : RX data received. Double buffered. */
yihui 1:fc2f9d636751 6101 #define SPIM_RXDDATA_RXD_Pos (0UL) /*!< Position of RXD field. */
yihui 1:fc2f9d636751 6102 #define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /*!< Bit mask of RXD field. */
yihui 1:fc2f9d636751 6103
yihui 1:fc2f9d636751 6104 /* Register: SPIM_TXDDATA */
yihui 1:fc2f9d636751 6105 /* Description: TXD register. */
yihui 1:fc2f9d636751 6106
yihui 1:fc2f9d636751 6107 /* Bits 7..0 : TX data to send. Double buffered. */
yihui 1:fc2f9d636751 6108 #define SPIM_TXDDATA_TXD_Pos (0UL) /*!< Position of TXD field. */
yihui 1:fc2f9d636751 6109 #define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /*!< Bit mask of TXD field. */
yihui 1:fc2f9d636751 6110
yihui 1:fc2f9d636751 6111 /* Register: SPIM_FREQUENCY */
yihui 1:fc2f9d636751 6112 /* Description: SPI frequency. */
yihui 1:fc2f9d636751 6113
yihui 1:fc2f9d636751 6114 /* Bits 31..0 : SPI master data rate. */
yihui 1:fc2f9d636751 6115 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
yihui 1:fc2f9d636751 6116 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
yihui 1:fc2f9d636751 6117 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */
yihui 1:fc2f9d636751 6118 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
yihui 1:fc2f9d636751 6119 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */
yihui 1:fc2f9d636751 6120 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */
yihui 1:fc2f9d636751 6121 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */
yihui 1:fc2f9d636751 6122 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */
yihui 1:fc2f9d636751 6123 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */
yihui 1:fc2f9d636751 6124
yihui 1:fc2f9d636751 6125 /* Register: SPIM_CONFIG */
yihui 1:fc2f9d636751 6126 /* Description: Configuration register. */
yihui 1:fc2f9d636751 6127
yihui 1:fc2f9d636751 6128 /* Bit 2 : Serial clock (SCK) polarity. */
yihui 1:fc2f9d636751 6129 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
yihui 1:fc2f9d636751 6130 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
yihui 1:fc2f9d636751 6131 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
yihui 1:fc2f9d636751 6132 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
yihui 1:fc2f9d636751 6133
yihui 1:fc2f9d636751 6134 /* Bit 1 : Serial clock (SCK) phase. */
yihui 1:fc2f9d636751 6135 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
yihui 1:fc2f9d636751 6136 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
yihui 1:fc2f9d636751 6137 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
yihui 1:fc2f9d636751 6138 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
yihui 1:fc2f9d636751 6139
yihui 1:fc2f9d636751 6140 /* Bit 0 : Bit order. */
yihui 1:fc2f9d636751 6141 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
yihui 1:fc2f9d636751 6142 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
yihui 1:fc2f9d636751 6143 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
yihui 1:fc2f9d636751 6144 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
yihui 1:fc2f9d636751 6145
yihui 1:fc2f9d636751 6146 /* Register: SPIM_ORC */
yihui 1:fc2f9d636751 6147 /* Description: Over-read character. */
yihui 1:fc2f9d636751 6148
yihui 1:fc2f9d636751 6149 /* Bits 7..0 : Over-read character. */
yihui 1:fc2f9d636751 6150 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
yihui 1:fc2f9d636751 6151 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
yihui 1:fc2f9d636751 6152
yihui 1:fc2f9d636751 6153 /* Register: SPIM_POWER */
yihui 1:fc2f9d636751 6154 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 6155
yihui 1:fc2f9d636751 6156 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 6157 #define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 6158 #define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 6159 #define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 6160 #define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 6161
yihui 1:fc2f9d636751 6162 /* Register: SPIM_RXD_PTR */
yihui 1:fc2f9d636751 6163 /* Description: Data pointer. */
yihui 1:fc2f9d636751 6164
yihui 1:fc2f9d636751 6165 /* Bits 31..0 : Data pointer. */
yihui 1:fc2f9d636751 6166 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
yihui 1:fc2f9d636751 6167 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
yihui 1:fc2f9d636751 6168
yihui 1:fc2f9d636751 6169 /* Register: SPIM_RXD_MAXCNT */
yihui 1:fc2f9d636751 6170 /* Description: Maximum number of buffer bytes to receive. */
yihui 1:fc2f9d636751 6171
yihui 1:fc2f9d636751 6172 /* Bits 7..0 : Maximum number of buffer bytes to receive. */
yihui 1:fc2f9d636751 6173 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
yihui 1:fc2f9d636751 6174 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
yihui 1:fc2f9d636751 6175
yihui 1:fc2f9d636751 6176 /* Register: SPIM_RXD_AMOUNT */
yihui 1:fc2f9d636751 6177 /* Description: Number of bytes received in the last transaction. */
yihui 1:fc2f9d636751 6178
yihui 1:fc2f9d636751 6179 /* Bits 7..0 : Number of bytes received in the last transaction. */
yihui 1:fc2f9d636751 6180 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
yihui 1:fc2f9d636751 6181 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
yihui 1:fc2f9d636751 6182
yihui 1:fc2f9d636751 6183 /* Register: SPIM_TXD_PTR */
yihui 1:fc2f9d636751 6184 /* Description: Data pointer. */
yihui 1:fc2f9d636751 6185
yihui 1:fc2f9d636751 6186 /* Bits 31..0 : Data pointer. */
yihui 1:fc2f9d636751 6187 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
yihui 1:fc2f9d636751 6188 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
yihui 1:fc2f9d636751 6189
yihui 1:fc2f9d636751 6190 /* Register: SPIM_TXD_MAXCNT */
yihui 1:fc2f9d636751 6191 /* Description: Maximum number of buffer bytes to send. */
yihui 1:fc2f9d636751 6192
yihui 1:fc2f9d636751 6193 /* Bits 7..0 : Maximum number of buffer bytes to send. */
yihui 1:fc2f9d636751 6194 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
yihui 1:fc2f9d636751 6195 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
yihui 1:fc2f9d636751 6196
yihui 1:fc2f9d636751 6197 /* Register: SPIM_TXD_AMOUNT */
yihui 1:fc2f9d636751 6198 /* Description: Number of bytes sent in the last transaction. */
yihui 1:fc2f9d636751 6199
yihui 1:fc2f9d636751 6200 /* Bits 7..0 : Number of bytes sent in the last transaction. */
yihui 1:fc2f9d636751 6201 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
yihui 1:fc2f9d636751 6202 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
yihui 1:fc2f9d636751 6203
yihui 1:fc2f9d636751 6204
yihui 1:fc2f9d636751 6205 /* Peripheral: SPIS */
yihui 1:fc2f9d636751 6206 /* Description: SPI slave 1. */
yihui 1:fc2f9d636751 6207
yihui 1:fc2f9d636751 6208 /* Register: SPIS_SHORTS */
yihui 1:fc2f9d636751 6209 /* Description: Shortcuts for SPIS. */
yihui 1:fc2f9d636751 6210
yihui 1:fc2f9d636751 6211 /* Bit 2 : Shortcut between END event and the ACQUIRE task. */
yihui 1:fc2f9d636751 6212 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
yihui 1:fc2f9d636751 6213 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
yihui 1:fc2f9d636751 6214 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 6215 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 6216
yihui 1:fc2f9d636751 6217 /* Register: SPIS_INTENSET */
yihui 1:fc2f9d636751 6218 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 6219
yihui 1:fc2f9d636751 6220 /* Bit 10 : Enable interrupt on ACQUIRED event. */
yihui 1:fc2f9d636751 6221 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
yihui 1:fc2f9d636751 6222 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
yihui 1:fc2f9d636751 6223 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6224 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6225 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6226
yihui 1:fc2f9d636751 6227 /* Bit 1 : Enable interrupt on END event. */
yihui 1:fc2f9d636751 6228 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
yihui 1:fc2f9d636751 6229 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
yihui 1:fc2f9d636751 6230 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6231 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6232 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6233
yihui 1:fc2f9d636751 6234 /* Register: SPIS_INTENCLR */
yihui 1:fc2f9d636751 6235 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 6236
yihui 1:fc2f9d636751 6237 /* Bit 10 : Disable interrupt on ACQUIRED event. */
yihui 1:fc2f9d636751 6238 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
yihui 1:fc2f9d636751 6239 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
yihui 1:fc2f9d636751 6240 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6241 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6242 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6243
yihui 1:fc2f9d636751 6244 /* Bit 1 : Disable interrupt on END event. */
yihui 1:fc2f9d636751 6245 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
yihui 1:fc2f9d636751 6246 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
yihui 1:fc2f9d636751 6247 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6248 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6249 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6250
yihui 1:fc2f9d636751 6251 /* Register: SPIS_SEMSTAT */
yihui 1:fc2f9d636751 6252 /* Description: Semaphore status. */
yihui 1:fc2f9d636751 6253
yihui 1:fc2f9d636751 6254 /* Bits 1..0 : Semaphore status. */
yihui 1:fc2f9d636751 6255 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
yihui 1:fc2f9d636751 6256 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
yihui 1:fc2f9d636751 6257 #define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
yihui 1:fc2f9d636751 6258 #define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
yihui 1:fc2f9d636751 6259 #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
yihui 1:fc2f9d636751 6260 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
yihui 1:fc2f9d636751 6261
yihui 1:fc2f9d636751 6262 /* Register: SPIS_STATUS */
yihui 1:fc2f9d636751 6263 /* Description: Status from last transaction. */
yihui 1:fc2f9d636751 6264
yihui 1:fc2f9d636751 6265 /* Bit 1 : RX buffer overflow detected, and prevented. */
yihui 1:fc2f9d636751 6266 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
yihui 1:fc2f9d636751 6267 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
yihui 1:fc2f9d636751 6268 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
yihui 1:fc2f9d636751 6269 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
yihui 1:fc2f9d636751 6270 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
yihui 1:fc2f9d636751 6271
yihui 1:fc2f9d636751 6272 /* Bit 0 : TX buffer overread detected, and prevented. */
yihui 1:fc2f9d636751 6273 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
yihui 1:fc2f9d636751 6274 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
yihui 1:fc2f9d636751 6275 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
yihui 1:fc2f9d636751 6276 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
yihui 1:fc2f9d636751 6277 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
yihui 1:fc2f9d636751 6278
yihui 1:fc2f9d636751 6279 /* Register: SPIS_ENABLE */
yihui 1:fc2f9d636751 6280 /* Description: Enable SPIS. */
yihui 1:fc2f9d636751 6281
yihui 1:fc2f9d636751 6282 /* Bits 2..0 : Enable or disable SPIS. */
yihui 1:fc2f9d636751 6283 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
yihui 1:fc2f9d636751 6284 #define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
yihui 1:fc2f9d636751 6285 #define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
yihui 1:fc2f9d636751 6286 #define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
yihui 1:fc2f9d636751 6287
yihui 1:fc2f9d636751 6288 /* Register: SPIS_MAXRX */
yihui 1:fc2f9d636751 6289 /* Description: Maximum number of bytes in the receive buffer. */
yihui 1:fc2f9d636751 6290
yihui 1:fc2f9d636751 6291 /* Bits 7..0 : Maximum number of bytes in the receive buffer. */
yihui 1:fc2f9d636751 6292 #define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
yihui 1:fc2f9d636751 6293 #define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
yihui 1:fc2f9d636751 6294
yihui 1:fc2f9d636751 6295 /* Register: SPIS_AMOUNTRX */
yihui 1:fc2f9d636751 6296 /* Description: Number of bytes received in last granted transaction. */
yihui 1:fc2f9d636751 6297
yihui 1:fc2f9d636751 6298 /* Bits 7..0 : Number of bytes received in last granted transaction. */
yihui 1:fc2f9d636751 6299 #define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
yihui 1:fc2f9d636751 6300 #define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
yihui 1:fc2f9d636751 6301
yihui 1:fc2f9d636751 6302 /* Register: SPIS_MAXTX */
yihui 1:fc2f9d636751 6303 /* Description: Maximum number of bytes in the transmit buffer. */
yihui 1:fc2f9d636751 6304
yihui 1:fc2f9d636751 6305 /* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
yihui 1:fc2f9d636751 6306 #define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
yihui 1:fc2f9d636751 6307 #define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
yihui 1:fc2f9d636751 6308
yihui 1:fc2f9d636751 6309 /* Register: SPIS_AMOUNTTX */
yihui 1:fc2f9d636751 6310 /* Description: Number of bytes transmitted in last granted transaction. */
yihui 1:fc2f9d636751 6311
yihui 1:fc2f9d636751 6312 /* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
yihui 1:fc2f9d636751 6313 #define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
yihui 1:fc2f9d636751 6314 #define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
yihui 1:fc2f9d636751 6315
yihui 1:fc2f9d636751 6316 /* Register: SPIS_CONFIG */
yihui 1:fc2f9d636751 6317 /* Description: Configuration register. */
yihui 1:fc2f9d636751 6318
yihui 1:fc2f9d636751 6319 /* Bit 2 : Serial clock (SCK) polarity. */
yihui 1:fc2f9d636751 6320 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
yihui 1:fc2f9d636751 6321 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
yihui 1:fc2f9d636751 6322 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
yihui 1:fc2f9d636751 6323 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
yihui 1:fc2f9d636751 6324
yihui 1:fc2f9d636751 6325 /* Bit 1 : Serial clock (SCK) phase. */
yihui 1:fc2f9d636751 6326 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
yihui 1:fc2f9d636751 6327 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
yihui 1:fc2f9d636751 6328 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
yihui 1:fc2f9d636751 6329 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
yihui 1:fc2f9d636751 6330
yihui 1:fc2f9d636751 6331 /* Bit 0 : Bit order. */
yihui 1:fc2f9d636751 6332 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
yihui 1:fc2f9d636751 6333 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
yihui 1:fc2f9d636751 6334 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
yihui 1:fc2f9d636751 6335 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
yihui 1:fc2f9d636751 6336
yihui 1:fc2f9d636751 6337 /* Register: SPIS_DEF */
yihui 1:fc2f9d636751 6338 /* Description: Default character. */
yihui 1:fc2f9d636751 6339
yihui 1:fc2f9d636751 6340 /* Bits 7..0 : Default character. */
yihui 1:fc2f9d636751 6341 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
yihui 1:fc2f9d636751 6342 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
yihui 1:fc2f9d636751 6343
yihui 1:fc2f9d636751 6344 /* Register: SPIS_ORC */
yihui 1:fc2f9d636751 6345 /* Description: Over-read character. */
yihui 1:fc2f9d636751 6346
yihui 1:fc2f9d636751 6347 /* Bits 7..0 : Over-read character. */
yihui 1:fc2f9d636751 6348 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
yihui 1:fc2f9d636751 6349 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
yihui 1:fc2f9d636751 6350
yihui 1:fc2f9d636751 6351 /* Register: SPIS_POWER */
yihui 1:fc2f9d636751 6352 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 6353
yihui 1:fc2f9d636751 6354 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 6355 #define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 6356 #define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 6357 #define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 6358 #define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 6359
yihui 1:fc2f9d636751 6360
yihui 1:fc2f9d636751 6361 /* Peripheral: TEMP */
yihui 1:fc2f9d636751 6362 /* Description: Temperature Sensor. */
yihui 1:fc2f9d636751 6363
yihui 1:fc2f9d636751 6364 /* Register: TEMP_INTENSET */
yihui 1:fc2f9d636751 6365 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 6366
yihui 1:fc2f9d636751 6367 /* Bit 0 : Enable interrupt on DATARDY event. */
yihui 1:fc2f9d636751 6368 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
yihui 1:fc2f9d636751 6369 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
yihui 1:fc2f9d636751 6370 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6371 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6372 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6373
yihui 1:fc2f9d636751 6374 /* Register: TEMP_INTENCLR */
yihui 1:fc2f9d636751 6375 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 6376
yihui 1:fc2f9d636751 6377 /* Bit 0 : Disable interrupt on DATARDY event. */
yihui 1:fc2f9d636751 6378 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
yihui 1:fc2f9d636751 6379 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
yihui 1:fc2f9d636751 6380 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6381 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6382 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6383
yihui 1:fc2f9d636751 6384 /* Register: TEMP_POWER */
yihui 1:fc2f9d636751 6385 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 6386
yihui 1:fc2f9d636751 6387 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 6388 #define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 6389 #define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 6390 #define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 6391 #define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 6392
yihui 1:fc2f9d636751 6393
yihui 1:fc2f9d636751 6394 /* Peripheral: TIMER */
yihui 1:fc2f9d636751 6395 /* Description: Timer 0. */
yihui 1:fc2f9d636751 6396
yihui 1:fc2f9d636751 6397 /* Register: TIMER_SHORTS */
yihui 1:fc2f9d636751 6398 /* Description: Shortcuts for Timer. */
yihui 1:fc2f9d636751 6399
yihui 1:fc2f9d636751 6400 /* Bit 11 : Shortcut between CC[3] event and the STOP task. */
yihui 1:fc2f9d636751 6401 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
yihui 1:fc2f9d636751 6402 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
yihui 1:fc2f9d636751 6403 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 6404 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 6405
yihui 1:fc2f9d636751 6406 /* Bit 10 : Shortcut between CC[2] event and the STOP task. */
yihui 1:fc2f9d636751 6407 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
yihui 1:fc2f9d636751 6408 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
yihui 1:fc2f9d636751 6409 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 6410 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 6411
yihui 1:fc2f9d636751 6412 /* Bit 9 : Shortcut between CC[1] event and the STOP task. */
yihui 1:fc2f9d636751 6413 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
yihui 1:fc2f9d636751 6414 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
yihui 1:fc2f9d636751 6415 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 6416 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 6417
yihui 1:fc2f9d636751 6418 /* Bit 8 : Shortcut between CC[0] event and the STOP task. */
yihui 1:fc2f9d636751 6419 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
yihui 1:fc2f9d636751 6420 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
yihui 1:fc2f9d636751 6421 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 6422 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 6423
yihui 1:fc2f9d636751 6424 /* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
yihui 1:fc2f9d636751 6425 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
yihui 1:fc2f9d636751 6426 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
yihui 1:fc2f9d636751 6427 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 6428 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 6429
yihui 1:fc2f9d636751 6430 /* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
yihui 1:fc2f9d636751 6431 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
yihui 1:fc2f9d636751 6432 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
yihui 1:fc2f9d636751 6433 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 6434 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 6435
yihui 1:fc2f9d636751 6436 /* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
yihui 1:fc2f9d636751 6437 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
yihui 1:fc2f9d636751 6438 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
yihui 1:fc2f9d636751 6439 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 6440 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 6441
yihui 1:fc2f9d636751 6442 /* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
yihui 1:fc2f9d636751 6443 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
yihui 1:fc2f9d636751 6444 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
yihui 1:fc2f9d636751 6445 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 6446 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 6447
yihui 1:fc2f9d636751 6448 /* Register: TIMER_INTENSET */
yihui 1:fc2f9d636751 6449 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 6450
yihui 1:fc2f9d636751 6451 /* Bit 19 : Enable interrupt on COMPARE[3] */
yihui 1:fc2f9d636751 6452 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
yihui 1:fc2f9d636751 6453 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
yihui 1:fc2f9d636751 6454 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6455 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6456 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6457
yihui 1:fc2f9d636751 6458 /* Bit 18 : Enable interrupt on COMPARE[2] */
yihui 1:fc2f9d636751 6459 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
yihui 1:fc2f9d636751 6460 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
yihui 1:fc2f9d636751 6461 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6462 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6463 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6464
yihui 1:fc2f9d636751 6465 /* Bit 17 : Enable interrupt on COMPARE[1] */
yihui 1:fc2f9d636751 6466 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
yihui 1:fc2f9d636751 6467 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
yihui 1:fc2f9d636751 6468 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6469 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6470 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6471
yihui 1:fc2f9d636751 6472 /* Bit 16 : Enable interrupt on COMPARE[0] */
yihui 1:fc2f9d636751 6473 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
yihui 1:fc2f9d636751 6474 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
yihui 1:fc2f9d636751 6475 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6476 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6477 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6478
yihui 1:fc2f9d636751 6479 /* Register: TIMER_INTENCLR */
yihui 1:fc2f9d636751 6480 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 6481
yihui 1:fc2f9d636751 6482 /* Bit 19 : Disable interrupt on COMPARE[3] */
yihui 1:fc2f9d636751 6483 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
yihui 1:fc2f9d636751 6484 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
yihui 1:fc2f9d636751 6485 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6486 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6487 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6488
yihui 1:fc2f9d636751 6489 /* Bit 18 : Disable interrupt on COMPARE[2] */
yihui 1:fc2f9d636751 6490 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
yihui 1:fc2f9d636751 6491 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
yihui 1:fc2f9d636751 6492 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6493 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6494 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6495
yihui 1:fc2f9d636751 6496 /* Bit 17 : Disable interrupt on COMPARE[1] */
yihui 1:fc2f9d636751 6497 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
yihui 1:fc2f9d636751 6498 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
yihui 1:fc2f9d636751 6499 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6500 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6501 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6502
yihui 1:fc2f9d636751 6503 /* Bit 16 : Disable interrupt on COMPARE[0] */
yihui 1:fc2f9d636751 6504 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
yihui 1:fc2f9d636751 6505 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
yihui 1:fc2f9d636751 6506 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6507 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6508 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6509
yihui 1:fc2f9d636751 6510 /* Register: TIMER_MODE */
yihui 1:fc2f9d636751 6511 /* Description: Timer Mode selection. */
yihui 1:fc2f9d636751 6512
yihui 1:fc2f9d636751 6513 /* Bit 0 : Select Normal or Counter mode. */
yihui 1:fc2f9d636751 6514 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
yihui 1:fc2f9d636751 6515 #define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
yihui 1:fc2f9d636751 6516 #define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
yihui 1:fc2f9d636751 6517 #define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
yihui 1:fc2f9d636751 6518
yihui 1:fc2f9d636751 6519 /* Register: TIMER_BITMODE */
yihui 1:fc2f9d636751 6520 /* Description: Sets timer behaviour. */
yihui 1:fc2f9d636751 6521
yihui 1:fc2f9d636751 6522 /* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
yihui 1:fc2f9d636751 6523 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
yihui 1:fc2f9d636751 6524 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
yihui 1:fc2f9d636751 6525 #define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
yihui 1:fc2f9d636751 6526 #define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
yihui 1:fc2f9d636751 6527 #define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
yihui 1:fc2f9d636751 6528 #define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
yihui 1:fc2f9d636751 6529
yihui 1:fc2f9d636751 6530 /* Register: TIMER_PRESCALER */
yihui 1:fc2f9d636751 6531 /* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
yihui 1:fc2f9d636751 6532
yihui 1:fc2f9d636751 6533 /* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
yihui 1:fc2f9d636751 6534 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
yihui 1:fc2f9d636751 6535 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
yihui 1:fc2f9d636751 6536
yihui 1:fc2f9d636751 6537 /* Register: TIMER_POWER */
yihui 1:fc2f9d636751 6538 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 6539
yihui 1:fc2f9d636751 6540 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 6541 #define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 6542 #define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 6543 #define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 6544 #define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 6545
yihui 1:fc2f9d636751 6546
yihui 1:fc2f9d636751 6547 /* Peripheral: TWI */
yihui 1:fc2f9d636751 6548 /* Description: Two-wire interface master 0. */
yihui 1:fc2f9d636751 6549
yihui 1:fc2f9d636751 6550 /* Register: TWI_SHORTS */
yihui 1:fc2f9d636751 6551 /* Description: Shortcuts for TWI. */
yihui 1:fc2f9d636751 6552
yihui 1:fc2f9d636751 6553 /* Bit 1 : Shortcut between BB event and the STOP task. */
yihui 1:fc2f9d636751 6554 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
yihui 1:fc2f9d636751 6555 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
yihui 1:fc2f9d636751 6556 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 6557 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 6558
yihui 1:fc2f9d636751 6559 /* Bit 0 : Shortcut between BB event and the SUSPEND task. */
yihui 1:fc2f9d636751 6560 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
yihui 1:fc2f9d636751 6561 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
yihui 1:fc2f9d636751 6562 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 6563 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 6564
yihui 1:fc2f9d636751 6565 /* Register: TWI_INTENSET */
yihui 1:fc2f9d636751 6566 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 6567
yihui 1:fc2f9d636751 6568 /* Bit 18 : Enable interrupt on SUSPENDED event. */
yihui 1:fc2f9d636751 6569 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
yihui 1:fc2f9d636751 6570 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
yihui 1:fc2f9d636751 6571 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6572 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6573 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6574
yihui 1:fc2f9d636751 6575 /* Bit 14 : Enable interrupt on BB event. */
yihui 1:fc2f9d636751 6576 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
yihui 1:fc2f9d636751 6577 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
yihui 1:fc2f9d636751 6578 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6579 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6580 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6581
yihui 1:fc2f9d636751 6582 /* Bit 9 : Enable interrupt on ERROR event. */
yihui 1:fc2f9d636751 6583 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
yihui 1:fc2f9d636751 6584 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
yihui 1:fc2f9d636751 6585 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6586 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6587 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6588
yihui 1:fc2f9d636751 6589 /* Bit 7 : Enable interrupt on TXDSENT event. */
yihui 1:fc2f9d636751 6590 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
yihui 1:fc2f9d636751 6591 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
yihui 1:fc2f9d636751 6592 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6593 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6594 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6595
yihui 1:fc2f9d636751 6596 /* Bit 2 : Enable interrupt on READY event. */
yihui 1:fc2f9d636751 6597 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
yihui 1:fc2f9d636751 6598 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
yihui 1:fc2f9d636751 6599 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6600 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6601 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6602
yihui 1:fc2f9d636751 6603 /* Bit 1 : Enable interrupt on STOPPED event. */
yihui 1:fc2f9d636751 6604 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
yihui 1:fc2f9d636751 6605 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
yihui 1:fc2f9d636751 6606 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6607 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6608 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6609
yihui 1:fc2f9d636751 6610 /* Register: TWI_INTENCLR */
yihui 1:fc2f9d636751 6611 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 6612
yihui 1:fc2f9d636751 6613 /* Bit 18 : Disable interrupt on SUSPENDED event. */
yihui 1:fc2f9d636751 6614 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
yihui 1:fc2f9d636751 6615 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
yihui 1:fc2f9d636751 6616 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6617 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6618 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6619
yihui 1:fc2f9d636751 6620 /* Bit 14 : Disable interrupt on BB event. */
yihui 1:fc2f9d636751 6621 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
yihui 1:fc2f9d636751 6622 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
yihui 1:fc2f9d636751 6623 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6624 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6625 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6626
yihui 1:fc2f9d636751 6627 /* Bit 9 : Disable interrupt on ERROR event. */
yihui 1:fc2f9d636751 6628 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
yihui 1:fc2f9d636751 6629 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
yihui 1:fc2f9d636751 6630 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6631 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6632 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6633
yihui 1:fc2f9d636751 6634 /* Bit 7 : Disable interrupt on TXDSENT event. */
yihui 1:fc2f9d636751 6635 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
yihui 1:fc2f9d636751 6636 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
yihui 1:fc2f9d636751 6637 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6638 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6639 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6640
yihui 1:fc2f9d636751 6641 /* Bit 2 : Disable interrupt on RXDREADY event. */
yihui 1:fc2f9d636751 6642 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
yihui 1:fc2f9d636751 6643 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
yihui 1:fc2f9d636751 6644 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6645 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6646 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6647
yihui 1:fc2f9d636751 6648 /* Bit 1 : Disable interrupt on STOPPED event. */
yihui 1:fc2f9d636751 6649 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
yihui 1:fc2f9d636751 6650 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
yihui 1:fc2f9d636751 6651 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6652 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6653 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6654
yihui 1:fc2f9d636751 6655 /* Register: TWI_ERRORSRC */
yihui 1:fc2f9d636751 6656 /* Description: Two-wire error source. Write error field to 1 to clear error. */
yihui 1:fc2f9d636751 6657
yihui 1:fc2f9d636751 6658 /* Bit 2 : NACK received after sending a data byte. */
yihui 1:fc2f9d636751 6659 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
yihui 1:fc2f9d636751 6660 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
yihui 1:fc2f9d636751 6661 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
yihui 1:fc2f9d636751 6662 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
yihui 1:fc2f9d636751 6663 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
yihui 1:fc2f9d636751 6664
yihui 1:fc2f9d636751 6665 /* Bit 1 : NACK received after sending the address. */
yihui 1:fc2f9d636751 6666 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
yihui 1:fc2f9d636751 6667 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
yihui 1:fc2f9d636751 6668 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
yihui 1:fc2f9d636751 6669 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
yihui 1:fc2f9d636751 6670 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
yihui 1:fc2f9d636751 6671
yihui 1:fc2f9d636751 6672 /* Register: TWI_ENABLE */
yihui 1:fc2f9d636751 6673 /* Description: Enable two-wire master. */
yihui 1:fc2f9d636751 6674
yihui 1:fc2f9d636751 6675 /* Bits 2..0 : Enable or disable W2M */
yihui 1:fc2f9d636751 6676 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
yihui 1:fc2f9d636751 6677 #define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
yihui 1:fc2f9d636751 6678 #define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
yihui 1:fc2f9d636751 6679 #define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
yihui 1:fc2f9d636751 6680
yihui 1:fc2f9d636751 6681 /* Register: TWI_RXD */
yihui 1:fc2f9d636751 6682 /* Description: RX data register. */
yihui 1:fc2f9d636751 6683
yihui 1:fc2f9d636751 6684 /* Bits 7..0 : RX data from last transfer. */
yihui 1:fc2f9d636751 6685 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
yihui 1:fc2f9d636751 6686 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
yihui 1:fc2f9d636751 6687
yihui 1:fc2f9d636751 6688 /* Register: TWI_TXD */
yihui 1:fc2f9d636751 6689 /* Description: TX data register. */
yihui 1:fc2f9d636751 6690
yihui 1:fc2f9d636751 6691 /* Bits 7..0 : TX data for next transfer. */
yihui 1:fc2f9d636751 6692 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
yihui 1:fc2f9d636751 6693 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
yihui 1:fc2f9d636751 6694
yihui 1:fc2f9d636751 6695 /* Register: TWI_FREQUENCY */
yihui 1:fc2f9d636751 6696 /* Description: Two-wire frequency. */
yihui 1:fc2f9d636751 6697
yihui 1:fc2f9d636751 6698 /* Bits 31..0 : Two-wire master clock frequency. */
yihui 1:fc2f9d636751 6699 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
yihui 1:fc2f9d636751 6700 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
yihui 1:fc2f9d636751 6701 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
yihui 1:fc2f9d636751 6702 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
yihui 1:fc2f9d636751 6703 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */
yihui 1:fc2f9d636751 6704
yihui 1:fc2f9d636751 6705 /* Register: TWI_ADDRESS */
yihui 1:fc2f9d636751 6706 /* Description: Address used in the two-wire transfer. */
yihui 1:fc2f9d636751 6707
yihui 1:fc2f9d636751 6708 /* Bits 6..0 : Two-wire address. */
yihui 1:fc2f9d636751 6709 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
yihui 1:fc2f9d636751 6710 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
yihui 1:fc2f9d636751 6711
yihui 1:fc2f9d636751 6712 /* Register: TWI_POWER */
yihui 1:fc2f9d636751 6713 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 6714
yihui 1:fc2f9d636751 6715 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 6716 #define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 6717 #define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 6718 #define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 6719 #define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 6720
yihui 1:fc2f9d636751 6721
yihui 1:fc2f9d636751 6722 /* Peripheral: UART */
yihui 1:fc2f9d636751 6723 /* Description: Universal Asynchronous Receiver/Transmitter. */
yihui 1:fc2f9d636751 6724
yihui 1:fc2f9d636751 6725 /* Register: UART_SHORTS */
yihui 1:fc2f9d636751 6726 /* Description: Shortcuts for UART. */
yihui 1:fc2f9d636751 6727
yihui 1:fc2f9d636751 6728 /* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
yihui 1:fc2f9d636751 6729 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
yihui 1:fc2f9d636751 6730 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
yihui 1:fc2f9d636751 6731 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 6732 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 6733
yihui 1:fc2f9d636751 6734 /* Bit 3 : Shortcut between CTS event and the STARTRX task. */
yihui 1:fc2f9d636751 6735 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
yihui 1:fc2f9d636751 6736 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
yihui 1:fc2f9d636751 6737 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
yihui 1:fc2f9d636751 6738 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
yihui 1:fc2f9d636751 6739
yihui 1:fc2f9d636751 6740 /* Register: UART_INTENSET */
yihui 1:fc2f9d636751 6741 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 6742
yihui 1:fc2f9d636751 6743 /* Bit 17 : Enable interrupt on RXTO event. */
yihui 1:fc2f9d636751 6744 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
yihui 1:fc2f9d636751 6745 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
yihui 1:fc2f9d636751 6746 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6747 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6748 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6749
yihui 1:fc2f9d636751 6750 /* Bit 9 : Enable interrupt on ERROR event. */
yihui 1:fc2f9d636751 6751 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
yihui 1:fc2f9d636751 6752 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
yihui 1:fc2f9d636751 6753 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6754 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6755 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6756
yihui 1:fc2f9d636751 6757 /* Bit 7 : Enable interrupt on TXRDY event. */
yihui 1:fc2f9d636751 6758 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
yihui 1:fc2f9d636751 6759 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
yihui 1:fc2f9d636751 6760 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6761 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6762 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6763
yihui 1:fc2f9d636751 6764 /* Bit 2 : Enable interrupt on RXRDY event. */
yihui 1:fc2f9d636751 6765 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
yihui 1:fc2f9d636751 6766 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
yihui 1:fc2f9d636751 6767 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6768 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6769 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6770
yihui 1:fc2f9d636751 6771 /* Bit 1 : Enable interrupt on NCTS event. */
yihui 1:fc2f9d636751 6772 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
yihui 1:fc2f9d636751 6773 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
yihui 1:fc2f9d636751 6774 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6775 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6776 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6777
yihui 1:fc2f9d636751 6778 /* Bit 0 : Enable interrupt on CTS event. */
yihui 1:fc2f9d636751 6779 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
yihui 1:fc2f9d636751 6780 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
yihui 1:fc2f9d636751 6781 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6782 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6783 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6784
yihui 1:fc2f9d636751 6785 /* Register: UART_INTENCLR */
yihui 1:fc2f9d636751 6786 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 6787
yihui 1:fc2f9d636751 6788 /* Bit 17 : Disable interrupt on RXTO event. */
yihui 1:fc2f9d636751 6789 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
yihui 1:fc2f9d636751 6790 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
yihui 1:fc2f9d636751 6791 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6792 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6793 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6794
yihui 1:fc2f9d636751 6795 /* Bit 9 : Disable interrupt on ERROR event. */
yihui 1:fc2f9d636751 6796 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
yihui 1:fc2f9d636751 6797 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
yihui 1:fc2f9d636751 6798 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6799 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6800 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6801
yihui 1:fc2f9d636751 6802 /* Bit 7 : Disable interrupt on TXRDY event. */
yihui 1:fc2f9d636751 6803 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
yihui 1:fc2f9d636751 6804 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
yihui 1:fc2f9d636751 6805 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6806 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6807 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6808
yihui 1:fc2f9d636751 6809 /* Bit 2 : Disable interrupt on RXRDY event. */
yihui 1:fc2f9d636751 6810 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
yihui 1:fc2f9d636751 6811 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
yihui 1:fc2f9d636751 6812 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6813 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6814 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6815
yihui 1:fc2f9d636751 6816 /* Bit 1 : Disable interrupt on NCTS event. */
yihui 1:fc2f9d636751 6817 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
yihui 1:fc2f9d636751 6818 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
yihui 1:fc2f9d636751 6819 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6820 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6821 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6822
yihui 1:fc2f9d636751 6823 /* Bit 0 : Disable interrupt on CTS event. */
yihui 1:fc2f9d636751 6824 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
yihui 1:fc2f9d636751 6825 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
yihui 1:fc2f9d636751 6826 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6827 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6828 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6829
yihui 1:fc2f9d636751 6830 /* Register: UART_ERRORSRC */
yihui 1:fc2f9d636751 6831 /* Description: Error source. Write error field to 1 to clear error. */
yihui 1:fc2f9d636751 6832
yihui 1:fc2f9d636751 6833 /* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
yihui 1:fc2f9d636751 6834 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
yihui 1:fc2f9d636751 6835 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
yihui 1:fc2f9d636751 6836 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
yihui 1:fc2f9d636751 6837 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
yihui 1:fc2f9d636751 6838 #define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
yihui 1:fc2f9d636751 6839
yihui 1:fc2f9d636751 6840 /* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
yihui 1:fc2f9d636751 6841 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
yihui 1:fc2f9d636751 6842 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
yihui 1:fc2f9d636751 6843 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
yihui 1:fc2f9d636751 6844 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
yihui 1:fc2f9d636751 6845 #define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
yihui 1:fc2f9d636751 6846
yihui 1:fc2f9d636751 6847 /* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
yihui 1:fc2f9d636751 6848 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
yihui 1:fc2f9d636751 6849 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
yihui 1:fc2f9d636751 6850 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
yihui 1:fc2f9d636751 6851 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
yihui 1:fc2f9d636751 6852 #define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
yihui 1:fc2f9d636751 6853
yihui 1:fc2f9d636751 6854 /* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
yihui 1:fc2f9d636751 6855 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
yihui 1:fc2f9d636751 6856 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
yihui 1:fc2f9d636751 6857 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
yihui 1:fc2f9d636751 6858 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
yihui 1:fc2f9d636751 6859 #define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
yihui 1:fc2f9d636751 6860
yihui 1:fc2f9d636751 6861 /* Register: UART_ENABLE */
yihui 1:fc2f9d636751 6862 /* Description: Enable UART and acquire IOs. */
yihui 1:fc2f9d636751 6863
yihui 1:fc2f9d636751 6864 /* Bits 2..0 : Enable or disable UART and acquire IOs. */
yihui 1:fc2f9d636751 6865 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
yihui 1:fc2f9d636751 6866 #define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
yihui 1:fc2f9d636751 6867 #define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
yihui 1:fc2f9d636751 6868 #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
yihui 1:fc2f9d636751 6869
yihui 1:fc2f9d636751 6870 /* Register: UART_RXD */
yihui 1:fc2f9d636751 6871 /* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
yihui 1:fc2f9d636751 6872
yihui 1:fc2f9d636751 6873 /* Bits 7..0 : RX data from previous transfer. Double buffered. */
yihui 1:fc2f9d636751 6874 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
yihui 1:fc2f9d636751 6875 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
yihui 1:fc2f9d636751 6876
yihui 1:fc2f9d636751 6877 /* Register: UART_TXD */
yihui 1:fc2f9d636751 6878 /* Description: TXD register. */
yihui 1:fc2f9d636751 6879
yihui 1:fc2f9d636751 6880 /* Bits 7..0 : TX data for transfer. */
yihui 1:fc2f9d636751 6881 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
yihui 1:fc2f9d636751 6882 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
yihui 1:fc2f9d636751 6883
yihui 1:fc2f9d636751 6884 /* Register: UART_BAUDRATE */
yihui 1:fc2f9d636751 6885 /* Description: UART Baudrate. */
yihui 1:fc2f9d636751 6886
yihui 1:fc2f9d636751 6887 /* Bits 31..0 : UART baudrate. */
yihui 1:fc2f9d636751 6888 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
yihui 1:fc2f9d636751 6889 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
yihui 1:fc2f9d636751 6890 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
yihui 1:fc2f9d636751 6891 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
yihui 1:fc2f9d636751 6892 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
yihui 1:fc2f9d636751 6893 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
yihui 1:fc2f9d636751 6894 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
yihui 1:fc2f9d636751 6895 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
yihui 1:fc2f9d636751 6896 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
yihui 1:fc2f9d636751 6897 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
yihui 1:fc2f9d636751 6898 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
yihui 1:fc2f9d636751 6899 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
yihui 1:fc2f9d636751 6900 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
yihui 1:fc2f9d636751 6901 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
yihui 1:fc2f9d636751 6902 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
yihui 1:fc2f9d636751 6903 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
yihui 1:fc2f9d636751 6904 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /*!< 921600 baud. */
yihui 1:fc2f9d636751 6905 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
yihui 1:fc2f9d636751 6906
yihui 1:fc2f9d636751 6907 /* Register: UART_CONFIG */
yihui 1:fc2f9d636751 6908 /* Description: Configuration of parity and hardware flow control register. */
yihui 1:fc2f9d636751 6909
yihui 1:fc2f9d636751 6910 /* Bits 3..1 : Include parity bit. */
yihui 1:fc2f9d636751 6911 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
yihui 1:fc2f9d636751 6912 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
yihui 1:fc2f9d636751 6913 #define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
yihui 1:fc2f9d636751 6914 #define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
yihui 1:fc2f9d636751 6915
yihui 1:fc2f9d636751 6916 /* Bit 0 : Hardware flow control. */
yihui 1:fc2f9d636751 6917 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
yihui 1:fc2f9d636751 6918 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
yihui 1:fc2f9d636751 6919 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
yihui 1:fc2f9d636751 6920 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
yihui 1:fc2f9d636751 6921
yihui 1:fc2f9d636751 6922 /* Register: UART_POWER */
yihui 1:fc2f9d636751 6923 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 6924
yihui 1:fc2f9d636751 6925 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 6926 #define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 6927 #define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 6928 #define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 6929 #define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 6930
yihui 1:fc2f9d636751 6931
yihui 1:fc2f9d636751 6932 /* Peripheral: UICR */
yihui 1:fc2f9d636751 6933 /* Description: User Information Configuration. */
yihui 1:fc2f9d636751 6934
yihui 1:fc2f9d636751 6935 /* Register: UICR_RBPCONF */
yihui 1:fc2f9d636751 6936 /* Description: Readback protection configuration. */
yihui 1:fc2f9d636751 6937
yihui 1:fc2f9d636751 6938 /* Bits 15..8 : Readback protect all code in the device. */
yihui 1:fc2f9d636751 6939 #define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
yihui 1:fc2f9d636751 6940 #define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
yihui 1:fc2f9d636751 6941 #define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
yihui 1:fc2f9d636751 6942 #define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
yihui 1:fc2f9d636751 6943
yihui 1:fc2f9d636751 6944 /* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
yihui 1:fc2f9d636751 6945 #define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
yihui 1:fc2f9d636751 6946 #define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
yihui 1:fc2f9d636751 6947 #define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
yihui 1:fc2f9d636751 6948 #define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
yihui 1:fc2f9d636751 6949
yihui 1:fc2f9d636751 6950 /* Register: UICR_XTALFREQ */
yihui 1:fc2f9d636751 6951 /* Description: Reset value for CLOCK XTALFREQ register. */
yihui 1:fc2f9d636751 6952
yihui 1:fc2f9d636751 6953 /* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
yihui 1:fc2f9d636751 6954 #define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
yihui 1:fc2f9d636751 6955 #define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
yihui 1:fc2f9d636751 6956 #define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
yihui 1:fc2f9d636751 6957 #define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
yihui 1:fc2f9d636751 6958
yihui 1:fc2f9d636751 6959 /* Register: UICR_FWID */
yihui 1:fc2f9d636751 6960 /* Description: Firmware ID. */
yihui 1:fc2f9d636751 6961
yihui 1:fc2f9d636751 6962 /* Bits 15..0 : Identification number for the firmware loaded into the chip. */
yihui 1:fc2f9d636751 6963 #define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
yihui 1:fc2f9d636751 6964 #define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
yihui 1:fc2f9d636751 6965
yihui 1:fc2f9d636751 6966
yihui 1:fc2f9d636751 6967 /* Peripheral: WDT */
yihui 1:fc2f9d636751 6968 /* Description: Watchdog Timer. */
yihui 1:fc2f9d636751 6969
yihui 1:fc2f9d636751 6970 /* Register: WDT_INTENSET */
yihui 1:fc2f9d636751 6971 /* Description: Interrupt enable set register. */
yihui 1:fc2f9d636751 6972
yihui 1:fc2f9d636751 6973 /* Bit 0 : Enable interrupt on TIMEOUT event. */
yihui 1:fc2f9d636751 6974 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
yihui 1:fc2f9d636751 6975 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
yihui 1:fc2f9d636751 6976 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6977 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6978 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
yihui 1:fc2f9d636751 6979
yihui 1:fc2f9d636751 6980 /* Register: WDT_INTENCLR */
yihui 1:fc2f9d636751 6981 /* Description: Interrupt enable clear register. */
yihui 1:fc2f9d636751 6982
yihui 1:fc2f9d636751 6983 /* Bit 0 : Disable interrupt on TIMEOUT event. */
yihui 1:fc2f9d636751 6984 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
yihui 1:fc2f9d636751 6985 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
yihui 1:fc2f9d636751 6986 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
yihui 1:fc2f9d636751 6987 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
yihui 1:fc2f9d636751 6988 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
yihui 1:fc2f9d636751 6989
yihui 1:fc2f9d636751 6990 /* Register: WDT_RUNSTATUS */
yihui 1:fc2f9d636751 6991 /* Description: Watchdog running status. */
yihui 1:fc2f9d636751 6992
yihui 1:fc2f9d636751 6993 /* Bit 0 : Watchdog running status. */
yihui 1:fc2f9d636751 6994 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
yihui 1:fc2f9d636751 6995 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
yihui 1:fc2f9d636751 6996 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
yihui 1:fc2f9d636751 6997 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
yihui 1:fc2f9d636751 6998
yihui 1:fc2f9d636751 6999 /* Register: WDT_REQSTATUS */
yihui 1:fc2f9d636751 7000 /* Description: Request status. */
yihui 1:fc2f9d636751 7001
yihui 1:fc2f9d636751 7002 /* Bit 7 : Request status for RR[7]. */
yihui 1:fc2f9d636751 7003 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
yihui 1:fc2f9d636751 7004 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
yihui 1:fc2f9d636751 7005 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
yihui 1:fc2f9d636751 7006 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
yihui 1:fc2f9d636751 7007
yihui 1:fc2f9d636751 7008 /* Bit 6 : Request status for RR[6]. */
yihui 1:fc2f9d636751 7009 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
yihui 1:fc2f9d636751 7010 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
yihui 1:fc2f9d636751 7011 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
yihui 1:fc2f9d636751 7012 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
yihui 1:fc2f9d636751 7013
yihui 1:fc2f9d636751 7014 /* Bit 5 : Request status for RR[5]. */
yihui 1:fc2f9d636751 7015 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
yihui 1:fc2f9d636751 7016 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
yihui 1:fc2f9d636751 7017 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
yihui 1:fc2f9d636751 7018 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
yihui 1:fc2f9d636751 7019
yihui 1:fc2f9d636751 7020 /* Bit 4 : Request status for RR[4]. */
yihui 1:fc2f9d636751 7021 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
yihui 1:fc2f9d636751 7022 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
yihui 1:fc2f9d636751 7023 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
yihui 1:fc2f9d636751 7024 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
yihui 1:fc2f9d636751 7025
yihui 1:fc2f9d636751 7026 /* Bit 3 : Request status for RR[3]. */
yihui 1:fc2f9d636751 7027 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
yihui 1:fc2f9d636751 7028 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
yihui 1:fc2f9d636751 7029 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
yihui 1:fc2f9d636751 7030 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
yihui 1:fc2f9d636751 7031
yihui 1:fc2f9d636751 7032 /* Bit 2 : Request status for RR[2]. */
yihui 1:fc2f9d636751 7033 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
yihui 1:fc2f9d636751 7034 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
yihui 1:fc2f9d636751 7035 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
yihui 1:fc2f9d636751 7036 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
yihui 1:fc2f9d636751 7037
yihui 1:fc2f9d636751 7038 /* Bit 1 : Request status for RR[1]. */
yihui 1:fc2f9d636751 7039 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
yihui 1:fc2f9d636751 7040 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
yihui 1:fc2f9d636751 7041 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
yihui 1:fc2f9d636751 7042 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
yihui 1:fc2f9d636751 7043
yihui 1:fc2f9d636751 7044 /* Bit 0 : Request status for RR[0]. */
yihui 1:fc2f9d636751 7045 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
yihui 1:fc2f9d636751 7046 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
yihui 1:fc2f9d636751 7047 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
yihui 1:fc2f9d636751 7048 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
yihui 1:fc2f9d636751 7049
yihui 1:fc2f9d636751 7050 /* Register: WDT_RREN */
yihui 1:fc2f9d636751 7051 /* Description: Reload request enable. */
yihui 1:fc2f9d636751 7052
yihui 1:fc2f9d636751 7053 /* Bit 7 : Enable or disable RR[7] register. */
yihui 1:fc2f9d636751 7054 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
yihui 1:fc2f9d636751 7055 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
yihui 1:fc2f9d636751 7056 #define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
yihui 1:fc2f9d636751 7057 #define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
yihui 1:fc2f9d636751 7058
yihui 1:fc2f9d636751 7059 /* Bit 6 : Enable or disable RR[6] register. */
yihui 1:fc2f9d636751 7060 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
yihui 1:fc2f9d636751 7061 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
yihui 1:fc2f9d636751 7062 #define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
yihui 1:fc2f9d636751 7063 #define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
yihui 1:fc2f9d636751 7064
yihui 1:fc2f9d636751 7065 /* Bit 5 : Enable or disable RR[5] register. */
yihui 1:fc2f9d636751 7066 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
yihui 1:fc2f9d636751 7067 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
yihui 1:fc2f9d636751 7068 #define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
yihui 1:fc2f9d636751 7069 #define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
yihui 1:fc2f9d636751 7070
yihui 1:fc2f9d636751 7071 /* Bit 4 : Enable or disable RR[4] register. */
yihui 1:fc2f9d636751 7072 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
yihui 1:fc2f9d636751 7073 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
yihui 1:fc2f9d636751 7074 #define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
yihui 1:fc2f9d636751 7075 #define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
yihui 1:fc2f9d636751 7076
yihui 1:fc2f9d636751 7077 /* Bit 3 : Enable or disable RR[3] register. */
yihui 1:fc2f9d636751 7078 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
yihui 1:fc2f9d636751 7079 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
yihui 1:fc2f9d636751 7080 #define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
yihui 1:fc2f9d636751 7081 #define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
yihui 1:fc2f9d636751 7082
yihui 1:fc2f9d636751 7083 /* Bit 2 : Enable or disable RR[2] register. */
yihui 1:fc2f9d636751 7084 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
yihui 1:fc2f9d636751 7085 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
yihui 1:fc2f9d636751 7086 #define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
yihui 1:fc2f9d636751 7087 #define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
yihui 1:fc2f9d636751 7088
yihui 1:fc2f9d636751 7089 /* Bit 1 : Enable or disable RR[1] register. */
yihui 1:fc2f9d636751 7090 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
yihui 1:fc2f9d636751 7091 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
yihui 1:fc2f9d636751 7092 #define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
yihui 1:fc2f9d636751 7093 #define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
yihui 1:fc2f9d636751 7094
yihui 1:fc2f9d636751 7095 /* Bit 0 : Enable or disable RR[0] register. */
yihui 1:fc2f9d636751 7096 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
yihui 1:fc2f9d636751 7097 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
yihui 1:fc2f9d636751 7098 #define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
yihui 1:fc2f9d636751 7099 #define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
yihui 1:fc2f9d636751 7100
yihui 1:fc2f9d636751 7101 /* Register: WDT_CONFIG */
yihui 1:fc2f9d636751 7102 /* Description: Configuration register. */
yihui 1:fc2f9d636751 7103
yihui 1:fc2f9d636751 7104 /* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
yihui 1:fc2f9d636751 7105 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
yihui 1:fc2f9d636751 7106 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
yihui 1:fc2f9d636751 7107 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
yihui 1:fc2f9d636751 7108 #define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
yihui 1:fc2f9d636751 7109
yihui 1:fc2f9d636751 7110 /* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
yihui 1:fc2f9d636751 7111 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
yihui 1:fc2f9d636751 7112 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
yihui 1:fc2f9d636751 7113 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
yihui 1:fc2f9d636751 7114 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
yihui 1:fc2f9d636751 7115
yihui 1:fc2f9d636751 7116 /* Register: WDT_RR */
yihui 1:fc2f9d636751 7117 /* Description: Reload requests registers. */
yihui 1:fc2f9d636751 7118
yihui 1:fc2f9d636751 7119 /* Bits 31..0 : Reload register. */
yihui 1:fc2f9d636751 7120 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
yihui 1:fc2f9d636751 7121 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
yihui 1:fc2f9d636751 7122 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
yihui 1:fc2f9d636751 7123
yihui 1:fc2f9d636751 7124 /* Register: WDT_POWER */
yihui 1:fc2f9d636751 7125 /* Description: Peripheral power control. */
yihui 1:fc2f9d636751 7126
yihui 1:fc2f9d636751 7127 /* Bit 0 : Peripheral power control. */
yihui 1:fc2f9d636751 7128 #define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
yihui 1:fc2f9d636751 7129 #define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
yihui 1:fc2f9d636751 7130 #define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
yihui 1:fc2f9d636751 7131 #define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
yihui 1:fc2f9d636751 7132
yihui 1:fc2f9d636751 7133
yihui 1:fc2f9d636751 7134 /*lint --flb "Leave library region" */
yihui 1:fc2f9d636751 7135 #endif