Seeed_Tiny_BLE_Get_Started - To get started with Seeed Tiny BLE, include detec…

Seeed » Code » Seeed_Tiny_BLE_Get_Started

Seeed / Mbed 2 deprecated Seeed_Tiny_BLE_Get_Started

To get started with Seeed Tiny BLE, include detecting motion, button and battery level.

Dependencies: BLE_API eMPL_MPU6050 mbed nRF51822

nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf51.h@1:fc2f9d636751, 2015-04-22 (annotated)

Committer:: yihui
Date:: Wed Apr 22 07:47:17 2015 +0000
Revision:: 1:fc2f9d636751

update libraries; ; delete nRF51822/nordic-sdk/components/gpiote/app_gpiote.c to solve GPIOTE_IRQHandler multiply defined issue. temperarily change nRF51822 library to folder

Who changed what in which revision?

User	Revision	Line number	New contents of line
yihui	1:fc2f9d636751	1
yihui	1:fc2f9d636751	2	/**************************************************************************************************//
yihui	1:fc2f9d636751	3	* @file nRF51.h
yihui	1:fc2f9d636751	4	*
yihui	1:fc2f9d636751	5	* @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
yihui	1:fc2f9d636751	6	* nRF51 from Nordic Semiconductor.
yihui	1:fc2f9d636751	7	*
yihui	1:fc2f9d636751	8	* @version V522
yihui	1:fc2f9d636751	9	* @date 31. October 2014
yihui	1:fc2f9d636751	10	*
yihui	1:fc2f9d636751	11	* @note Generated with SVDConv V2.81d
yihui	1:fc2f9d636751	12	* from CMSIS SVD File 'nRF51.xml' Version 522,
yihui	1:fc2f9d636751	13	*
yihui	1:fc2f9d636751	14	* @par Copyright (c) 2013, Nordic Semiconductor ASA
yihui	1:fc2f9d636751	15	* All rights reserved.
yihui	1:fc2f9d636751	16	*
yihui	1:fc2f9d636751	17	* Redistribution and use in source and binary forms, with or without
yihui	1:fc2f9d636751	18	* modification, are permitted provided that the following conditions are met:
yihui	1:fc2f9d636751	19	*
yihui	1:fc2f9d636751	20	* * Redistributions of source code must retain the above copyright notice, this
yihui	1:fc2f9d636751	21	* list of conditions and the following disclaimer.
yihui	1:fc2f9d636751	22	*
yihui	1:fc2f9d636751	23	* * Redistributions in binary form must reproduce the above copyright notice,
yihui	1:fc2f9d636751	24	* this list of conditions and the following disclaimer in the documentation
yihui	1:fc2f9d636751	25	* and/or other materials provided with the distribution.
yihui	1:fc2f9d636751	26	*
yihui	1:fc2f9d636751	27	* * Neither the name of Nordic Semiconductor ASA nor the names of its
yihui	1:fc2f9d636751	28	* contributors may be used to endorse or promote products derived from
yihui	1:fc2f9d636751	29	* this software without specific prior written permission.
yihui	1:fc2f9d636751	30	*
yihui	1:fc2f9d636751	31	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
yihui	1:fc2f9d636751	32	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
yihui	1:fc2f9d636751	33	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
yihui	1:fc2f9d636751	34	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
yihui	1:fc2f9d636751	35	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
yihui	1:fc2f9d636751	36	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
yihui	1:fc2f9d636751	37	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
yihui	1:fc2f9d636751	38	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
yihui	1:fc2f9d636751	39	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
yihui	1:fc2f9d636751	40	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
yihui	1:fc2f9d636751	41	*
yihui	1:fc2f9d636751	42	*
yihui	1:fc2f9d636751	43	*******************************************************************************************************/
yihui	1:fc2f9d636751	44
yihui	1:fc2f9d636751	45
yihui	1:fc2f9d636751	46
yihui	1:fc2f9d636751	47	/** @addtogroup Nordic Semiconductor
yihui	1:fc2f9d636751	48	* @{
yihui	1:fc2f9d636751	49	*/
yihui	1:fc2f9d636751	50
yihui	1:fc2f9d636751	51	/** @addtogroup nRF51
yihui	1:fc2f9d636751	52	* @{
yihui	1:fc2f9d636751	53	*/
yihui	1:fc2f9d636751	54
yihui	1:fc2f9d636751	55	#ifndef NRF51_H
yihui	1:fc2f9d636751	56	#define NRF51_H
yihui	1:fc2f9d636751	57
yihui	1:fc2f9d636751	58	#ifdef __cplusplus
yihui	1:fc2f9d636751	59	extern "C" {
yihui	1:fc2f9d636751	60	#endif
yihui	1:fc2f9d636751	61
yihui	1:fc2f9d636751	62
yihui	1:fc2f9d636751	63	/* ------------------------- Interrupt Number Definition ------------------------ */
yihui	1:fc2f9d636751	64
yihui	1:fc2f9d636751	65	typedef enum {
yihui	1:fc2f9d636751	66	/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
yihui	1:fc2f9d636751	67	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
yihui	1:fc2f9d636751	68	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
yihui	1:fc2f9d636751	69	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
yihui	1:fc2f9d636751	70	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
yihui	1:fc2f9d636751	71	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
yihui	1:fc2f9d636751	72	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
yihui	1:fc2f9d636751	73	SysTick_IRQn = -1, /!< 15 System Tick Timer /
yihui	1:fc2f9d636751	74	/* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
yihui	1:fc2f9d636751	75	POWER_CLOCK_IRQn = 0, /!< 0 POWER_CLOCK /
yihui	1:fc2f9d636751	76	RADIO_IRQn = 1, /!< 1 RADIO /
yihui	1:fc2f9d636751	77	UART0_IRQn = 2, /!< 2 UART0 /
yihui	1:fc2f9d636751	78	SPI0_TWI0_IRQn = 3, /!< 3 SPI0_TWI0 /
yihui	1:fc2f9d636751	79	SPI1_TWI1_IRQn = 4, /!< 4 SPI1_TWI1 /
yihui	1:fc2f9d636751	80	GPIOTE_IRQn = 6, /!< 6 GPIOTE /
yihui	1:fc2f9d636751	81	ADC_IRQn = 7, /!< 7 ADC /
yihui	1:fc2f9d636751	82	TIMER0_IRQn = 8, /!< 8 TIMER0 /
yihui	1:fc2f9d636751	83	TIMER1_IRQn = 9, /!< 9 TIMER1 /
yihui	1:fc2f9d636751	84	TIMER2_IRQn = 10, /!< 10 TIMER2 /
yihui	1:fc2f9d636751	85	RTC0_IRQn = 11, /!< 11 RTC0 /
yihui	1:fc2f9d636751	86	TEMP_IRQn = 12, /!< 12 TEMP /
yihui	1:fc2f9d636751	87	RNG_IRQn = 13, /!< 13 RNG /
yihui	1:fc2f9d636751	88	ECB_IRQn = 14, /!< 14 ECB /
yihui	1:fc2f9d636751	89	CCM_AAR_IRQn = 15, /!< 15 CCM_AAR /
yihui	1:fc2f9d636751	90	WDT_IRQn = 16, /!< 16 WDT /
yihui	1:fc2f9d636751	91	RTC1_IRQn = 17, /!< 17 RTC1 /
yihui	1:fc2f9d636751	92	QDEC_IRQn = 18, /!< 18 QDEC /
yihui	1:fc2f9d636751	93	LPCOMP_IRQn = 19, /!< 19 LPCOMP /
yihui	1:fc2f9d636751	94	SWI0_IRQn = 20, /!< 20 SWI0 /
yihui	1:fc2f9d636751	95	SWI1_IRQn = 21, /!< 21 SWI1 /
yihui	1:fc2f9d636751	96	SWI2_IRQn = 22, /!< 22 SWI2 /
yihui	1:fc2f9d636751	97	SWI3_IRQn = 23, /!< 23 SWI3 /
yihui	1:fc2f9d636751	98	SWI4_IRQn = 24, /!< 24 SWI4 /
yihui	1:fc2f9d636751	99	SWI5_IRQn = 25 /!< 25 SWI5 /
yihui	1:fc2f9d636751	100	} IRQn_Type;
yihui	1:fc2f9d636751	101
yihui	1:fc2f9d636751	102
yihui	1:fc2f9d636751	103	/** @addtogroup Configuration_of_CMSIS
yihui	1:fc2f9d636751	104	* @{
yihui	1:fc2f9d636751	105	*/
yihui	1:fc2f9d636751	106
yihui	1:fc2f9d636751	107
yihui	1:fc2f9d636751	108	/* ================================================================================ */
yihui	1:fc2f9d636751	109	/* ================ Processor and Core Peripheral Section ================ */
yihui	1:fc2f9d636751	110	/* ================================================================================ */
yihui	1:fc2f9d636751	111
yihui	1:fc2f9d636751	112	/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
yihui	1:fc2f9d636751	113	#define __CM0_REV 0x0301 /!< Cortex-M0 Core Revision /
yihui	1:fc2f9d636751	114	#define __MPU_PRESENT 0 /!< MPU present or not /
yihui	1:fc2f9d636751	115	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
yihui	1:fc2f9d636751	116	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
yihui	1:fc2f9d636751	117	/** @} / / End of group Configuration_of_CMSIS */
yihui	1:fc2f9d636751	118
yihui	1:fc2f9d636751	119	#include "core_cm0.h" /!< Cortex-M0 processor and core peripherals /
yihui	1:fc2f9d636751	120	#include "system_nrf51.h" /!< nRF51 System /
yihui	1:fc2f9d636751	121
yihui	1:fc2f9d636751	122
yihui	1:fc2f9d636751	123	/* ================================================================================ */
yihui	1:fc2f9d636751	124	/* ================ Device Specific Peripheral Section ================ */
yihui	1:fc2f9d636751	125	/* ================================================================================ */
yihui	1:fc2f9d636751	126
yihui	1:fc2f9d636751	127
yihui	1:fc2f9d636751	128	/** @addtogroup Device_Peripheral_Registers
yihui	1:fc2f9d636751	129	* @{
yihui	1:fc2f9d636751	130	*/
yihui	1:fc2f9d636751	131
yihui	1:fc2f9d636751	132
yihui	1:fc2f9d636751	133	/* ------------------- Start of section using anonymous unions ------------------ */
yihui	1:fc2f9d636751	134	#if defined(__CC_ARM)
yihui	1:fc2f9d636751	135	#pragma push
yihui	1:fc2f9d636751	136	#pragma anon_unions
yihui	1:fc2f9d636751	137	#elif defined(__ICCARM__)
yihui	1:fc2f9d636751	138	#pragma language=extended
yihui	1:fc2f9d636751	139	#elif defined(__GNUC__)
yihui	1:fc2f9d636751	140	/* anonymous unions are enabled by default */
yihui	1:fc2f9d636751	141	#elif defined(__TMS470__)
yihui	1:fc2f9d636751	142	/* anonymous unions are enabled by default */
yihui	1:fc2f9d636751	143	#elif defined(__TASKING__)
yihui	1:fc2f9d636751	144	#pragma warning 586
yihui	1:fc2f9d636751	145	#else
yihui	1:fc2f9d636751	146	#warning Not supported compiler type
yihui	1:fc2f9d636751	147	#endif
yihui	1:fc2f9d636751	148
yihui	1:fc2f9d636751	149
yihui	1:fc2f9d636751	150	typedef struct {
yihui	1:fc2f9d636751	151	__IO uint32_t CPU0; /!< Configurable priority configuration register for CPU0. /
yihui	1:fc2f9d636751	152	__IO uint32_t SPIS1; /!< Configurable priority configuration register for SPIS1. /
yihui	1:fc2f9d636751	153	__IO uint32_t RADIO; /!< Configurable priority configuration register for RADIO. /
yihui	1:fc2f9d636751	154	__IO uint32_t ECB; /!< Configurable priority configuration register for ECB. /
yihui	1:fc2f9d636751	155	__IO uint32_t CCM; /!< Configurable priority configuration register for CCM. /
yihui	1:fc2f9d636751	156	__IO uint32_t AAR; /!< Configurable priority configuration register for AAR. /
yihui	1:fc2f9d636751	157	} AMLI_RAMPRI_Type;
yihui	1:fc2f9d636751	158
yihui	1:fc2f9d636751	159	typedef struct {
yihui	1:fc2f9d636751	160	__IO uint32_t SCK; /!< Pin select for SCK. /
yihui	1:fc2f9d636751	161	__IO uint32_t MOSI; /!< Pin select for MOSI. /
yihui	1:fc2f9d636751	162	__IO uint32_t MISO; /!< Pin select for MISO. /
yihui	1:fc2f9d636751	163	} SPIM_PSEL_Type;
yihui	1:fc2f9d636751	164
yihui	1:fc2f9d636751	165	typedef struct {
yihui	1:fc2f9d636751	166	__IO uint32_t PTR; /!< Data pointer. /
yihui	1:fc2f9d636751	167	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to receive. /
yihui	1:fc2f9d636751	168	__I uint32_t AMOUNT; /!< Number of bytes received in the last transaction. /
yihui	1:fc2f9d636751	169	} SPIM_RXD_Type;
yihui	1:fc2f9d636751	170
yihui	1:fc2f9d636751	171	typedef struct {
yihui	1:fc2f9d636751	172	__IO uint32_t PTR; /!< Data pointer. /
yihui	1:fc2f9d636751	173	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to send. /
yihui	1:fc2f9d636751	174	__I uint32_t AMOUNT; /!< Number of bytes sent in the last transaction. /
yihui	1:fc2f9d636751	175	} SPIM_TXD_Type;
yihui	1:fc2f9d636751	176
yihui	1:fc2f9d636751	177	typedef struct {
yihui	1:fc2f9d636751	178	__O uint32_t EN; /!< Enable channel group. /
yihui	1:fc2f9d636751	179	__O uint32_t DIS; /!< Disable channel group. /
yihui	1:fc2f9d636751	180	} PPI_TASKS_CHG_Type;
yihui	1:fc2f9d636751	181
yihui	1:fc2f9d636751	182	typedef struct {
yihui	1:fc2f9d636751	183	__IO uint32_t EEP; /!< Channel event end-point. /
yihui	1:fc2f9d636751	184	__IO uint32_t TEP; /!< Channel task end-point. /
yihui	1:fc2f9d636751	185	} PPI_CH_Type;
yihui	1:fc2f9d636751	186
yihui	1:fc2f9d636751	187	typedef struct {
yihui	1:fc2f9d636751	188	__I uint32_t PART; /!< Part code /
yihui	1:fc2f9d636751	189	__I uint32_t VARIANT; /!< Part variant /
yihui	1:fc2f9d636751	190	__I uint32_t PACKAGE; /!< Package option /
yihui	1:fc2f9d636751	191	__I uint32_t RAM; /!< RAM variant /
yihui	1:fc2f9d636751	192	__I uint32_t FLASH; /!< Flash variant /
yihui	1:fc2f9d636751	193	__I uint32_t RESERVED[3]; /!< Reserved /
yihui	1:fc2f9d636751	194	} FICR_INFO_Type;
yihui	1:fc2f9d636751	195
yihui	1:fc2f9d636751	196
yihui	1:fc2f9d636751	197	/* ================================================================================ */
yihui	1:fc2f9d636751	198	/* ================ POWER ================ */
yihui	1:fc2f9d636751	199	/* ================================================================================ */
yihui	1:fc2f9d636751	200
yihui	1:fc2f9d636751	201
yihui	1:fc2f9d636751	202	/**
yihui	1:fc2f9d636751	203	* @brief Power Control. (POWER)
yihui	1:fc2f9d636751	204	*/
yihui	1:fc2f9d636751	205
yihui	1:fc2f9d636751	206	typedef struct { /!< POWER Structure /
yihui	1:fc2f9d636751	207	__I uint32_t RESERVED0[30];
yihui	1:fc2f9d636751	208	__O uint32_t TASKS_CONSTLAT; /!< Enable constant latency mode. /
yihui	1:fc2f9d636751	209	__O uint32_t TASKS_LOWPWR; /!< Enable low power mode (variable latency). /
yihui	1:fc2f9d636751	210	__I uint32_t RESERVED1[34];
yihui	1:fc2f9d636751	211	__IO uint32_t EVENTS_POFWARN; /!< Power failure warning. /
yihui	1:fc2f9d636751	212	__I uint32_t RESERVED2[126];
yihui	1:fc2f9d636751	213	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	214	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	215	__I uint32_t RESERVED3[61];
yihui	1:fc2f9d636751	216	__IO uint32_t RESETREAS; /!< Reset reason. /
yihui	1:fc2f9d636751	217	__I uint32_t RESERVED4[9];
yihui	1:fc2f9d636751	218	__I uint32_t RAMSTATUS; /!< Ram status register. /
yihui	1:fc2f9d636751	219	__I uint32_t RESERVED5[53];
yihui	1:fc2f9d636751	220	__O uint32_t SYSTEMOFF; /!< System off register. /
yihui	1:fc2f9d636751	221	__I uint32_t RESERVED6[3];
yihui	1:fc2f9d636751	222	__IO uint32_t POFCON; /!< Power failure configuration. /
yihui	1:fc2f9d636751	223	__I uint32_t RESERVED7[2];
yihui	1:fc2f9d636751	224	__IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
yihui	1:fc2f9d636751	225	register. */
yihui	1:fc2f9d636751	226	__I uint32_t RESERVED8;
yihui	1:fc2f9d636751	227	__IO uint32_t RAMON; /!< Ram on/off. /
yihui	1:fc2f9d636751	228	__I uint32_t RESERVED9[7];
yihui	1:fc2f9d636751	229	__IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
yihui	1:fc2f9d636751	230	is a retained register. */
yihui	1:fc2f9d636751	231	__I uint32_t RESERVED10[3];
yihui	1:fc2f9d636751	232	__IO uint32_t RAMONB; /!< Ram on/off. /
yihui	1:fc2f9d636751	233	__I uint32_t RESERVED11[8];
yihui	1:fc2f9d636751	234	__IO uint32_t DCDCEN; /!< DCDC converter enable configuration register. /
yihui	1:fc2f9d636751	235	__I uint32_t RESERVED12[291];
yihui	1:fc2f9d636751	236	__IO uint32_t DCDCFORCE; /!< DCDC power-up force register. /
yihui	1:fc2f9d636751	237	} NRF_POWER_Type;
yihui	1:fc2f9d636751	238
yihui	1:fc2f9d636751	239
yihui	1:fc2f9d636751	240	/* ================================================================================ */
yihui	1:fc2f9d636751	241	/* ================ CLOCK ================ */
yihui	1:fc2f9d636751	242	/* ================================================================================ */
yihui	1:fc2f9d636751	243
yihui	1:fc2f9d636751	244
yihui	1:fc2f9d636751	245	/**
yihui	1:fc2f9d636751	246	* @brief Clock control. (CLOCK)
yihui	1:fc2f9d636751	247	*/
yihui	1:fc2f9d636751	248
yihui	1:fc2f9d636751	249	typedef struct { /!< CLOCK Structure /
yihui	1:fc2f9d636751	250	__O uint32_t TASKS_HFCLKSTART; /!< Start HFCLK clock source. /
yihui	1:fc2f9d636751	251	__O uint32_t TASKS_HFCLKSTOP; /!< Stop HFCLK clock source. /
yihui	1:fc2f9d636751	252	__O uint32_t TASKS_LFCLKSTART; /!< Start LFCLK clock source. /
yihui	1:fc2f9d636751	253	__O uint32_t TASKS_LFCLKSTOP; /!< Stop LFCLK clock source. /
yihui	1:fc2f9d636751	254	__O uint32_t TASKS_CAL; /!< Start calibration of LFCLK RC oscillator. /
yihui	1:fc2f9d636751	255	__O uint32_t TASKS_CTSTART; /!< Start calibration timer. /
yihui	1:fc2f9d636751	256	__O uint32_t TASKS_CTSTOP; /!< Stop calibration timer. /
yihui	1:fc2f9d636751	257	__I uint32_t RESERVED0[57];
yihui	1:fc2f9d636751	258	__IO uint32_t EVENTS_HFCLKSTARTED; /!< HFCLK oscillator started. /
yihui	1:fc2f9d636751	259	__IO uint32_t EVENTS_LFCLKSTARTED; /!< LFCLK oscillator started. /
yihui	1:fc2f9d636751	260	__I uint32_t RESERVED1;
yihui	1:fc2f9d636751	261	__IO uint32_t EVENTS_DONE; /!< Calibration of LFCLK RC oscillator completed. /
yihui	1:fc2f9d636751	262	__IO uint32_t EVENTS_CTTO; /!< Calibration timer timeout. /
yihui	1:fc2f9d636751	263	__I uint32_t RESERVED2[124];
yihui	1:fc2f9d636751	264	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	265	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	266	__I uint32_t RESERVED3[63];
yihui	1:fc2f9d636751	267	__I uint32_t HFCLKRUN; /!< Task HFCLKSTART trigger status. /
yihui	1:fc2f9d636751	268	__I uint32_t HFCLKSTAT; /!< High frequency clock status. /
yihui	1:fc2f9d636751	269	__I uint32_t RESERVED4;
yihui	1:fc2f9d636751	270	__I uint32_t LFCLKRUN; /!< Task LFCLKSTART triggered status. /
yihui	1:fc2f9d636751	271	__I uint32_t LFCLKSTAT; /!< Low frequency clock status. /
yihui	1:fc2f9d636751	272	__I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
yihui	1:fc2f9d636751	273	triggered. */
yihui	1:fc2f9d636751	274	__I uint32_t RESERVED5[62];
yihui	1:fc2f9d636751	275	__IO uint32_t LFCLKSRC; /!< Clock source for the LFCLK clock. /
yihui	1:fc2f9d636751	276	__I uint32_t RESERVED6[7];
yihui	1:fc2f9d636751	277	__IO uint32_t CTIV; /!< Calibration timer interval. /
yihui	1:fc2f9d636751	278	__I uint32_t RESERVED7[5];
yihui	1:fc2f9d636751	279	__IO uint32_t XTALFREQ; /!< Crystal frequency. /
yihui	1:fc2f9d636751	280	} NRF_CLOCK_Type;
yihui	1:fc2f9d636751	281
yihui	1:fc2f9d636751	282
yihui	1:fc2f9d636751	283	/* ================================================================================ */
yihui	1:fc2f9d636751	284	/* ================ MPU ================ */
yihui	1:fc2f9d636751	285	/* ================================================================================ */
yihui	1:fc2f9d636751	286
yihui	1:fc2f9d636751	287
yihui	1:fc2f9d636751	288	/**
yihui	1:fc2f9d636751	289	* @brief Memory Protection Unit. (MPU)
yihui	1:fc2f9d636751	290	*/
yihui	1:fc2f9d636751	291
yihui	1:fc2f9d636751	292	typedef struct { /!< MPU Structure /
yihui	1:fc2f9d636751	293	__I uint32_t RESERVED0[330];
yihui	1:fc2f9d636751	294	__IO uint32_t PERR0; /!< Configuration of peripherals in mpu regions. /
yihui	1:fc2f9d636751	295	__IO uint32_t RLENR0; /!< Length of RAM region 0. /
yihui	1:fc2f9d636751	296	__I uint32_t RESERVED1[52];
yihui	1:fc2f9d636751	297	__IO uint32_t PROTENSET0; /!< Erase and write protection bit enable set register. /
yihui	1:fc2f9d636751	298	__IO uint32_t PROTENSET1; /!< Erase and write protection bit enable set register. /
yihui	1:fc2f9d636751	299	__IO uint32_t DISABLEINDEBUG; /!< Disable erase and write protection mechanism in debug mode. /
yihui	1:fc2f9d636751	300	__IO uint32_t PROTBLOCKSIZE; /!< Erase and write protection block size. /
yihui	1:fc2f9d636751	301	} NRF_MPU_Type;
yihui	1:fc2f9d636751	302
yihui	1:fc2f9d636751	303
yihui	1:fc2f9d636751	304	/* ================================================================================ */
yihui	1:fc2f9d636751	305	/* ================ PU ================ */
yihui	1:fc2f9d636751	306	/* ================================================================================ */
yihui	1:fc2f9d636751	307
yihui	1:fc2f9d636751	308
yihui	1:fc2f9d636751	309	/**
yihui	1:fc2f9d636751	310	* @brief Patch unit. (PU)
yihui	1:fc2f9d636751	311	*/
yihui	1:fc2f9d636751	312
yihui	1:fc2f9d636751	313	typedef struct { /!< PU Structure /
yihui	1:fc2f9d636751	314	__I uint32_t RESERVED0[448];
yihui	1:fc2f9d636751	315	__IO uint32_t REPLACEADDR[8]; /!< Address of first instruction to replace. /
yihui	1:fc2f9d636751	316	__I uint32_t RESERVED1[24];
yihui	1:fc2f9d636751	317	__IO uint32_t PATCHADDR[8]; /!< Relative address of patch instructions. /
yihui	1:fc2f9d636751	318	__I uint32_t RESERVED2[24];
yihui	1:fc2f9d636751	319	__IO uint32_t PATCHEN; /!< Patch enable register. /
yihui	1:fc2f9d636751	320	__IO uint32_t PATCHENSET; /!< Patch enable register. /
yihui	1:fc2f9d636751	321	__IO uint32_t PATCHENCLR; /!< Patch disable register. /
yihui	1:fc2f9d636751	322	} NRF_PU_Type;
yihui	1:fc2f9d636751	323
yihui	1:fc2f9d636751	324
yihui	1:fc2f9d636751	325	/* ================================================================================ */
yihui	1:fc2f9d636751	326	/* ================ AMLI ================ */
yihui	1:fc2f9d636751	327	/* ================================================================================ */
yihui	1:fc2f9d636751	328
yihui	1:fc2f9d636751	329
yihui	1:fc2f9d636751	330	/**
yihui	1:fc2f9d636751	331	* @brief AHB Multi-Layer Interface. (AMLI)
yihui	1:fc2f9d636751	332	*/
yihui	1:fc2f9d636751	333
yihui	1:fc2f9d636751	334	typedef struct { /!< AMLI Structure /
yihui	1:fc2f9d636751	335	__I uint32_t RESERVED0[896];
yihui	1:fc2f9d636751	336	AMLI_RAMPRI_Type RAMPRI; /!< RAM configurable priority configuration structure. /
yihui	1:fc2f9d636751	337	} NRF_AMLI_Type;
yihui	1:fc2f9d636751	338
yihui	1:fc2f9d636751	339
yihui	1:fc2f9d636751	340	/* ================================================================================ */
yihui	1:fc2f9d636751	341	/* ================ RADIO ================ */
yihui	1:fc2f9d636751	342	/* ================================================================================ */
yihui	1:fc2f9d636751	343
yihui	1:fc2f9d636751	344
yihui	1:fc2f9d636751	345	/**
yihui	1:fc2f9d636751	346	* @brief The radio. (RADIO)
yihui	1:fc2f9d636751	347	*/
yihui	1:fc2f9d636751	348
yihui	1:fc2f9d636751	349	typedef struct { /!< RADIO Structure /
yihui	1:fc2f9d636751	350	__O uint32_t TASKS_TXEN; /!< Enable radio in TX mode. /
yihui	1:fc2f9d636751	351	__O uint32_t TASKS_RXEN; /!< Enable radio in RX mode. /
yihui	1:fc2f9d636751	352	__O uint32_t TASKS_START; /!< Start radio. /
yihui	1:fc2f9d636751	353	__O uint32_t TASKS_STOP; /!< Stop radio. /
yihui	1:fc2f9d636751	354	__O uint32_t TASKS_DISABLE; /!< Disable radio. /
yihui	1:fc2f9d636751	355	__O uint32_t TASKS_RSSISTART; /!< Start the RSSI and take one sample of the receive signal strength. /
yihui	1:fc2f9d636751	356	__O uint32_t TASKS_RSSISTOP; /!< Stop the RSSI measurement. /
yihui	1:fc2f9d636751	357	__O uint32_t TASKS_BCSTART; /!< Start the bit counter. /
yihui	1:fc2f9d636751	358	__O uint32_t TASKS_BCSTOP; /!< Stop the bit counter. /
yihui	1:fc2f9d636751	359	__I uint32_t RESERVED0[55];
yihui	1:fc2f9d636751	360	__IO uint32_t EVENTS_READY; /!< Ready event. /
yihui	1:fc2f9d636751	361	__IO uint32_t EVENTS_ADDRESS; /!< Address event. /
yihui	1:fc2f9d636751	362	__IO uint32_t EVENTS_PAYLOAD; /!< Payload event. /
yihui	1:fc2f9d636751	363	__IO uint32_t EVENTS_END; /!< End event. /
yihui	1:fc2f9d636751	364	__IO uint32_t EVENTS_DISABLED; /!< Disable event. /
yihui	1:fc2f9d636751	365	__IO uint32_t EVENTS_DEVMATCH; /!< A device address match occurred on the last received packet. /
yihui	1:fc2f9d636751	366	__IO uint32_t EVENTS_DEVMISS; /!< No device address match occurred on the last received packet. /
yihui	1:fc2f9d636751	367	__IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
yihui	1:fc2f9d636751	368	sample is ready for readout at the RSSISAMPLE register. */
yihui	1:fc2f9d636751	369	__I uint32_t RESERVED1[2];
yihui	1:fc2f9d636751	370	__IO uint32_t EVENTS_BCMATCH; /!< Bit counter reached bit count value specified in BC register. /
yihui	1:fc2f9d636751	371	__I uint32_t RESERVED2[53];
yihui	1:fc2f9d636751	372	__IO uint32_t SHORTS; /!< Shortcuts for the radio. /
yihui	1:fc2f9d636751	373	__I uint32_t RESERVED3[64];
yihui	1:fc2f9d636751	374	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	375	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	376	__I uint32_t RESERVED4[61];
yihui	1:fc2f9d636751	377	__I uint32_t CRCSTATUS; /!< CRC status of received packet. /
yihui	1:fc2f9d636751	378	__I uint32_t CD; /!< Carrier detect. /
yihui	1:fc2f9d636751	379	__I uint32_t RXMATCH; /!< Received address. /
yihui	1:fc2f9d636751	380	__I uint32_t RXCRC; /!< Received CRC. /
yihui	1:fc2f9d636751	381	__I uint32_t DAI; /!< Device address match index. /
yihui	1:fc2f9d636751	382	__I uint32_t RESERVED5[60];
yihui	1:fc2f9d636751	383	__IO uint32_t PACKETPTR; /!< Packet pointer. Decision point: START task. /
yihui	1:fc2f9d636751	384	__IO uint32_t FREQUENCY; /!< Frequency. /
yihui	1:fc2f9d636751	385	__IO uint32_t TXPOWER; /!< Output power. /
yihui	1:fc2f9d636751	386	__IO uint32_t MODE; /!< Data rate and modulation. /
yihui	1:fc2f9d636751	387	__IO uint32_t PCNF0; /!< Packet configuration 0. /
yihui	1:fc2f9d636751	388	__IO uint32_t PCNF1; /!< Packet configuration 1. /
yihui	1:fc2f9d636751	389	__IO uint32_t BASE0; /!< Radio base address 0. Decision point: START task. /
yihui	1:fc2f9d636751	390	__IO uint32_t BASE1; /!< Radio base address 1. Decision point: START task. /
yihui	1:fc2f9d636751	391	__IO uint32_t PREFIX0; /!< Prefixes bytes for logical addresses 0 to 3. /
yihui	1:fc2f9d636751	392	__IO uint32_t PREFIX1; /!< Prefixes bytes for logical addresses 4 to 7. /
yihui	1:fc2f9d636751	393	__IO uint32_t TXADDRESS; /!< Transmit address select. /
yihui	1:fc2f9d636751	394	__IO uint32_t RXADDRESSES; /!< Receive address select. /
yihui	1:fc2f9d636751	395	__IO uint32_t CRCCNF; /!< CRC configuration. /
yihui	1:fc2f9d636751	396	__IO uint32_t CRCPOLY; /!< CRC polynomial. /
yihui	1:fc2f9d636751	397	__IO uint32_t CRCINIT; /!< CRC initial value. /
yihui	1:fc2f9d636751	398	__IO uint32_t TEST; /!< Test features enable register. /
yihui	1:fc2f9d636751	399	__IO uint32_t TIFS; /!< Inter Frame Spacing in microseconds. /
yihui	1:fc2f9d636751	400	__I uint32_t RSSISAMPLE; /!< RSSI sample. /
yihui	1:fc2f9d636751	401	__I uint32_t RESERVED6;
yihui	1:fc2f9d636751	402	__I uint32_t STATE; /!< Current radio state. /
yihui	1:fc2f9d636751	403	__IO uint32_t DATAWHITEIV; /!< Data whitening initial value. /
yihui	1:fc2f9d636751	404	__I uint32_t RESERVED7[2];
yihui	1:fc2f9d636751	405	__IO uint32_t BCC; /!< Bit counter compare. /
yihui	1:fc2f9d636751	406	__I uint32_t RESERVED8[39];
yihui	1:fc2f9d636751	407	__IO uint32_t DAB[8]; /!< Device address base segment. /
yihui	1:fc2f9d636751	408	__IO uint32_t DAP[8]; /!< Device address prefix. /
yihui	1:fc2f9d636751	409	__IO uint32_t DACNF; /!< Device address match configuration. /
yihui	1:fc2f9d636751	410	__I uint32_t RESERVED9[56];
yihui	1:fc2f9d636751	411	__IO uint32_t OVERRIDE0; /!< Trim value override register 0. /
yihui	1:fc2f9d636751	412	__IO uint32_t OVERRIDE1; /!< Trim value override register 1. /
yihui	1:fc2f9d636751	413	__IO uint32_t OVERRIDE2; /!< Trim value override register 2. /
yihui	1:fc2f9d636751	414	__IO uint32_t OVERRIDE3; /!< Trim value override register 3. /
yihui	1:fc2f9d636751	415	__IO uint32_t OVERRIDE4; /!< Trim value override register 4. /
yihui	1:fc2f9d636751	416	__I uint32_t RESERVED10[561];
yihui	1:fc2f9d636751	417	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	418	} NRF_RADIO_Type;
yihui	1:fc2f9d636751	419
yihui	1:fc2f9d636751	420
yihui	1:fc2f9d636751	421	/* ================================================================================ */
yihui	1:fc2f9d636751	422	/* ================ UART ================ */
yihui	1:fc2f9d636751	423	/* ================================================================================ */
yihui	1:fc2f9d636751	424
yihui	1:fc2f9d636751	425
yihui	1:fc2f9d636751	426	/**
yihui	1:fc2f9d636751	427	* @brief Universal Asynchronous Receiver/Transmitter. (UART)
yihui	1:fc2f9d636751	428	*/
yihui	1:fc2f9d636751	429
yihui	1:fc2f9d636751	430	typedef struct { /!< UART Structure /
yihui	1:fc2f9d636751	431	__O uint32_t TASKS_STARTRX; /!< Start UART receiver. /
yihui	1:fc2f9d636751	432	__O uint32_t TASKS_STOPRX; /!< Stop UART receiver. /
yihui	1:fc2f9d636751	433	__O uint32_t TASKS_STARTTX; /!< Start UART transmitter. /
yihui	1:fc2f9d636751	434	__O uint32_t TASKS_STOPTX; /!< Stop UART transmitter. /
yihui	1:fc2f9d636751	435	__I uint32_t RESERVED0[3];
yihui	1:fc2f9d636751	436	__O uint32_t TASKS_SUSPEND; /!< Suspend UART. /
yihui	1:fc2f9d636751	437	__I uint32_t RESERVED1[56];
yihui	1:fc2f9d636751	438	__IO uint32_t EVENTS_CTS; /!< CTS activated. /
yihui	1:fc2f9d636751	439	__IO uint32_t EVENTS_NCTS; /!< CTS deactivated. /
yihui	1:fc2f9d636751	440	__IO uint32_t EVENTS_RXDRDY; /!< Data received in RXD. /
yihui	1:fc2f9d636751	441	__I uint32_t RESERVED2[4];
yihui	1:fc2f9d636751	442	__IO uint32_t EVENTS_TXDRDY; /!< Data sent from TXD. /
yihui	1:fc2f9d636751	443	__I uint32_t RESERVED3;
yihui	1:fc2f9d636751	444	__IO uint32_t EVENTS_ERROR; /!< Error detected. /
yihui	1:fc2f9d636751	445	__I uint32_t RESERVED4[7];
yihui	1:fc2f9d636751	446	__IO uint32_t EVENTS_RXTO; /!< Receiver timeout. /
yihui	1:fc2f9d636751	447	__I uint32_t RESERVED5[46];
yihui	1:fc2f9d636751	448	__IO uint32_t SHORTS; /!< Shortcuts for UART. /
yihui	1:fc2f9d636751	449	__I uint32_t RESERVED6[64];
yihui	1:fc2f9d636751	450	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	451	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	452	__I uint32_t RESERVED7[93];
yihui	1:fc2f9d636751	453	__IO uint32_t ERRORSRC; /!< Error source. Write error field to 1 to clear error. /
yihui	1:fc2f9d636751	454	__I uint32_t RESERVED8[31];
yihui	1:fc2f9d636751	455	__IO uint32_t ENABLE; /!< Enable UART and acquire IOs. /
yihui	1:fc2f9d636751	456	__I uint32_t RESERVED9;
yihui	1:fc2f9d636751	457	__IO uint32_t PSELRTS; /!< Pin select for RTS. /
yihui	1:fc2f9d636751	458	__IO uint32_t PSELTXD; /!< Pin select for TXD. /
yihui	1:fc2f9d636751	459	__IO uint32_t PSELCTS; /!< Pin select for CTS. /
yihui	1:fc2f9d636751	460	__IO uint32_t PSELRXD; /!< Pin select for RXD. /
yihui	1:fc2f9d636751	461	__I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
yihui	1:fc2f9d636751	462	Once read the character is consumed. If read when no character
yihui	1:fc2f9d636751	463	available, the UART will stop working. */
yihui	1:fc2f9d636751	464	__O uint32_t TXD; /!< TXD register. /
yihui	1:fc2f9d636751	465	__I uint32_t RESERVED10;
yihui	1:fc2f9d636751	466	__IO uint32_t BAUDRATE; /!< UART Baudrate. /
yihui	1:fc2f9d636751	467	__I uint32_t RESERVED11[17];
yihui	1:fc2f9d636751	468	__IO uint32_t CONFIG; /!< Configuration of parity and hardware flow control register. /
yihui	1:fc2f9d636751	469	__I uint32_t RESERVED12[675];
yihui	1:fc2f9d636751	470	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	471	} NRF_UART_Type;
yihui	1:fc2f9d636751	472
yihui	1:fc2f9d636751	473
yihui	1:fc2f9d636751	474	/* ================================================================================ */
yihui	1:fc2f9d636751	475	/* ================ SPI ================ */
yihui	1:fc2f9d636751	476	/* ================================================================================ */
yihui	1:fc2f9d636751	477
yihui	1:fc2f9d636751	478
yihui	1:fc2f9d636751	479	/**
yihui	1:fc2f9d636751	480	* @brief SPI master 0. (SPI)
yihui	1:fc2f9d636751	481	*/
yihui	1:fc2f9d636751	482
yihui	1:fc2f9d636751	483	typedef struct { /!< SPI Structure /
yihui	1:fc2f9d636751	484	__I uint32_t RESERVED0[66];
yihui	1:fc2f9d636751	485	__IO uint32_t EVENTS_READY; /!< TXD byte sent and RXD byte received. /
yihui	1:fc2f9d636751	486	__I uint32_t RESERVED1[126];
yihui	1:fc2f9d636751	487	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	488	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	489	__I uint32_t RESERVED2[125];
yihui	1:fc2f9d636751	490	__IO uint32_t ENABLE; /!< Enable SPI. /
yihui	1:fc2f9d636751	491	__I uint32_t RESERVED3;
yihui	1:fc2f9d636751	492	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
yihui	1:fc2f9d636751	493	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
yihui	1:fc2f9d636751	494	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
yihui	1:fc2f9d636751	495	__I uint32_t RESERVED4;
yihui	1:fc2f9d636751	496	__I uint32_t RXD; /!< RX data. /
yihui	1:fc2f9d636751	497	__IO uint32_t TXD; /!< TX data. /
yihui	1:fc2f9d636751	498	__I uint32_t RESERVED5;
yihui	1:fc2f9d636751	499	__IO uint32_t FREQUENCY; /!< SPI frequency /
yihui	1:fc2f9d636751	500	__I uint32_t RESERVED6[11];
yihui	1:fc2f9d636751	501	__IO uint32_t CONFIG; /!< Configuration register. /
yihui	1:fc2f9d636751	502	__I uint32_t RESERVED7[681];
yihui	1:fc2f9d636751	503	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	504	} NRF_SPI_Type;
yihui	1:fc2f9d636751	505
yihui	1:fc2f9d636751	506
yihui	1:fc2f9d636751	507	/* ================================================================================ */
yihui	1:fc2f9d636751	508	/* ================ TWI ================ */
yihui	1:fc2f9d636751	509	/* ================================================================================ */
yihui	1:fc2f9d636751	510
yihui	1:fc2f9d636751	511
yihui	1:fc2f9d636751	512	/**
yihui	1:fc2f9d636751	513	* @brief Two-wire interface master 0. (TWI)
yihui	1:fc2f9d636751	514	*/
yihui	1:fc2f9d636751	515
yihui	1:fc2f9d636751	516	typedef struct { /!< TWI Structure /
yihui	1:fc2f9d636751	517	__O uint32_t TASKS_STARTRX; /!< Start 2-Wire master receive sequence. /
yihui	1:fc2f9d636751	518	__I uint32_t RESERVED0;
yihui	1:fc2f9d636751	519	__O uint32_t TASKS_STARTTX; /!< Start 2-Wire master transmit sequence. /
yihui	1:fc2f9d636751	520	__I uint32_t RESERVED1[2];
yihui	1:fc2f9d636751	521	__O uint32_t TASKS_STOP; /!< Stop 2-Wire transaction. /
yihui	1:fc2f9d636751	522	__I uint32_t RESERVED2;
yihui	1:fc2f9d636751	523	__O uint32_t TASKS_SUSPEND; /!< Suspend 2-Wire transaction. /
yihui	1:fc2f9d636751	524	__O uint32_t TASKS_RESUME; /!< Resume 2-Wire transaction. /
yihui	1:fc2f9d636751	525	__I uint32_t RESERVED3[56];
yihui	1:fc2f9d636751	526	__IO uint32_t EVENTS_STOPPED; /!< Two-wire stopped. /
yihui	1:fc2f9d636751	527	__IO uint32_t EVENTS_RXDREADY; /!< Two-wire ready to deliver new RXD byte received. /
yihui	1:fc2f9d636751	528	__I uint32_t RESERVED4[4];
yihui	1:fc2f9d636751	529	__IO uint32_t EVENTS_TXDSENT; /!< Two-wire finished sending last TXD byte. /
yihui	1:fc2f9d636751	530	__I uint32_t RESERVED5;
yihui	1:fc2f9d636751	531	__IO uint32_t EVENTS_ERROR; /!< Two-wire error detected. /
yihui	1:fc2f9d636751	532	__I uint32_t RESERVED6[4];
yihui	1:fc2f9d636751	533	__IO uint32_t EVENTS_BB; /!< Two-wire byte boundary. /
yihui	1:fc2f9d636751	534	__I uint32_t RESERVED7[3];
yihui	1:fc2f9d636751	535	__IO uint32_t EVENTS_SUSPENDED; /!< Two-wire suspended. /
yihui	1:fc2f9d636751	536	__I uint32_t RESERVED8[45];
yihui	1:fc2f9d636751	537	__IO uint32_t SHORTS; /!< Shortcuts for TWI. /
yihui	1:fc2f9d636751	538	__I uint32_t RESERVED9[64];
yihui	1:fc2f9d636751	539	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	540	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	541	__I uint32_t RESERVED10[110];
yihui	1:fc2f9d636751	542	__IO uint32_t ERRORSRC; /!< Two-wire error source. Write error field to 1 to clear error. /
yihui	1:fc2f9d636751	543	__I uint32_t RESERVED11[14];
yihui	1:fc2f9d636751	544	__IO uint32_t ENABLE; /!< Enable two-wire master. /
yihui	1:fc2f9d636751	545	__I uint32_t RESERVED12;
yihui	1:fc2f9d636751	546	__IO uint32_t PSELSCL; /!< Pin select for SCL. /
yihui	1:fc2f9d636751	547	__IO uint32_t PSELSDA; /!< Pin select for SDA. /
yihui	1:fc2f9d636751	548	__I uint32_t RESERVED13[2];
yihui	1:fc2f9d636751	549	__I uint32_t RXD; /!< RX data register. /
yihui	1:fc2f9d636751	550	__IO uint32_t TXD; /!< TX data register. /
yihui	1:fc2f9d636751	551	__I uint32_t RESERVED14;
yihui	1:fc2f9d636751	552	__IO uint32_t FREQUENCY; /!< Two-wire frequency. /
yihui	1:fc2f9d636751	553	__I uint32_t RESERVED15[24];
yihui	1:fc2f9d636751	554	__IO uint32_t ADDRESS; /!< Address used in the two-wire transfer. /
yihui	1:fc2f9d636751	555	__I uint32_t RESERVED16[668];
yihui	1:fc2f9d636751	556	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	557	} NRF_TWI_Type;
yihui	1:fc2f9d636751	558
yihui	1:fc2f9d636751	559
yihui	1:fc2f9d636751	560	/* ================================================================================ */
yihui	1:fc2f9d636751	561	/* ================ SPIS ================ */
yihui	1:fc2f9d636751	562	/* ================================================================================ */
yihui	1:fc2f9d636751	563
yihui	1:fc2f9d636751	564
yihui	1:fc2f9d636751	565	/**
yihui	1:fc2f9d636751	566	* @brief SPI slave 1. (SPIS)
yihui	1:fc2f9d636751	567	*/
yihui	1:fc2f9d636751	568
yihui	1:fc2f9d636751	569	typedef struct { /!< SPIS Structure /
yihui	1:fc2f9d636751	570	__I uint32_t RESERVED0[9];
yihui	1:fc2f9d636751	571	__O uint32_t TASKS_ACQUIRE; /!< Acquire SPI semaphore. /
yihui	1:fc2f9d636751	572	__O uint32_t TASKS_RELEASE; /!< Release SPI semaphore. /
yihui	1:fc2f9d636751	573	__I uint32_t RESERVED1[54];
yihui	1:fc2f9d636751	574	__IO uint32_t EVENTS_END; /!< Granted transaction completed. /
yihui	1:fc2f9d636751	575	__I uint32_t RESERVED2[8];
yihui	1:fc2f9d636751	576	__IO uint32_t EVENTS_ACQUIRED; /!< Semaphore acquired. /
yihui	1:fc2f9d636751	577	__I uint32_t RESERVED3[53];
yihui	1:fc2f9d636751	578	__IO uint32_t SHORTS; /!< Shortcuts for SPIS. /
yihui	1:fc2f9d636751	579	__I uint32_t RESERVED4[64];
yihui	1:fc2f9d636751	580	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	581	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	582	__I uint32_t RESERVED5[61];
yihui	1:fc2f9d636751	583	__I uint32_t SEMSTAT; /!< Semaphore status. /
yihui	1:fc2f9d636751	584	__I uint32_t RESERVED6[15];
yihui	1:fc2f9d636751	585	__IO uint32_t STATUS; /!< Status from last transaction. /
yihui	1:fc2f9d636751	586	__I uint32_t RESERVED7[47];
yihui	1:fc2f9d636751	587	__IO uint32_t ENABLE; /!< Enable SPIS. /
yihui	1:fc2f9d636751	588	__I uint32_t RESERVED8;
yihui	1:fc2f9d636751	589	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
yihui	1:fc2f9d636751	590	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
yihui	1:fc2f9d636751	591	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
yihui	1:fc2f9d636751	592	__IO uint32_t PSELCSN; /!< Pin select for CSN. /
yihui	1:fc2f9d636751	593	__I uint32_t RESERVED9[7];
yihui	1:fc2f9d636751	594	__IO uint32_t RXDPTR; /!< RX data pointer. /
yihui	1:fc2f9d636751	595	__IO uint32_t MAXRX; /!< Maximum number of bytes in the receive buffer. /
yihui	1:fc2f9d636751	596	__I uint32_t AMOUNTRX; /!< Number of bytes received in last granted transaction. /
yihui	1:fc2f9d636751	597	__I uint32_t RESERVED10;
yihui	1:fc2f9d636751	598	__IO uint32_t TXDPTR; /!< TX data pointer. /
yihui	1:fc2f9d636751	599	__IO uint32_t MAXTX; /!< Maximum number of bytes in the transmit buffer. /
yihui	1:fc2f9d636751	600	__I uint32_t AMOUNTTX; /!< Number of bytes transmitted in last granted transaction. /
yihui	1:fc2f9d636751	601	__I uint32_t RESERVED11;
yihui	1:fc2f9d636751	602	__IO uint32_t CONFIG; /!< Configuration register. /
yihui	1:fc2f9d636751	603	__I uint32_t RESERVED12;
yihui	1:fc2f9d636751	604	__IO uint32_t DEF; /!< Default character. /
yihui	1:fc2f9d636751	605	__I uint32_t RESERVED13[24];
yihui	1:fc2f9d636751	606	__IO uint32_t ORC; /!< Over-read character. /
yihui	1:fc2f9d636751	607	__I uint32_t RESERVED14[654];
yihui	1:fc2f9d636751	608	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	609	} NRF_SPIS_Type;
yihui	1:fc2f9d636751	610
yihui	1:fc2f9d636751	611
yihui	1:fc2f9d636751	612	/* ================================================================================ */
yihui	1:fc2f9d636751	613	/* ================ SPIM ================ */
yihui	1:fc2f9d636751	614	/* ================================================================================ */
yihui	1:fc2f9d636751	615
yihui	1:fc2f9d636751	616
yihui	1:fc2f9d636751	617	/**
yihui	1:fc2f9d636751	618	* @brief SPI master with easyDMA 1. (SPIM)
yihui	1:fc2f9d636751	619	*/
yihui	1:fc2f9d636751	620
yihui	1:fc2f9d636751	621	typedef struct { /!< SPIM Structure /
yihui	1:fc2f9d636751	622	__I uint32_t RESERVED0[4];
yihui	1:fc2f9d636751	623	__O uint32_t TASKS_START; /!< Start SPI transaction. /
yihui	1:fc2f9d636751	624	__O uint32_t TASKS_STOP; /!< Stop SPI transaction. /
yihui	1:fc2f9d636751	625	__I uint32_t RESERVED1;
yihui	1:fc2f9d636751	626	__O uint32_t TASKS_SUSPEND; /!< Suspend SPI transaction. /
yihui	1:fc2f9d636751	627	__O uint32_t TASKS_RESUME; /!< Resume SPI transaction. /
yihui	1:fc2f9d636751	628	__I uint32_t RESERVED2[56];
yihui	1:fc2f9d636751	629	__IO uint32_t EVENTS_STOPPED; /!< SPI transaction has stopped. /
yihui	1:fc2f9d636751	630	__I uint32_t RESERVED3[2];
yihui	1:fc2f9d636751	631	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached. /
yihui	1:fc2f9d636751	632	__I uint32_t RESERVED4;
yihui	1:fc2f9d636751	633	__IO uint32_t EVENTS_END; /!< End of RXD buffer and TXD buffer reached. /
yihui	1:fc2f9d636751	634	__I uint32_t RESERVED5;
yihui	1:fc2f9d636751	635	__IO uint32_t EVENTS_ENDTX; /!< End of TXD buffer reached. /
yihui	1:fc2f9d636751	636	__I uint32_t RESERVED6[10];
yihui	1:fc2f9d636751	637	__IO uint32_t EVENTS_STARTED; /!< Transaction started. /
yihui	1:fc2f9d636751	638	__I uint32_t RESERVED7[44];
yihui	1:fc2f9d636751	639	__IO uint32_t SHORTS; /!< Shortcuts for SPIM. /
yihui	1:fc2f9d636751	640	__I uint32_t RESERVED8[64];
yihui	1:fc2f9d636751	641	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	642	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	643	__I uint32_t RESERVED9[125];
yihui	1:fc2f9d636751	644	__IO uint32_t ENABLE; /!< Enable SPIM. /
yihui	1:fc2f9d636751	645	__I uint32_t RESERVED10;
yihui	1:fc2f9d636751	646	SPIM_PSEL_Type PSEL; /!< Pin select configuration. /
yihui	1:fc2f9d636751	647	__I uint32_t RESERVED11;
yihui	1:fc2f9d636751	648	__I uint32_t RXDDATA; /!< RXD register. /
yihui	1:fc2f9d636751	649	__IO uint32_t TXDDATA; /!< TXD register. /
yihui	1:fc2f9d636751	650	__I uint32_t RESERVED12;
yihui	1:fc2f9d636751	651	__IO uint32_t FREQUENCY; /!< SPI frequency. /
yihui	1:fc2f9d636751	652	__I uint32_t RESERVED13[3];
yihui	1:fc2f9d636751	653	SPIM_RXD_Type RXD; /!< RXD EasyDMA configuration and status. /
yihui	1:fc2f9d636751	654	__I uint32_t RESERVED14;
yihui	1:fc2f9d636751	655	SPIM_TXD_Type TXD; /!< TXD EasyDMA configuration and status. /
yihui	1:fc2f9d636751	656	__I uint32_t RESERVED15;
yihui	1:fc2f9d636751	657	__IO uint32_t CONFIG; /!< Configuration register. /
yihui	1:fc2f9d636751	658	__I uint32_t RESERVED16[26];
yihui	1:fc2f9d636751	659	__IO uint32_t ORC; /!< Over-read character. /
yihui	1:fc2f9d636751	660	__I uint32_t RESERVED17[654];
yihui	1:fc2f9d636751	661	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	662	} NRF_SPIM_Type;
yihui	1:fc2f9d636751	663
yihui	1:fc2f9d636751	664
yihui	1:fc2f9d636751	665	/* ================================================================================ */
yihui	1:fc2f9d636751	666	/* ================ GPIOTE ================ */
yihui	1:fc2f9d636751	667	/* ================================================================================ */
yihui	1:fc2f9d636751	668
yihui	1:fc2f9d636751	669
yihui	1:fc2f9d636751	670	/**
yihui	1:fc2f9d636751	671	* @brief GPIO tasks and events. (GPIOTE)
yihui	1:fc2f9d636751	672	*/
yihui	1:fc2f9d636751	673
yihui	1:fc2f9d636751	674	typedef struct { /!< GPIOTE Structure /
yihui	1:fc2f9d636751	675	__O uint32_t TASKS_OUT[4]; /!< Tasks asssociated with GPIOTE channels. /
yihui	1:fc2f9d636751	676	__I uint32_t RESERVED0[60];
yihui	1:fc2f9d636751	677	__IO uint32_t EVENTS_IN[4]; /!< Tasks asssociated with GPIOTE channels. /
yihui	1:fc2f9d636751	678	__I uint32_t RESERVED1[27];
yihui	1:fc2f9d636751	679	__IO uint32_t EVENTS_PORT; /!< Event generated from multiple pins. /
yihui	1:fc2f9d636751	680	__I uint32_t RESERVED2[97];
yihui	1:fc2f9d636751	681	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	682	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	683	__I uint32_t RESERVED3[129];
yihui	1:fc2f9d636751	684	__IO uint32_t CONFIG[4]; /!< Channel configuration registers. /
yihui	1:fc2f9d636751	685	__I uint32_t RESERVED4[695];
yihui	1:fc2f9d636751	686	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	687	} NRF_GPIOTE_Type;
yihui	1:fc2f9d636751	688
yihui	1:fc2f9d636751	689
yihui	1:fc2f9d636751	690	/* ================================================================================ */
yihui	1:fc2f9d636751	691	/* ================ ADC ================ */
yihui	1:fc2f9d636751	692	/* ================================================================================ */
yihui	1:fc2f9d636751	693
yihui	1:fc2f9d636751	694
yihui	1:fc2f9d636751	695	/**
yihui	1:fc2f9d636751	696	* @brief Analog to digital converter. (ADC)
yihui	1:fc2f9d636751	697	*/
yihui	1:fc2f9d636751	698
yihui	1:fc2f9d636751	699	typedef struct { /!< ADC Structure /
yihui	1:fc2f9d636751	700	__O uint32_t TASKS_START; /!< Start an ADC conversion. /
yihui	1:fc2f9d636751	701	__O uint32_t TASKS_STOP; /!< Stop ADC. /
yihui	1:fc2f9d636751	702	__I uint32_t RESERVED0[62];
yihui	1:fc2f9d636751	703	__IO uint32_t EVENTS_END; /!< ADC conversion complete. /
yihui	1:fc2f9d636751	704	__I uint32_t RESERVED1[128];
yihui	1:fc2f9d636751	705	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	706	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	707	__I uint32_t RESERVED2[61];
yihui	1:fc2f9d636751	708	__I uint32_t BUSY; /!< ADC busy register. /
yihui	1:fc2f9d636751	709	__I uint32_t RESERVED3[63];
yihui	1:fc2f9d636751	710	__IO uint32_t ENABLE; /!< ADC enable. /
yihui	1:fc2f9d636751	711	__IO uint32_t CONFIG; /!< ADC configuration register. /
yihui	1:fc2f9d636751	712	__I uint32_t RESULT; /!< Result of ADC conversion. /
yihui	1:fc2f9d636751	713	__I uint32_t RESERVED4[700];
yihui	1:fc2f9d636751	714	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	715	} NRF_ADC_Type;
yihui	1:fc2f9d636751	716
yihui	1:fc2f9d636751	717
yihui	1:fc2f9d636751	718	/* ================================================================================ */
yihui	1:fc2f9d636751	719	/* ================ TIMER ================ */
yihui	1:fc2f9d636751	720	/* ================================================================================ */
yihui	1:fc2f9d636751	721
yihui	1:fc2f9d636751	722
yihui	1:fc2f9d636751	723	/**
yihui	1:fc2f9d636751	724	* @brief Timer 0. (TIMER)
yihui	1:fc2f9d636751	725	*/
yihui	1:fc2f9d636751	726
yihui	1:fc2f9d636751	727	typedef struct { /!< TIMER Structure /
yihui	1:fc2f9d636751	728	__O uint32_t TASKS_START; /!< Start Timer. /
yihui	1:fc2f9d636751	729	__O uint32_t TASKS_STOP; /!< Stop Timer. /
yihui	1:fc2f9d636751	730	__O uint32_t TASKS_COUNT; /!< Increment Timer (In counter mode). /
yihui	1:fc2f9d636751	731	__O uint32_t TASKS_CLEAR; /!< Clear timer. /
yihui	1:fc2f9d636751	732	__O uint32_t TASKS_SHUTDOWN; /!< Shutdown timer. /
yihui	1:fc2f9d636751	733	__I uint32_t RESERVED0[11];
yihui	1:fc2f9d636751	734	__O uint32_t TASKS_CAPTURE[4]; /!< Capture Timer value to CC[n] registers. /
yihui	1:fc2f9d636751	735	__I uint32_t RESERVED1[60];
yihui	1:fc2f9d636751	736	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
yihui	1:fc2f9d636751	737	__I uint32_t RESERVED2[44];
yihui	1:fc2f9d636751	738	__IO uint32_t SHORTS; /!< Shortcuts for Timer. /
yihui	1:fc2f9d636751	739	__I uint32_t RESERVED3[64];
yihui	1:fc2f9d636751	740	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	741	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	742	__I uint32_t RESERVED4[126];
yihui	1:fc2f9d636751	743	__IO uint32_t MODE; /!< Timer Mode selection. /
yihui	1:fc2f9d636751	744	__IO uint32_t BITMODE; /!< Sets timer behaviour. /
yihui	1:fc2f9d636751	745	__I uint32_t RESERVED5;
yihui	1:fc2f9d636751	746	__IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
yihui	1:fc2f9d636751	747	clock frequency is divided by 2^SCALE. */
yihui	1:fc2f9d636751	748	__I uint32_t RESERVED6[11];
yihui	1:fc2f9d636751	749	__IO uint32_t CC[4]; /!< Capture/compare registers. /
yihui	1:fc2f9d636751	750	__I uint32_t RESERVED7[683];
yihui	1:fc2f9d636751	751	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	752	} NRF_TIMER_Type;
yihui	1:fc2f9d636751	753
yihui	1:fc2f9d636751	754
yihui	1:fc2f9d636751	755	/* ================================================================================ */
yihui	1:fc2f9d636751	756	/* ================ RTC ================ */
yihui	1:fc2f9d636751	757	/* ================================================================================ */
yihui	1:fc2f9d636751	758
yihui	1:fc2f9d636751	759
yihui	1:fc2f9d636751	760	/**
yihui	1:fc2f9d636751	761	* @brief Real time counter 0. (RTC)
yihui	1:fc2f9d636751	762	*/
yihui	1:fc2f9d636751	763
yihui	1:fc2f9d636751	764	typedef struct { /!< RTC Structure /
yihui	1:fc2f9d636751	765	__O uint32_t TASKS_START; /!< Start RTC Counter. /
yihui	1:fc2f9d636751	766	__O uint32_t TASKS_STOP; /!< Stop RTC Counter. /
yihui	1:fc2f9d636751	767	__O uint32_t TASKS_CLEAR; /!< Clear RTC Counter. /
yihui	1:fc2f9d636751	768	__O uint32_t TASKS_TRIGOVRFLW; /!< Set COUNTER to 0xFFFFFFF0. /
yihui	1:fc2f9d636751	769	__I uint32_t RESERVED0[60];
yihui	1:fc2f9d636751	770	__IO uint32_t EVENTS_TICK; /!< Event on COUNTER increment. /
yihui	1:fc2f9d636751	771	__IO uint32_t EVENTS_OVRFLW; /!< Event on COUNTER overflow. /
yihui	1:fc2f9d636751	772	__I uint32_t RESERVED1[14];
yihui	1:fc2f9d636751	773	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
yihui	1:fc2f9d636751	774	__I uint32_t RESERVED2[109];
yihui	1:fc2f9d636751	775	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	776	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	777	__I uint32_t RESERVED3[13];
yihui	1:fc2f9d636751	778	__IO uint32_t EVTEN; /!< Configures event enable routing to PPI for each RTC event. /
yihui	1:fc2f9d636751	779	__IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
yihui	1:fc2f9d636751	780	the value of EVTEN. */
yihui	1:fc2f9d636751	781	__IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
yihui	1:fc2f9d636751	782	gives the value of EVTEN. */
yihui	1:fc2f9d636751	783	__I uint32_t RESERVED4[110];
yihui	1:fc2f9d636751	784	__I uint32_t COUNTER; /!< Current COUNTER value. /
yihui	1:fc2f9d636751	785	__IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
yihui	1:fc2f9d636751	786	Must be written when RTC is STOPed. */
yihui	1:fc2f9d636751	787	__I uint32_t RESERVED5[13];
yihui	1:fc2f9d636751	788	__IO uint32_t CC[4]; /!< Capture/compare registers. /
yihui	1:fc2f9d636751	789	__I uint32_t RESERVED6[683];
yihui	1:fc2f9d636751	790	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	791	} NRF_RTC_Type;
yihui	1:fc2f9d636751	792
yihui	1:fc2f9d636751	793
yihui	1:fc2f9d636751	794	/* ================================================================================ */
yihui	1:fc2f9d636751	795	/* ================ TEMP ================ */
yihui	1:fc2f9d636751	796	/* ================================================================================ */
yihui	1:fc2f9d636751	797
yihui	1:fc2f9d636751	798
yihui	1:fc2f9d636751	799	/**
yihui	1:fc2f9d636751	800	* @brief Temperature Sensor. (TEMP)
yihui	1:fc2f9d636751	801	*/
yihui	1:fc2f9d636751	802
yihui	1:fc2f9d636751	803	typedef struct { /!< TEMP Structure /
yihui	1:fc2f9d636751	804	__O uint32_t TASKS_START; /!< Start temperature measurement. /
yihui	1:fc2f9d636751	805	__O uint32_t TASKS_STOP; /!< Stop temperature measurement. /
yihui	1:fc2f9d636751	806	__I uint32_t RESERVED0[62];
yihui	1:fc2f9d636751	807	__IO uint32_t EVENTS_DATARDY; /!< Temperature measurement complete, data ready event. /
yihui	1:fc2f9d636751	808	__I uint32_t RESERVED1[128];
yihui	1:fc2f9d636751	809	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	810	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	811	__I uint32_t RESERVED2[127];
yihui	1:fc2f9d636751	812	__I int32_t TEMP; /!< Die temperature in degC, 2's complement format, 0.25 degC pecision. /
yihui	1:fc2f9d636751	813	__I uint32_t RESERVED3[700];
yihui	1:fc2f9d636751	814	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	815	} NRF_TEMP_Type;
yihui	1:fc2f9d636751	816
yihui	1:fc2f9d636751	817
yihui	1:fc2f9d636751	818	/* ================================================================================ */
yihui	1:fc2f9d636751	819	/* ================ RNG ================ */
yihui	1:fc2f9d636751	820	/* ================================================================================ */
yihui	1:fc2f9d636751	821
yihui	1:fc2f9d636751	822
yihui	1:fc2f9d636751	823	/**
yihui	1:fc2f9d636751	824	* @brief Random Number Generator. (RNG)
yihui	1:fc2f9d636751	825	*/
yihui	1:fc2f9d636751	826
yihui	1:fc2f9d636751	827	typedef struct { /!< RNG Structure /
yihui	1:fc2f9d636751	828	__O uint32_t TASKS_START; /!< Start the random number generator. /
yihui	1:fc2f9d636751	829	__O uint32_t TASKS_STOP; /!< Stop the random number generator. /
yihui	1:fc2f9d636751	830	__I uint32_t RESERVED0[62];
yihui	1:fc2f9d636751	831	__IO uint32_t EVENTS_VALRDY; /!< New random number generated and written to VALUE register. /
yihui	1:fc2f9d636751	832	__I uint32_t RESERVED1[63];
yihui	1:fc2f9d636751	833	__IO uint32_t SHORTS; /!< Shortcuts for the RNG. /
yihui	1:fc2f9d636751	834	__I uint32_t RESERVED2[64];
yihui	1:fc2f9d636751	835	__IO uint32_t INTENSET; /!< Interrupt enable set register /
yihui	1:fc2f9d636751	836	__IO uint32_t INTENCLR; /!< Interrupt enable clear register /
yihui	1:fc2f9d636751	837	__I uint32_t RESERVED3[126];
yihui	1:fc2f9d636751	838	__IO uint32_t CONFIG; /!< Configuration register. /
yihui	1:fc2f9d636751	839	__I uint32_t VALUE; /!< RNG random number. /
yihui	1:fc2f9d636751	840	__I uint32_t RESERVED4[700];
yihui	1:fc2f9d636751	841	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	842	} NRF_RNG_Type;
yihui	1:fc2f9d636751	843
yihui	1:fc2f9d636751	844
yihui	1:fc2f9d636751	845	/* ================================================================================ */
yihui	1:fc2f9d636751	846	/* ================ ECB ================ */
yihui	1:fc2f9d636751	847	/* ================================================================================ */
yihui	1:fc2f9d636751	848
yihui	1:fc2f9d636751	849
yihui	1:fc2f9d636751	850	/**
yihui	1:fc2f9d636751	851	* @brief AES ECB Mode Encryption. (ECB)
yihui	1:fc2f9d636751	852	*/
yihui	1:fc2f9d636751	853
yihui	1:fc2f9d636751	854	typedef struct { /!< ECB Structure /
yihui	1:fc2f9d636751	855	__O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
yihui	1:fc2f9d636751	856	will not initiate a new encryption and the ERRORECB event will
yihui	1:fc2f9d636751	857	be triggered. */
yihui	1:fc2f9d636751	858	__O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
yihui	1:fc2f9d636751	859	this will will trigger the ERRORECB event. */
yihui	1:fc2f9d636751	860	__I uint32_t RESERVED0[62];
yihui	1:fc2f9d636751	861	__IO uint32_t EVENTS_ENDECB; /!< ECB block encrypt complete. /
yihui	1:fc2f9d636751	862	__IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
yihui	1:fc2f9d636751	863	error. */
yihui	1:fc2f9d636751	864	__I uint32_t RESERVED1[127];
yihui	1:fc2f9d636751	865	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	866	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	867	__I uint32_t RESERVED2[126];
yihui	1:fc2f9d636751	868	__IO uint32_t ECBDATAPTR; /!< ECB block encrypt memory pointer. /
yihui	1:fc2f9d636751	869	__I uint32_t RESERVED3[701];
yihui	1:fc2f9d636751	870	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	871	} NRF_ECB_Type;
yihui	1:fc2f9d636751	872
yihui	1:fc2f9d636751	873
yihui	1:fc2f9d636751	874	/* ================================================================================ */
yihui	1:fc2f9d636751	875	/* ================ AAR ================ */
yihui	1:fc2f9d636751	876	/* ================================================================================ */
yihui	1:fc2f9d636751	877
yihui	1:fc2f9d636751	878
yihui	1:fc2f9d636751	879	/**
yihui	1:fc2f9d636751	880	* @brief Accelerated Address Resolver. (AAR)
yihui	1:fc2f9d636751	881	*/
yihui	1:fc2f9d636751	882
yihui	1:fc2f9d636751	883	typedef struct { /!< AAR Structure /
yihui	1:fc2f9d636751	884	__O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
yihui	1:fc2f9d636751	885	data structure. */
yihui	1:fc2f9d636751	886	__I uint32_t RESERVED0;
yihui	1:fc2f9d636751	887	__O uint32_t TASKS_STOP; /!< Stop resolving addresses. /
yihui	1:fc2f9d636751	888	__I uint32_t RESERVED1[61];
yihui	1:fc2f9d636751	889	__IO uint32_t EVENTS_END; /!< Address resolution procedure completed. /
yihui	1:fc2f9d636751	890	__IO uint32_t EVENTS_RESOLVED; /!< Address resolved. /
yihui	1:fc2f9d636751	891	__IO uint32_t EVENTS_NOTRESOLVED; /!< Address not resolved. /
yihui	1:fc2f9d636751	892	__I uint32_t RESERVED2[126];
yihui	1:fc2f9d636751	893	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	894	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	895	__I uint32_t RESERVED3[61];
yihui	1:fc2f9d636751	896	__I uint32_t STATUS; /!< Resolution status. /
yihui	1:fc2f9d636751	897	__I uint32_t RESERVED4[63];
yihui	1:fc2f9d636751	898	__IO uint32_t ENABLE; /!< Enable AAR. /
yihui	1:fc2f9d636751	899	__IO uint32_t NIRK; /!< Number of Identity root Keys in the IRK data structure. /
yihui	1:fc2f9d636751	900	__IO uint32_t IRKPTR; /!< Pointer to the IRK data structure. /
yihui	1:fc2f9d636751	901	__I uint32_t RESERVED5;
yihui	1:fc2f9d636751	902	__IO uint32_t ADDRPTR; /!< Pointer to the resolvable address (6 bytes). /
yihui	1:fc2f9d636751	903	__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
yihui	1:fc2f9d636751	904	during resolution. A minimum of 3 bytes must be reserved. */
yihui	1:fc2f9d636751	905	__I uint32_t RESERVED6[697];
yihui	1:fc2f9d636751	906	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	907	} NRF_AAR_Type;
yihui	1:fc2f9d636751	908
yihui	1:fc2f9d636751	909
yihui	1:fc2f9d636751	910	/* ================================================================================ */
yihui	1:fc2f9d636751	911	/* ================ CCM ================ */
yihui	1:fc2f9d636751	912	/* ================================================================================ */
yihui	1:fc2f9d636751	913
yihui	1:fc2f9d636751	914
yihui	1:fc2f9d636751	915	/**
yihui	1:fc2f9d636751	916	* @brief AES CCM Mode Encryption. (CCM)
yihui	1:fc2f9d636751	917	*/
yihui	1:fc2f9d636751	918
yihui	1:fc2f9d636751	919	typedef struct { /!< CCM Structure /
yihui	1:fc2f9d636751	920	__O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
yihui	1:fc2f9d636751	921	itself when completed. */
yihui	1:fc2f9d636751	922	__O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
yihui	1:fc2f9d636751	923	completed. */
yihui	1:fc2f9d636751	924	__O uint32_t TASKS_STOP; /!< Stop encrypt/decrypt. /
yihui	1:fc2f9d636751	925	__I uint32_t RESERVED0[61];
yihui	1:fc2f9d636751	926	__IO uint32_t EVENTS_ENDKSGEN; /!< Keystream generation completed. /
yihui	1:fc2f9d636751	927	__IO uint32_t EVENTS_ENDCRYPT; /!< Encrypt/decrypt completed. /
yihui	1:fc2f9d636751	928	__IO uint32_t EVENTS_ERROR; /!< Error happened. /
yihui	1:fc2f9d636751	929	__I uint32_t RESERVED1[61];
yihui	1:fc2f9d636751	930	__IO uint32_t SHORTS; /!< Shortcuts for the CCM. /
yihui	1:fc2f9d636751	931	__I uint32_t RESERVED2[64];
yihui	1:fc2f9d636751	932	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	933	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	934	__I uint32_t RESERVED3[61];
yihui	1:fc2f9d636751	935	__I uint32_t MICSTATUS; /!< CCM RX MIC check result. /
yihui	1:fc2f9d636751	936	__I uint32_t RESERVED4[63];
yihui	1:fc2f9d636751	937	__IO uint32_t ENABLE; /!< CCM enable. /
yihui	1:fc2f9d636751	938	__IO uint32_t MODE; /!< Operation mode. /
yihui	1:fc2f9d636751	939	__IO uint32_t CNFPTR; /!< Pointer to a data structure holding AES key and NONCE vector. /
yihui	1:fc2f9d636751	940	__IO uint32_t INPTR; /!< Pointer to the input packet. /
yihui	1:fc2f9d636751	941	__IO uint32_t OUTPTR; /!< Pointer to the output packet. /
yihui	1:fc2f9d636751	942	__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
yihui	1:fc2f9d636751	943	during resolution. A minimum of 43 bytes must be reserved. */
yihui	1:fc2f9d636751	944	__I uint32_t RESERVED5[697];
yihui	1:fc2f9d636751	945	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	946	} NRF_CCM_Type;
yihui	1:fc2f9d636751	947
yihui	1:fc2f9d636751	948
yihui	1:fc2f9d636751	949	/* ================================================================================ */
yihui	1:fc2f9d636751	950	/* ================ WDT ================ */
yihui	1:fc2f9d636751	951	/* ================================================================================ */
yihui	1:fc2f9d636751	952
yihui	1:fc2f9d636751	953
yihui	1:fc2f9d636751	954	/**
yihui	1:fc2f9d636751	955	* @brief Watchdog Timer. (WDT)
yihui	1:fc2f9d636751	956	*/
yihui	1:fc2f9d636751	957
yihui	1:fc2f9d636751	958	typedef struct { /!< WDT Structure /
yihui	1:fc2f9d636751	959	__O uint32_t TASKS_START; /!< Start the watchdog. /
yihui	1:fc2f9d636751	960	__I uint32_t RESERVED0[63];
yihui	1:fc2f9d636751	961	__IO uint32_t EVENTS_TIMEOUT; /!< Watchdog timeout. /
yihui	1:fc2f9d636751	962	__I uint32_t RESERVED1[128];
yihui	1:fc2f9d636751	963	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	964	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	965	__I uint32_t RESERVED2[61];
yihui	1:fc2f9d636751	966	__I uint32_t RUNSTATUS; /!< Watchdog running status. /
yihui	1:fc2f9d636751	967	__I uint32_t REQSTATUS; /!< Request status. /
yihui	1:fc2f9d636751	968	__I uint32_t RESERVED3[63];
yihui	1:fc2f9d636751	969	__IO uint32_t CRV; /!< Counter reload value in number of 32kiHz clock cycles. /
yihui	1:fc2f9d636751	970	__IO uint32_t RREN; /!< Reload request enable. /
yihui	1:fc2f9d636751	971	__IO uint32_t CONFIG; /!< Configuration register. /
yihui	1:fc2f9d636751	972	__I uint32_t RESERVED4[60];
yihui	1:fc2f9d636751	973	__O uint32_t RR[8]; /!< Reload requests registers. /
yihui	1:fc2f9d636751	974	__I uint32_t RESERVED5[631];
yihui	1:fc2f9d636751	975	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	976	} NRF_WDT_Type;
yihui	1:fc2f9d636751	977
yihui	1:fc2f9d636751	978
yihui	1:fc2f9d636751	979	/* ================================================================================ */
yihui	1:fc2f9d636751	980	/* ================ QDEC ================ */
yihui	1:fc2f9d636751	981	/* ================================================================================ */
yihui	1:fc2f9d636751	982
yihui	1:fc2f9d636751	983
yihui	1:fc2f9d636751	984	/**
yihui	1:fc2f9d636751	985	* @brief Rotary decoder. (QDEC)
yihui	1:fc2f9d636751	986	*/
yihui	1:fc2f9d636751	987
yihui	1:fc2f9d636751	988	typedef struct { /!< QDEC Structure /
yihui	1:fc2f9d636751	989	__O uint32_t TASKS_START; /!< Start the quadrature decoder. /
yihui	1:fc2f9d636751	990	__O uint32_t TASKS_STOP; /!< Stop the quadrature decoder. /
yihui	1:fc2f9d636751	991	__O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
yihui	1:fc2f9d636751	992	and clears the ACC registers. */
yihui	1:fc2f9d636751	993	__I uint32_t RESERVED0[61];
yihui	1:fc2f9d636751	994	__IO uint32_t EVENTS_SAMPLERDY; /!< A new sample is written to the sample register. /
yihui	1:fc2f9d636751	995	__IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
yihui	1:fc2f9d636751	996	ACC register different than zero. */
yihui	1:fc2f9d636751	997	__IO uint32_t EVENTS_ACCOF; /!< ACC or ACCDBL register overflow. /
yihui	1:fc2f9d636751	998	__I uint32_t RESERVED1[61];
yihui	1:fc2f9d636751	999	__IO uint32_t SHORTS; /!< Shortcuts for the QDEC. /
yihui	1:fc2f9d636751	1000	__I uint32_t RESERVED2[64];
yihui	1:fc2f9d636751	1001	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	1002	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	1003	__I uint32_t RESERVED3[125];
yihui	1:fc2f9d636751	1004	__IO uint32_t ENABLE; /!< Enable the QDEC. /
yihui	1:fc2f9d636751	1005	__IO uint32_t LEDPOL; /!< LED output pin polarity. /
yihui	1:fc2f9d636751	1006	__IO uint32_t SAMPLEPER; /!< Sample period. /
yihui	1:fc2f9d636751	1007	__I int32_t SAMPLE; /!< Motion sample value. /
yihui	1:fc2f9d636751	1008	__IO uint32_t REPORTPER; /!< Number of samples to generate an EVENT_REPORTRDY. /
yihui	1:fc2f9d636751	1009	__I int32_t ACC; /!< Accumulated valid transitions register. /
yihui	1:fc2f9d636751	1010	__I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
yihui	1:fc2f9d636751	1011	task. */
yihui	1:fc2f9d636751	1012	__IO uint32_t PSELLED; /!< Pin select for LED output. /
yihui	1:fc2f9d636751	1013	__IO uint32_t PSELA; /!< Pin select for phase A input. /
yihui	1:fc2f9d636751	1014	__IO uint32_t PSELB; /!< Pin select for phase B input. /
yihui	1:fc2f9d636751	1015	__IO uint32_t DBFEN; /!< Enable debouncer input filters. /
yihui	1:fc2f9d636751	1016	__I uint32_t RESERVED4[5];
yihui	1:fc2f9d636751	1017	__IO uint32_t LEDPRE; /!< Time LED is switched ON before the sample. /
yihui	1:fc2f9d636751	1018	__I uint32_t ACCDBL; /!< Accumulated double (error) transitions register. /
yihui	1:fc2f9d636751	1019	__I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
yihui	1:fc2f9d636751	1020	task. */
yihui	1:fc2f9d636751	1021	__I uint32_t RESERVED5[684];
yihui	1:fc2f9d636751	1022	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	1023	} NRF_QDEC_Type;
yihui	1:fc2f9d636751	1024
yihui	1:fc2f9d636751	1025
yihui	1:fc2f9d636751	1026	/* ================================================================================ */
yihui	1:fc2f9d636751	1027	/* ================ LPCOMP ================ */
yihui	1:fc2f9d636751	1028	/* ================================================================================ */
yihui	1:fc2f9d636751	1029
yihui	1:fc2f9d636751	1030
yihui	1:fc2f9d636751	1031	/**
yihui	1:fc2f9d636751	1032	* @brief Low power comparator. (LPCOMP)
yihui	1:fc2f9d636751	1033	*/
yihui	1:fc2f9d636751	1034
yihui	1:fc2f9d636751	1035	typedef struct { /!< LPCOMP Structure /
yihui	1:fc2f9d636751	1036	__O uint32_t TASKS_START; /!< Start the comparator. /
yihui	1:fc2f9d636751	1037	__O uint32_t TASKS_STOP; /!< Stop the comparator. /
yihui	1:fc2f9d636751	1038	__O uint32_t TASKS_SAMPLE; /!< Sample comparator value. /
yihui	1:fc2f9d636751	1039	__I uint32_t RESERVED0[61];
yihui	1:fc2f9d636751	1040	__IO uint32_t EVENTS_READY; /!< LPCOMP is ready and output is valid. /
yihui	1:fc2f9d636751	1041	__IO uint32_t EVENTS_DOWN; /!< Input voltage crossed the threshold going down. /
yihui	1:fc2f9d636751	1042	__IO uint32_t EVENTS_UP; /!< Input voltage crossed the threshold going up. /
yihui	1:fc2f9d636751	1043	__IO uint32_t EVENTS_CROSS; /!< Input voltage crossed the threshold in any direction. /
yihui	1:fc2f9d636751	1044	__I uint32_t RESERVED1[60];
yihui	1:fc2f9d636751	1045	__IO uint32_t SHORTS; /!< Shortcuts for the LPCOMP. /
yihui	1:fc2f9d636751	1046	__I uint32_t RESERVED2[64];
yihui	1:fc2f9d636751	1047	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
yihui	1:fc2f9d636751	1048	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
yihui	1:fc2f9d636751	1049	__I uint32_t RESERVED3[61];
yihui	1:fc2f9d636751	1050	__I uint32_t RESULT; /!< Result of last compare. /
yihui	1:fc2f9d636751	1051	__I uint32_t RESERVED4[63];
yihui	1:fc2f9d636751	1052	__IO uint32_t ENABLE; /!< Enable the LPCOMP. /
yihui	1:fc2f9d636751	1053	__IO uint32_t PSEL; /!< Input pin select. /
yihui	1:fc2f9d636751	1054	__IO uint32_t REFSEL; /!< Reference select. /
yihui	1:fc2f9d636751	1055	__IO uint32_t EXTREFSEL; /!< External reference select. /
yihui	1:fc2f9d636751	1056	__I uint32_t RESERVED5[4];
yihui	1:fc2f9d636751	1057	__IO uint32_t ANADETECT; /!< Analog detect configuration. /
yihui	1:fc2f9d636751	1058	__I uint32_t RESERVED6[694];
yihui	1:fc2f9d636751	1059	__IO uint32_t POWER; /!< Peripheral power control. /
yihui	1:fc2f9d636751	1060	} NRF_LPCOMP_Type;
yihui	1:fc2f9d636751	1061
yihui	1:fc2f9d636751	1062
yihui	1:fc2f9d636751	1063	/* ================================================================================ */
yihui	1:fc2f9d636751	1064	/* ================ SWI ================ */
yihui	1:fc2f9d636751	1065	/* ================================================================================ */
yihui	1:fc2f9d636751	1066
yihui	1:fc2f9d636751	1067
yihui	1:fc2f9d636751	1068	/**
yihui	1:fc2f9d636751	1069	* @brief SW Interrupts. (SWI)
yihui	1:fc2f9d636751	1070	*/
yihui	1:fc2f9d636751	1071
yihui	1:fc2f9d636751	1072	typedef struct { /!< SWI Structure /
yihui	1:fc2f9d636751	1073	__I uint32_t UNUSED; /!< Unused. /
yihui	1:fc2f9d636751	1074	} NRF_SWI_Type;
yihui	1:fc2f9d636751	1075
yihui	1:fc2f9d636751	1076
yihui	1:fc2f9d636751	1077	/* ================================================================================ */
yihui	1:fc2f9d636751	1078	/* ================ NVMC ================ */
yihui	1:fc2f9d636751	1079	/* ================================================================================ */
yihui	1:fc2f9d636751	1080
yihui	1:fc2f9d636751	1081
yihui	1:fc2f9d636751	1082	/**
yihui	1:fc2f9d636751	1083	* @brief Non Volatile Memory Controller. (NVMC)
yihui	1:fc2f9d636751	1084	*/
yihui	1:fc2f9d636751	1085
yihui	1:fc2f9d636751	1086	typedef struct { /!< NVMC Structure /
yihui	1:fc2f9d636751	1087	__I uint32_t RESERVED0[256];
yihui	1:fc2f9d636751	1088	__I uint32_t READY; /!< Ready flag. /
yihui	1:fc2f9d636751	1089	__I uint32_t RESERVED1[64];
yihui	1:fc2f9d636751	1090	__IO uint32_t CONFIG; /!< Configuration register. /
yihui	1:fc2f9d636751	1091	__IO uint32_t ERASEPAGE; /!< Register for erasing a non-protected non-volatile memory page. /
yihui	1:fc2f9d636751	1092	__IO uint32_t ERASEALL; /!< Register for erasing all non-volatile user memory. /
yihui	1:fc2f9d636751	1093	__IO uint32_t ERASEPROTECTEDPAGE; /!< Register for erasing a protected non-volatile memory page. /
yihui	1:fc2f9d636751	1094	__IO uint32_t ERASEUICR; /!< Register for start erasing User Information Congfiguration Registers. /
yihui	1:fc2f9d636751	1095	} NRF_NVMC_Type;
yihui	1:fc2f9d636751	1096
yihui	1:fc2f9d636751	1097
yihui	1:fc2f9d636751	1098	/* ================================================================================ */
yihui	1:fc2f9d636751	1099	/* ================ PPI ================ */
yihui	1:fc2f9d636751	1100	/* ================================================================================ */
yihui	1:fc2f9d636751	1101
yihui	1:fc2f9d636751	1102
yihui	1:fc2f9d636751	1103	/**
yihui	1:fc2f9d636751	1104	* @brief PPI controller. (PPI)
yihui	1:fc2f9d636751	1105	*/
yihui	1:fc2f9d636751	1106
yihui	1:fc2f9d636751	1107	typedef struct { /!< PPI Structure /
yihui	1:fc2f9d636751	1108	PPI_TASKS_CHG_Type TASKS_CHG[4]; /!< Channel group tasks. /
yihui	1:fc2f9d636751	1109	__I uint32_t RESERVED0[312];
yihui	1:fc2f9d636751	1110	__IO uint32_t CHEN; /!< Channel enable. /
yihui	1:fc2f9d636751	1111	__IO uint32_t CHENSET; /!< Channel enable set. /
yihui	1:fc2f9d636751	1112	__IO uint32_t CHENCLR; /!< Channel enable clear. /
yihui	1:fc2f9d636751	1113	__I uint32_t RESERVED1;
yihui	1:fc2f9d636751	1114	PPI_CH_Type CH[16]; /!< PPI Channel. /
yihui	1:fc2f9d636751	1115	__I uint32_t RESERVED2[156];
yihui	1:fc2f9d636751	1116	__IO uint32_t CHG[4]; /!< Channel group configuration. /
yihui	1:fc2f9d636751	1117	} NRF_PPI_Type;
yihui	1:fc2f9d636751	1118
yihui	1:fc2f9d636751	1119
yihui	1:fc2f9d636751	1120	/* ================================================================================ */
yihui	1:fc2f9d636751	1121	/* ================ FICR ================ */
yihui	1:fc2f9d636751	1122	/* ================================================================================ */
yihui	1:fc2f9d636751	1123
yihui	1:fc2f9d636751	1124
yihui	1:fc2f9d636751	1125	/**
yihui	1:fc2f9d636751	1126	* @brief Factory Information Configuration. (FICR)
yihui	1:fc2f9d636751	1127	*/
yihui	1:fc2f9d636751	1128
yihui	1:fc2f9d636751	1129	typedef struct { /!< FICR Structure /
yihui	1:fc2f9d636751	1130	__I uint32_t RESERVED0[4];
yihui	1:fc2f9d636751	1131	__I uint32_t CODEPAGESIZE; /!< Code memory page size in bytes. /
yihui	1:fc2f9d636751	1132	__I uint32_t CODESIZE; /!< Code memory size in pages. /
yihui	1:fc2f9d636751	1133	__I uint32_t RESERVED1[4];
yihui	1:fc2f9d636751	1134	__I uint32_t CLENR0; /!< Length of code region 0 in bytes. /
yihui	1:fc2f9d636751	1135	__I uint32_t PPFC; /!< Pre-programmed factory code present. /
yihui	1:fc2f9d636751	1136	__I uint32_t RESERVED2;
yihui	1:fc2f9d636751	1137	__I uint32_t NUMRAMBLOCK; /!< Number of individualy controllable RAM blocks. /
yihui	1:fc2f9d636751	1138
yihui	1:fc2f9d636751	1139	union {
yihui	1:fc2f9d636751	1140	__I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
yihui	1:fc2f9d636751	1141	kept for backward compatinility purposes. Use SIZERAMBLOCKS
yihui	1:fc2f9d636751	1142	instead. */
yihui	1:fc2f9d636751	1143	__I uint32_t SIZERAMBLOCKS; /!< Size of RAM blocks in bytes. /
yihui	1:fc2f9d636751	1144	};
yihui	1:fc2f9d636751	1145	__I uint32_t RESERVED3[5];
yihui	1:fc2f9d636751	1146	__I uint32_t CONFIGID; /!< Configuration identifier. /
yihui	1:fc2f9d636751	1147	__I uint32_t DEVICEID[2]; /!< Device identifier. /
yihui	1:fc2f9d636751	1148	__I uint32_t RESERVED4[6];
yihui	1:fc2f9d636751	1149	__I uint32_t ER[4]; /!< Encryption root. /
yihui	1:fc2f9d636751	1150	__I uint32_t IR[4]; /!< Identity root. /
yihui	1:fc2f9d636751	1151	__I uint32_t DEVICEADDRTYPE; /!< Device address type. /
yihui	1:fc2f9d636751	1152	__I uint32_t DEVICEADDR[2]; /!< Device address. /
yihui	1:fc2f9d636751	1153	__I uint32_t OVERRIDEEN; /!< Radio calibration override enable. /
yihui	1:fc2f9d636751	1154	__I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
yihui	1:fc2f9d636751	1155	mode. */
yihui	1:fc2f9d636751	1156	__I uint32_t RESERVED5[10];
yihui	1:fc2f9d636751	1157	__I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
yihui	1:fc2f9d636751	1158	mode. */
yihui	1:fc2f9d636751	1159	FICR_INFO_Type INFO; /!< Device info /
yihui	1:fc2f9d636751	1160	} NRF_FICR_Type;
yihui	1:fc2f9d636751	1161
yihui	1:fc2f9d636751	1162
yihui	1:fc2f9d636751	1163	/* ================================================================================ */
yihui	1:fc2f9d636751	1164	/* ================ UICR ================ */
yihui	1:fc2f9d636751	1165	/* ================================================================================ */
yihui	1:fc2f9d636751	1166
yihui	1:fc2f9d636751	1167
yihui	1:fc2f9d636751	1168	/**
yihui	1:fc2f9d636751	1169	* @brief User Information Configuration. (UICR)
yihui	1:fc2f9d636751	1170	*/
yihui	1:fc2f9d636751	1171
yihui	1:fc2f9d636751	1172	typedef struct { /!< UICR Structure /
yihui	1:fc2f9d636751	1173	__IO uint32_t CLENR0; /!< Length of code region 0. /
yihui	1:fc2f9d636751	1174	__IO uint32_t RBPCONF; /!< Readback protection configuration. /
yihui	1:fc2f9d636751	1175	__IO uint32_t XTALFREQ; /!< Reset value for CLOCK XTALFREQ register. /
yihui	1:fc2f9d636751	1176	__I uint32_t RESERVED0;
yihui	1:fc2f9d636751	1177	__I uint32_t FWID; /!< Firmware ID. /
yihui	1:fc2f9d636751	1178	__IO uint32_t BOOTLOADERADDR; /!< Bootloader start address. /
yihui	1:fc2f9d636751	1179	} NRF_UICR_Type;
yihui	1:fc2f9d636751	1180
yihui	1:fc2f9d636751	1181
yihui	1:fc2f9d636751	1182	/* ================================================================================ */
yihui	1:fc2f9d636751	1183	/* ================ GPIO ================ */
yihui	1:fc2f9d636751	1184	/* ================================================================================ */
yihui	1:fc2f9d636751	1185
yihui	1:fc2f9d636751	1186
yihui	1:fc2f9d636751	1187	/**
yihui	1:fc2f9d636751	1188	* @brief General purpose input and output. (GPIO)
yihui	1:fc2f9d636751	1189	*/
yihui	1:fc2f9d636751	1190
yihui	1:fc2f9d636751	1191	typedef struct { /!< GPIO Structure /
yihui	1:fc2f9d636751	1192	__I uint32_t RESERVED0[321];
yihui	1:fc2f9d636751	1193	__IO uint32_t OUT; /!< Write GPIO port. /
yihui	1:fc2f9d636751	1194	__IO uint32_t OUTSET; /!< Set individual bits in GPIO port. /
yihui	1:fc2f9d636751	1195	__IO uint32_t OUTCLR; /!< Clear individual bits in GPIO port. /
yihui	1:fc2f9d636751	1196	__I uint32_t IN; /!< Read GPIO port. /
yihui	1:fc2f9d636751	1197	__IO uint32_t DIR; /!< Direction of GPIO pins. /
yihui	1:fc2f9d636751	1198	__IO uint32_t DIRSET; /!< DIR set register. /
yihui	1:fc2f9d636751	1199	__IO uint32_t DIRCLR; /!< DIR clear register. /
yihui	1:fc2f9d636751	1200	__I uint32_t RESERVED1[120];
yihui	1:fc2f9d636751	1201	__IO uint32_t PIN_CNF[32]; /!< Configuration of GPIO pins. /
yihui	1:fc2f9d636751	1202	} NRF_GPIO_Type;
yihui	1:fc2f9d636751	1203
yihui	1:fc2f9d636751	1204
yihui	1:fc2f9d636751	1205	/* -------------------- End of section using anonymous unions ------------------- */
yihui	1:fc2f9d636751	1206	#if defined(__CC_ARM)
yihui	1:fc2f9d636751	1207	#pragma pop
yihui	1:fc2f9d636751	1208	#elif defined(__ICCARM__)
yihui	1:fc2f9d636751	1209	/* leave anonymous unions enabled */
yihui	1:fc2f9d636751	1210	#elif defined(__GNUC__)
yihui	1:fc2f9d636751	1211	/* anonymous unions are enabled by default */
yihui	1:fc2f9d636751	1212	#elif defined(__TMS470__)
yihui	1:fc2f9d636751	1213	/* anonymous unions are enabled by default */
yihui	1:fc2f9d636751	1214	#elif defined(__TASKING__)
yihui	1:fc2f9d636751	1215	#pragma warning restore
yihui	1:fc2f9d636751	1216	#else
yihui	1:fc2f9d636751	1217	#warning Not supported compiler type
yihui	1:fc2f9d636751	1218	#endif
yihui	1:fc2f9d636751	1219
yihui	1:fc2f9d636751	1220
yihui	1:fc2f9d636751	1221
yihui	1:fc2f9d636751	1222
yihui	1:fc2f9d636751	1223	/* ================================================================================ */
yihui	1:fc2f9d636751	1224	/* ================ Peripheral memory map ================ */
yihui	1:fc2f9d636751	1225	/* ================================================================================ */
yihui	1:fc2f9d636751	1226
yihui	1:fc2f9d636751	1227	#define NRF_POWER_BASE 0x40000000UL
yihui	1:fc2f9d636751	1228	#define NRF_CLOCK_BASE 0x40000000UL
yihui	1:fc2f9d636751	1229	#define NRF_MPU_BASE 0x40000000UL
yihui	1:fc2f9d636751	1230	#define NRF_PU_BASE 0x40000000UL
yihui	1:fc2f9d636751	1231	#define NRF_AMLI_BASE 0x40000000UL
yihui	1:fc2f9d636751	1232	#define NRF_RADIO_BASE 0x40001000UL
yihui	1:fc2f9d636751	1233	#define NRF_UART0_BASE 0x40002000UL
yihui	1:fc2f9d636751	1234	#define NRF_SPI0_BASE 0x40003000UL
yihui	1:fc2f9d636751	1235	#define NRF_TWI0_BASE 0x40003000UL
yihui	1:fc2f9d636751	1236	#define NRF_SPI1_BASE 0x40004000UL
yihui	1:fc2f9d636751	1237	#define NRF_TWI1_BASE 0x40004000UL
yihui	1:fc2f9d636751	1238	#define NRF_SPIS1_BASE 0x40004000UL
yihui	1:fc2f9d636751	1239	#define NRF_SPIM1_BASE 0x40004000UL
yihui	1:fc2f9d636751	1240	#define NRF_GPIOTE_BASE 0x40006000UL
yihui	1:fc2f9d636751	1241	#define NRF_ADC_BASE 0x40007000UL
yihui	1:fc2f9d636751	1242	#define NRF_TIMER0_BASE 0x40008000UL
yihui	1:fc2f9d636751	1243	#define NRF_TIMER1_BASE 0x40009000UL
yihui	1:fc2f9d636751	1244	#define NRF_TIMER2_BASE 0x4000A000UL
yihui	1:fc2f9d636751	1245	#define NRF_RTC0_BASE 0x4000B000UL
yihui	1:fc2f9d636751	1246	#define NRF_TEMP_BASE 0x4000C000UL
yihui	1:fc2f9d636751	1247	#define NRF_RNG_BASE 0x4000D000UL
yihui	1:fc2f9d636751	1248	#define NRF_ECB_BASE 0x4000E000UL
yihui	1:fc2f9d636751	1249	#define NRF_AAR_BASE 0x4000F000UL
yihui	1:fc2f9d636751	1250	#define NRF_CCM_BASE 0x4000F000UL
yihui	1:fc2f9d636751	1251	#define NRF_WDT_BASE 0x40010000UL
yihui	1:fc2f9d636751	1252	#define NRF_RTC1_BASE 0x40011000UL
yihui	1:fc2f9d636751	1253	#define NRF_QDEC_BASE 0x40012000UL
yihui	1:fc2f9d636751	1254	#define NRF_LPCOMP_BASE 0x40013000UL
yihui	1:fc2f9d636751	1255	#define NRF_SWI_BASE 0x40014000UL
yihui	1:fc2f9d636751	1256	#define NRF_NVMC_BASE 0x4001E000UL
yihui	1:fc2f9d636751	1257	#define NRF_PPI_BASE 0x4001F000UL
yihui	1:fc2f9d636751	1258	#define NRF_FICR_BASE 0x10000000UL
yihui	1:fc2f9d636751	1259	#define NRF_UICR_BASE 0x10001000UL
yihui	1:fc2f9d636751	1260	#define NRF_GPIO_BASE 0x50000000UL
yihui	1:fc2f9d636751	1261
yihui	1:fc2f9d636751	1262
yihui	1:fc2f9d636751	1263	/* ================================================================================ */
yihui	1:fc2f9d636751	1264	/* ================ Peripheral declaration ================ */
yihui	1:fc2f9d636751	1265	/* ================================================================================ */
yihui	1:fc2f9d636751	1266
yihui	1:fc2f9d636751	1267	#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
yihui	1:fc2f9d636751	1268	#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
yihui	1:fc2f9d636751	1269	#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
yihui	1:fc2f9d636751	1270	#define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
yihui	1:fc2f9d636751	1271	#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
yihui	1:fc2f9d636751	1272	#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
yihui	1:fc2f9d636751	1273	#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
yihui	1:fc2f9d636751	1274	#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
yihui	1:fc2f9d636751	1275	#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
yihui	1:fc2f9d636751	1276	#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
yihui	1:fc2f9d636751	1277	#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
yihui	1:fc2f9d636751	1278	#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
yihui	1:fc2f9d636751	1279	#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
yihui	1:fc2f9d636751	1280	#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
yihui	1:fc2f9d636751	1281	#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
yihui	1:fc2f9d636751	1282	#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
yihui	1:fc2f9d636751	1283	#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
yihui	1:fc2f9d636751	1284	#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
yihui	1:fc2f9d636751	1285	#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
yihui	1:fc2f9d636751	1286	#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
yihui	1:fc2f9d636751	1287	#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
yihui	1:fc2f9d636751	1288	#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
yihui	1:fc2f9d636751	1289	#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
yihui	1:fc2f9d636751	1290	#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
yihui	1:fc2f9d636751	1291	#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
yihui	1:fc2f9d636751	1292	#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
yihui	1:fc2f9d636751	1293	#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
yihui	1:fc2f9d636751	1294	#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
yihui	1:fc2f9d636751	1295	#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
yihui	1:fc2f9d636751	1296	#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
yihui	1:fc2f9d636751	1297	#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
yihui	1:fc2f9d636751	1298	#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
yihui	1:fc2f9d636751	1299	#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
yihui	1:fc2f9d636751	1300	#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
yihui	1:fc2f9d636751	1301
yihui	1:fc2f9d636751	1302
yihui	1:fc2f9d636751	1303	/** @} / / End of group Device_Peripheral_Registers */
yihui	1:fc2f9d636751	1304	/** @} / / End of group nRF51 */
yihui	1:fc2f9d636751	1305	/** @} / / End of group Nordic Semiconductor */
yihui	1:fc2f9d636751	1306
yihui	1:fc2f9d636751	1307	#ifdef __cplusplus
yihui	1:fc2f9d636751	1308	}
yihui	1:fc2f9d636751	1309	#endif
yihui	1:fc2f9d636751	1310
yihui	1:fc2f9d636751	1311
yihui	1:fc2f9d636751	1312	#endif /* nRF51_H */
yihui	1:fc2f9d636751	1313

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	07 Feb 2015
Imports:	1480
Forks:	3
Commits:	4
Dependents:	0
Dependencies:	4
Followers:	71

nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf51.h@1:fc2f9d636751, 2015-04-22 (annotated)

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