SafeDetect / Mbed OS multithread_ADC_timing

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Dependencies:   FastAnalogIn fastADC

main.cpp@114:cb1ac5905df4, 2019-12-08 (annotated)

Committer:
yutonggu
Date:
Sun Dec 08 05:27:35 2019 +0000
Revision:
114:cb1ac5905df4
Parent:
113:233a2fac1911 
Changed to use fastADC and sample at 20KHz

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 82:abf1b1785bd7 1 /* mbed Microcontroller Library
mbed_official 82:abf1b1785bd7 2 * Copyright (c) 2018 ARM Limited
mbed_official 82:abf1b1785bd7 3 * SPDX-License-Identifier: Apache-2.0
mbed_official 82:abf1b1785bd7 4 */
mbed_official 82:abf1b1785bd7 5
Jonathan Austin 0:2757d7abb7d9 6 #include "mbed.h"
mbed_official 100:ec006d6f3cb6 7 #include "platform/mbed_thread.h"
mbed_official 82:abf1b1785bd7 8 #include "stats_report.h"
candre97 102:14fd65f261a2 9 #include <AnalogIn.h>
candre97 102:14fd65f261a2 10 #include <AnalogOut.h>
candre97 109:1d95a4596fb5 11 #include "circ_buff.hpp"
yutonggu 114:cb1ac5905df4 12 #include "fastADC.h"
Jonathan Austin 0:2757d7abb7d9 13
candre97 111:f6bf8ca71128 14
candre97 102:14fd65f261a2 15 AnalogOut v_src(GPIO0);
candre97 102:14fd65f261a2 16 AnalogIn therm(GPIO2);
Jonathan Austin 0:2757d7abb7d9 17
mbed_official 88:bea4f2daa48c 18 #define SLEEP_TIME 500 // (msec)
mbed_official 88:bea4f2daa48c 19 #define PRINT_AFTER_N_LOOPS 20
mbed_official 88:bea4f2daa48c 20
candre97 110:037667235b6d 21 //define defaults for mfcc
candre97 110:037667235b6d 22 #define DEF_NUMCEPSTRA 12
candre97 110:037667235b6d 23 #define DEF_NUMFILTERS 40
candre97 110:037667235b6d 24 #define DEF_SAMPLINGRATE 16000
candre97 110:037667235b6d 25 #define DEF_WINLENGTH 25
candre97 110:037667235b6d 26 #define DEF_FRAMESHIFT 10
candre97 110:037667235b6d 27 #define DEF_LOWFREQ 50
candre97 110:037667235b6d 28 #define DEF_HIGHFREQ DEF_SAMPLINGRATE/2
candre97 110:037667235b6d 29 #define WINDOW_SIZE DEF_WINLENGTH - DEF_FRAMESHIFT
candre97 110:037667235b6d 30 #define ARRAY_SIZE 800
candre97 102:14fd65f261a2 31
yutonggu 114:cb1ac5905df4 32 #define BUFFSIZE 1000 // size of buffer = sampling_time * sampling_rate * size(float)
candre97 109:1d95a4596fb5 33 //DigitalOut led1(LED1);
candre97 109:1d95a4596fb5 34 //DigitalOut led2(LED2);
candre97 109:1d95a4596fb5 35 Thread thread_adc;
candre97 110:037667235b6d 36 Thread thread_mfcc;
yutonggu 114:cb1ac5905df4 37 Ticker read_ADC_ticker;
candre97 109:1d95a4596fb5 38
candre97 110:037667235b6d 39 // PIN DEFINITIONS
candre97 110:037667235b6d 40 DigitalOut vcc(GPIO0);
candre97 110:037667235b6d 41 AnalogIn mic(PB_0);
candre97 110:037667235b6d 42 CircularBuff<uint16_t> buff(BUFFSIZE);
candre97 110:037667235b6d 43
yutonggu 114:cb1ac5905df4 44 Serial pc(USBTX, USBRX);
candre97 111:f6bf8ca71128 45
yutonggu 114:cb1ac5905df4 46 volatile int num_readings = 0;
candre97 111:f6bf8ca71128 47 int z = 0;
yutonggu 114:cb1ac5905df4 48 volatile uint16_t raw_adc = 0;
candre97 111:f6bf8ca71128 49 uint16_t* pop_val;
candre97 111:f6bf8ca71128 50
candre97 109:1d95a4596fb5 51 void adc_thread() {
yutonggu 114:cb1ac5905df4 52 // while (true) {
yutonggu 114:cb1ac5905df4 53 // wait_us(42);
yutonggu 114:cb1ac5905df4 54 raw_adc = readADC(); /* Read AD converted value */
yutonggu 114:cb1ac5905df4 55 num_readings++;
yutonggu 114:cb1ac5905df4 56
candre97 111:f6bf8ca71128 57
yutonggu 114:cb1ac5905df4 58 // }
Jonathan Austin 0:2757d7abb7d9 59 }
candre97 103:2da5fc276330 60
candre97 111:f6bf8ca71128 61 //To sleep, 'wait' should be replaced by 'ThisThread::sleep_for' (C++) or 'thread_sleep_for' (C). If you wish to wait (without sleeping), call 'wait_us'. 'wait_us' is safe to call from ISR context. [since mbed-os-5.14] [-Wdeprecated-declarations] in "main.cpp", Line: 59, Col: 9
candre97 111:f6bf8ca71128 62
candre97 109:1d95a4596fb5 63 /*
candre97 109:1d95a4596fb5 64 this thread is in charge of converting
candre97 109:1d95a4596fb5 65 */
candre97 109:1d95a4596fb5 66 void mfcc_thread() {
candre97 102:14fd65f261a2 67 while (true) {
candre97 110:037667235b6d 68 //printf("Top of MFCC thread");
yutonggu 114:cb1ac5905df4 69 thread_sleep_for(5000);
yutonggu 114:cb1ac5905df4 70 double rate = num_readings/5000.0;
yutonggu 114:cb1ac5905df4 71 pc.printf("Readings / second: %f Ksps\n\n", rate);
candre97 110:037667235b6d 72 num_readings = 0;
yutonggu 114:cb1ac5905df4 73 //pop_val = buff.pop();
yutonggu 114:cb1ac5905df4 74 //pc.printf("last reading: %u\n", *pop_val);
yutonggu 114:cb1ac5905df4 75 //buff.clear();
candre97 102:14fd65f261a2 76 }
candre97 102:14fd65f261a2 77 }
candre97 102:14fd65f261a2 78
candre97 111:f6bf8ca71128 79 /*
candre97 111:f6bf8ca71128 80 The following sequence should be followed to configure a DMA channelx (where x is the
candre97 111:f6bf8ca71128 81 channel number).
candre97 111:f6bf8ca71128 82 1. Set the peripheral register address in the DMA_CPARx register. The data will be
candre97 111:f6bf8ca71128 83 moved from/ to this address to/ from the memory after the peripheral event.
candre97 111:f6bf8ca71128 84 2. Set the memory address in the DMA_CMARx register. The data will be written to or
candre97 111:f6bf8ca71128 85 read from this memory after the peripheral event.
candre97 111:f6bf8ca71128 86 3. Configure the total number of data to be transferred in the DMA_CNDTRx register.
candre97 111:f6bf8ca71128 87 After each peripheral event, this value will be decremented.
candre97 111:f6bf8ca71128 88 4. Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register
candre97 111:f6bf8ca71128 89 5. Configure data transfer direction, circular mode, peripheral & memory incremented
candre97 111:f6bf8ca71128 90 mode, peripheral & memory data size, and interrupt after half and/or full transfer in the
candre97 111:f6bf8ca71128 91 DMA_CCRx register
candre97 111:f6bf8ca71128 92 6. Activate the channel by setting the ENABLE bit in the DMA_CCRx register
candre97 111:f6bf8ca71128 93 */
yutonggu 114:cb1ac5905df4 94 //
yutonggu 114:cb1ac5905df4 95 //void config_dma() {
yutonggu 114:cb1ac5905df4 96 // /*
yutonggu 114:cb1ac5905df4 97 // 1. Set the peripheral register address in the DMA_CPARx register. The data will be
yutonggu 114:cb1ac5905df4 98 // moved from/ to this address to/ from the memory after the peripheral event.
yutonggu 114:cb1ac5905df4 99 // */
yutonggu 114:cb1ac5905df4 100 // //RCC->DMA_CPAR1 &= 0x00000000;
yutonggu 114:cb1ac5905df4 101 //
yutonggu 114:cb1ac5905df4 102 //}
candre97 111:f6bf8ca71128 103
candre97 111:f6bf8ca71128 104
candre97 111:f6bf8ca71128 105
candre97 111:f6bf8ca71128 106
candre97 111:f6bf8ca71128 107
candre97 111:f6bf8ca71128 108
candre97 111:f6bf8ca71128 109
candre97 102:14fd65f261a2 110 int main() {
yutonggu 114:cb1ac5905df4 111 // config_dma();
yutonggu 114:cb1ac5905df4 112 pc.printf("configuring DMA\n");
candre97 111:f6bf8ca71128 113
yutonggu 114:cb1ac5905df4 114 pc.printf("Creating buff of size %d\n", BUFFSIZE);
candre97 110:037667235b6d 115 /* clear the buffer */
yutonggu 114:cb1ac5905df4 116 // buff.clear();
yutonggu 114:cb1ac5905df4 117 pc.printf("Setting up ADC\n");
candre97 110:037667235b6d 118
yutonggu 114:cb1ac5905df4 119 /* Setup and initialize ADC converter https://www.davidkebo.com/microcontroller-interfacing */
yutonggu 114:cb1ac5905df4 120 // RCC->APB2RSTR |= 1 << 9; /* Enable ADC1 clock */
yutonggu 114:cb1ac5905df4 121 initADC();
yutonggu 114:cb1ac5905df4 122 // ADC->SMPR1 = 5 << 12; /* Channel 14 sample time is 55.5 cyc */
yutonggu 114:cb1ac5905df4 123 // ADC->SMPR2 = 0x00000000; /* Clear register */
yutonggu 114:cb1ac5905df4 124 // ADC->CR1 = 1 << 8; /* Scan mode on */
yutonggu 114:cb1ac5905df4 125 // ADC->CR2 = (1 << 20) | /* Enable external trigger */
candre97 113:233a2fac1911 126 // (7 << 17) | /* EXTSEL = SWSTART */
candre97 113:233a2fac1911 127 // (1 << 1) | /* Continuous conversion */
candre97 113:233a2fac1911 128 // (1 << 0) ; /* ADC enable */
candre97 113:233a2fac1911 129 // ADC1->CR2 |= 1 << 3; /* Initialize calibration registers */
candre97 113:233a2fac1911 130 // while (ADC1->CR2 & (1 << 3)); /* Wait for initialization to finish */
candre97 113:233a2fac1911 131 // ADC1->CR2 |= 1 << 2; /* Start calibration */
candre97 113:233a2fac1911 132 // while (ADC1->CR2 & (1 << 2)); /* Wait for calibration to finish */
candre97 113:233a2fac1911 133 // ADC1->CR2 |= 1 << 22; /* Start first conversion */
candre97 113:233a2fac1911 134 //
yutonggu 114:cb1ac5905df4 135
yutonggu 114:cb1ac5905df4 136 //for (;;) { /* Loop forever */
yutonggu 114:cb1ac5905df4 137 // raw_adc = readADC();
yutonggu 114:cb1ac5905df4 138 // pc.printf("register read val: %u\n", raw_adc);
candre97 113:233a2fac1911 139 // }
candre97 111:f6bf8ca71128 140
candre97 111:f6bf8ca71128 141
candre97 111:f6bf8ca71128 142
yutonggu 114:cb1ac5905df4 143
yutonggu 114:cb1ac5905df4 144 read_ADC_ticker.attach_us(&adc_thread, 50);
candre97 109:1d95a4596fb5 145 thread_mfcc.start(mfcc_thread);
yutonggu 114:cb1ac5905df4 146 while(1){
yutonggu 114:cb1ac5905df4 147 thread_sleep_for(10000);
yutonggu 114:cb1ac5905df4 148 }
candre97 102:14fd65f261a2 149 }