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3-axis MEMS ultra low power magnetometer
Dependencies: X_NUCLEO_COMMON ST_INTERFACES
Dependents: X_NUCLEO_IKS01A3 X_NUCLEO_IKS01A3
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lis2mdl_reg.c
00001 /* 00002 ****************************************************************************** 00003 * @file lis2mdl_reg.c 00004 * @author Sensors Software Solution Team 00005 * @brief LIS2MDL driver file 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without 00012 * modification, are permitted provided that the following conditions 00013 * are met: 00014 * 1. Redistributions of source code must retain the above copyright notice, 00015 * this list of conditions and the following disclaimer. 00016 * 2. Redistributions in binary form must reproduce the above copyright 00017 * notice, this list of conditions and the following disclaimer in the 00018 * documentation and/or other materials provided with the distribution. 00019 * 3. Neither the name of STMicroelectronics nor the names of its 00020 * contributors may be used to endorse or promote products derived from 00021 * this software without specific prior written permission. 00022 * 00023 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00024 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00025 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00026 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 00027 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00028 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00029 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00030 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00031 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00032 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00033 * POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 */ 00036 #include "lis2mdl_reg.h" 00037 00038 /** 00039 * @defgroup LIS2MDL 00040 * @brief This file provides a set of functions needed to drive the 00041 * lis2mdl enhanced inertial module. 00042 * @{ 00043 * 00044 */ 00045 00046 /** 00047 * @defgroup LIS2MDL_Interfaces_Functions 00048 * @brief This section provide a set of functions used to read and 00049 * write a generic register of the device. 00050 * MANDATORY: return 0 -> no Error. 00051 * @{ 00052 * 00053 */ 00054 00055 /** 00056 * @brief Read generic device register 00057 * 00058 * @param ctx read / write interface definitions(ptr) 00059 * @param reg register to read 00060 * @param data pointer to buffer that store the data read(ptr) 00061 * @param len number of consecutive register to read 00062 * @retval interface status (MANDATORY: return 0 -> no Error) 00063 * 00064 */ 00065 int32_t lis2mdl_read_reg(lis2mdl_ctx_t *ctx, uint8_t reg, uint8_t *data, 00066 uint16_t len) 00067 { 00068 int32_t ret; 00069 ret = ctx->read_reg(ctx->handle, reg, data, len); 00070 return ret; 00071 } 00072 00073 /** 00074 * @brief Write generic device register 00075 * 00076 * @param ctx read / write interface definitions(ptr) 00077 * @param reg register to write 00078 * @param data pointer to data to write in register reg(ptr) 00079 * @param len number of consecutive register to write 00080 * @retval interface status (MANDATORY: return 0 -> no Error) 00081 * 00082 */ 00083 int32_t lis2mdl_write_reg(lis2mdl_ctx_t *ctx, uint8_t reg, uint8_t *data, 00084 uint16_t len) 00085 { 00086 int32_t ret; 00087 ret = ctx->write_reg(ctx->handle, reg, data, len); 00088 return ret; 00089 } 00090 00091 /** 00092 * @} 00093 * 00094 */ 00095 00096 /** 00097 * @defgroup LIS2MDL_Sensitivity 00098 * @brief These functions convert raw-data into engineering units. 00099 * @{ 00100 * 00101 */ 00102 float_t lis2mdl_from_lsb_to_mgauss(int16_t lsb) 00103 { 00104 return ((float_t)lsb * 1.5f); 00105 } 00106 00107 float_t lis2mdl_from_lsb_to_celsius(int16_t lsb) 00108 { 00109 return (((float_t)lsb / 8.0f) + 25.0f); 00110 } 00111 00112 /** 00113 * @} 00114 * 00115 */ 00116 00117 /** 00118 * @defgroup LIS2MDL_data_generation 00119 * @brief This section group all the functions concerning 00120 * data generation 00121 * @{ 00122 * 00123 */ 00124 00125 /** 00126 * @brief These registers comprise a 3 group of 16-bit number and represent 00127 * hard-iron offset in order to compensate environmental effects. 00128 * Data format is the same of output data raw: two’s complement 00129 * with 1LSb = 1.5mG. These values act on the magnetic output data 00130 * value in order to delete the environmental offset.[set] 00131 * 00132 * @param ctx read / write interface definitions.(ptr) 00133 * @param buff buffer that contains data to write 00134 * @retval interface status.(MANDATORY: return 0 -> no Error) 00135 * 00136 */ 00137 int32_t lis2mdl_mag_user_offset_set(lis2mdl_ctx_t *ctx, uint8_t *buff) 00138 { 00139 int32_t ret; 00140 ret = lis2mdl_write_reg(ctx, LIS2MDL_OFFSET_X_REG_L, buff, 6); 00141 return ret; 00142 } 00143 00144 /** 00145 * @brief These registers comprise a 3 group of 16-bit number and represent 00146 * hard-iron offset in order to compensate environmental effects. 00147 * Data format is the same of output data raw: two’s complement 00148 * with 1LSb = 1.5mG. These values act on the magnetic output data 00149 * value in order to delete the environmental offset.[get] 00150 * 00151 * @param ctx read / write interface definitions.(ptr) 00152 * @param buff that stores data read 00153 * @retval interface status.(MANDATORY: return 0 -> no Error) 00154 * 00155 */ 00156 int32_t lis2mdl_mag_user_offset_get(lis2mdl_ctx_t *ctx, uint8_t *buff) 00157 { 00158 int32_t ret; 00159 ret = lis2mdl_read_reg(ctx, LIS2MDL_OFFSET_X_REG_L, buff, 6); 00160 return ret; 00161 } 00162 00163 /** 00164 * @brief Operating mode selection.[set] 00165 * 00166 * @param ctx read / write interface definitions.(ptr) 00167 * @param val change the values of md in reg CFG_REG_A 00168 * @retval interface status.(MANDATORY: return 0 -> no Error) 00169 * 00170 */ 00171 int32_t lis2mdl_operating_mode_set(lis2mdl_ctx_t *ctx, lis2mdl_md_t val) 00172 { 00173 lis2mdl_cfg_reg_a_t reg; 00174 int32_t ret; 00175 00176 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00177 00178 if (ret == 0) { 00179 reg.md = (uint8_t)val; 00180 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00181 } 00182 00183 return ret; 00184 } 00185 00186 /** 00187 * @brief Operating mode selection.[get] 00188 * 00189 * @param ctx read / write interface definitions.(ptr) 00190 * @param val Get the values of md in reg CFG_REG_A.(ptr) 00191 * @retval interface status.(MANDATORY: return 0 -> no Error) 00192 * 00193 */ 00194 int32_t lis2mdl_operating_mode_get(lis2mdl_ctx_t *ctx, lis2mdl_md_t *val) 00195 { 00196 lis2mdl_cfg_reg_a_t reg; 00197 int32_t ret; 00198 00199 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00200 switch (reg.md) { 00201 case LIS2MDL_POWER_DOWN: 00202 *val = LIS2MDL_POWER_DOWN; 00203 break; 00204 case LIS2MDL_CONTINUOUS_MODE: 00205 *val = LIS2MDL_CONTINUOUS_MODE; 00206 break; 00207 case LIS2MDL_SINGLE_TRIGGER: 00208 *val = LIS2MDL_SINGLE_TRIGGER; 00209 break; 00210 default: 00211 *val = LIS2MDL_POWER_DOWN; 00212 break; 00213 } 00214 00215 return ret; 00216 } 00217 00218 /** 00219 * @brief Output data rate selection.[set] 00220 * 00221 * @param ctx read / write interface definitions.(ptr) 00222 * @param val change the values of odr in reg CFG_REG_A 00223 * @retval interface status.(MANDATORY: return 0 -> no Error) 00224 * 00225 */ 00226 int32_t lis2mdl_data_rate_set(lis2mdl_ctx_t *ctx, lis2mdl_odr_t val) 00227 { 00228 lis2mdl_cfg_reg_a_t reg; 00229 int32_t ret; 00230 00231 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00232 00233 if (ret == 0) { 00234 reg.odr = (uint8_t)val; 00235 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00236 } 00237 00238 return ret; 00239 } 00240 00241 /** 00242 * @brief Output data rate selection.[get] 00243 * 00244 * @param ctx read / write interface definitions.(ptr) 00245 * @param val Get the values of odr in reg CFG_REG_A.(ptr) 00246 * @retval interface status.(MANDATORY: return 0 -> no Error) 00247 * 00248 */ 00249 int32_t lis2mdl_data_rate_get(lis2mdl_ctx_t *ctx, lis2mdl_odr_t *val) 00250 { 00251 lis2mdl_cfg_reg_a_t reg; 00252 int32_t ret; 00253 00254 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00255 switch (reg.odr) { 00256 case LIS2MDL_ODR_10Hz: 00257 *val = LIS2MDL_ODR_10Hz; 00258 break; 00259 case LIS2MDL_ODR_20Hz: 00260 *val = LIS2MDL_ODR_20Hz; 00261 break; 00262 case LIS2MDL_ODR_50Hz: 00263 *val = LIS2MDL_ODR_50Hz; 00264 break; 00265 case LIS2MDL_ODR_100Hz: 00266 *val = LIS2MDL_ODR_100Hz; 00267 break; 00268 default: 00269 *val = LIS2MDL_ODR_10Hz; 00270 break; 00271 } 00272 return ret; 00273 } 00274 00275 /** 00276 * @brief Enables high-resolution/low-power mode.[set] 00277 * 00278 * @param ctx read / write interface definitions.(ptr) 00279 * @param val change the values of lp in reg CFG_REG_A 00280 * @retval interface status.(MANDATORY: return 0 -> no Error) 00281 * 00282 */ 00283 int32_t lis2mdl_power_mode_set(lis2mdl_ctx_t *ctx, lis2mdl_lp_t val) 00284 { 00285 lis2mdl_cfg_reg_a_t reg; 00286 int32_t ret; 00287 00288 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00289 00290 if (ret == 0) { 00291 reg.lp = (uint8_t)val; 00292 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00293 } 00294 00295 return ret; 00296 } 00297 00298 /** 00299 * @brief Enables high-resolution/low-power mode.[get] 00300 * 00301 * @param ctx read / write interface definitions.(ptr) 00302 * @param val Get the values of lp in reg CFG_REG_A.(ptr) 00303 * @retval interface status.(MANDATORY: return 0 -> no Error) 00304 * 00305 */ 00306 int32_t lis2mdl_power_mode_get(lis2mdl_ctx_t *ctx, lis2mdl_lp_t *val) 00307 { 00308 lis2mdl_cfg_reg_a_t reg; 00309 int32_t ret; 00310 00311 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00312 switch (reg.lp) { 00313 case LIS2MDL_HIGH_RESOLUTION: 00314 *val = LIS2MDL_HIGH_RESOLUTION; 00315 break; 00316 case LIS2MDL_LOW_POWER: 00317 *val = LIS2MDL_LOW_POWER; 00318 break; 00319 default: 00320 *val = LIS2MDL_HIGH_RESOLUTION; 00321 break; 00322 } 00323 return ret; 00324 } 00325 00326 /** 00327 * @brief Enables the magnetometer temperature compensation.[set] 00328 * 00329 * @param ctx read / write interface definitions.(ptr) 00330 * @param val change the values of comp_temp_en in reg CFG_REG_A 00331 * @retval interface status.(MANDATORY: return 0 -> no Error) 00332 * 00333 */ 00334 int32_t lis2mdl_offset_temp_comp_set(lis2mdl_ctx_t *ctx, uint8_t val) 00335 { 00336 lis2mdl_cfg_reg_a_t reg; 00337 int32_t ret; 00338 00339 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00340 00341 if (ret == 0) { 00342 reg.comp_temp_en = val; 00343 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00344 } 00345 00346 return ret; 00347 } 00348 00349 /** 00350 * @brief Enables the magnetometer temperature compensation.[get] 00351 * 00352 * @param ctx read / write interface definitions.(ptr) 00353 * @param val change the values of comp_temp_en in reg CFG_REG_A.(ptr) 00354 * @retval interface status.(MANDATORY: return 0 -> no Error) 00355 * 00356 */ 00357 int32_t lis2mdl_offset_temp_comp_get(lis2mdl_ctx_t *ctx, uint8_t *val) 00358 { 00359 lis2mdl_cfg_reg_a_t reg; 00360 int32_t ret; 00361 00362 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00363 *val = reg.comp_temp_en; 00364 00365 return ret; 00366 } 00367 00368 /** 00369 * @brief Low-pass bandwidth selection.[set] 00370 * 00371 * @param ctx read / write interface definitions.(ptr) 00372 * @param val change the values of lpf in reg CFG_REG_B 00373 * @retval interface status.(MANDATORY: return 0 -> no Error) 00374 * 00375 */ 00376 int32_t lis2mdl_low_pass_bandwidth_set(lis2mdl_ctx_t *ctx, 00377 lis2mdl_lpf_t val) 00378 { 00379 lis2mdl_cfg_reg_b_t reg; 00380 int32_t ret; 00381 00382 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1); 00383 00384 if (ret == 0) { 00385 reg.lpf = (uint8_t)val; 00386 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1); 00387 } 00388 00389 return ret; 00390 } 00391 00392 /** 00393 * @brief Low-pass bandwidth selection.[get] 00394 * 00395 * @param ctx read / write interface definitions.(ptr) 00396 * @param val Get the values of lpf in reg CFG_REG_B.(ptr) 00397 * @retval interface status.(MANDATORY: return 0 -> no Error) 00398 * 00399 */ 00400 int32_t lis2mdl_low_pass_bandwidth_get(lis2mdl_ctx_t *ctx, 00401 lis2mdl_lpf_t *val) 00402 { 00403 lis2mdl_cfg_reg_b_t reg; 00404 int32_t ret; 00405 00406 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1); 00407 switch (reg.lpf) { 00408 case LIS2MDL_ODR_DIV_2: 00409 *val = LIS2MDL_ODR_DIV_2; 00410 break; 00411 case LIS2MDL_ODR_DIV_4: 00412 *val = LIS2MDL_ODR_DIV_4; 00413 break; 00414 default: 00415 *val = LIS2MDL_ODR_DIV_2; 00416 break; 00417 } 00418 return ret; 00419 } 00420 00421 /** 00422 * @brief Reset mode.[set] 00423 * 00424 * @param ctx read / write interface definitions.(ptr) 00425 * @param val change the values of set_rst in reg CFG_REG_B 00426 * @retval interface status.(MANDATORY: return 0 -> no Error) 00427 * 00428 */ 00429 int32_t lis2mdl_set_rst_mode_set(lis2mdl_ctx_t *ctx, lis2mdl_set_rst_t val) 00430 { 00431 lis2mdl_cfg_reg_b_t reg; 00432 int32_t ret; 00433 00434 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1); 00435 00436 if (ret == 0) { 00437 reg.set_rst = (uint8_t)val; 00438 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1); 00439 } 00440 00441 return ret; 00442 } 00443 00444 /** 00445 * @brief Reset mode.[get] 00446 * 00447 * @param ctx read / write interface definitions.(ptr) 00448 * @param val Get the values of set_rst in reg CFG_REG_B.(ptr) 00449 * @retval interface status.(MANDATORY: return 0 -> no Error) 00450 * 00451 */ 00452 int32_t lis2mdl_set_rst_mode_get(lis2mdl_ctx_t *ctx, lis2mdl_set_rst_t *val) 00453 { 00454 lis2mdl_cfg_reg_b_t reg; 00455 int32_t ret; 00456 00457 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1); 00458 switch (reg.set_rst) { 00459 case LIS2MDL_SET_SENS_ODR_DIV_63: 00460 *val = LIS2MDL_SET_SENS_ODR_DIV_63; 00461 break; 00462 case LIS2MDL_SENS_OFF_CANC_EVERY_ODR: 00463 *val = LIS2MDL_SENS_OFF_CANC_EVERY_ODR; 00464 break; 00465 case LIS2MDL_SET_SENS_ONLY_AT_POWER_ON: 00466 *val = LIS2MDL_SET_SENS_ONLY_AT_POWER_ON; 00467 break; 00468 default: 00469 *val = LIS2MDL_SET_SENS_ODR_DIV_63; 00470 break; 00471 } 00472 return ret; 00473 } 00474 00475 /** 00476 * @brief Enables offset cancellation in single measurement mode. 00477 * The OFF_CANC bit must be set to 1 when enabling offset 00478 * cancellation in single measurement mode this means a 00479 * call function: set_rst_mode(SENS_OFF_CANC_EVERY_ODR) 00480 * is need.[set] 00481 * 00482 * @param ctx read / write interface definitions.(ptr) 00483 * @param val change the values of off_canc_one_shot in reg CFG_REG_B 00484 * @retval interface status.(MANDATORY: return 0 -> no Error) 00485 * 00486 */ 00487 int32_t lis2mdl_set_rst_sensor_single_set(lis2mdl_ctx_t *ctx, uint8_t val) 00488 { 00489 lis2mdl_cfg_reg_b_t reg; 00490 int32_t ret; 00491 00492 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1); 00493 00494 if (ret == 0) { 00495 reg.off_canc_one_shot = val; 00496 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1); 00497 } 00498 00499 return ret; 00500 } 00501 00502 /** 00503 * @brief Enables offset cancellation in single measurement mode. 00504 * The OFF_CANC bit must be set to 1 when enabling offset 00505 * cancellation in single measurement mode this means a 00506 * call function: set_rst_mode(SENS_OFF_CANC_EVERY_ODR) 00507 * is need.[get] 00508 * 00509 * @param ctx read / write interface definitions.(ptr) 00510 * @param val change the values of off_canc_one_shot in reg CFG_REG_B.(ptr) 00511 * @retval interface status.(MANDATORY: return 0 -> no Error) 00512 * 00513 */ 00514 int32_t lis2mdl_set_rst_sensor_single_get(lis2mdl_ctx_t *ctx, uint8_t *val) 00515 { 00516 lis2mdl_cfg_reg_b_t reg; 00517 int32_t ret; 00518 00519 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1); 00520 *val = reg.off_canc_one_shot; 00521 00522 return ret; 00523 } 00524 00525 /** 00526 * @brief Blockdataupdate.[set] 00527 * 00528 * @param ctx read / write interface definitions.(ptr) 00529 * @param val change the values of bdu in reg CFG_REG_C 00530 * @retval interface status.(MANDATORY: return 0 -> no Error) 00531 * 00532 */ 00533 int32_t lis2mdl_block_data_update_set(lis2mdl_ctx_t *ctx, uint8_t val) 00534 { 00535 lis2mdl_cfg_reg_c_t reg; 00536 int32_t ret; 00537 00538 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 00539 00540 if (ret == 0) { 00541 reg.bdu = val; 00542 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 00543 } 00544 00545 return ret; 00546 } 00547 00548 /** 00549 * @brief Blockdataupdate.[get] 00550 * 00551 * @param ctx read / write interface definitions.(ptr) 00552 * @param val change the values of bdu in reg CFG_REG_C.(ptr) 00553 * @retval interface status.(MANDATORY: return 0 -> no Error) 00554 * 00555 */ 00556 int32_t lis2mdl_block_data_update_get(lis2mdl_ctx_t *ctx, uint8_t *val) 00557 { 00558 lis2mdl_cfg_reg_c_t reg; 00559 int32_t ret; 00560 00561 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 00562 *val = reg.bdu; 00563 00564 return ret; 00565 } 00566 00567 /** 00568 * @brief Magnetic set of data available.[get] 00569 * 00570 * @param ctx read / write interface definitions.(ptr) 00571 * @param val change the values of zyxda in reg STATUS_REG.(ptr) 00572 * @retval interface status.(MANDATORY: return 0 -> no Error) 00573 * 00574 */ 00575 int32_t lis2mdl_mag_data_ready_get(lis2mdl_ctx_t *ctx, uint8_t *val) 00576 { 00577 lis2mdl_status_reg_t reg; 00578 int32_t ret; 00579 00580 ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *)®, 1); 00581 *val = reg.zyxda; 00582 00583 return ret; 00584 } 00585 00586 /** 00587 * @brief Magnetic set of data overrun.[get] 00588 * 00589 * @param ctx read / write interface definitions.(ptr) 00590 * @param val change the values of zyxor in reg STATUS_REG.(ptr) 00591 * @retval interface status.(MANDATORY: return 0 -> no Error) 00592 * 00593 */ 00594 int32_t lis2mdl_mag_data_ovr_get(lis2mdl_ctx_t *ctx, uint8_t *val) 00595 { 00596 lis2mdl_status_reg_t reg; 00597 int32_t ret; 00598 00599 ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *)®, 1); 00600 *val = reg.zyxor; 00601 00602 return ret; 00603 } 00604 00605 /** 00606 * @brief Magnetic output value.[get] 00607 * 00608 * @param ctx read / write interface definitions.(ptr) 00609 * @param buff that stores data read 00610 * @retval interface status.(MANDATORY: return 0 -> no Error) 00611 * 00612 */ 00613 int32_t lis2mdl_magnetic_raw_get(lis2mdl_ctx_t *ctx, uint8_t *buff) 00614 { 00615 int32_t ret; 00616 ret = lis2mdl_read_reg(ctx, LIS2MDL_OUTX_L_REG, buff, 6); 00617 return ret; 00618 } 00619 00620 /** 00621 * @brief Temperature output value.[get] 00622 * 00623 * @param ctx read / write interface definitions.(ptr) 00624 * @param buff that stores data read 00625 * @retval interface status.(MANDATORY: return 0 -> no Error) 00626 * 00627 */ 00628 int32_t lis2mdl_temperature_raw_get(lis2mdl_ctx_t *ctx, uint8_t *buff) 00629 { 00630 int32_t ret; 00631 ret = lis2mdl_read_reg(ctx, LIS2MDL_TEMP_OUT_L_REG, buff, 2); 00632 return ret; 00633 } 00634 00635 /** 00636 * @} 00637 * 00638 */ 00639 00640 /** 00641 * @defgroup LIS2MDL_common 00642 * @brief This section group common usefull functions 00643 * @{ 00644 * 00645 */ 00646 00647 /** 00648 * @brief DeviceWhoamI.[get] 00649 * 00650 * @param ctx read / write interface definitions.(ptr) 00651 * @param buff that stores data read 00652 * @retval interface status.(MANDATORY: return 0 -> no Error) 00653 * 00654 */ 00655 int32_t lis2mdl_device_id_get(lis2mdl_ctx_t *ctx, uint8_t *buff) 00656 { 00657 int32_t ret; 00658 ret = lis2mdl_read_reg(ctx, LIS2MDL_WHO_AM_I, buff, 1); 00659 return ret; 00660 } 00661 00662 /** 00663 * @brief Software reset. Restore the default values in user registers.[set] 00664 * 00665 * @param ctx read / write interface definitions.(ptr) 00666 * @param val change the values of soft_rst in reg CFG_REG_A 00667 * @retval interface status.(MANDATORY: return 0 -> no Error) 00668 * 00669 */ 00670 int32_t lis2mdl_reset_set(lis2mdl_ctx_t *ctx, uint8_t val) 00671 { 00672 lis2mdl_cfg_reg_a_t reg; 00673 int32_t ret; 00674 00675 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00676 00677 if (ret == 0) { 00678 reg.soft_rst = val; 00679 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00680 } 00681 00682 return ret; 00683 } 00684 00685 /** 00686 * @brief Software reset. Restore the default values in user registers.[get] 00687 * 00688 * @param ctx read / write interface definitions.(ptr) 00689 * @param val change the values of soft_rst in reg CFG_REG_A.(ptr) 00690 * @retval interface status.(MANDATORY: return 0 -> no Error) 00691 * 00692 */ 00693 int32_t lis2mdl_reset_get(lis2mdl_ctx_t *ctx, uint8_t *val) 00694 { 00695 lis2mdl_cfg_reg_a_t reg; 00696 int32_t ret; 00697 00698 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00699 *val = reg.soft_rst; 00700 00701 return ret; 00702 } 00703 00704 /** 00705 * @brief Reboot memory content. Reload the calibration parameters.[set] 00706 * 00707 * @param ctx read / write interface definitions.(ptr) 00708 * @param val change the values of reboot in reg CFG_REG_A 00709 * @retval interface status.(MANDATORY: return 0 -> no Error) 00710 * 00711 */ 00712 int32_t lis2mdl_boot_set(lis2mdl_ctx_t *ctx, uint8_t val) 00713 { 00714 lis2mdl_cfg_reg_a_t reg; 00715 int32_t ret; 00716 00717 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00718 00719 if (ret == 0) { 00720 reg.reboot = val; 00721 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00722 } 00723 00724 return ret; 00725 } 00726 00727 /** 00728 * @brief Reboot memory content. Reload the calibration parameters.[get] 00729 * 00730 * @param ctx read / write interface definitions.(ptr) 00731 * @param val change the values of reboot in reg CFG_REG_A.(ptr) 00732 * @retval interface status.(MANDATORY: return 0 -> no Error) 00733 * 00734 */ 00735 int32_t lis2mdl_boot_get(lis2mdl_ctx_t *ctx, uint8_t *val) 00736 { 00737 lis2mdl_cfg_reg_a_t reg; 00738 int32_t ret; 00739 00740 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); 00741 *val = reg.reboot; 00742 00743 return ret; 00744 } 00745 00746 /** 00747 * @brief Selftest.[set] 00748 * 00749 * @param ctx read / write interface definitions.(ptr) 00750 * @param val change the values of self_test in reg CFG_REG_C 00751 * @retval interface status.(MANDATORY: return 0 -> no Error) 00752 * 00753 */ 00754 int32_t lis2mdl_self_test_set(lis2mdl_ctx_t *ctx, uint8_t val) 00755 { 00756 lis2mdl_cfg_reg_c_t reg; 00757 int32_t ret; 00758 00759 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 00760 00761 if (ret == 0) { 00762 reg.self_test = val; 00763 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 00764 } 00765 00766 return ret; 00767 } 00768 00769 /** 00770 * @brief Selftest.[get] 00771 * 00772 * @param ctx read / write interface definitions.(ptr) 00773 * @param val change the values of self_test in reg CFG_REG_C.(ptr) 00774 * @retval interface status.(MANDATORY: return 0 -> no Error) 00775 * 00776 */ 00777 int32_t lis2mdl_self_test_get(lis2mdl_ctx_t *ctx, uint8_t *val) 00778 { 00779 lis2mdl_cfg_reg_c_t reg; 00780 int32_t ret; 00781 00782 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 00783 *val = reg.self_test; 00784 00785 return ret; 00786 } 00787 00788 /** 00789 * @brief Big/Little Endian data selection.[set] 00790 * 00791 * @param ctx read / write interface definitions.(ptr) 00792 * @param val change the values of ble in reg CFG_REG_C 00793 * @retval interface status.(MANDATORY: return 0 -> no Error) 00794 * 00795 */ 00796 int32_t lis2mdl_data_format_set(lis2mdl_ctx_t *ctx, lis2mdl_ble_t val) 00797 { 00798 lis2mdl_cfg_reg_c_t reg; 00799 int32_t ret; 00800 00801 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 00802 00803 if (ret == 0) { 00804 reg.ble = (uint8_t)val; 00805 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 00806 } 00807 00808 return ret; 00809 } 00810 00811 /** 00812 * @brief Big/Little Endian data selection.[get] 00813 * 00814 * @param ctx read / write interface definitions.(ptr) 00815 * @param val Get the values of ble in reg CFG_REG_C.(ptr) 00816 * @retval interface status.(MANDATORY: return 0 -> no Error) 00817 * 00818 */ 00819 int32_t lis2mdl_data_format_get(lis2mdl_ctx_t *ctx, lis2mdl_ble_t *val) 00820 { 00821 lis2mdl_cfg_reg_c_t reg; 00822 int32_t ret; 00823 00824 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 00825 switch (reg.ble) { 00826 case LIS2MDL_LSB_AT_LOW_ADD: 00827 *val = LIS2MDL_LSB_AT_LOW_ADD; 00828 break; 00829 case LIS2MDL_MSB_AT_LOW_ADD: 00830 *val = LIS2MDL_MSB_AT_LOW_ADD; 00831 break; 00832 default: 00833 *val = LIS2MDL_LSB_AT_LOW_ADD; 00834 break; 00835 } 00836 return ret; 00837 } 00838 00839 /** 00840 * @brief Info about device status.[get] 00841 * 00842 * @param ctx read / write interface definitions.(ptr) 00843 * @param val registers STATUS_REG.(ptr) 00844 * @retval interface status.(MANDATORY: return 0 -> no Error) 00845 * 00846 */ 00847 int32_t lis2mdl_status_get(lis2mdl_ctx_t *ctx, lis2mdl_status_reg_t *val) 00848 { 00849 int32_t ret; 00850 ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *) val, 1); 00851 return ret; 00852 } 00853 00854 /** 00855 * @} 00856 * 00857 */ 00858 00859 /** 00860 * @defgroup LIS2MDL_interrupts 00861 * @brief This section group all the functions that manage interrupts 00862 * @{ 00863 * 00864 */ 00865 00866 /** 00867 * @brief The interrupt block recognition checks data after/before the 00868 * hard-iron correction to discover the interrupt.[set] 00869 * 00870 * @param ctx read / write interface definitions.(ptr) 00871 * @param val change the values of int_on_dataoff in reg CFG_REG_B 00872 * @retval interface status.(MANDATORY: return 0 -> no Error) 00873 * 00874 */ 00875 int32_t lis2mdl_offset_int_conf_set(lis2mdl_ctx_t *ctx, 00876 lis2mdl_int_on_dataoff_t val) 00877 { 00878 lis2mdl_cfg_reg_b_t reg; 00879 int32_t ret; 00880 00881 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1); 00882 00883 if (ret == 0) { 00884 reg.int_on_dataoff = (uint8_t)val; 00885 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1); 00886 } 00887 00888 return ret; 00889 } 00890 00891 /** 00892 * @brief The interrupt block recognition checks data after/before the 00893 * hard-iron correction to discover the interrupt.[get] 00894 * 00895 * @param ctx read / write interface definitions.(ptr) 00896 * @param val Get the values of int_on_dataoff in reg CFG_REG_B.(ptr) 00897 * @retval interface status.(MANDATORY: return 0 -> no Error) 00898 * 00899 */ 00900 int32_t lis2mdl_offset_int_conf_get(lis2mdl_ctx_t *ctx, 00901 lis2mdl_int_on_dataoff_t *val) 00902 { 00903 lis2mdl_cfg_reg_b_t reg; 00904 int32_t ret; 00905 00906 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1); 00907 switch (reg.int_on_dataoff) { 00908 case LIS2MDL_CHECK_BEFORE: 00909 *val = LIS2MDL_CHECK_BEFORE; 00910 break; 00911 case LIS2MDL_CHECK_AFTER: 00912 *val = LIS2MDL_CHECK_AFTER; 00913 break; 00914 default: 00915 *val = LIS2MDL_CHECK_BEFORE; 00916 break; 00917 } 00918 return ret; 00919 } 00920 00921 /** 00922 * @brief Data-ready signal on INT_DRDY pin.[set] 00923 * 00924 * @param ctx read / write interface definitions.(ptr) 00925 * @param val change the values of drdy_on_pin in reg CFG_REG_C 00926 * @retval interface status.(MANDATORY: return 0 -> no Error) 00927 * 00928 */ 00929 int32_t lis2mdl_drdy_on_pin_set(lis2mdl_ctx_t *ctx, uint8_t val) 00930 { 00931 lis2mdl_cfg_reg_c_t reg; 00932 int32_t ret; 00933 00934 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 00935 00936 if (ret == 0) { 00937 reg.drdy_on_pin = val; 00938 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 00939 } 00940 00941 return ret; 00942 } 00943 00944 /** 00945 * @brief Data-ready signal on INT_DRDY pin.[get] 00946 * 00947 * @param ctx read / write interface definitions.(ptr) 00948 * @param val change the values of drdy_on_pin in reg CFG_REG_C.(ptr) 00949 * @retval interface status.(MANDATORY: return 0 -> no Error) 00950 * 00951 */ 00952 int32_t lis2mdl_drdy_on_pin_get(lis2mdl_ctx_t *ctx, uint8_t *val) 00953 { 00954 lis2mdl_cfg_reg_c_t reg; 00955 int32_t ret; 00956 00957 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 00958 *val = reg.drdy_on_pin; 00959 00960 return ret; 00961 } 00962 00963 /** 00964 * @brief Interrupt signal on INT_DRDY pin.[set] 00965 * 00966 * @param ctx read / write interface definitions.(ptr) 00967 * @param val change the values of int_on_pin in reg CFG_REG_C 00968 * @retval interface status.(MANDATORY: return 0 -> no Error) 00969 * 00970 */ 00971 int32_t lis2mdl_int_on_pin_set(lis2mdl_ctx_t *ctx, uint8_t val) 00972 { 00973 lis2mdl_cfg_reg_c_t reg; 00974 int32_t ret; 00975 00976 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 00977 00978 if (ret == 0) { 00979 reg.int_on_pin = val; 00980 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 00981 } 00982 00983 return ret; 00984 } 00985 00986 /** 00987 * @brief Interrupt signal on INT_DRDY pin.[get] 00988 * 00989 * @param ctx read / write interface definitions.(ptr) 00990 * @param val change the values of int_on_pin in reg CFG_REG_C.(ptr) 00991 * @retval interface status.(MANDATORY: return 0 -> no Error) 00992 * 00993 */ 00994 int32_t lis2mdl_int_on_pin_get(lis2mdl_ctx_t *ctx, uint8_t *val) 00995 { 00996 lis2mdl_cfg_reg_c_t reg; 00997 int32_t ret; 00998 00999 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 01000 *val = reg.int_on_pin; 01001 01002 return ret; 01003 } 01004 01005 /** 01006 * @brief Interrupt generator configuration register.[set] 01007 * 01008 * @param ctx read / write interface definitions.(ptr) 01009 * @param val registers INT_CRTL_REG.(ptr) 01010 * @retval interface status.(MANDATORY: return 0 -> no Error) 01011 * 01012 */ 01013 int32_t lis2mdl_int_gen_conf_set(lis2mdl_ctx_t *ctx, 01014 lis2mdl_int_crtl_reg_t *val) 01015 { 01016 int32_t ret; 01017 ret = lis2mdl_write_reg(ctx, LIS2MDL_INT_CRTL_REG, (uint8_t *) val, 1); 01018 return ret; 01019 } 01020 01021 /** 01022 * @brief Interrupt generator configuration register.[get] 01023 * 01024 * @param ctx read / write interface definitions.(ptr) 01025 * @param val registers INT_CRTL_REG.(ptr) 01026 * @retval interface status.(MANDATORY: return 0 -> no Error) 01027 * 01028 */ 01029 int32_t lis2mdl_int_gen_conf_get(lis2mdl_ctx_t *ctx, 01030 lis2mdl_int_crtl_reg_t *val) 01031 { 01032 int32_t ret; 01033 ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_CRTL_REG, (uint8_t *) val, 1); 01034 return ret; 01035 } 01036 01037 /** 01038 * @brief Interrupt generator source register.[get] 01039 * 01040 * @param ctx read / write interface definitions.(ptr) 01041 * @param val registers INT_SOURCE_REG.(ptr) 01042 * @retval interface status.(MANDATORY: return 0 -> no Error) 01043 * 01044 */ 01045 int32_t lis2mdl_int_gen_source_get(lis2mdl_ctx_t *ctx, 01046 lis2mdl_int_source_reg_t *val) 01047 { 01048 int32_t ret; 01049 ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_SOURCE_REG, (uint8_t *) val, 1); 01050 return ret; 01051 } 01052 01053 /** 01054 * @brief User-defined threshold value for xl interrupt event on generator. 01055 * Data format is the same of output data raw: two’s complement with 01056 * 1LSb = 1.5mG.[set] 01057 * 01058 * @param ctx read / write interface definitions.(ptr) 01059 * @param buff that contains data to write 01060 * @retval interface status.(MANDATORY: return 0 -> no Error) 01061 * 01062 */ 01063 int32_t lis2mdl_int_gen_treshold_set(lis2mdl_ctx_t *ctx, uint8_t *buff) 01064 { 01065 int32_t ret; 01066 ret = lis2mdl_write_reg(ctx, LIS2MDL_INT_THS_L_REG, buff, 2); 01067 return ret; 01068 } 01069 01070 /** 01071 * @brief User-defined threshold value for xl interrupt event on generator. 01072 * Data format is the same of output data raw: two’s complement with 01073 * 1LSb = 1.5mG.[get] 01074 * 01075 * @param ctx read / write interface definitions.(ptr) 01076 * @param buff that stores data read 01077 * @retval interface status.(MANDATORY: return 0 -> no Error) 01078 * 01079 */ 01080 int32_t lis2mdl_int_gen_treshold_get(lis2mdl_ctx_t *ctx, uint8_t *buff) 01081 { 01082 int32_t ret; 01083 ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_THS_L_REG, buff, 2); 01084 return ret; 01085 } 01086 01087 /** 01088 * @} 01089 * 01090 */ 01091 01092 /** 01093 * @defgroup LIS2MDL_serial_interface 01094 * @brief This section group all the functions concerning serial 01095 * interface management 01096 * @{ 01097 * 01098 */ 01099 01100 /** 01101 * @brief Enable/Disable I2C interface.[set] 01102 * 01103 * @param ctx read / write interface definitions.(ptr) 01104 * @param val change the values of i2c_dis in reg CFG_REG_C 01105 * @retval interface status.(MANDATORY: return 0 -> no Error) 01106 * 01107 */ 01108 int32_t lis2mdl_i2c_interface_set(lis2mdl_ctx_t *ctx, lis2mdl_i2c_dis_t val) 01109 { 01110 lis2mdl_cfg_reg_c_t reg; 01111 int32_t ret; 01112 01113 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 01114 01115 if (ret == 0) { 01116 reg.i2c_dis = (uint8_t)val; 01117 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 01118 } 01119 01120 return ret; 01121 } 01122 01123 /** 01124 * @brief Enable/Disable I2C interface.[get] 01125 * 01126 * @param ctx read / write interface definitions.(ptr) 01127 * @param val Get the values of i2c_dis in reg CFG_REG_C.(ptr) 01128 * @retval interface status.(MANDATORY: return 0 -> no Error) 01129 * 01130 */ 01131 int32_t lis2mdl_i2c_interface_get(lis2mdl_ctx_t *ctx, lis2mdl_i2c_dis_t *val) 01132 { 01133 lis2mdl_cfg_reg_c_t reg; 01134 int32_t ret; 01135 01136 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); 01137 switch (reg.i2c_dis) { 01138 case LIS2MDL_I2C_ENABLE: 01139 *val = LIS2MDL_I2C_ENABLE; 01140 break; 01141 case LIS2MDL_I2C_DISABLE: 01142 *val = LIS2MDL_I2C_DISABLE; 01143 break; 01144 default: 01145 *val = LIS2MDL_I2C_ENABLE; 01146 break; 01147 } 01148 return ret; 01149 } 01150 01151 /** 01152 * @} 01153 * 01154 */ 01155 01156 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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