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3-axis MEMS ultra low power accelerometer
Dependencies: X_NUCLEO_COMMON ST_INTERFACES
Dependents: X_NUCLEO_IKS01A3 X_NUCLEO_IKS01A3
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lis2dw12_reg.h
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00001 /** 00002 ****************************************************************************** 00003 * @file lis2dw12_reg.h 00004 * @author Sensors Software Solution Team 00005 * @brief This file contains all the functions prototypes for the 00006 * lis2dw12_reg.c driver. 00007 ****************************************************************************** 00008 * @attention 00009 * 00010 * <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2> 00011 * 00012 * Redistribution and use in source and binary forms, with or without 00013 * modification, are permitted provided that the following conditions 00014 * are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright 00018 * notice, this list of conditions and the following disclaimer in the 00019 * documentation and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its 00021 * contributors may be used to endorse or promote products derived from 00022 * this software without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00027 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 00028 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00029 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00032 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00034 * POSSIBILITY OF SUCH DAMAGE. 00035 * 00036 ****************************************************************************** 00037 */ 00038 00039 /* Define to prevent recursive inclusion -------------------------------------*/ 00040 #ifndef LIS2DW12_REGS_H 00041 #define LIS2DW12_REGS_H 00042 00043 #ifdef __cplusplus 00044 extern "C" { 00045 #endif 00046 00047 /* Includes ------------------------------------------------------------------*/ 00048 #include <stdint.h> 00049 #include <math.h> 00050 00051 /** @addtogroup LIS2DW12 00052 * @{ 00053 * 00054 */ 00055 00056 /** @defgroup LIS2DW12_sensors_common_types 00057 * @{ 00058 * 00059 */ 00060 00061 #ifndef MEMS_SHARED_TYPES 00062 #define MEMS_SHARED_TYPES 00063 00064 /** 00065 * @defgroup axisXbitXX_t 00066 * @brief These unions are useful to represent different sensors data type. 00067 * These unions are not need by the driver. 00068 * 00069 * REMOVING the unions you are compliant with: 00070 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 00071 * 00072 * @{ 00073 * 00074 */ 00075 00076 typedef union { 00077 int16_t i16bit[3]; 00078 uint8_t u8bit[6]; 00079 } axis3bit16_t; 00080 00081 typedef union { 00082 int16_t i16bit; 00083 uint8_t u8bit[2]; 00084 } axis1bit16_t; 00085 00086 typedef union { 00087 int32_t i32bit[3]; 00088 uint8_t u8bit[12]; 00089 } axis3bit32_t; 00090 00091 typedef union { 00092 int32_t i32bit; 00093 uint8_t u8bit[4]; 00094 } axis1bit32_t; 00095 00096 /** 00097 * @} 00098 * 00099 */ 00100 00101 typedef struct { 00102 uint8_t bit0 : 1; 00103 uint8_t bit1 : 1; 00104 uint8_t bit2 : 1; 00105 uint8_t bit3 : 1; 00106 uint8_t bit4 : 1; 00107 uint8_t bit5 : 1; 00108 uint8_t bit6 : 1; 00109 uint8_t bit7 : 1; 00110 } bitwise_t; 00111 00112 #define PROPERTY_DISABLE (0U) 00113 #define PROPERTY_ENABLE (1U) 00114 00115 #endif /* MEMS_SHARED_TYPES */ 00116 00117 /** 00118 * @} 00119 * 00120 */ 00121 00122 /** @addtogroup LIS2DW12_Interfaces_Functions 00123 * @brief This section provide a set of functions used to read and 00124 * write a generic register of the device. 00125 * MANDATORY: return 0 -> no Error. 00126 * @{ 00127 * 00128 */ 00129 00130 typedef int32_t (*lis2dw12_write_ptr)(void *, uint8_t, uint8_t *, uint16_t); 00131 typedef int32_t (*lis2dw12_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 00132 00133 typedef struct { 00134 /** Component mandatory fields **/ 00135 lis2dw12_write_ptr write_reg; 00136 lis2dw12_read_ptr read_reg; 00137 /** Customizable optional pointer **/ 00138 void *handle; 00139 } lis2dw12_ctx_t; 00140 00141 /** 00142 * @} 00143 * 00144 */ 00145 00146 /** @defgroup LIS2DW12_Infos 00147 * @{ 00148 * 00149 */ 00150 00151 /** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/ 00152 #define LIS2DW12_I2C_ADD_L 0x31U 00153 #define LIS2DW12_I2C_ADD_H 0x33U 00154 00155 /** Device Identification (Who am I) **/ 00156 #define LIS2DW12_ID 0x44U 00157 00158 /** 00159 * @} 00160 * 00161 */ 00162 00163 /** 00164 * @addtogroup LIS2DW12_Sensitivity 00165 * @brief These macro are maintained for back compatibility. 00166 * in order to convert data into engineering units please 00167 * use functions: 00168 * -> _from_fs2_to_mg(int16_t lsb); 00169 * -> _from_fs4_to_mg(int16_t lsb); 00170 * -> _from_fs8_to_mg(int16_t lsb); 00171 * -> _from_fs16_to_mg(int16_t lsb); 00172 * -> _from_fs2_lp1_to_mg(int16_t lsb); 00173 * -> _from_fs4_lp1_to_mg(int16_t lsb); 00174 * -> _from_fs8_lp1_to_mg(int16_t lsb); 00175 * -> _from_fs16_lp1_to_mg(int16_t lsb); 00176 * -> _from_lsb_to_celsius(int16_t lsb); 00177 * 00178 * REMOVING the MACRO you are compliant with: 00179 * MISRA-C 2012 [Dir 4.9] -> " avoid function-like macros " 00180 * @{ 00181 * 00182 */ 00183 00184 #define LIS2DW12_FROM_FS_2g_TO_mg(lsb) (float)((int16_t)lsb >> 2) * 0.244f 00185 #define LIS2DW12_FROM_FS_4g_TO_mg(lsb) (float)((int16_t)lsb >> 2) * 0.488f 00186 #define LIS2DW12_FROM_FS_8g_TO_mg(lsb) (float)((int16_t)lsb >> 2) * 0.976f 00187 #define LIS2DW12_FROM_FS_16g_TO_mg(lsb) (float)((int16_t)lsb >> 2) * 1.952f 00188 00189 #define LIS2DW12_FROM_FS_2g_LP1_TO_mg(lsb) (float)((int16_t)lsb>>4)* 0.976f 00190 #define LIS2DW12_FROM_FS_4g_LP1_TO_mg(lsb) (float)((int16_t)lsb>>4)* 1.952f 00191 #define LIS2DW12_FROM_FS_8g_LP1_TO_mg(lsb) (float)((int16_t)lsb>>4)* 3.904f 00192 #define LIS2DW12_FROM_FS_16g_LP1_TO_mg(lsb) (float)((int16_t)lsb>>4)* 7.808f 00193 00194 #define LIS2DW12_FROM_LSB_TO_degC(lsb) (float)((int16_t)lsb) / 16.0f+25.0f 00195 00196 /** 00197 * @} 00198 * 00199 */ 00200 00201 #define LIS2DW12_OUT_T_L 0x0DU 00202 #define LIS2DW12_OUT_T_H 0x0EU 00203 #define LIS2DW12_WHO_AM_I 0x0FU 00204 #define LIS2DW12_CTRL1 0x20U 00205 typedef struct { 00206 uint8_t lp_mode : 2; 00207 uint8_t mode : 2; 00208 uint8_t odr : 4; 00209 } lis2dw12_ctrl1_t; 00210 00211 #define LIS2DW12_CTRL2 0x21U 00212 typedef struct { 00213 uint8_t sim : 1; 00214 uint8_t i2c_disable : 1; 00215 uint8_t if_add_inc : 1; 00216 uint8_t bdu : 1; 00217 uint8_t cs_pu_disc : 1; 00218 uint8_t not_used_01 : 1; 00219 uint8_t soft_reset : 1; 00220 uint8_t boot : 1; 00221 } lis2dw12_ctrl2_t; 00222 00223 #define LIS2DW12_CTRL3 0x22U 00224 typedef struct { 00225 uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */ 00226 uint8_t not_used_01 : 1; 00227 uint8_t h_lactive : 1; 00228 uint8_t lir : 1; 00229 uint8_t pp_od : 1; 00230 uint8_t st : 2; 00231 } lis2dw12_ctrl3_t; 00232 00233 #define LIS2DW12_CTRL4_INT1_PAD_CTRL 0x23U 00234 typedef struct { 00235 uint8_t int1_drdy : 1; 00236 uint8_t int1_fth : 1; 00237 uint8_t int1_diff5 : 1; 00238 uint8_t int1_tap : 1; 00239 uint8_t int1_ff : 1; 00240 uint8_t int1_wu : 1; 00241 uint8_t int1_single_tap : 1; 00242 uint8_t int1_6d : 1; 00243 } lis2dw12_ctrl4_int1_pad_ctrl_t; 00244 00245 #define LIS2DW12_CTRL5_INT2_PAD_CTRL 0x24U 00246 typedef struct { 00247 uint8_t int2_drdy : 1; 00248 uint8_t int2_fth : 1; 00249 uint8_t int2_diff5 : 1; 00250 uint8_t int2_ovr : 1; 00251 uint8_t int2_drdy_t : 1; 00252 uint8_t int2_boot : 1; 00253 uint8_t int2_sleep_chg : 1; 00254 uint8_t int2_sleep_state : 1; 00255 } lis2dw12_ctrl5_int2_pad_ctrl_t; 00256 00257 #define LIS2DW12_CTRL6 0x25U 00258 typedef struct { 00259 uint8_t not_used_01 : 2; 00260 uint8_t low_noise : 1; 00261 uint8_t fds : 1; 00262 uint8_t fs : 2; 00263 uint8_t bw_filt : 2; 00264 } lis2dw12_ctrl6_t; 00265 00266 #define LIS2DW12_OUT_T 0x26U 00267 #define LIS2DW12_STATUS 0x27U 00268 typedef struct { 00269 uint8_t drdy : 1; 00270 uint8_t ff_ia : 1; 00271 uint8_t _6d_ia : 1; 00272 uint8_t single_tap : 1; 00273 uint8_t double_tap : 1; 00274 uint8_t sleep_state : 1; 00275 uint8_t wu_ia : 1; 00276 uint8_t fifo_ths : 1; 00277 } lis2dw12_status_t; 00278 00279 #define LIS2DW12_OUT_X_L 0x28U 00280 #define LIS2DW12_OUT_X_H 0x29U 00281 #define LIS2DW12_OUT_Y_L 0x2AU 00282 #define LIS2DW12_OUT_Y_H 0x2BU 00283 #define LIS2DW12_OUT_Z_L 0x2CU 00284 #define LIS2DW12_OUT_Z_H 0x2DU 00285 #define LIS2DW12_FIFO_CTRL 0x2EU 00286 typedef struct { 00287 uint8_t fth : 5; 00288 uint8_t fmode : 3; 00289 } lis2dw12_fifo_ctrl_t; 00290 00291 #define LIS2DW12_FIFO_SAMPLES 0x2FU 00292 typedef struct { 00293 uint8_t diff : 6; 00294 uint8_t fifo_ovr : 1; 00295 uint8_t fifo_fth : 1; 00296 } lis2dw12_fifo_samples_t; 00297 00298 #define LIS2DW12_TAP_THS_X 0x30U 00299 typedef struct { 00300 uint8_t tap_thsx : 5; 00301 uint8_t _6d_ths : 2; 00302 uint8_t _4d_en : 1; 00303 } lis2dw12_tap_ths_x_t; 00304 00305 #define LIS2DW12_TAP_THS_Y 0x31U 00306 typedef struct { 00307 uint8_t tap_thsy : 5; 00308 uint8_t tap_prior : 3; 00309 } lis2dw12_tap_ths_y_t; 00310 00311 #define LIS2DW12_TAP_THS_Z 0x32U 00312 typedef struct { 00313 uint8_t tap_thsz : 5; 00314 uint8_t tap_z_en : 1; 00315 uint8_t tap_y_en : 1; 00316 uint8_t tap_x_en : 1; 00317 } lis2dw12_tap_ths_z_t; 00318 00319 #define LIS2DW12_INT_DUR 0x33U 00320 typedef struct { 00321 uint8_t shock : 2; 00322 uint8_t quiet : 2; 00323 uint8_t latency : 4; 00324 } lis2dw12_int_dur_t; 00325 00326 #define LIS2DW12_WAKE_UP_THS 0x34U 00327 typedef struct { 00328 uint8_t wk_ths : 6; 00329 uint8_t sleep_on : 1; 00330 uint8_t single_double_tap : 1; 00331 } lis2dw12_wake_up_ths_t; 00332 00333 #define LIS2DW12_WAKE_UP_DUR 0x35U 00334 typedef struct { 00335 uint8_t sleep_dur : 4; 00336 uint8_t stationary : 1; 00337 uint8_t wake_dur : 2; 00338 uint8_t ff_dur : 1; 00339 } lis2dw12_wake_up_dur_t; 00340 00341 #define LIS2DW12_FREE_FALL 0x36U 00342 typedef struct { 00343 uint8_t ff_ths : 3; 00344 uint8_t ff_dur : 5; 00345 } lis2dw12_free_fall_t; 00346 00347 #define LIS2DW12_STATUS_DUP 0x37U 00348 typedef struct { 00349 uint8_t drdy : 1; 00350 uint8_t ff_ia : 1; 00351 uint8_t _6d_ia : 1; 00352 uint8_t single_tap : 1; 00353 uint8_t double_tap : 1; 00354 uint8_t sleep_state_ia : 1; 00355 uint8_t drdy_t : 1; 00356 uint8_t ovr : 1; 00357 } lis2dw12_status_dup_t; 00358 00359 #define LIS2DW12_WAKE_UP_SRC 0x38U 00360 typedef struct { 00361 uint8_t z_wu : 1; 00362 uint8_t y_wu : 1; 00363 uint8_t x_wu : 1; 00364 uint8_t wu_ia : 1; 00365 uint8_t sleep_state_ia : 1; 00366 uint8_t ff_ia : 1; 00367 uint8_t not_used_01 : 2; 00368 } lis2dw12_wake_up_src_t; 00369 00370 #define LIS2DW12_TAP_SRC 0x39U 00371 typedef struct { 00372 uint8_t z_tap : 1; 00373 uint8_t y_tap : 1; 00374 uint8_t x_tap : 1; 00375 uint8_t tap_sign : 1; 00376 uint8_t double_tap : 1; 00377 uint8_t single_tap : 1; 00378 uint8_t tap_ia : 1; 00379 uint8_t not_used_01 : 1; 00380 } lis2dw12_tap_src_t; 00381 00382 #define LIS2DW12_SIXD_SRC 0x3AU 00383 typedef struct { 00384 uint8_t xl : 1; 00385 uint8_t xh : 1; 00386 uint8_t yl : 1; 00387 uint8_t yh : 1; 00388 uint8_t zl : 1; 00389 uint8_t zh : 1; 00390 uint8_t _6d_ia : 1; 00391 uint8_t not_used_01 : 1; 00392 } lis2dw12_sixd_src_t; 00393 00394 #define LIS2DW12_ALL_INT_SRC 0x3BU 00395 typedef struct { 00396 uint8_t ff_ia : 1; 00397 uint8_t wu_ia : 1; 00398 uint8_t single_tap : 1; 00399 uint8_t double_tap : 1; 00400 uint8_t _6d_ia : 1; 00401 uint8_t sleep_change_ia : 1; 00402 uint8_t not_used_01 : 2; 00403 } lis2dw12_all_int_src_t; 00404 00405 #define LIS2DW12_X_OFS_USR 0x3CU 00406 #define LIS2DW12_Y_OFS_USR 0x3DU 00407 #define LIS2DW12_Z_OFS_USR 0x3EU 00408 #define LIS2DW12_CTRL_REG7 0x3FU 00409 typedef struct { 00410 uint8_t lpass_on6d : 1; 00411 uint8_t hp_ref_mode : 1; 00412 uint8_t usr_off_w : 1; 00413 uint8_t usr_off_on_wu : 1; 00414 uint8_t usr_off_on_out : 1; 00415 uint8_t interrupts_enable : 1; 00416 uint8_t int2_on_int1 : 1; 00417 uint8_t drdy_pulsed : 1; 00418 } lis2dw12_ctrl_reg7_t; 00419 00420 /** 00421 * @defgroup LIS2DW12_Register_Union 00422 * @brief This union group all the registers that has a bitfield 00423 * description. 00424 * This union is useful but not need by the driver. 00425 * 00426 * REMOVING this union you are compliant with: 00427 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 00428 * 00429 * @{ 00430 * 00431 */ 00432 typedef union { 00433 lis2dw12_ctrl1_t ctrl1; 00434 lis2dw12_ctrl2_t ctrl2; 00435 lis2dw12_ctrl3_t ctrl3; 00436 lis2dw12_ctrl4_int1_pad_ctrl_t ctrl4_int1_pad_ctrl; 00437 lis2dw12_ctrl5_int2_pad_ctrl_t ctrl5_int2_pad_ctrl; 00438 lis2dw12_ctrl6_t ctrl6; 00439 lis2dw12_status_t status; 00440 lis2dw12_fifo_ctrl_t fifo_ctrl; 00441 lis2dw12_fifo_samples_t fifo_samples; 00442 lis2dw12_tap_ths_x_t tap_ths_x; 00443 lis2dw12_tap_ths_y_t tap_ths_y; 00444 lis2dw12_tap_ths_z_t tap_ths_z; 00445 lis2dw12_int_dur_t int_dur; 00446 lis2dw12_wake_up_ths_t wake_up_ths; 00447 lis2dw12_wake_up_dur_t wake_up_dur; 00448 lis2dw12_free_fall_t free_fall; 00449 lis2dw12_status_dup_t status_dup; 00450 lis2dw12_wake_up_src_t wake_up_src; 00451 lis2dw12_tap_src_t tap_src; 00452 lis2dw12_sixd_src_t sixd_src; 00453 lis2dw12_all_int_src_t all_int_src; 00454 lis2dw12_ctrl_reg7_t ctrl_reg7; 00455 bitwise_t bitwise; 00456 uint8_t byte; 00457 } lis2dw12_reg_t; 00458 00459 /** 00460 * @} 00461 * 00462 */ 00463 00464 int32_t lis2dw12_read_reg(lis2dw12_ctx_t *ctx, uint8_t reg, uint8_t *data, 00465 uint16_t len); 00466 int32_t lis2dw12_write_reg(lis2dw12_ctx_t *ctx, uint8_t reg, uint8_t *data, 00467 uint16_t len); 00468 00469 extern float lis2dw12_from_fs2_to_mg(int16_t lsb); 00470 extern float lis2dw12_from_fs4_to_mg(int16_t lsb); 00471 extern float lis2dw12_from_fs8_to_mg(int16_t lsb); 00472 extern float lis2dw12_from_fs16_to_mg(int16_t lsb); 00473 extern float lis2dw12_from_fs2_lp1_to_mg(int16_t lsb); 00474 extern float lis2dw12_from_fs4_lp1_to_mg(int16_t lsb); 00475 extern float lis2dw12_from_fs8_lp1_to_mg(int16_t lsb); 00476 extern float lis2dw12_from_fs16_lp1_to_mg(int16_t lsb); 00477 extern float lis2dw12_from_lsb_to_celsius(int16_t lsb); 00478 00479 typedef enum { 00480 LIS2DW12_HIGH_PERFORMANCE = 0x04, 00481 LIS2DW12_CONT_LOW_PWR_4 = 0x03, 00482 LIS2DW12_CONT_LOW_PWR_3 = 0x02, 00483 LIS2DW12_CONT_LOW_PWR_2 = 0x01, 00484 LIS2DW12_CONT_LOW_PWR_12bit = 0x00, 00485 LIS2DW12_SINGLE_LOW_PWR_4 = 0x0B, 00486 LIS2DW12_SINGLE_LOW_PWR_3 = 0x0A, 00487 LIS2DW12_SINGLE_LOW_PWR_2 = 0x09, 00488 LIS2DW12_SINGLE_LOW_PWR_12bit = 0x08, 00489 LIS2DW12_HIGH_PERFORMANCE_LOW_NOISE = 0x14, 00490 LIS2DW12_CONT_LOW_PWR_LOW_NOISE_4 = 0x13, 00491 LIS2DW12_CONT_LOW_PWR_LOW_NOISE_3 = 0x12, 00492 LIS2DW12_CONT_LOW_PWR_LOW_NOISE_2 = 0x11, 00493 LIS2DW12_CONT_LOW_PWR_LOW_NOISE_12bit = 0x10, 00494 LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_4 = 0x1B, 00495 LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_3 = 0x1A, 00496 LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2 = 0x19, 00497 LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit = 0x18, 00498 } lis2dw12_mode_t; 00499 int32_t lis2dw12_power_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_mode_t val); 00500 int32_t lis2dw12_power_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_mode_t *val); 00501 00502 typedef enum { 00503 LIS2DW12_XL_ODR_OFF = 0x00, 00504 LIS2DW12_XL_ODR_1Hz6_LP_ONLY = 0x01, 00505 LIS2DW12_XL_ODR_12Hz5 = 0x02, 00506 LIS2DW12_XL_ODR_25Hz = 0x03, 00507 LIS2DW12_XL_ODR_50Hz = 0x04, 00508 LIS2DW12_XL_ODR_100Hz = 0x05, 00509 LIS2DW12_XL_ODR_200Hz = 0x06, 00510 LIS2DW12_XL_ODR_400Hz = 0x07, 00511 LIS2DW12_XL_ODR_800Hz = 0x08, 00512 LIS2DW12_XL_ODR_1k6Hz = 0x09, 00513 LIS2DW12_XL_SET_SW_TRIG = 0x10, /* Use this only in SINGLE mode */ 00514 LIS2DW12_XL_SET_PIN_TRIG = 0x20, /* Use this only in SINGLE mode */ 00515 } lis2dw12_odr_t; 00516 int32_t lis2dw12_data_rate_set(lis2dw12_ctx_t *ctx, lis2dw12_odr_t val); 00517 int32_t lis2dw12_data_rate_get(lis2dw12_ctx_t *ctx, lis2dw12_odr_t *val); 00518 00519 int32_t lis2dw12_block_data_update_set(lis2dw12_ctx_t *ctx, uint8_t val); 00520 int32_t lis2dw12_block_data_update_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00521 00522 typedef enum { 00523 LIS2DW12_2g = 0, 00524 LIS2DW12_4g = 1, 00525 LIS2DW12_8g = 2, 00526 LIS2DW12_16g = 3, 00527 } lis2dw12_fs_t; 00528 int32_t lis2dw12_full_scale_set(lis2dw12_ctx_t *ctx, lis2dw12_fs_t val); 00529 int32_t lis2dw12_full_scale_get(lis2dw12_ctx_t *ctx, lis2dw12_fs_t *val); 00530 00531 int32_t lis2dw12_status_reg_get(lis2dw12_ctx_t *ctx, lis2dw12_status_t *val); 00532 00533 int32_t lis2dw12_flag_data_ready_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00534 00535 typedef struct { 00536 lis2dw12_status_dup_t status_dup; 00537 lis2dw12_wake_up_src_t wake_up_src; 00538 lis2dw12_tap_src_t tap_src; 00539 lis2dw12_sixd_src_t sixd_src; 00540 lis2dw12_all_int_src_t all_int_src; 00541 } lis2dw12_all_sources_t; 00542 int32_t lis2dw12_all_sources_get(lis2dw12_ctx_t *ctx, 00543 lis2dw12_all_sources_t *val); 00544 00545 int32_t lis2dw12_usr_offset_x_set(lis2dw12_ctx_t *ctx, uint8_t *buff); 00546 int32_t lis2dw12_usr_offset_x_get(lis2dw12_ctx_t *ctx, uint8_t *buff); 00547 00548 int32_t lis2dw12_usr_offset_y_set(lis2dw12_ctx_t *ctx, uint8_t *buff); 00549 int32_t lis2dw12_usr_offset_y_get(lis2dw12_ctx_t *ctx, uint8_t *buff); 00550 00551 int32_t lis2dw12_usr_offset_z_set(lis2dw12_ctx_t *ctx, uint8_t *buff); 00552 int32_t lis2dw12_usr_offset_z_get(lis2dw12_ctx_t *ctx, uint8_t *buff); 00553 00554 typedef enum { 00555 LIS2DW12_LSb_977ug = 0, 00556 LIS2DW12_LSb_15mg6 = 1, 00557 } lis2dw12_usr_off_w_t; 00558 int32_t lis2dw12_offset_weight_set(lis2dw12_ctx_t *ctx, 00559 lis2dw12_usr_off_w_t val); 00560 int32_t lis2dw12_offset_weight_get(lis2dw12_ctx_t *ctx, 00561 lis2dw12_usr_off_w_t *val); 00562 00563 int32_t lis2dw12_temperature_raw_get(lis2dw12_ctx_t *ctx, uint8_t *buff); 00564 00565 int32_t lis2dw12_acceleration_raw_get(lis2dw12_ctx_t *ctx, uint8_t *buff); 00566 00567 int32_t lis2dw12_device_id_get(lis2dw12_ctx_t *ctx, uint8_t *buff); 00568 00569 int32_t lis2dw12_auto_increment_set(lis2dw12_ctx_t *ctx, uint8_t val); 00570 int32_t lis2dw12_auto_increment_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00571 00572 int32_t lis2dw12_reset_set(lis2dw12_ctx_t *ctx, uint8_t val); 00573 int32_t lis2dw12_reset_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00574 00575 int32_t lis2dw12_boot_set(lis2dw12_ctx_t *ctx, uint8_t val); 00576 int32_t lis2dw12_boot_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00577 00578 typedef enum { 00579 LIS2DW12_XL_ST_DISABLE = 0, 00580 LIS2DW12_XL_ST_POSITIVE = 1, 00581 LIS2DW12_XL_ST_NEGATIVE = 2, 00582 } lis2dw12_st_t; 00583 int32_t lis2dw12_self_test_set(lis2dw12_ctx_t *ctx, lis2dw12_st_t val); 00584 int32_t lis2dw12_self_test_get(lis2dw12_ctx_t *ctx, lis2dw12_st_t *val); 00585 00586 typedef enum { 00587 LIS2DW12_DRDY_LATCHED = 0, 00588 LIS2DW12_DRDY_PULSED = 1, 00589 } lis2dw12_drdy_pulsed_t; 00590 int32_t lis2dw12_data_ready_mode_set(lis2dw12_ctx_t *ctx, 00591 lis2dw12_drdy_pulsed_t val); 00592 int32_t lis2dw12_data_ready_mode_get(lis2dw12_ctx_t *ctx, 00593 lis2dw12_drdy_pulsed_t *val); 00594 00595 typedef enum { 00596 LIS2DW12_LPF_ON_OUT = 0x00, 00597 LIS2DW12_USER_OFFSET_ON_OUT = 0x01, 00598 LIS2DW12_HIGH_PASS_ON_OUT = 0x10, 00599 } lis2dw12_fds_t; 00600 int32_t lis2dw12_filter_path_set(lis2dw12_ctx_t *ctx, lis2dw12_fds_t val); 00601 int32_t lis2dw12_filter_path_get(lis2dw12_ctx_t *ctx, lis2dw12_fds_t *val); 00602 00603 typedef enum { 00604 LIS2DW12_ODR_DIV_2 = 0, 00605 LIS2DW12_ODR_DIV_4 = 1, 00606 LIS2DW12_ODR_DIV_10 = 2, 00607 LIS2DW12_ODR_DIV_20 = 3, 00608 } lis2dw12_bw_filt_t; 00609 int32_t lis2dw12_filter_bandwidth_set(lis2dw12_ctx_t *ctx, 00610 lis2dw12_bw_filt_t val); 00611 int32_t lis2dw12_filter_bandwidth_get(lis2dw12_ctx_t *ctx, 00612 lis2dw12_bw_filt_t *val); 00613 00614 int32_t lis2dw12_reference_mode_set(lis2dw12_ctx_t *ctx, uint8_t val); 00615 int32_t lis2dw12_reference_mode_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00616 00617 typedef enum { 00618 LIS2DW12_SPI_4_WIRE = 0, 00619 LIS2DW12_SPI_3_WIRE = 1, 00620 } lis2dw12_sim_t; 00621 int32_t lis2dw12_spi_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_sim_t val); 00622 int32_t lis2dw12_spi_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_sim_t *val); 00623 00624 typedef enum { 00625 LIS2DW12_I2C_ENABLE = 0, 00626 LIS2DW12_I2C_DISABLE = 1, 00627 } lis2dw12_i2c_disable_t; 00628 int32_t lis2dw12_i2c_interface_set(lis2dw12_ctx_t *ctx, 00629 lis2dw12_i2c_disable_t val); 00630 int32_t lis2dw12_i2c_interface_get(lis2dw12_ctx_t *ctx, 00631 lis2dw12_i2c_disable_t *val); 00632 00633 typedef enum { 00634 LIS2DW12_PULL_UP_CONNECT = 0, 00635 LIS2DW12_PULL_UP_DISCONNECT = 1, 00636 } lis2dw12_cs_pu_disc_t; 00637 int32_t lis2dw12_cs_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_cs_pu_disc_t val); 00638 int32_t lis2dw12_cs_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_cs_pu_disc_t *val); 00639 00640 typedef enum { 00641 LIS2DW12_ACTIVE_HIGH = 0, 00642 LIS2DW12_ACTIVE_LOW = 1, 00643 } lis2dw12_h_lactive_t; 00644 int32_t lis2dw12_pin_polarity_set(lis2dw12_ctx_t *ctx, 00645 lis2dw12_h_lactive_t val); 00646 int32_t lis2dw12_pin_polarity_get(lis2dw12_ctx_t *ctx, 00647 lis2dw12_h_lactive_t *val); 00648 00649 typedef enum { 00650 LIS2DW12_INT_PULSED = 0, 00651 LIS2DW12_INT_LATCHED = 1, 00652 } lis2dw12_lir_t; 00653 int32_t lis2dw12_int_notification_set(lis2dw12_ctx_t *ctx, 00654 lis2dw12_lir_t val); 00655 int32_t lis2dw12_int_notification_get(lis2dw12_ctx_t *ctx, 00656 lis2dw12_lir_t *val); 00657 00658 typedef enum { 00659 LIS2DW12_PUSH_PULL = 0, 00660 LIS2DW12_OPEN_DRAIN = 1, 00661 } lis2dw12_pp_od_t; 00662 int32_t lis2dw12_pin_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_pp_od_t val); 00663 int32_t lis2dw12_pin_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_pp_od_t *val); 00664 00665 int32_t lis2dw12_pin_int1_route_set(lis2dw12_ctx_t *ctx, 00666 lis2dw12_ctrl4_int1_pad_ctrl_t *val); 00667 int32_t lis2dw12_pin_int1_route_get(lis2dw12_ctx_t *ctx, 00668 lis2dw12_ctrl4_int1_pad_ctrl_t *val); 00669 00670 int32_t lis2dw12_pin_int2_route_set(lis2dw12_ctx_t *ctx, 00671 lis2dw12_ctrl5_int2_pad_ctrl_t *val); 00672 int32_t lis2dw12_pin_int2_route_get(lis2dw12_ctx_t *ctx, 00673 lis2dw12_ctrl5_int2_pad_ctrl_t *val); 00674 00675 int32_t lis2dw12_all_on_int1_set(lis2dw12_ctx_t *ctx, uint8_t val); 00676 int32_t lis2dw12_all_on_int1_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00677 00678 int32_t lis2dw12_wkup_threshold_set(lis2dw12_ctx_t *ctx, uint8_t val); 00679 int32_t lis2dw12_wkup_threshold_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00680 00681 int32_t lis2dw12_wkup_dur_set(lis2dw12_ctx_t *ctx, uint8_t val); 00682 int32_t lis2dw12_wkup_dur_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00683 00684 typedef enum { 00685 LIS2DW12_HP_FEED = 0, 00686 LIS2DW12_USER_OFFSET_FEED = 1, 00687 } lis2dw12_usr_off_on_wu_t; 00688 int32_t lis2dw12_wkup_feed_data_set(lis2dw12_ctx_t *ctx, 00689 lis2dw12_usr_off_on_wu_t val); 00690 int32_t lis2dw12_wkup_feed_data_get(lis2dw12_ctx_t *ctx, 00691 lis2dw12_usr_off_on_wu_t *val); 00692 00693 typedef enum { 00694 LIS2DW12_NO_DETECTION = 0, 00695 LIS2DW12_DETECT_ACT_INACT = 1, 00696 LIS2DW12_DETECT_STAT_MOTION = 3, 00697 } lis2dw12_sleep_on_t; 00698 int32_t lis2dw12_act_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_sleep_on_t val); 00699 int32_t lis2dw12_act_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_sleep_on_t *val); 00700 00701 int32_t lis2dw12_act_sleep_dur_set(lis2dw12_ctx_t *ctx, uint8_t val); 00702 int32_t lis2dw12_act_sleep_dur_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00703 00704 int32_t lis2dw12_tap_threshold_x_set(lis2dw12_ctx_t *ctx, uint8_t val); 00705 int32_t lis2dw12_tap_threshold_x_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00706 00707 int32_t lis2dw12_tap_threshold_y_set(lis2dw12_ctx_t *ctx, uint8_t val); 00708 int32_t lis2dw12_tap_threshold_y_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00709 00710 typedef enum { 00711 LIS2DW12_XYZ = 0, 00712 LIS2DW12_YXZ = 1, 00713 LIS2DW12_XZY = 2, 00714 LIS2DW12_ZYX = 3, 00715 LIS2DW12_YZX = 5, 00716 LIS2DW12_ZXY = 6, 00717 } lis2dw12_tap_prior_t; 00718 int32_t lis2dw12_tap_axis_priority_set(lis2dw12_ctx_t *ctx, 00719 lis2dw12_tap_prior_t val); 00720 int32_t lis2dw12_tap_axis_priority_get(lis2dw12_ctx_t *ctx, 00721 lis2dw12_tap_prior_t *val); 00722 00723 int32_t lis2dw12_tap_threshold_z_set(lis2dw12_ctx_t *ctx, uint8_t val); 00724 int32_t lis2dw12_tap_threshold_z_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00725 00726 int32_t lis2dw12_tap_detection_on_z_set(lis2dw12_ctx_t *ctx, uint8_t val); 00727 int32_t lis2dw12_tap_detection_on_z_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00728 00729 int32_t lis2dw12_tap_detection_on_y_set(lis2dw12_ctx_t *ctx, uint8_t val); 00730 int32_t lis2dw12_tap_detection_on_y_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00731 00732 int32_t lis2dw12_tap_detection_on_x_set(lis2dw12_ctx_t *ctx, uint8_t val); 00733 int32_t lis2dw12_tap_detection_on_x_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00734 00735 int32_t lis2dw12_tap_shock_set(lis2dw12_ctx_t *ctx, uint8_t val); 00736 int32_t lis2dw12_tap_shock_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00737 00738 int32_t lis2dw12_tap_quiet_set(lis2dw12_ctx_t *ctx, uint8_t val); 00739 int32_t lis2dw12_tap_quiet_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00740 00741 int32_t lis2dw12_tap_dur_set(lis2dw12_ctx_t *ctx, uint8_t val); 00742 int32_t lis2dw12_tap_dur_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00743 00744 typedef enum { 00745 LIS2DW12_ONLY_SINGLE = 0, 00746 LIS2DW12_BOTH_SINGLE_DOUBLE = 1, 00747 } lis2dw12_single_double_tap_t; 00748 int32_t lis2dw12_tap_mode_set(lis2dw12_ctx_t *ctx, 00749 lis2dw12_single_double_tap_t val); 00750 int32_t lis2dw12_tap_mode_get(lis2dw12_ctx_t *ctx, 00751 lis2dw12_single_double_tap_t *val); 00752 00753 int32_t lis2dw12_tap_src_get(lis2dw12_ctx_t *ctx, lis2dw12_tap_src_t *val); 00754 00755 int32_t lis2dw12_6d_threshold_set(lis2dw12_ctx_t *ctx, uint8_t val); 00756 int32_t lis2dw12_6d_threshold_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00757 00758 int32_t lis2dw12_4d_mode_set(lis2dw12_ctx_t *ctx, uint8_t val); 00759 int32_t lis2dw12_4d_mode_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00760 00761 int32_t lis2dw12_6d_src_get(lis2dw12_ctx_t *ctx, lis2dw12_sixd_src_t *val); 00762 00763 typedef enum { 00764 LIS2DW12_ODR_DIV_2_FEED = 0, 00765 LIS2DW12_LPF2_FEED = 1, 00766 } lis2dw12_lpass_on6d_t; 00767 int32_t lis2dw12_6d_feed_data_set(lis2dw12_ctx_t *ctx, 00768 lis2dw12_lpass_on6d_t val); 00769 int32_t lis2dw12_6d_feed_data_get(lis2dw12_ctx_t *ctx, 00770 lis2dw12_lpass_on6d_t *val); 00771 00772 int32_t lis2dw12_ff_dur_set(lis2dw12_ctx_t *ctx, uint8_t val); 00773 int32_t lis2dw12_ff_dur_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00774 00775 typedef enum { 00776 LIS2DW12_FF_TSH_5LSb_FS2g = 0, 00777 LIS2DW12_FF_TSH_7LSb_FS2g = 1, 00778 LIS2DW12_FF_TSH_8LSb_FS2g = 2, 00779 LIS2DW12_FF_TSH_10LSb_FS2g = 3, 00780 LIS2DW12_FF_TSH_11LSb_FS2g = 4, 00781 LIS2DW12_FF_TSH_13LSb_FS2g = 5, 00782 LIS2DW12_FF_TSH_15LSb_FS2g = 6, 00783 LIS2DW12_FF_TSH_16LSb_FS2g = 7, 00784 } lis2dw12_ff_ths_t; 00785 int32_t lis2dw12_ff_threshold_set(lis2dw12_ctx_t *ctx, 00786 lis2dw12_ff_ths_t val); 00787 int32_t lis2dw12_ff_threshold_get(lis2dw12_ctx_t *ctx, 00788 lis2dw12_ff_ths_t *val); 00789 00790 int32_t lis2dw12_fifo_watermark_set(lis2dw12_ctx_t *ctx, uint8_t val); 00791 int32_t lis2dw12_fifo_watermark_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00792 00793 typedef enum { 00794 LIS2DW12_BYPASS_MODE = 0, 00795 LIS2DW12_FIFO_MODE = 1, 00796 LIS2DW12_STREAM_TO_FIFO_MODE = 3, 00797 LIS2DW12_BYPASS_TO_STREAM_MODE = 4, 00798 LIS2DW12_STREAM_MODE = 6, 00799 } lis2dw12_fmode_t; 00800 int32_t lis2dw12_fifo_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_fmode_t val); 00801 int32_t lis2dw12_fifo_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_fmode_t *val); 00802 00803 int32_t lis2dw12_fifo_data_level_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00804 00805 int32_t lis2dw12_fifo_ovr_flag_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00806 00807 int32_t lis2dw12_fifo_wtm_flag_get(lis2dw12_ctx_t *ctx, uint8_t *val); 00808 00809 /** 00810 * @} 00811 * 00812 */ 00813 00814 #ifdef __cplusplus 00815 } 00816 #endif 00817 00818 #endif /*LIS2DW12_REGS_H */ 00819 00820 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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