iis2dlpc_reg.h

00001 /**
00002  ******************************************************************************
00003  * @file    iis2dlpc_reg.h
00004  * @author  Sensors Software Solution Team
00005  * @brief   This file contains all the functions prototypes for the 
00006  *          iis2dlpc_reg.c driver.
00007  ******************************************************************************
00008  * @attention
00009  *
00010  * <h2><center>&copy; COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
00011  *
00012  * Redistribution and use in source and binary forms, with or without
00013  * modification, are permitted provided that the following conditions
00014  * are met:
00015  *   1. Redistributions of source code must retain the above copyright notice,
00016  *      this list of conditions and the following disclaimer.
00017  *   2. Redistributions in binary form must reproduce the above copyright
00018  *      notice, this list of conditions and the following disclaimer in the
00019  *      documentation and/or other materials provided with the distribution.
00020  *   3. Neither the name of STMicroelectronics nor the names of its
00021  *      contributors may be used to endorse or promote products derived from
00022  *      this software without specific prior written permission.
00023  *
00024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
00028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00034  * POSSIBILITY OF SUCH DAMAGE.
00035  *
00036  ******************************************************************************
00037  */
00038  
00039 /* Define to prevent recursive inclusion -------------------------------------*/
00040 #ifndef IIS2DLPC_REGS_H
00041 #define IIS2DLPC_REGS_H
00042 
00043 #ifdef __cplusplus
00044   extern "C" {
00045 #endif
00046 
00047 /* Includes ------------------------------------------------------------------*/
00048 #include <stdint.h>
00049 #include <math.h>
00050 
00051 /** @addtogroup IIS2DLPC
00052   * @{
00053   *
00054   */
00055 
00056 /** @defgroup IIS2DLPC_sensors_common_types
00057   * @{
00058   *
00059   */
00060 
00061 #ifndef MEMS_SHARED_TYPES
00062 #define MEMS_SHARED_TYPES
00063 
00064 /**
00065   * @defgroup axisXbitXX_t
00066   * @brief    These unions are useful to represent different sensors data type.
00067   *           These unions are not need by the driver.
00068   *
00069   *           REMOVING the unions you are compliant with:
00070   *           MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
00071   *
00072   * @{
00073   *
00074   */
00075 
00076 typedef union{
00077   int16_t i16bit[3];
00078   uint8_t u8bit[6];
00079 } axis3bit16_t;
00080 
00081 typedef union{
00082   int16_t i16bit;
00083   uint8_t u8bit[2];
00084 } axis1bit16_t;
00085 
00086 typedef union{
00087   int32_t i32bit[3];
00088   uint8_t u8bit[12];
00089 } axis3bit32_t;
00090 
00091 typedef union{
00092   int32_t i32bit;
00093   uint8_t u8bit[4];
00094 } axis1bit32_t;
00095 
00096 /**
00097   * @}
00098   *
00099   */
00100 
00101 typedef struct{
00102   uint8_t bit0       : 1;
00103   uint8_t bit1       : 1;
00104   uint8_t bit2       : 1;
00105   uint8_t bit3       : 1;
00106   uint8_t bit4       : 1;
00107   uint8_t bit5       : 1;
00108   uint8_t bit6       : 1;
00109   uint8_t bit7       : 1;
00110 } bitwise_t;
00111 
00112 #define PROPERTY_DISABLE                (0U)
00113 #define PROPERTY_ENABLE                 (1U)
00114 
00115 #endif /* MEMS_SHARED_TYPES */
00116 
00117 /**
00118   * @}
00119   *
00120   */
00121 
00122 /** @addtogroup  IIS2DLPC_Interfaces_Functions
00123   * @brief       This section provide a set of functions used to read and
00124   *              write a generic register of the device.
00125   *              MANDATORY: return 0 -> no Error.
00126   * @{
00127   *
00128   */ 
00129 
00130 typedef int32_t (*iis2dlpc_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
00131 typedef int32_t (*iis2dlpc_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
00132 
00133 typedef struct {
00134   /** Component mandatory fields **/
00135   iis2dlpc_write_ptr  write_reg;
00136   iis2dlpc_read_ptr   read_reg;
00137   /** Customizable optional pointer **/
00138   void *handle;
00139 } iis2dlpc_ctx_t;
00140 
00141 /**
00142   * @}
00143   *
00144   */
00145 
00146 /** @defgroup IIS2DLPC_Infos
00147   * @{
00148   *
00149   */
00150   
00151 /** I2C Device Address 8 bit format  if SA0=0 -> 31 if SA0=1 -> 33 **/
00152 #define IIS2DLPC_I2C_ADD_L   0x31U
00153 #define IIS2DLPC_I2C_ADD_H   0x33U
00154 
00155 /** Device Identification (Who am I) **/
00156 #define IIS2DLPC_ID            0x44U
00157 
00158 /**
00159   * @}
00160   *
00161   */
00162 
00163 #define IIS2DLPC_OUT_T_L                     0x0DU
00164 #define IIS2DLPC_OUT_T_H                     0x0EU
00165 #define IIS2DLPC_WHO_AM_I                    0x0FU
00166 #define IIS2DLPC_CTRL1                       0x20U
00167 typedef struct {
00168   uint8_t lp_mode                    : 2;
00169   uint8_t mode                       : 2;
00170   uint8_t odr                        : 4;
00171 } iis2dlpc_ctrl1_t;
00172 
00173 #define IIS2DLPC_CTRL2                       0x21U
00174 typedef struct {
00175   uint8_t sim                        : 1;
00176   uint8_t i2c_disable                : 1;
00177   uint8_t if_add_inc                 : 1;
00178   uint8_t bdu                        : 1;
00179   uint8_t cs_pu_disc                 : 1;
00180   uint8_t not_used_01                : 1;
00181   uint8_t soft_reset                 : 1;
00182   uint8_t boot                       : 1;
00183 } iis2dlpc_ctrl2_t;
00184 
00185 #define IIS2DLPC_CTRL3                       0x22U
00186 typedef struct {
00187   uint8_t slp_mode                   : 2;  /* slp_mode_sel + slp_mode_1 */
00188   uint8_t not_used_01                : 1;
00189   uint8_t h_lactive                  : 1;
00190   uint8_t lir                        : 1;
00191   uint8_t pp_od                      : 1;
00192   uint8_t st                         : 2;
00193 } iis2dlpc_ctrl3_t;
00194 
00195 #define IIS2DLPC_CTRL4_INT1_PAD_CTRL         0x23U
00196 typedef struct {
00197   uint8_t int1_drdy                  : 1;
00198   uint8_t int1_fth                   : 1;
00199   uint8_t int1_diff5                 : 1;
00200   uint8_t int1_tap                   : 1;
00201   uint8_t int1_ff                    : 1;
00202   uint8_t int1_wu                    : 1;
00203   uint8_t int1_single_tap            : 1;
00204   uint8_t int1_6d                    : 1;
00205 } iis2dlpc_ctrl4_int1_pad_ctrl_t;
00206 
00207 #define IIS2DLPC_CTRL5_INT2_PAD_CTRL         0x24U
00208 typedef struct {
00209   uint8_t int2_drdy                  : 1;
00210   uint8_t int2_fth                   : 1;
00211   uint8_t int2_diff5                 : 1;
00212   uint8_t int2_ovr                   : 1;
00213   uint8_t int2_drdy_t                : 1;
00214   uint8_t int2_boot                  : 1;
00215   uint8_t int2_sleep_chg             : 1;
00216   uint8_t int2_sleep_state           : 1;
00217 } iis2dlpc_ctrl5_int2_pad_ctrl_t;
00218 
00219 #define IIS2DLPC_CTRL6                       0x25U
00220 typedef struct {
00221   uint8_t not_used_01                : 2;
00222   uint8_t low_noise                  : 1;
00223   uint8_t fds                        : 1;
00224   uint8_t fs                         : 2;
00225   uint8_t bw_filt                    : 2;
00226 } iis2dlpc_ctrl6_t;
00227 
00228 #define IIS2DLPC_OUT_T                       0x26U
00229 #define IIS2DLPC_STATUS                      0x27U
00230 typedef struct {
00231   uint8_t drdy                       : 1;
00232   uint8_t ff_ia                      : 1;
00233   uint8_t _6d_ia                     : 1;
00234   uint8_t single_tap                 : 1;
00235   uint8_t double_tap                 : 1;
00236   uint8_t sleep_state                : 1;
00237   uint8_t wu_ia                      : 1;
00238   uint8_t fifo_ths                   : 1;
00239 } iis2dlpc_status_t;
00240 
00241 #define IIS2DLPC_OUT_X_L                     0x28U
00242 #define IIS2DLPC_OUT_X_H                     0x29U
00243 #define IIS2DLPC_OUT_Y_L                     0x2AU
00244 #define IIS2DLPC_OUT_Y_H                     0x2BU
00245 #define IIS2DLPC_OUT_Z_L                     0x2CU
00246 #define IIS2DLPC_OUT_Z_H                     0x2DU
00247 #define IIS2DLPC_FIFO_CTRL                   0x2EU
00248 typedef struct {
00249   uint8_t fth                        : 5;
00250   uint8_t fmode                      : 3;
00251 } iis2dlpc_fifo_ctrl_t;
00252 
00253 #define IIS2DLPC_FIFO_SAMPLES                0x2FU
00254 typedef struct {
00255   uint8_t diff                       : 6;
00256   uint8_t fifo_ovr                   : 1;
00257   uint8_t fifo_fth                   : 1;
00258 } iis2dlpc_fifo_samples_t;
00259 
00260 #define IIS2DLPC_TAP_THS_X                   0x30U
00261 typedef struct {
00262   uint8_t tap_thsx                    : 5;
00263   uint8_t _6d_ths                     : 2;
00264   uint8_t _4d_en                      : 1;
00265 } iis2dlpc_tap_ths_x_t;
00266 
00267 #define IIS2DLPC_TAP_THS_Y                   0x31U
00268 typedef struct {
00269   uint8_t tap_thsy                   : 5;
00270   uint8_t tap_prior                  : 3;
00271 } iis2dlpc_tap_ths_y_t;
00272 
00273 #define IIS2DLPC_TAP_THS_Z                   0x32U
00274 typedef struct {
00275   uint8_t tap_thsz                   : 5;
00276   uint8_t tap_z_en                   : 1;
00277   uint8_t tap_y_en                   : 1;
00278   uint8_t tap_x_en                   : 1;
00279 } iis2dlpc_tap_ths_z_t;
00280 
00281 #define IIS2DLPC_INT_DUR                     0x33U
00282 typedef struct {
00283   uint8_t shock                      : 2;
00284   uint8_t quiet                      : 2;
00285   uint8_t latency                    : 4;
00286 } iis2dlpc_int_dur_t;
00287 
00288 #define IIS2DLPC_WAKE_UP_THS                 0x34U
00289 typedef struct {
00290   uint8_t wk_ths                     : 6;
00291   uint8_t sleep_on                   : 1;
00292   uint8_t single_double_tap          : 1;
00293 } iis2dlpc_wake_up_ths_t;
00294 
00295 #define IIS2DLPC_WAKE_UP_DUR                 0x35U
00296 typedef struct {
00297   uint8_t sleep_dur                  : 4;
00298   uint8_t stationary                 : 1;
00299   uint8_t wake_dur                   : 2;
00300   uint8_t ff_dur                     : 1;
00301 } iis2dlpc_wake_up_dur_t;
00302 
00303 #define IIS2DLPC_FREE_FALL                   0x36U
00304 typedef struct {
00305   uint8_t ff_ths                     : 3;
00306   uint8_t ff_dur                     : 5;
00307 } iis2dlpc_free_fall_t;
00308 
00309 #define IIS2DLPC_STATUS_DUP                  0x37U
00310 typedef struct {
00311   uint8_t drdy                       : 1;
00312   uint8_t ff_ia                      : 1;
00313   uint8_t _6d_ia                     : 1;
00314   uint8_t single_tap                 : 1;
00315   uint8_t double_tap                 : 1;
00316   uint8_t sleep_state_ia             : 1;
00317   uint8_t drdy_t                     : 1;
00318   uint8_t ovr                        : 1;
00319 } iis2dlpc_status_dup_t;
00320 
00321 #define IIS2DLPC_WAKE_UP_SRC                 0x38U
00322 typedef struct {
00323   uint8_t z_wu                       : 1;
00324   uint8_t y_wu                       : 1;
00325   uint8_t x_wu                       : 1;
00326   uint8_t wu_ia                      : 1;
00327   uint8_t sleep_state_ia             : 1;
00328   uint8_t ff_ia                      : 1;
00329   uint8_t not_used_01                : 2;
00330 } iis2dlpc_wake_up_src_t;
00331 
00332 #define IIS2DLPC_TAP_SRC                     0x39U
00333 typedef struct {
00334   uint8_t z_tap                      : 1;
00335   uint8_t y_tap                      : 1;
00336   uint8_t x_tap                      : 1;
00337   uint8_t tap_sign                   : 1;
00338   uint8_t double_tap                 : 1;
00339   uint8_t single_tap                 : 1;
00340   uint8_t tap_ia                     : 1;
00341   uint8_t not_used_01                : 1;
00342 } iis2dlpc_tap_src_t;
00343 
00344 #define IIS2DLPC_SIXD_SRC                    0x3AU
00345 typedef struct {
00346   uint8_t xl                         : 1;
00347   uint8_t xh                         : 1;
00348   uint8_t yl                         : 1;
00349   uint8_t yh                         : 1;
00350   uint8_t zl                         : 1;
00351   uint8_t zh                         : 1;
00352   uint8_t _6d_ia                     : 1;
00353   uint8_t not_used_01                : 1;
00354 } iis2dlpc_sixd_src_t;
00355 
00356 #define IIS2DLPC_ALL_INT_SRC                 0x3BU
00357 typedef struct {
00358   uint8_t ff_ia                      : 1;
00359   uint8_t wu_ia                      : 1;
00360   uint8_t single_tap                 : 1;
00361   uint8_t double_tap                 : 1;
00362   uint8_t _6d_ia                     : 1;
00363   uint8_t sleep_change_ia            : 1;
00364   uint8_t not_used_01                : 2;
00365 } iis2dlpc_all_int_src_t;
00366 
00367 #define IIS2DLPC_X_OFS_USR                   0x3CU
00368 #define IIS2DLPC_Y_OFS_USR                   0x3DU
00369 #define IIS2DLPC_Z_OFS_USR                   0x3EU
00370 #define IIS2DLPC_CTRL_REG7                   0x3FU
00371 typedef struct {
00372   uint8_t lpass_on6d                 : 1;
00373   uint8_t hp_ref_mode                : 1;
00374   uint8_t usr_off_w                  : 1;
00375   uint8_t usr_off_on_wu              : 1;
00376   uint8_t usr_off_on_out             : 1;
00377   uint8_t interrupts_enable          : 1;
00378   uint8_t int2_on_int1               : 1;
00379   uint8_t drdy_pulsed                : 1;
00380 } iis2dlpc_ctrl_reg7_t;
00381 
00382 /**
00383   * @defgroup IIS2DLPC_Register_Union
00384   * @brief    This union group all the registers that has a bitfield
00385   *           description.
00386   *           This union is usefull but not need by the driver.
00387   *
00388   *           REMOVING this union you are complient with:
00389   *           MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
00390   *
00391   * @{
00392   *
00393   */
00394 typedef union{
00395   iis2dlpc_ctrl1_t                   ctrl1;
00396   iis2dlpc_ctrl2_t                   ctrl2;
00397   iis2dlpc_ctrl3_t                   ctrl3;
00398   iis2dlpc_ctrl4_int1_pad_ctrl_t     ctrl4_int1_pad_ctrl;
00399   iis2dlpc_ctrl5_int2_pad_ctrl_t     ctrl5_int2_pad_ctrl;
00400   iis2dlpc_ctrl6_t                   ctrl6;
00401   iis2dlpc_status_t                  status;
00402   iis2dlpc_fifo_ctrl_t               fifo_ctrl;
00403   iis2dlpc_fifo_samples_t            fifo_samples;
00404   iis2dlpc_tap_ths_x_t               tap_ths_x;
00405   iis2dlpc_tap_ths_y_t               tap_ths_y;
00406   iis2dlpc_tap_ths_z_t               tap_ths_z;
00407   iis2dlpc_int_dur_t                 int_dur;
00408   iis2dlpc_wake_up_ths_t             wake_up_ths;
00409   iis2dlpc_wake_up_dur_t             wake_up_dur;
00410   iis2dlpc_free_fall_t               free_fall;
00411   iis2dlpc_status_dup_t              status_dup;
00412   iis2dlpc_wake_up_src_t             wake_up_src;
00413   iis2dlpc_tap_src_t                 tap_src;
00414   iis2dlpc_sixd_src_t                sixd_src;
00415   iis2dlpc_all_int_src_t             all_int_src;
00416   iis2dlpc_ctrl_reg7_t               ctrl_reg7;
00417   bitwise_t                          bitwise;
00418   uint8_t                            byte;
00419 } iis2dlpc_reg_t;
00420 
00421 /**
00422   * @}
00423   *
00424   */
00425 
00426 int32_t iis2dlpc_read_reg(iis2dlpc_ctx_t *ctx, uint8_t reg, uint8_t* data,
00427                           uint16_t len);
00428 int32_t iis2dlpc_write_reg(iis2dlpc_ctx_t *ctx, uint8_t reg, uint8_t* data,
00429                            uint16_t len);
00430                            
00431 extern float iis2dlpc_from_fs2_to_mg(int16_t lsb);
00432 extern float iis2dlpc_from_fs4_to_mg(int16_t lsb);
00433 extern float iis2dlpc_from_fs8_to_mg(int16_t lsb);
00434 extern float iis2dlpc_from_fs16_to_mg(int16_t lsb);
00435 extern float iis2dlpc_from_fs2_lp1_to_mg(int16_t lsb);
00436 extern float iis2dlpc_from_fs4_lp1_to_mg(int16_t lsb);
00437 extern float iis2dlpc_from_fs8_lp1_to_mg(int16_t lsb);
00438 extern float iis2dlpc_from_fs16_lp1_to_mg(int16_t lsb);
00439 extern float iis2dlpc_from_lsb_to_celsius(int16_t lsb);
00440 
00441 typedef enum {
00442   IIS2DLPC_HIGH_PERFORMANCE                    = 0x04,
00443   IIS2DLPC_CONT_LOW_PWR_4                      = 0x03,
00444   IIS2DLPC_CONT_LOW_PWR_3                      = 0x02,
00445   IIS2DLPC_CONT_LOW_PWR_2                      = 0x01,
00446   IIS2DLPC_CONT_LOW_PWR_12bit                  = 0x00,
00447   IIS2DLPC_SINGLE_LOW_PWR_4                    = 0x0B,
00448   IIS2DLPC_SINGLE_LOW_PWR_3                    = 0x0A,
00449   IIS2DLPC_SINGLE_LOW_PWR_2                    = 0x09,
00450   IIS2DLPC_SINGLE_LOW_PWR_12bit                = 0x08,
00451   IIS2DLPC_HIGH_PERFORMANCE_LOW_NOISE          = 0x14,
00452   IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_4            = 0x13,
00453   IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_3            = 0x12,
00454   IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_2            = 0x11,
00455   IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_12bit        = 0x10,
00456   IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_4          = 0x1B,
00457   IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_3          = 0x1A,
00458   IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_2          = 0x19,
00459   IIS2DLPC_SINGLE_LOW_LOW_NOISE_PWR_12bit      = 0x18,
00460 } iis2dlpc_mode_t;
00461 int32_t iis2dlpc_power_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_mode_t val);
00462 int32_t iis2dlpc_power_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_mode_t *val);
00463 
00464 typedef enum {
00465   IIS2DLPC_XL_ODR_OFF            = 0x00,
00466   IIS2DLPC_XL_ODR_1Hz6_LP_ONLY   = 0x01,
00467   IIS2DLPC_XL_ODR_12Hz5          = 0x02,
00468   IIS2DLPC_XL_ODR_25Hz           = 0x03,
00469   IIS2DLPC_XL_ODR_50Hz           = 0x04,
00470   IIS2DLPC_XL_ODR_100Hz          = 0x05,
00471   IIS2DLPC_XL_ODR_200Hz          = 0x06,
00472   IIS2DLPC_XL_ODR_400Hz          = 0x07,
00473   IIS2DLPC_XL_ODR_800Hz          = 0x08,
00474   IIS2DLPC_XL_ODR_1k6Hz          = 0x09,
00475   IIS2DLPC_XL_SET_SW_TRIG        = 0x10,  /* Use this only in SINGLE mode */
00476   IIS2DLPC_XL_SET_PIN_TRIG       = 0x20,  /* Use this only in SINGLE mode */
00477 } iis2dlpc_odr_t;
00478 int32_t iis2dlpc_data_rate_set(iis2dlpc_ctx_t *ctx, iis2dlpc_odr_t val);
00479 int32_t iis2dlpc_data_rate_get(iis2dlpc_ctx_t *ctx, iis2dlpc_odr_t *val);
00480 
00481 int32_t iis2dlpc_block_data_update_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00482 int32_t iis2dlpc_block_data_update_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00483 
00484 typedef enum {
00485   IIS2DLPC_2g     = 0,
00486   IIS2DLPC_4g     = 1,
00487   IIS2DLPC_8g     = 2,
00488   IIS2DLPC_16g    = 3,
00489 } iis2dlpc_fs_t;
00490 int32_t iis2dlpc_full_scale_set(iis2dlpc_ctx_t *ctx, iis2dlpc_fs_t val);
00491 int32_t iis2dlpc_full_scale_get(iis2dlpc_ctx_t *ctx, iis2dlpc_fs_t *val);
00492 
00493 int32_t iis2dlpc_status_reg_get(iis2dlpc_ctx_t *ctx, iis2dlpc_status_t *val);
00494 
00495 int32_t iis2dlpc_flag_data_ready_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00496 
00497 typedef struct{
00498   iis2dlpc_status_dup_t   status_dup;
00499   iis2dlpc_wake_up_src_t  wake_up_src;
00500   iis2dlpc_tap_src_t      tap_src;
00501   iis2dlpc_sixd_src_t     sixd_src;
00502   iis2dlpc_all_int_src_t  all_int_src;
00503 } iis2dlpc_all_sources_t;
00504 int32_t iis2dlpc_all_sources_get(iis2dlpc_ctx_t *ctx,
00505                                  iis2dlpc_all_sources_t *val);
00506 
00507 int32_t iis2dlpc_usr_offset_x_set(iis2dlpc_ctx_t *ctx, uint8_t *buff);
00508 int32_t iis2dlpc_usr_offset_x_get(iis2dlpc_ctx_t *ctx, uint8_t *buff);
00509 
00510 int32_t iis2dlpc_usr_offset_y_set(iis2dlpc_ctx_t *ctx, uint8_t *buff);
00511 int32_t iis2dlpc_usr_offset_y_get(iis2dlpc_ctx_t *ctx, uint8_t *buff);
00512 
00513 int32_t iis2dlpc_usr_offset_z_set(iis2dlpc_ctx_t *ctx, uint8_t *buff);
00514 int32_t iis2dlpc_usr_offset_z_get(iis2dlpc_ctx_t *ctx, uint8_t *buff);
00515 
00516 typedef enum {
00517   IIS2DLPC_LSb_977ug    = 0,
00518   IIS2DLPC_LSb_15mg6    = 1,
00519 } iis2dlpc_usr_off_w_t;
00520 int32_t iis2dlpc_offset_weight_set(iis2dlpc_ctx_t *ctx,
00521                                       iis2dlpc_usr_off_w_t val);
00522 int32_t iis2dlpc_offset_weight_get(iis2dlpc_ctx_t *ctx,
00523                                       iis2dlpc_usr_off_w_t *val);
00524 
00525 int32_t iis2dlpc_temperature_raw_get(iis2dlpc_ctx_t *ctx, uint8_t *buff);
00526 
00527 int32_t iis2dlpc_acceleration_raw_get(iis2dlpc_ctx_t *ctx, uint8_t *buff);
00528 
00529 int32_t iis2dlpc_device_id_get(iis2dlpc_ctx_t *ctx, uint8_t *buff);
00530 
00531 int32_t iis2dlpc_auto_increment_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00532 int32_t iis2dlpc_auto_increment_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00533 
00534 int32_t iis2dlpc_reset_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00535 int32_t iis2dlpc_reset_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00536 
00537 int32_t iis2dlpc_boot_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00538 int32_t iis2dlpc_boot_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00539 
00540 typedef enum {
00541   IIS2DLPC_XL_ST_DISABLE      = 0,
00542   IIS2DLPC_XL_ST_POSITIVE     = 1,
00543   IIS2DLPC_XL_ST_NEGATIVE     = 2,
00544 } iis2dlpc_st_t;
00545 int32_t iis2dlpc_self_test_set(iis2dlpc_ctx_t *ctx, iis2dlpc_st_t val);
00546 int32_t iis2dlpc_self_test_get(iis2dlpc_ctx_t *ctx, iis2dlpc_st_t *val);
00547 
00548 typedef enum {
00549   IIS2DLPC_DRDY_LATCHED   = 0,
00550   IIS2DLPC_DRDY_PULSED    = 1,
00551 } iis2dlpc_drdy_pulsed_t;
00552 int32_t iis2dlpc_data_ready_mode_set(iis2dlpc_ctx_t *ctx,
00553                                      iis2dlpc_drdy_pulsed_t val);
00554 int32_t iis2dlpc_data_ready_mode_get(iis2dlpc_ctx_t *ctx,
00555                                      iis2dlpc_drdy_pulsed_t *val);
00556 
00557 typedef enum {
00558   IIS2DLPC_LPF_ON_OUT         = 0x00,
00559   IIS2DLPC_USER_OFFSET_ON_OUT  = 0x01,    
00560   IIS2DLPC_HIGH_PASS_ON_OUT    = 0x10,
00561 } iis2dlpc_fds_t;
00562 int32_t iis2dlpc_filter_path_set(iis2dlpc_ctx_t *ctx, iis2dlpc_fds_t val);
00563 int32_t iis2dlpc_filter_path_get(iis2dlpc_ctx_t *ctx, iis2dlpc_fds_t *val);
00564 
00565 typedef enum {
00566   IIS2DLPC_ODR_DIV_2     = 0,
00567   IIS2DLPC_ODR_DIV_4     = 1,
00568   IIS2DLPC_ODR_DIV_10    = 2,
00569   IIS2DLPC_ODR_DIV_20    = 3,
00570 } iis2dlpc_bw_filt_t;
00571 int32_t iis2dlpc_filter_bandwidth_set(iis2dlpc_ctx_t *ctx,
00572                                          iis2dlpc_bw_filt_t val);
00573 int32_t iis2dlpc_filter_bandwidth_get(iis2dlpc_ctx_t *ctx,
00574                                          iis2dlpc_bw_filt_t *val);
00575 
00576 int32_t iis2dlpc_reference_mode_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00577 int32_t iis2dlpc_reference_mode_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00578 
00579 typedef enum {
00580   IIS2DLPC_SPI_4_WIRE   = 0,
00581   IIS2DLPC_SPI_3_WIRE   = 1,
00582 } iis2dlpc_sim_t;
00583 int32_t iis2dlpc_spi_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_sim_t val);
00584 int32_t iis2dlpc_spi_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_sim_t *val);
00585 
00586 typedef enum {
00587   IIS2DLPC_I2C_ENABLE    = 0,
00588   IIS2DLPC_I2C_DISABLE   = 1,
00589 } iis2dlpc_i2c_disable_t;
00590 int32_t iis2dlpc_i2c_interface_set(iis2dlpc_ctx_t *ctx,
00591                                    iis2dlpc_i2c_disable_t val);
00592 int32_t iis2dlpc_i2c_interface_get(iis2dlpc_ctx_t *ctx,
00593                                    iis2dlpc_i2c_disable_t *val);
00594 
00595 typedef enum {
00596   IIS2DLPC_PULL_UP_CONNECT     = 0,
00597   IIS2DLPC_PULL_UP_DISCONNECT  = 1,
00598 } iis2dlpc_cs_pu_disc_t;
00599 int32_t iis2dlpc_cs_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_cs_pu_disc_t val);
00600 int32_t iis2dlpc_cs_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_cs_pu_disc_t *val);
00601 
00602 typedef enum {
00603   IIS2DLPC_ACTIVE_HIGH  = 0,
00604   IIS2DLPC_ACTIVE_LOW   = 1,
00605 } iis2dlpc_h_lactive_t;
00606 int32_t iis2dlpc_pin_polarity_set(iis2dlpc_ctx_t *ctx,
00607                                   iis2dlpc_h_lactive_t val);
00608 int32_t iis2dlpc_pin_polarity_get(iis2dlpc_ctx_t *ctx,
00609                                   iis2dlpc_h_lactive_t *val);
00610 
00611 typedef enum {
00612   IIS2DLPC_INT_PULSED   = 0,
00613   IIS2DLPC_INT_LATCHED  = 1,
00614 } iis2dlpc_lir_t;
00615 int32_t iis2dlpc_int_notification_set(iis2dlpc_ctx_t *ctx,
00616                                       iis2dlpc_lir_t val);
00617 int32_t iis2dlpc_int_notification_get(iis2dlpc_ctx_t *ctx,
00618                                       iis2dlpc_lir_t *val);
00619 
00620 typedef enum {
00621   IIS2DLPC_PUSH_PULL   = 0,
00622   IIS2DLPC_OPEN_DRAIN  = 1,
00623 } iis2dlpc_pp_od_t;
00624 int32_t iis2dlpc_pin_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_pp_od_t val);
00625 int32_t iis2dlpc_pin_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_pp_od_t *val);
00626 
00627 int32_t iis2dlpc_pin_int1_route_set(iis2dlpc_ctx_t *ctx, 
00628                                     iis2dlpc_ctrl4_int1_pad_ctrl_t *val);
00629 int32_t iis2dlpc_pin_int1_route_get(iis2dlpc_ctx_t *ctx,
00630                                     iis2dlpc_ctrl4_int1_pad_ctrl_t *val);
00631 
00632 int32_t iis2dlpc_pin_int2_route_set(iis2dlpc_ctx_t *ctx,
00633                                     iis2dlpc_ctrl5_int2_pad_ctrl_t *val);
00634 int32_t iis2dlpc_pin_int2_route_get(iis2dlpc_ctx_t *ctx,
00635                                     iis2dlpc_ctrl5_int2_pad_ctrl_t *val);
00636 
00637 int32_t iis2dlpc_all_on_int1_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00638 int32_t iis2dlpc_all_on_int1_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00639 
00640 int32_t iis2dlpc_wkup_threshold_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00641 int32_t iis2dlpc_wkup_threshold_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00642 
00643 int32_t iis2dlpc_wkup_dur_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00644 int32_t iis2dlpc_wkup_dur_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00645 
00646 typedef enum {
00647   IIS2DLPC_HP_FEED           = 0,
00648   IIS2DLPC_USER_OFFSET_FEED  = 1,
00649 } iis2dlpc_usr_off_on_wu_t;
00650 int32_t iis2dlpc_wkup_feed_data_set(iis2dlpc_ctx_t *ctx,
00651                                     iis2dlpc_usr_off_on_wu_t val);
00652 int32_t iis2dlpc_wkup_feed_data_get(iis2dlpc_ctx_t *ctx,
00653                                     iis2dlpc_usr_off_on_wu_t *val);
00654 
00655 typedef enum {
00656   IIS2DLPC_NO_DETECTION        = 0,
00657   IIS2DLPC_DETECT_ACT_INACT    = 1,
00658   IIS2DLPC_DETECT_STAT_MOTION  = 3,
00659 } iis2dlpc_sleep_on_t;
00660 int32_t iis2dlpc_act_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_sleep_on_t val);
00661 int32_t iis2dlpc_act_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_sleep_on_t *val);
00662 
00663 int32_t iis2dlpc_act_sleep_dur_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00664 int32_t iis2dlpc_act_sleep_dur_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00665 
00666 int32_t iis2dlpc_tap_threshold_x_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00667 int32_t iis2dlpc_tap_threshold_x_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00668 
00669 int32_t iis2dlpc_tap_threshold_y_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00670 int32_t iis2dlpc_tap_threshold_y_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00671 
00672 typedef enum {
00673   IIS2DLPC_XYZ    = 0,
00674   IIS2DLPC_YXZ    = 1,
00675   IIS2DLPC_XZY    = 2,
00676   IIS2DLPC_ZYX    = 3,
00677   IIS2DLPC_YZX    = 5,
00678   IIS2DLPC_ZXY    = 6,
00679 } iis2dlpc_tap_prior_t;
00680 int32_t iis2dlpc_tap_axis_priority_set(iis2dlpc_ctx_t *ctx,
00681                                        iis2dlpc_tap_prior_t val);
00682 int32_t iis2dlpc_tap_axis_priority_get(iis2dlpc_ctx_t *ctx,
00683                                        iis2dlpc_tap_prior_t *val);
00684 
00685 int32_t iis2dlpc_tap_threshold_z_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00686 int32_t iis2dlpc_tap_threshold_z_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00687 
00688 int32_t iis2dlpc_tap_detection_on_z_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00689 int32_t iis2dlpc_tap_detection_on_z_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00690 
00691 int32_t iis2dlpc_tap_detection_on_y_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00692 int32_t iis2dlpc_tap_detection_on_y_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00693 
00694 int32_t iis2dlpc_tap_detection_on_x_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00695 int32_t iis2dlpc_tap_detection_on_x_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00696 
00697 int32_t iis2dlpc_tap_shock_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00698 int32_t iis2dlpc_tap_shock_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00699 
00700 int32_t iis2dlpc_tap_quiet_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00701 int32_t iis2dlpc_tap_quiet_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00702 
00703 int32_t iis2dlpc_tap_dur_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00704 int32_t iis2dlpc_tap_dur_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00705 
00706 typedef enum {
00707   IIS2DLPC_ONLY_SINGLE          = 0,
00708   IIS2DLPC_BOTH_SINGLE_DOUBLE   = 1,
00709 } iis2dlpc_single_double_tap_t;
00710 int32_t iis2dlpc_tap_mode_set(iis2dlpc_ctx_t *ctx,
00711                               iis2dlpc_single_double_tap_t val);
00712 int32_t iis2dlpc_tap_mode_get(iis2dlpc_ctx_t *ctx,
00713                               iis2dlpc_single_double_tap_t *val);
00714 
00715 int32_t iis2dlpc_tap_src_get(iis2dlpc_ctx_t *ctx, iis2dlpc_tap_src_t *val);
00716 
00717 int32_t iis2dlpc_6d_threshold_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00718 int32_t iis2dlpc_6d_threshold_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00719 
00720 int32_t iis2dlpc_4d_mode_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00721 int32_t iis2dlpc_4d_mode_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00722 
00723 int32_t iis2dlpc_6d_src_get(iis2dlpc_ctx_t *ctx, iis2dlpc_sixd_src_t *val);
00724 
00725 typedef enum {
00726   IIS2DLPC_ODR_DIV_2_FEED   = 0,
00727   IIS2DLPC_LPF2_FEED        = 1,
00728 } iis2dlpc_lpass_on6d_t;
00729 int32_t iis2dlpc_6d_feed_data_set(iis2dlpc_ctx_t *ctx,
00730                                   iis2dlpc_lpass_on6d_t val);
00731 int32_t iis2dlpc_6d_feed_data_get(iis2dlpc_ctx_t *ctx,
00732                                   iis2dlpc_lpass_on6d_t *val);
00733 
00734 int32_t iis2dlpc_ff_dur_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00735 int32_t iis2dlpc_ff_dur_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00736 
00737 typedef enum {
00738   IIS2DLPC_FF_TSH_5LSb_FS2g  = 0,
00739   IIS2DLPC_FF_TSH_7LSb_FS2g  = 1,
00740   IIS2DLPC_FF_TSH_8LSb_FS2g  = 2,
00741   IIS2DLPC_FF_TSH_10LSb_FS2g = 3,
00742   IIS2DLPC_FF_TSH_11LSb_FS2g = 4,
00743   IIS2DLPC_FF_TSH_13LSb_FS2g = 5,
00744   IIS2DLPC_FF_TSH_15LSb_FS2g = 6,
00745   IIS2DLPC_FF_TSH_16LSb_FS2g = 7,
00746 } iis2dlpc_ff_ths_t;
00747 int32_t iis2dlpc_ff_threshold_set(iis2dlpc_ctx_t *ctx,
00748                                   iis2dlpc_ff_ths_t val);
00749 int32_t iis2dlpc_ff_threshold_get(iis2dlpc_ctx_t *ctx,
00750                                   iis2dlpc_ff_ths_t *val);
00751 
00752 int32_t iis2dlpc_fifo_watermark_set(iis2dlpc_ctx_t *ctx, uint8_t val);
00753 int32_t iis2dlpc_fifo_watermark_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00754 
00755 typedef enum {
00756   IIS2DLPC_BYPASS_MODE             = 0,
00757   IIS2DLPC_FIFO_MODE               = 1,
00758   IIS2DLPC_STREAM_TO_FIFO_MODE     = 3,
00759   IIS2DLPC_BYPASS_TO_STREAM_MODE   = 4,
00760   IIS2DLPC_STREAM_MODE             = 6,
00761 } iis2dlpc_fmode_t;
00762 int32_t iis2dlpc_fifo_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_fmode_t val);
00763 int32_t iis2dlpc_fifo_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_fmode_t *val);
00764 
00765 int32_t iis2dlpc_fifo_data_level_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00766 
00767 int32_t iis2dlpc_fifo_ovr_flag_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00768 
00769 int32_t iis2dlpc_fifo_wtm_flag_get(iis2dlpc_ctx_t *ctx, uint8_t *val);
00770 
00771 /**
00772   * @}
00773   *
00774   */
00775 
00776 #ifdef __cplusplus
00777 }
00778 #endif
00779 
00780 #endif /*IIS2DLPC_REGS_H */
00781 
00782 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/