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IIS2DLPC
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Dependencies: X_NUCLEO_COMMON ST_INTERFACES
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iis2dlpc_reg.c
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00001 /** 00002 ****************************************************************************** 00003 * @file iis2dlpc_reg.c 00004 * @author Sensors Software Solution Team 00005 * @brief IIS2DLPC driver file 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without 00012 * modification, are permitted provided that the following conditions 00013 * are met: 00014 * 1. Redistributions of source code must retain the above copyright notice, 00015 * this list of conditions and the following disclaimer. 00016 * 2. Redistributions in binary form must reproduce the above copyright 00017 * notice, this list of conditions and the following disclaimer in the 00018 * documentation and/or other materials provided with the distribution. 00019 * 3. Neither the name of STMicroelectronics nor the names of its 00020 * contributors may be used to endorse or promote products derived from 00021 * this software without specific prior written permission. 00022 * 00023 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00024 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00025 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00026 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 00027 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00028 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00029 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00030 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00031 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00032 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00033 * POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 #include "iis2dlpc_reg.h" 00039 00040 /** 00041 * @defgroup IIS2DLPC 00042 * @brief This file provides a set of functions needed to drive the 00043 * iis2dlpc enanced inertial module. 00044 * @{ 00045 * 00046 */ 00047 00048 /** 00049 * @defgroup IIS2DLPC_Interfaces_Functions 00050 * @brief This section provide a set of functions used to read and 00051 * write a generic register of the device. 00052 * MANDATORY: return 0 -> no Error. 00053 * @{ 00054 * 00055 */ 00056 00057 /** 00058 * @brief Read generic device register 00059 * 00060 * @param ctx read / write interface definitions(ptr) 00061 * @param reg register to read 00062 * @param data pointer to buffer that store the data read(ptr) 00063 * @param len number of consecutive register to read 00064 * @retval interface status (MANDATORY: return 0 -> no Error) 00065 * 00066 */ 00067 int32_t iis2dlpc_read_reg(iis2dlpc_ctx_t* ctx, uint8_t reg, uint8_t* data, 00068 uint16_t len) 00069 { 00070 int32_t ret; 00071 ret = ctx->read_reg(ctx->handle, reg, data, len); 00072 return ret; 00073 } 00074 00075 /** 00076 * @brief Write generic device register 00077 * 00078 * @param ctx read / write interface definitions(ptr) 00079 * @param reg register to write 00080 * @param data pointer to data to write in register reg(ptr) 00081 * @param len number of consecutive register to write 00082 * @retval interface status (MANDATORY: return 0 -> no Error) 00083 * 00084 */ 00085 int32_t iis2dlpc_write_reg(iis2dlpc_ctx_t* ctx, uint8_t reg, uint8_t* data, 00086 uint16_t len) 00087 { 00088 int32_t ret; 00089 ret = ctx->write_reg(ctx->handle, reg, data, len); 00090 return ret; 00091 } 00092 00093 /** 00094 * @} 00095 * 00096 */ 00097 00098 /** 00099 * @defgroup IIS2DLPC_Sensitivity 00100 * @brief These functions convert raw-data into engineering units. 00101 * @{ 00102 * 00103 */ 00104 00105 float iis2dlpc_from_fs2_to_mg(int16_t lsb) 00106 { 00107 return ((float)lsb) * 0.061f; 00108 } 00109 00110 float iis2dlpc_from_fs4_to_mg(int16_t lsb) 00111 { 00112 return ((float)lsb) * 0.122f; 00113 } 00114 00115 float iis2dlpc_from_fs8_to_mg(int16_t lsb) 00116 { 00117 return ((float)lsb) * 0.244f; 00118 } 00119 00120 float iis2dlpc_from_fs16_to_mg(int16_t lsb) 00121 { 00122 return ((float)lsb) *0.488f; 00123 } 00124 00125 float iis2dlpc_from_fs2_lp1_to_mg(int16_t lsb) 00126 { 00127 return ((float)lsb) * 0.061f; 00128 } 00129 00130 float iis2dlpc_from_fs4_lp1_to_mg(int16_t lsb) 00131 { 00132 return ((float)lsb) * 0.122f; 00133 } 00134 00135 float iis2dlpc_from_fs8_lp1_to_mg(int16_t lsb) 00136 { 00137 return ((float)lsb) * 0.244f; 00138 } 00139 00140 float iis2dlpc_from_fs16_lp1_to_mg(int16_t lsb) 00141 { 00142 return ((float)lsb) * 0.488f; 00143 } 00144 00145 float iis2dlpc_from_lsb_to_celsius(int16_t lsb) 00146 { 00147 return (((float)lsb / 16.0f) + 25.0f); 00148 } 00149 00150 /** 00151 * @} 00152 * 00153 */ 00154 00155 /** 00156 * @defgroup IIS2DLPC_Data_Generation 00157 * @brief This section groups all the functions concerning 00158 * data generation 00159 * @{ 00160 * 00161 */ 00162 00163 /** 00164 * @brief Select accelerometer operating modes.[set] 00165 * 00166 * @param ctx read / write interface definitions 00167 * @param val change the values of mode / lp_mode in reg CTRL1 00168 * and low_noise in reg CTRL6 00169 * @retval interface status (MANDATORY: return 0 -> no Error) 00170 * 00171 */ 00172 int32_t iis2dlpc_power_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_mode_t val) 00173 { 00174 iis2dlpc_ctrl1_t ctrl1; 00175 iis2dlpc_ctrl6_t ctrl6; 00176 int32_t ret; 00177 00178 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1); 00179 if (ret == 0) { 00180 ctrl1.mode = ( (uint8_t) val & 0x0CU ) >> 2; 00181 ctrl1.lp_mode = (uint8_t) val & 0x03U ; 00182 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1); 00183 } 00184 if (ret == 0) { 00185 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1); 00186 } 00187 if (ret == 0) { 00188 ctrl6.low_noise = ( (uint8_t) val & 0x10U ) >> 4; 00189 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1); 00190 } else { 00191 ret = ret; 00192 } 00193 return ret; 00194 } 00195 00196 /** 00197 * @brief Select accelerometer operating modes.[get] 00198 * 00199 * @param ctx read / write interface definitions 00200 * @param val change the values of mode / lp_mode in reg CTRL1 00201 * and low_noise in reg CTRL6 00202 * @retval interface status (MANDATORY: return 0 -> no Error) 00203 * 00204 */ 00205 int32_t iis2dlpc_power_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_mode_t *val) 00206 { 00207 iis2dlpc_ctrl1_t ctrl1; 00208 iis2dlpc_ctrl6_t ctrl6; 00209 int32_t ret; 00210 00211 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1); 00212 if (ret == 0) { 00213 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1); 00214 00215 switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) + 00216 ctrl1.lp_mode)) { 00217 case IIS2DLPC_HIGH_PERFORMANCE: 00218 *val = IIS2DLPC_HIGH_PERFORMANCE; 00219 break; 00220 case IIS2DLPC_CONT_LOW_PWR_4: 00221 *val = IIS2DLPC_CONT_LOW_PWR_4; 00222 break; 00223 case IIS2DLPC_CONT_LOW_PWR_3: 00224 *val = IIS2DLPC_CONT_LOW_PWR_3; 00225 break; 00226 case IIS2DLPC_CONT_LOW_PWR_2: 00227 *val = IIS2DLPC_CONT_LOW_PWR_2; 00228 break; 00229 case IIS2DLPC_CONT_LOW_PWR_12bit: 00230 *val = IIS2DLPC_CONT_LOW_PWR_12bit; 00231 break; 00232 case IIS2DLPC_SINGLE_LOW_PWR_4: 00233 *val = IIS2DLPC_SINGLE_LOW_PWR_4; 00234 break; 00235 case IIS2DLPC_SINGLE_LOW_PWR_3: 00236 *val = IIS2DLPC_SINGLE_LOW_PWR_3; 00237 break; 00238 case IIS2DLPC_SINGLE_LOW_PWR_2: 00239 *val = IIS2DLPC_SINGLE_LOW_PWR_2; 00240 break; 00241 case IIS2DLPC_SINGLE_LOW_PWR_12bit: 00242 *val = IIS2DLPC_SINGLE_LOW_PWR_12bit; 00243 break; 00244 case IIS2DLPC_HIGH_PERFORMANCE_LOW_NOISE: 00245 *val = IIS2DLPC_HIGH_PERFORMANCE_LOW_NOISE; 00246 break; 00247 case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_4: 00248 *val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_4; 00249 break; 00250 case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_3: 00251 *val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_3; 00252 break; 00253 case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_2: 00254 *val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_2; 00255 break; 00256 case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_12bit: 00257 *val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_12bit; 00258 break; 00259 case IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_4: 00260 *val = IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_4; 00261 break; 00262 case IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_3: 00263 *val = IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_3; 00264 break; 00265 case IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_2: 00266 *val = IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_2; 00267 break; 00268 case IIS2DLPC_SINGLE_LOW_LOW_NOISE_PWR_12bit: 00269 *val = IIS2DLPC_SINGLE_LOW_LOW_NOISE_PWR_12bit; 00270 break; 00271 default: 00272 *val = IIS2DLPC_HIGH_PERFORMANCE; 00273 break; 00274 } 00275 } 00276 return ret; 00277 } 00278 00279 /** 00280 * @brief Accelerometer data rate selection.[set] 00281 * 00282 * @param ctx read / write interface definitions 00283 * @param val change the values of odr in reg CTRL1 00284 * @retval interface status (MANDATORY: return 0 -> no Error) 00285 * 00286 */ 00287 int32_t iis2dlpc_data_rate_set(iis2dlpc_ctx_t *ctx, iis2dlpc_odr_t val) 00288 { 00289 iis2dlpc_ctrl1_t ctrl1; 00290 iis2dlpc_ctrl3_t ctrl3; 00291 int32_t ret; 00292 00293 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1); 00294 if (ret == 0) { 00295 ctrl1.odr = (uint8_t) val; 00296 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1); 00297 } 00298 if (ret == 0) { 00299 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &ctrl3, 1); 00300 } 00301 if (ret == 0) { 00302 ctrl3.slp_mode = ( (uint8_t) val & 0x30U ) >> 4; 00303 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &ctrl3, 1); 00304 } else { 00305 ret = ret; 00306 } 00307 return ret; 00308 } 00309 00310 /** 00311 * @brief Accelerometer data rate selection.[get] 00312 * 00313 * @param ctx read / write interface definitions 00314 * @param val Get the values of odr in reg CTRL1 00315 * @retval interface status (MANDATORY: return 0 -> no Error) 00316 * 00317 */ 00318 int32_t iis2dlpc_data_rate_get(iis2dlpc_ctx_t *ctx, iis2dlpc_odr_t *val) 00319 { 00320 iis2dlpc_ctrl1_t ctrl1; 00321 iis2dlpc_ctrl3_t ctrl3; 00322 int32_t ret; 00323 00324 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1); 00325 if (ret == 0) { 00326 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &ctrl3, 1); 00327 00328 switch ((ctrl3.slp_mode << 4) + ctrl1.odr) { 00329 case IIS2DLPC_XL_ODR_OFF: 00330 *val = IIS2DLPC_XL_ODR_OFF; 00331 break; 00332 case IIS2DLPC_XL_ODR_1Hz6_LP_ONLY: 00333 *val = IIS2DLPC_XL_ODR_1Hz6_LP_ONLY; 00334 break; 00335 case IIS2DLPC_XL_ODR_12Hz5: 00336 *val = IIS2DLPC_XL_ODR_12Hz5; 00337 break; 00338 case IIS2DLPC_XL_ODR_25Hz: 00339 *val = IIS2DLPC_XL_ODR_25Hz; 00340 break; 00341 case IIS2DLPC_XL_ODR_50Hz: 00342 *val = IIS2DLPC_XL_ODR_50Hz; 00343 break; 00344 case IIS2DLPC_XL_ODR_100Hz: 00345 *val = IIS2DLPC_XL_ODR_100Hz; 00346 break; 00347 case IIS2DLPC_XL_ODR_200Hz: 00348 *val = IIS2DLPC_XL_ODR_200Hz; 00349 break; 00350 case IIS2DLPC_XL_ODR_400Hz: 00351 *val = IIS2DLPC_XL_ODR_400Hz; 00352 break; 00353 case IIS2DLPC_XL_ODR_800Hz: 00354 *val = IIS2DLPC_XL_ODR_800Hz; 00355 break; 00356 case IIS2DLPC_XL_ODR_1k6Hz: 00357 *val = IIS2DLPC_XL_ODR_1k6Hz; 00358 break; 00359 case IIS2DLPC_XL_SET_SW_TRIG: 00360 *val = IIS2DLPC_XL_SET_SW_TRIG; 00361 break; 00362 case IIS2DLPC_XL_SET_PIN_TRIG: 00363 *val = IIS2DLPC_XL_SET_PIN_TRIG; 00364 break; 00365 default: 00366 *val = IIS2DLPC_XL_ODR_OFF; 00367 break; 00368 } 00369 } 00370 return ret; 00371 } 00372 00373 /** 00374 * @brief Block data update.[set] 00375 * 00376 * @param ctx read / write interface definitions 00377 * @param val change the values of bdu in reg CTRL2 00378 * @retval interface status (MANDATORY: return 0 -> no Error) 00379 * 00380 */ 00381 int32_t iis2dlpc_block_data_update_set(iis2dlpc_ctx_t *ctx, uint8_t val) 00382 { 00383 iis2dlpc_ctrl2_t reg; 00384 int32_t ret; 00385 00386 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 00387 if (ret == 0) { 00388 reg.bdu = val; 00389 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 00390 } 00391 return ret; 00392 } 00393 00394 /** 00395 * @brief Block data update.[get] 00396 * 00397 * @param ctx read / write interface definitions 00398 * @param val change the values of bdu in reg CTRL2 00399 * @retval interface status (MANDATORY: return 0 -> no Error) 00400 * 00401 */ 00402 int32_t iis2dlpc_block_data_update_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 00403 { 00404 iis2dlpc_ctrl2_t reg; 00405 int32_t ret; 00406 00407 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 00408 *val = reg.bdu; 00409 00410 return ret; 00411 } 00412 00413 /** 00414 * @brief Accelerometer full-scale selection.[set] 00415 * 00416 * @param ctx read / write interface definitions 00417 * @param val change the values of fs in reg CTRL6 00418 * @retval interface status (MANDATORY: return 0 -> no Error) 00419 * 00420 */ 00421 int32_t iis2dlpc_full_scale_set(iis2dlpc_ctx_t *ctx, iis2dlpc_fs_t val) 00422 { 00423 iis2dlpc_ctrl6_t reg; 00424 int32_t ret; 00425 00426 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) ®, 1); 00427 if (ret == 0) { 00428 reg.fs = (uint8_t) val; 00429 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) ®, 1); 00430 } 00431 return ret; 00432 } 00433 00434 /** 00435 * @brief Accelerometer full-scale selection.[get] 00436 * 00437 * @param ctx read / write interface definitions 00438 * @param val Get the values of fs in reg CTRL6 00439 * @retval interface status (MANDATORY: return 0 -> no Error) 00440 * 00441 */ 00442 int32_t iis2dlpc_full_scale_get(iis2dlpc_ctx_t *ctx, iis2dlpc_fs_t *val) 00443 { 00444 iis2dlpc_ctrl6_t reg; 00445 int32_t ret; 00446 00447 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) ®, 1); 00448 00449 switch (reg.fs) { 00450 case IIS2DLPC_2g: 00451 *val = IIS2DLPC_2g; 00452 break; 00453 case IIS2DLPC_4g: 00454 *val = IIS2DLPC_4g; 00455 break; 00456 case IIS2DLPC_8g: 00457 *val = IIS2DLPC_8g; 00458 break; 00459 case IIS2DLPC_16g: 00460 *val = IIS2DLPC_16g; 00461 break; 00462 default: 00463 *val = IIS2DLPC_2g; 00464 break; 00465 } 00466 return ret; 00467 } 00468 00469 /** 00470 * @brief The STATUS_REG register of the device.[get] 00471 * 00472 * @param ctx read / write interface definitions 00473 * @param val union of registers from STATUS to 00474 * @retval interface status (MANDATORY: return 0 -> no Error) 00475 * 00476 */ 00477 int32_t iis2dlpc_status_reg_get(iis2dlpc_ctx_t *ctx, iis2dlpc_status_t *val) 00478 { 00479 int32_t ret; 00480 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS, (uint8_t*) val, 1); 00481 return ret; 00482 } 00483 00484 /** 00485 * @brief Accelerometer new data available.[get] 00486 * 00487 * @param ctx read / write interface definitions 00488 * @param val change the values of drdy in reg STATUS 00489 * @retval interface status (MANDATORY: return 0 -> no Error) 00490 * 00491 */ 00492 int32_t iis2dlpc_flag_data_ready_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 00493 { 00494 iis2dlpc_status_t reg; 00495 int32_t ret; 00496 00497 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS,(uint8_t*) ®, 1); 00498 *val = reg.drdy; 00499 00500 return ret; 00501 } 00502 /** 00503 * @brief Read all the interrupt/status flag of the device.[get] 00504 * 00505 * @param ctx read / write interface definitions 00506 * @param val registers STATUS_DUP, WAKE_UP_SRC, 00507 * TAP_SRC, SIXD_SRC, ALL_INT_SRC 00508 * @retval interface status (MANDATORY: return 0 -> no Error) 00509 * 00510 */ 00511 int32_t iis2dlpc_all_sources_get(iis2dlpc_ctx_t *ctx, 00512 iis2dlpc_all_sources_t *val) 00513 { 00514 int32_t ret; 00515 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS_DUP, (uint8_t*) val, 5); 00516 return ret; 00517 } 00518 00519 /** 00520 * @brief Accelerometer X-axis user offset correction expressed in two’s 00521 * complement, weight depends on bit USR_OFF_W. The value must be 00522 * in the range [-127 127].[set] 00523 * 00524 * @param ctx read / write interface definitions 00525 * @param buff buffer that contains data to write 00526 * @retval interface status (MANDATORY: return 0 -> no Error) 00527 * 00528 */ 00529 int32_t iis2dlpc_usr_offset_x_set(iis2dlpc_ctx_t *ctx, uint8_t *buff) 00530 { 00531 int32_t ret; 00532 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_X_OFS_USR, buff, 1); 00533 return ret; 00534 } 00535 00536 /** 00537 * @brief Accelerometer X-axis user offset correction expressed in two’s 00538 * complement, weight depends on bit USR_OFF_W. The value must be 00539 * in the range [-127 127].[get] 00540 * 00541 * @param ctx read / write interface definitions 00542 * @param buff buffer that stores data read 00543 * @retval interface status (MANDATORY: return 0 -> no Error) 00544 * 00545 */ 00546 int32_t iis2dlpc_usr_offset_x_get(iis2dlpc_ctx_t *ctx, uint8_t *buff) 00547 { 00548 int32_t ret; 00549 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_X_OFS_USR, buff, 1); 00550 return ret; 00551 } 00552 00553 /** 00554 * @brief Accelerometer Y-axis user offset correction expressed in two’s 00555 * complement, weight depends on bit USR_OFF_W. The value must be 00556 * in the range [-127 127].[set] 00557 * 00558 * @param ctx read / write interface definitions 00559 * @param buff buffer that contains data to write 00560 * @retval interface status (MANDATORY: return 0 -> no Error) 00561 * 00562 */ 00563 int32_t iis2dlpc_usr_offset_y_set(iis2dlpc_ctx_t *ctx, uint8_t *buff) 00564 { 00565 int32_t ret; 00566 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_Y_OFS_USR, buff, 1); 00567 return ret; 00568 } 00569 00570 /** 00571 * @brief Accelerometer Y-axis user offset correction expressed in two’s 00572 * complement, weight depends on bit USR_OFF_W. The value must be 00573 * in the range [-127 127].[get] 00574 * 00575 * @param ctx read / write interface definitions 00576 * @param buff buffer that stores data read 00577 * @retval interface status (MANDATORY: return 0 -> no Error) 00578 * 00579 */ 00580 int32_t iis2dlpc_usr_offset_y_get(iis2dlpc_ctx_t *ctx, uint8_t *buff) 00581 { 00582 int32_t ret; 00583 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_Y_OFS_USR, buff, 1); 00584 return ret; 00585 } 00586 00587 /** 00588 * @brief Accelerometer Z-axis user offset correction expressed in two’s 00589 * complement, weight depends on bit USR_OFF_W. The value must be 00590 * in the range [-127 127].[set] 00591 * 00592 * @param ctx read / write interface definitions 00593 * @param buff buffer that contains data to write 00594 * @retval interface status (MANDATORY: return 0 -> no Error) 00595 * 00596 */ 00597 int32_t iis2dlpc_usr_offset_z_set(iis2dlpc_ctx_t *ctx, uint8_t *buff) 00598 { 00599 int32_t ret; 00600 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_Z_OFS_USR, buff, 1); 00601 return ret; 00602 } 00603 00604 /** 00605 * @brief Accelerometer Z-axis user offset correction expressed in two’s 00606 * complement, weight depends on bit USR_OFF_W. The value must be 00607 * in the range [-127 127].[get] 00608 * 00609 * @param ctx read / write interface definitions 00610 * @param buff buffer that stores data read 00611 * @retval interface status (MANDATORY: return 0 -> no Error) 00612 * 00613 */ 00614 int32_t iis2dlpc_usr_offset_z_get(iis2dlpc_ctx_t *ctx, uint8_t *buff) 00615 { 00616 int32_t ret; 00617 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_Z_OFS_USR, buff, 1); 00618 return ret; 00619 } 00620 00621 /** 00622 * @brief Weight of XL user offset bits of registers X_OFS_USR, 00623 * Y_OFS_USR, Z_OFS_USR.[set] 00624 * 00625 * @param ctx read / write interface definitions 00626 * @param val change the values of usr_off_w in 00627 * reg CTRL_REG7 00628 * @retval interface status (MANDATORY: return 0 -> no Error) 00629 * 00630 */ 00631 int32_t iis2dlpc_offset_weight_set(iis2dlpc_ctx_t *ctx, 00632 iis2dlpc_usr_off_w_t val) 00633 { 00634 iis2dlpc_ctrl_reg7_t reg; 00635 int32_t ret; 00636 00637 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 00638 if (ret == 0) { 00639 reg.usr_off_w = (uint8_t) val; 00640 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 00641 } 00642 return ret; 00643 } 00644 00645 /** 00646 * @brief Weight of XL user offset bits of registers X_OFS_USR, 00647 * Y_OFS_USR, Z_OFS_USR.[get] 00648 * 00649 * @param ctx read / write interface definitions 00650 * @param val Get the values of usr_off_w in reg CTRL_REG7 00651 * @retval interface status (MANDATORY: return 0 -> no Error) 00652 * 00653 */ 00654 int32_t iis2dlpc_offset_weight_get(iis2dlpc_ctx_t *ctx, 00655 iis2dlpc_usr_off_w_t *val) 00656 { 00657 iis2dlpc_ctrl_reg7_t reg; 00658 int32_t ret; 00659 00660 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 00661 switch (reg.usr_off_w) { 00662 case IIS2DLPC_LSb_977ug: 00663 *val = IIS2DLPC_LSb_977ug; 00664 break; 00665 case IIS2DLPC_LSb_15mg6: 00666 *val = IIS2DLPC_LSb_15mg6; 00667 break; 00668 default: 00669 *val = IIS2DLPC_LSb_977ug; 00670 break; 00671 } 00672 return ret; 00673 } 00674 00675 /** 00676 * @} 00677 * 00678 */ 00679 00680 /** 00681 * @defgroup IIS2DLPC_Data_Output 00682 * @brief This section groups all the data output functions. 00683 * @{ 00684 * 00685 */ 00686 00687 /** 00688 * @brief Temperature data output register (r). L and H registers 00689 * together express a 16-bit word in two’s complement.[get] 00690 * 00691 * @param ctx read / write interface definitions 00692 * @param buff buffer that stores data read 00693 * @retval interface status (MANDATORY: return 0 -> no Error) 00694 * 00695 */ 00696 int32_t iis2dlpc_temperature_raw_get(iis2dlpc_ctx_t *ctx, uint8_t *buff) 00697 { 00698 int32_t ret; 00699 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_OUT_T_L, buff, 2); 00700 return ret; 00701 } 00702 00703 /** 00704 * @brief Linear acceleration output register. The value is expressed as 00705 * a 16-bit word in two’s complement.[get] 00706 * 00707 * @param ctx read / write interface definitions 00708 * @param buff buffer that stores data read 00709 * @retval interface status (MANDATORY: return 0 -> no Error) 00710 * 00711 */ 00712 int32_t iis2dlpc_acceleration_raw_get(iis2dlpc_ctx_t *ctx, uint8_t *buff) 00713 { 00714 int32_t ret; 00715 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_OUT_X_L, buff, 6); 00716 return ret; 00717 } 00718 00719 /** 00720 * @} 00721 * 00722 */ 00723 00724 /** 00725 * @defgroup IIS2DLPC_Common 00726 * @brief This section groups common useful functions. 00727 * @{ 00728 * 00729 */ 00730 00731 /** 00732 * @brief Device Who am I.[get] 00733 * 00734 * @param ctx read / write interface definitions 00735 * @param buff buffer that stores data read 00736 * @retval interface status (MANDATORY: return 0 -> no Error) 00737 * 00738 */ 00739 int32_t iis2dlpc_device_id_get(iis2dlpc_ctx_t *ctx, uint8_t *buff) 00740 { 00741 int32_t ret; 00742 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WHO_AM_I, buff, 1); 00743 return ret; 00744 } 00745 00746 /** 00747 * @brief Register address automatically incremented during multiple byte 00748 * access with a serial interface.[set] 00749 * 00750 * @param ctx read / write interface definitions 00751 * @param val change the values of if_add_inc in reg CTRL2 00752 * @retval interface status (MANDATORY: return 0 -> no Error) 00753 * 00754 */ 00755 int32_t iis2dlpc_auto_increment_set(iis2dlpc_ctx_t *ctx, uint8_t val) 00756 { 00757 iis2dlpc_ctrl2_t reg; 00758 int32_t ret; 00759 00760 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 00761 if (ret == 0) { 00762 reg.if_add_inc = val; 00763 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 00764 } 00765 return ret; 00766 } 00767 00768 /** 00769 * @brief Register address automatically incremented during multiple 00770 * byte access with a serial interface.[get] 00771 * 00772 * @param ctx read / write interface definitions 00773 * @param val change the values of if_add_inc in reg CTRL2 00774 * @retval interface status (MANDATORY: return 0 -> no Error) 00775 * 00776 */ 00777 int32_t iis2dlpc_auto_increment_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 00778 { 00779 iis2dlpc_ctrl2_t reg; 00780 int32_t ret; 00781 00782 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 00783 *val = reg.if_add_inc; 00784 00785 return ret; 00786 } 00787 00788 /** 00789 * @brief Software reset. Restore the default values in user registers.[set] 00790 * 00791 * @param ctx read / write interface definitions 00792 * @param val change the values of soft_reset in reg CTRL2 00793 * @retval interface status (MANDATORY: return 0 -> no Error) 00794 * 00795 */ 00796 int32_t iis2dlpc_reset_set(iis2dlpc_ctx_t *ctx, uint8_t val) 00797 { 00798 iis2dlpc_ctrl2_t reg; 00799 int32_t ret; 00800 00801 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 00802 if (ret == 0) { 00803 reg.soft_reset = val; 00804 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 00805 } 00806 00807 return ret; 00808 } 00809 00810 /** 00811 * @brief Software reset. Restore the default values in user registers.[get] 00812 * 00813 * @param ctx read / write interface definitions 00814 * @param val change the values of soft_reset in reg CTRL2 00815 * @retval interface status (MANDATORY: return 0 -> no Error) 00816 * 00817 */ 00818 int32_t iis2dlpc_reset_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 00819 { 00820 iis2dlpc_ctrl2_t reg; 00821 int32_t ret; 00822 00823 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 00824 *val = reg.soft_reset; 00825 00826 return ret; 00827 } 00828 00829 /** 00830 * @brief Reboot memory content. Reload the calibration parameters.[set] 00831 * 00832 * @param ctx read / write interface definitions 00833 * @param val change the values of boot in reg CTRL2 00834 * @retval interface status (MANDATORY: return 0 -> no Error) 00835 * 00836 */ 00837 int32_t iis2dlpc_boot_set(iis2dlpc_ctx_t *ctx, uint8_t val) 00838 { 00839 iis2dlpc_ctrl2_t reg; 00840 int32_t ret; 00841 00842 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 00843 if (ret == 0) { 00844 reg.boot = val; 00845 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 00846 } 00847 return ret; 00848 } 00849 00850 /** 00851 * @brief Reboot memory content. Reload the calibration parameters.[get] 00852 * 00853 * @param ctx read / write interface definitions 00854 * @param val change the values of boot in reg CTRL2 00855 * @retval interface status (MANDATORY: return 0 -> no Error) 00856 * 00857 */ 00858 int32_t iis2dlpc_boot_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 00859 { 00860 iis2dlpc_ctrl2_t reg; 00861 int32_t ret; 00862 00863 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 00864 *val = reg.boot; 00865 00866 return ret; 00867 } 00868 00869 /** 00870 * @brief Sensor self-test enable.[set] 00871 * 00872 * @param ctx read / write interface definitions 00873 * @param val change the values of st in reg CTRL3 00874 * @retval interface status (MANDATORY: return 0 -> no Error) 00875 * 00876 */ 00877 int32_t iis2dlpc_self_test_set(iis2dlpc_ctx_t *ctx, iis2dlpc_st_t val) 00878 { 00879 iis2dlpc_ctrl3_t reg; 00880 int32_t ret; 00881 00882 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1); 00883 if (ret == 0) { 00884 reg.st = (uint8_t) val; 00885 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1); 00886 } 00887 00888 return ret; 00889 } 00890 00891 /** 00892 * @brief Sensor self-test enable.[get] 00893 * 00894 * @param ctx read / write interface definitions 00895 * @param val Get the values of st in reg CTRL3 00896 * @retval interface status (MANDATORY: return 0 -> no Error) 00897 * 00898 */ 00899 int32_t iis2dlpc_self_test_get(iis2dlpc_ctx_t *ctx, iis2dlpc_st_t *val) 00900 { 00901 iis2dlpc_ctrl3_t reg; 00902 int32_t ret; 00903 00904 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1); 00905 00906 switch (reg.st) { 00907 case IIS2DLPC_XL_ST_DISABLE: 00908 *val = IIS2DLPC_XL_ST_DISABLE; 00909 break; 00910 case IIS2DLPC_XL_ST_POSITIVE: 00911 *val = IIS2DLPC_XL_ST_POSITIVE; 00912 break; 00913 case IIS2DLPC_XL_ST_NEGATIVE: 00914 *val = IIS2DLPC_XL_ST_NEGATIVE; 00915 break; 00916 default: 00917 *val = IIS2DLPC_XL_ST_DISABLE; 00918 break; 00919 } 00920 return ret; 00921 } 00922 00923 /** 00924 * @brief Data-ready pulsed / letched mode.[set] 00925 * 00926 * @param ctx read / write interface definitions 00927 * @param val change the values of drdy_pulsed in reg CTRL_REG7 00928 * @retval interface status (MANDATORY: return 0 -> no Error) 00929 * 00930 */ 00931 int32_t iis2dlpc_data_ready_mode_set(iis2dlpc_ctx_t *ctx, 00932 iis2dlpc_drdy_pulsed_t val) 00933 { 00934 iis2dlpc_ctrl_reg7_t reg; 00935 int32_t ret; 00936 00937 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 00938 if (ret == 0) { 00939 reg.drdy_pulsed = (uint8_t) val; 00940 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 00941 } 00942 00943 return ret; 00944 } 00945 00946 /** 00947 * @brief Data-ready pulsed / letched mode.[get] 00948 * 00949 * @param ctx read / write interface definitions 00950 * @param val Get the values of drdy_pulsed in reg CTRL_REG7 00951 * @retval interface status (MANDATORY: return 0 -> no Error) 00952 * 00953 */ 00954 int32_t iis2dlpc_data_ready_mode_get(iis2dlpc_ctx_t *ctx, 00955 iis2dlpc_drdy_pulsed_t *val) 00956 { 00957 iis2dlpc_ctrl_reg7_t reg; 00958 int32_t ret; 00959 00960 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 00961 00962 switch (reg.drdy_pulsed) { 00963 case IIS2DLPC_DRDY_LATCHED: 00964 *val = IIS2DLPC_DRDY_LATCHED; 00965 break; 00966 case IIS2DLPC_DRDY_PULSED: 00967 *val = IIS2DLPC_DRDY_PULSED; 00968 break; 00969 default: 00970 *val = IIS2DLPC_DRDY_LATCHED; 00971 break; 00972 } 00973 return ret; 00974 } 00975 00976 /** 00977 * @} 00978 * 00979 */ 00980 00981 /** 00982 * @defgroup IIS2DLPC_Filters 00983 * @brief This section group all the functions concerning the filters 00984 * configuration. 00985 * @{ 00986 * 00987 */ 00988 00989 /** 00990 * @brief Accelerometer filtering path for outputs.[set] 00991 * 00992 * @param ctx read / write interface definitions 00993 * @param val change the values of fds in reg CTRL6 00994 * @retval interface status (MANDATORY: return 0 -> no Error) 00995 * 00996 */ 00997 int32_t iis2dlpc_filter_path_set(iis2dlpc_ctx_t *ctx, iis2dlpc_fds_t val) 00998 { 00999 iis2dlpc_ctrl6_t ctrl6; 01000 iis2dlpc_ctrl_reg7_t ctrl_reg7; 01001 int32_t ret; 01002 01003 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1); 01004 if (ret == 0) { 01005 ctrl6.fds = ( (uint8_t) val & 0x10U ) >> 4; 01006 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1); 01007 } 01008 if (ret == 0) { 01009 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1); 01010 } 01011 if (ret == 0) { 01012 ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U; 01013 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1); 01014 } else { 01015 ret = ret; 01016 } 01017 return ret; 01018 } 01019 01020 /** 01021 * @brief Accelerometer filtering path for outputs.[get] 01022 * 01023 * @param ctx read / write interface definitions 01024 * @param val Get the values of fds in reg CTRL6 01025 * @retval interface status (MANDATORY: return 0 -> no Error) 01026 * 01027 */ 01028 int32_t iis2dlpc_filter_path_get(iis2dlpc_ctx_t *ctx, iis2dlpc_fds_t *val) 01029 { 01030 iis2dlpc_ctrl6_t ctrl6; 01031 iis2dlpc_ctrl_reg7_t ctrl_reg7; 01032 int32_t ret; 01033 01034 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1); 01035 if (ret == 0) { 01036 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1); 01037 01038 switch ((ctrl6.fds << 4 ) + ctrl_reg7.usr_off_on_out) { 01039 case IIS2DLPC_LPF_ON_OUT: 01040 *val = IIS2DLPC_LPF_ON_OUT; 01041 break; 01042 case IIS2DLPC_USER_OFFSET_ON_OUT: 01043 *val = IIS2DLPC_USER_OFFSET_ON_OUT; 01044 break; 01045 case IIS2DLPC_HIGH_PASS_ON_OUT: 01046 *val = IIS2DLPC_HIGH_PASS_ON_OUT; 01047 break; 01048 default: 01049 *val = IIS2DLPC_LPF_ON_OUT; 01050 break; 01051 } 01052 } 01053 return ret; 01054 } 01055 01056 /** 01057 * @brief Accelerometer cutoff filter frequency. Valid for low and high 01058 * pass filter.[set] 01059 * 01060 * @param ctx read / write interface definitions 01061 * @param val change the values of bw_filt in reg CTRL6 01062 * @retval interface status (MANDATORY: return 0 -> no Error) 01063 * 01064 */ 01065 int32_t iis2dlpc_filter_bandwidth_set(iis2dlpc_ctx_t *ctx, 01066 iis2dlpc_bw_filt_t val) 01067 { 01068 iis2dlpc_ctrl6_t reg; 01069 int32_t ret; 01070 01071 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) ®, 1); 01072 if (ret == 0) { 01073 reg.bw_filt = (uint8_t) val; 01074 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) ®, 1); 01075 } 01076 01077 return ret; 01078 } 01079 01080 /** 01081 * @brief Accelerometer cutoff filter frequency. Valid for low and 01082 * high pass filter.[get] 01083 * 01084 * @param ctx read / write interface definitions 01085 * @param val Get the values of bw_filt in reg CTRL6 01086 * @retval interface status (MANDATORY: return 0 -> no Error) 01087 * 01088 */ 01089 int32_t iis2dlpc_filter_bandwidth_get(iis2dlpc_ctx_t *ctx, 01090 iis2dlpc_bw_filt_t *val) 01091 { 01092 iis2dlpc_ctrl6_t reg; 01093 int32_t ret; 01094 01095 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) ®, 1); 01096 01097 switch (reg.bw_filt) { 01098 case IIS2DLPC_ODR_DIV_2: 01099 *val = IIS2DLPC_ODR_DIV_2; 01100 break; 01101 case IIS2DLPC_ODR_DIV_4: 01102 *val = IIS2DLPC_ODR_DIV_4; 01103 break; 01104 case IIS2DLPC_ODR_DIV_10: 01105 *val = IIS2DLPC_ODR_DIV_10; 01106 break; 01107 case IIS2DLPC_ODR_DIV_20: 01108 *val = IIS2DLPC_ODR_DIV_20; 01109 break; 01110 default: 01111 *val = IIS2DLPC_ODR_DIV_2; 01112 break; 01113 } 01114 return ret; 01115 } 01116 01117 /** 01118 * @brief Enable HP filter reference mode.[set] 01119 * 01120 * @param ctx read / write interface definitions 01121 * @param val change the values of hp_ref_mode in reg CTRL_REG7 01122 * @retval interface status (MANDATORY: return 0 -> no Error) 01123 * 01124 */ 01125 int32_t iis2dlpc_reference_mode_set(iis2dlpc_ctx_t *ctx, uint8_t val) 01126 { 01127 iis2dlpc_ctrl_reg7_t reg; 01128 int32_t ret; 01129 01130 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 01131 if (ret == 0) { 01132 reg.hp_ref_mode = val; 01133 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 01134 } 01135 return ret; 01136 } 01137 01138 /** 01139 * @brief Enable HP filter reference mode.[get] 01140 * 01141 * @param ctx read / write interface definitions 01142 * @param val change the values of hp_ref_mode in reg CTRL_REG7 01143 * @retval interface status (MANDATORY: return 0 -> no Error) 01144 * 01145 */ 01146 int32_t iis2dlpc_reference_mode_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 01147 { 01148 iis2dlpc_ctrl_reg7_t reg; 01149 int32_t ret; 01150 01151 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 01152 *val = reg.hp_ref_mode; 01153 01154 return ret; 01155 } 01156 01157 /** 01158 * @} 01159 * 01160 */ 01161 01162 /** 01163 * @defgroup IIS2DLPC_Serial_Interface 01164 * @brief This section groups all the functions concerning main serial 01165 * interface management (not auxiliary) 01166 * @{ 01167 * 01168 */ 01169 01170 /** 01171 * @brief SPI Serial Interface Mode selection.[set] 01172 * 01173 * @param ctx read / write interface definitions 01174 * @param val change the values of sim in reg CTRL2 01175 * @retval interface status (MANDATORY: return 0 -> no Error) 01176 * 01177 */ 01178 int32_t iis2dlpc_spi_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_sim_t val) 01179 { 01180 iis2dlpc_ctrl2_t reg; 01181 int32_t ret; 01182 01183 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 01184 if (ret == 0) { 01185 reg.sim = (uint8_t) val; 01186 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 01187 } 01188 return ret; 01189 } 01190 01191 /** 01192 * @brief SPI Serial Interface Mode selection.[get] 01193 * 01194 * @param ctx read / write interface definitions 01195 * @param val Get the values of sim in reg CTRL2 01196 * @retval interface status (MANDATORY: return 0 -> no Error) 01197 * 01198 */ 01199 int32_t iis2dlpc_spi_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_sim_t *val) 01200 { 01201 iis2dlpc_ctrl2_t reg; 01202 int32_t ret; 01203 01204 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 01205 01206 switch (reg.sim) { 01207 case IIS2DLPC_SPI_4_WIRE: 01208 *val = IIS2DLPC_SPI_4_WIRE; 01209 break; 01210 case IIS2DLPC_SPI_3_WIRE: 01211 *val = IIS2DLPC_SPI_3_WIRE; 01212 break; 01213 default: 01214 *val = IIS2DLPC_SPI_4_WIRE; 01215 break; 01216 } 01217 return ret; 01218 } 01219 01220 /** 01221 * @brief Disable / Enable I2C interface.[set] 01222 * 01223 * @param ctx read / write interface definitions 01224 * @param val change the values of i2c_disable in 01225 * reg CTRL2 01226 * @retval interface status (MANDATORY: return 0 -> no Error) 01227 * 01228 */ 01229 int32_t iis2dlpc_i2c_interface_set(iis2dlpc_ctx_t *ctx, 01230 iis2dlpc_i2c_disable_t val) 01231 { 01232 iis2dlpc_ctrl2_t reg; 01233 int32_t ret; 01234 01235 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 01236 if (ret == 0) { 01237 reg.i2c_disable = (uint8_t) val; 01238 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 01239 } 01240 return ret; 01241 } 01242 01243 /** 01244 * @brief Disable / Enable I2C interface.[get] 01245 * 01246 * @param ctx read / write interface definitions 01247 * @param val Get the values of i2c_disable in reg CTRL2 01248 * @retval interface status (MANDATORY: return 0 -> no Error) 01249 * 01250 */ 01251 int32_t iis2dlpc_i2c_interface_get(iis2dlpc_ctx_t *ctx, 01252 iis2dlpc_i2c_disable_t *val) 01253 { 01254 iis2dlpc_ctrl2_t reg; 01255 int32_t ret; 01256 01257 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 01258 01259 switch (reg.i2c_disable) { 01260 case IIS2DLPC_I2C_ENABLE: 01261 *val = IIS2DLPC_I2C_ENABLE; 01262 break; 01263 case IIS2DLPC_I2C_DISABLE: 01264 *val = IIS2DLPC_I2C_DISABLE; 01265 break; 01266 default: 01267 *val = IIS2DLPC_I2C_ENABLE; 01268 break; 01269 } 01270 return ret; 01271 } 01272 01273 /** 01274 * @brief Disconnect CS pull-up.[set] 01275 * 01276 * @param ctx read / write interface definitions 01277 * @param val change the values of cs_pu_disc in reg CTRL2 01278 * @retval interface status (MANDATORY: return 0 -> no Error) 01279 * 01280 */ 01281 int32_t iis2dlpc_cs_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_cs_pu_disc_t val) 01282 { 01283 iis2dlpc_ctrl2_t reg; 01284 int32_t ret; 01285 01286 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 01287 if (ret == 0) { 01288 reg.cs_pu_disc = (uint8_t) val; 01289 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 01290 } 01291 return ret; 01292 } 01293 01294 /** 01295 * @brief Disconnect CS pull-up.[get] 01296 * 01297 * @param ctx read / write interface definitions 01298 * @param val Get the values of cs_pu_disc in reg CTRL2 01299 * @retval interface status (MANDATORY: return 0 -> no Error) 01300 * 01301 */ 01302 int32_t iis2dlpc_cs_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_cs_pu_disc_t *val) 01303 { 01304 iis2dlpc_ctrl2_t reg; 01305 int32_t ret; 01306 01307 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1); 01308 01309 switch (reg.cs_pu_disc) { 01310 case IIS2DLPC_PULL_UP_CONNECT: 01311 *val = IIS2DLPC_PULL_UP_CONNECT; 01312 break; 01313 case IIS2DLPC_PULL_UP_DISCONNECT: 01314 *val = IIS2DLPC_PULL_UP_DISCONNECT; 01315 break; 01316 default: 01317 *val = IIS2DLPC_PULL_UP_CONNECT; 01318 break; 01319 } 01320 return ret; 01321 } 01322 01323 /** 01324 * @} 01325 * 01326 */ 01327 01328 /** 01329 * @defgroup IIS2DLPC_Interrupt_Pins 01330 * @brief This section groups all the functions that manage interrupt pins 01331 * @{ 01332 * 01333 */ 01334 01335 /** 01336 * @brief Interrupt active-high/low.[set] 01337 * 01338 * @param ctx read / write interface definitions 01339 * @param val change the values of h_lactive in reg CTRL3 01340 * @retval interface status (MANDATORY: return 0 -> no Error) 01341 * 01342 */ 01343 int32_t iis2dlpc_pin_polarity_set(iis2dlpc_ctx_t *ctx, 01344 iis2dlpc_h_lactive_t val) 01345 { 01346 iis2dlpc_ctrl3_t reg; 01347 int32_t ret; 01348 01349 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1); 01350 if (ret == 0) { 01351 reg.h_lactive = (uint8_t) val; 01352 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1); 01353 } 01354 return ret; 01355 } 01356 01357 /** 01358 * @brief Interrupt active-high/low.[get] 01359 * 01360 * @param ctx read / write interface definitions 01361 * @param val Get the values of h_lactive in reg CTRL3 01362 * @retval interface status (MANDATORY: return 0 -> no Error) 01363 * 01364 */ 01365 int32_t iis2dlpc_pin_polarity_get(iis2dlpc_ctx_t *ctx, 01366 iis2dlpc_h_lactive_t *val) 01367 { 01368 iis2dlpc_ctrl3_t reg; 01369 int32_t ret; 01370 01371 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1); 01372 01373 switch (reg.h_lactive) { 01374 case IIS2DLPC_ACTIVE_HIGH: 01375 *val = IIS2DLPC_ACTIVE_HIGH; 01376 break; 01377 case IIS2DLPC_ACTIVE_LOW: 01378 *val = IIS2DLPC_ACTIVE_LOW; 01379 break; 01380 default: 01381 *val = IIS2DLPC_ACTIVE_HIGH; 01382 break; 01383 } 01384 return ret; 01385 } 01386 01387 /** 01388 * @brief Latched/pulsed interrupt.[set] 01389 * 01390 * @param ctx read / write interface definitions 01391 * @param val change the values of lir in reg CTRL3 01392 * @retval interface status (MANDATORY: return 0 -> no Error) 01393 * 01394 */ 01395 int32_t iis2dlpc_int_notification_set(iis2dlpc_ctx_t *ctx, 01396 iis2dlpc_lir_t val) 01397 { 01398 iis2dlpc_ctrl3_t reg; 01399 int32_t ret; 01400 01401 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1); 01402 if (ret == 0) { 01403 reg.lir = (uint8_t) val; 01404 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1); 01405 } 01406 return ret; 01407 } 01408 01409 /** 01410 * @brief Latched/pulsed interrupt.[get] 01411 * 01412 * @param ctx read / write interface definitions 01413 * @param val Get the values of lir in reg CTRL3 01414 * @retval interface status (MANDATORY: return 0 -> no Error) 01415 * 01416 */ 01417 int32_t iis2dlpc_int_notification_get(iis2dlpc_ctx_t *ctx, 01418 iis2dlpc_lir_t *val) 01419 { 01420 iis2dlpc_ctrl3_t reg; 01421 int32_t ret; 01422 01423 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1); 01424 01425 switch (reg.lir) { 01426 case IIS2DLPC_INT_PULSED: 01427 *val = IIS2DLPC_INT_PULSED; 01428 break; 01429 case IIS2DLPC_INT_LATCHED: 01430 *val = IIS2DLPC_INT_LATCHED; 01431 break; 01432 default: 01433 *val = IIS2DLPC_INT_PULSED; 01434 break; 01435 } 01436 return ret; 01437 } 01438 01439 /** 01440 * @brief Push-pull/open drain selection on interrupt pads.[set] 01441 * 01442 * @param ctx read / write interface definitions 01443 * @param val change the values of pp_od in reg CTRL3 01444 * @retval interface status (MANDATORY: return 0 -> no Error) 01445 * 01446 */ 01447 int32_t iis2dlpc_pin_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_pp_od_t val) 01448 { 01449 iis2dlpc_ctrl3_t reg; 01450 int32_t ret; 01451 01452 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1); 01453 if (ret == 0) { 01454 reg.pp_od = (uint8_t) val; 01455 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1); 01456 } 01457 return ret; 01458 } 01459 01460 /** 01461 * @brief Push-pull/open drain selection on interrupt pads.[get] 01462 * 01463 * @param ctx read / write interface definitions 01464 * @param val Get the values of pp_od in reg CTRL3 01465 * @retval interface status (MANDATORY: return 0 -> no Error) 01466 * 01467 */ 01468 int32_t iis2dlpc_pin_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_pp_od_t *val) 01469 { 01470 iis2dlpc_ctrl3_t reg; 01471 int32_t ret; 01472 01473 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1); 01474 01475 switch (reg.pp_od) { 01476 case IIS2DLPC_PUSH_PULL: 01477 *val = IIS2DLPC_PUSH_PULL; 01478 break; 01479 case IIS2DLPC_OPEN_DRAIN: 01480 *val = IIS2DLPC_OPEN_DRAIN; 01481 break; 01482 default: 01483 *val = IIS2DLPC_PUSH_PULL; 01484 break; 01485 } 01486 return ret; 01487 } 01488 01489 /** 01490 * @brief Select the signal that need to route on int1 pad.[set] 01491 * 01492 * @param ctx read / write interface definitions 01493 * @param val register CTRL4_INT1_PAD_CTRL. 01494 * @retval interface status (MANDATORY: return 0 -> no Error) 01495 * 01496 */ 01497 int32_t iis2dlpc_pin_int1_route_set(iis2dlpc_ctx_t *ctx, 01498 iis2dlpc_ctrl4_int1_pad_ctrl_t *val) 01499 { 01500 iis2dlpc_ctrl_reg7_t reg; 01501 int32_t ret; 01502 01503 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 01504 if (ret == 0) { 01505 if ((val->int1_tap | val->int1_ff | val->int1_wu | val->int1_single_tap | 01506 val->int1_6d) != PROPERTY_DISABLE){ 01507 reg.interrupts_enable = PROPERTY_ENABLE; 01508 } 01509 else{ 01510 reg.interrupts_enable = PROPERTY_DISABLE; 01511 } 01512 01513 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL4_INT1_PAD_CTRL, 01514 (uint8_t*) val, 1); 01515 } 01516 if (ret == 0) { 01517 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 01518 } else { 01519 ret = ret; 01520 } 01521 return ret; 01522 } 01523 01524 /** 01525 * @brief Select the signal that need to route on int1 pad.[get] 01526 * 01527 * @param ctx read / write interface definitions 01528 * @param val register CTRL4_INT1_PAD_CTRL. 01529 * @retval interface status (MANDATORY: return 0 -> no Error) 01530 * 01531 */ 01532 int32_t iis2dlpc_pin_int1_route_get(iis2dlpc_ctx_t *ctx, 01533 iis2dlpc_ctrl4_int1_pad_ctrl_t *val) 01534 { 01535 int32_t ret; 01536 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL4_INT1_PAD_CTRL, 01537 (uint8_t*) val, 1); 01538 return ret; 01539 } 01540 01541 /** 01542 * @brief Select the signal that need to route on int2 pad.[set] 01543 * 01544 * @param ctx read / write interface definitions 01545 * @param val register CTRL5_INT2_PAD_CTRL. 01546 * @retval interface status (MANDATORY: return 0 -> no Error) 01547 * 01548 */ 01549 int32_t iis2dlpc_pin_int2_route_set(iis2dlpc_ctx_t *ctx, 01550 iis2dlpc_ctrl5_int2_pad_ctrl_t *val) 01551 { 01552 iis2dlpc_ctrl_reg7_t reg; 01553 int32_t ret; 01554 01555 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 01556 if (ret == 0) { 01557 if ((val->int2_sleep_state | val->int2_sleep_chg ) != PROPERTY_DISABLE) { 01558 reg.interrupts_enable = PROPERTY_ENABLE; 01559 } 01560 else{ 01561 reg.interrupts_enable = PROPERTY_DISABLE; 01562 } 01563 01564 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL5_INT2_PAD_CTRL, 01565 (uint8_t*) val, 1); 01566 } 01567 if (ret == 0) { 01568 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 01569 } else { 01570 ret = ret; 01571 } 01572 return ret; 01573 } 01574 01575 /** 01576 * @brief Select the signal that need to route on int2 pad.[get] 01577 * 01578 * @param ctx read / write interface definitions 01579 * @param val register CTRL5_INT2_PAD_CTRL 01580 * @retval interface status (MANDATORY: return 0 -> no Error) 01581 * 01582 */ 01583 int32_t iis2dlpc_pin_int2_route_get(iis2dlpc_ctx_t *ctx, 01584 iis2dlpc_ctrl5_int2_pad_ctrl_t *val) 01585 { 01586 int32_t ret; 01587 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL5_INT2_PAD_CTRL, 01588 (uint8_t*) val, 1); 01589 return ret; 01590 } 01591 /** 01592 * @brief All interrupt signals become available on INT1 pin.[set] 01593 * 01594 * @param ctx read / write interface definitions 01595 * @param val change the values of int2_on_int1 in reg CTRL_REG7 01596 * @retval interface status (MANDATORY: return 0 -> no Error) 01597 * 01598 */ 01599 int32_t iis2dlpc_all_on_int1_set(iis2dlpc_ctx_t *ctx, uint8_t val) 01600 { 01601 iis2dlpc_ctrl_reg7_t reg; 01602 int32_t ret; 01603 01604 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 01605 if (ret == 0) { 01606 reg.int2_on_int1 = val; 01607 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 01608 } 01609 return ret; 01610 } 01611 01612 /** 01613 * @brief All interrupt signals become available on INT1 pin.[get] 01614 * 01615 * @param ctx read / write interface definitions 01616 * @param val change the values of int2_on_int1 in reg CTRL_REG7 01617 * @retval interface status (MANDATORY: return 0 -> no Error) 01618 * 01619 */ 01620 int32_t iis2dlpc_all_on_int1_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 01621 { 01622 iis2dlpc_ctrl_reg7_t reg; 01623 int32_t ret; 01624 01625 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 01626 *val = reg.int2_on_int1; 01627 01628 return ret; 01629 } 01630 01631 /** 01632 * @} 01633 * 01634 */ 01635 01636 /** 01637 * @defgroup IIS2DLPC_Wake_Up_Event 01638 * @brief This section groups all the functions that manage the Wake 01639 * Up event generation. 01640 * @{ 01641 * 01642 */ 01643 01644 /** 01645 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set] 01646 * 01647 * @param ctx read / write interface definitions 01648 * @param val change the values of wk_ths in reg WAKE_UP_THS 01649 * @retval interface status (MANDATORY: return 0 -> no Error) 01650 * 01651 */ 01652 int32_t iis2dlpc_wkup_threshold_set(iis2dlpc_ctx_t *ctx, uint8_t val) 01653 { 01654 iis2dlpc_wake_up_ths_t reg; 01655 int32_t ret; 01656 01657 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) ®, 1); 01658 if (ret == 0) { 01659 reg.wk_ths = val; 01660 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) ®, 1); 01661 } 01662 return ret; 01663 } 01664 01665 /** 01666 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get] 01667 * 01668 * @param ctx read / write interface definitions 01669 * @param val change the values of wk_ths in reg WAKE_UP_THS 01670 * @retval interface status (MANDATORY: return 0 -> no Error) 01671 * 01672 */ 01673 int32_t iis2dlpc_wkup_threshold_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 01674 { 01675 iis2dlpc_wake_up_ths_t reg; 01676 int32_t ret; 01677 01678 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) ®, 1); 01679 *val = reg.wk_ths; 01680 01681 return ret; 01682 } 01683 01684 /** 01685 * @brief Wake up duration event.1LSb = 1 / ODR.[set] 01686 * 01687 * @param ctx read / write interface definitions 01688 * @param val change the values of wake_dur in reg WAKE_UP_DUR 01689 * @retval interface status (MANDATORY: return 0 -> no Error) 01690 * 01691 */ 01692 int32_t iis2dlpc_wkup_dur_set(iis2dlpc_ctx_t *ctx, uint8_t val) 01693 { 01694 iis2dlpc_wake_up_dur_t reg; 01695 int32_t ret; 01696 01697 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) ®, 1); 01698 if (ret == 0) { 01699 reg.wake_dur = val; 01700 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) ®, 1); 01701 } 01702 return ret; 01703 } 01704 01705 /** 01706 * @brief Wake up duration event.1LSb = 1 / ODR.[get] 01707 * 01708 * @param ctx read / write interface definitions 01709 * @param val change the values of wake_dur in reg WAKE_UP_DUR 01710 * @retval interface status (MANDATORY: return 0 -> no Error) 01711 * 01712 */ 01713 int32_t iis2dlpc_wkup_dur_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 01714 { 01715 iis2dlpc_wake_up_dur_t reg; 01716 int32_t ret; 01717 01718 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) ®, 1); 01719 *val = reg.wake_dur; 01720 01721 return ret; 01722 } 01723 01724 /** 01725 * @brief Data sent to wake-up interrupt function.[set] 01726 * 01727 * @param ctx read / write interface definitions 01728 * @param val change the values of usr_off_on_wu in reg CTRL_REG7 01729 * @retval interface status (MANDATORY: return 0 -> no Error) 01730 * 01731 */ 01732 int32_t iis2dlpc_wkup_feed_data_set(iis2dlpc_ctx_t *ctx, 01733 iis2dlpc_usr_off_on_wu_t val) 01734 { 01735 iis2dlpc_ctrl_reg7_t reg; 01736 int32_t ret; 01737 01738 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 01739 if (ret == 0) { 01740 reg.usr_off_on_wu = (uint8_t) val; 01741 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 01742 } 01743 return ret; 01744 } 01745 01746 /** 01747 * @brief Data sent to wake-up interrupt function.[get] 01748 * 01749 * @param ctx read / write interface definitions 01750 * @param val Get the values of usr_off_on_wu in reg CTRL_REG7 01751 * @retval interface status (MANDATORY: return 0 -> no Error) 01752 * 01753 */ 01754 int32_t iis2dlpc_wkup_feed_data_get(iis2dlpc_ctx_t *ctx, 01755 iis2dlpc_usr_off_on_wu_t *val) 01756 { 01757 iis2dlpc_ctrl_reg7_t reg; 01758 int32_t ret; 01759 01760 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 01761 01762 switch (reg.usr_off_on_wu) { 01763 case IIS2DLPC_HP_FEED: 01764 *val = IIS2DLPC_HP_FEED; 01765 break; 01766 case IIS2DLPC_USER_OFFSET_FEED: 01767 *val = IIS2DLPC_USER_OFFSET_FEED; 01768 break; 01769 default: 01770 *val = IIS2DLPC_HP_FEED; 01771 break; 01772 } 01773 return ret; 01774 } 01775 01776 /** 01777 * @} 01778 * 01779 */ 01780 01781 /** 01782 * @defgroup IIS2DLPC_Activity/Inactivity_Detection 01783 * @brief This section groups all the functions concerning 01784 * activity/inactivity detection. 01785 * @{ 01786 * 01787 */ 01788 01789 /** 01790 * @brief Config activity / inactivity or 01791 * stationary / motion detection.[set] 01792 * 01793 * @param ctx read / write interface definitions 01794 * @param val change the values of sleep_on / stationary in 01795 * reg WAKE_UP_THS / WAKE_UP_DUR 01796 * @retval interface status (MANDATORY: return 0 -> no Error) 01797 * 01798 */ 01799 int32_t iis2dlpc_act_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_sleep_on_t val) 01800 { 01801 iis2dlpc_wake_up_ths_t wake_up_ths; 01802 iis2dlpc_wake_up_dur_t wake_up_dur; 01803 int32_t ret; 01804 01805 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1); 01806 if (ret == 0) { 01807 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1); 01808 } 01809 if (ret == 0) { 01810 wake_up_ths.sleep_on = (uint8_t) val & 0x01U; 01811 wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1; 01812 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 2); 01813 } else { 01814 ret = ret; 01815 } 01816 01817 return ret; 01818 } 01819 01820 /** 01821 * @brief Config activity / inactivity or 01822 * stationary / motion detection. [get] 01823 * 01824 * @param ctx read / write interface definitions 01825 * @param val Get the values of sleep_on in reg WAKE_UP_THS 01826 * @retval interface status (MANDATORY: return 0 -> no Error) 01827 * 01828 */ 01829 int32_t iis2dlpc_act_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_sleep_on_t *val) 01830 { 01831 iis2dlpc_wake_up_ths_t wake_up_ths; 01832 iis2dlpc_wake_up_dur_t wake_up_dur;; 01833 int32_t ret; 01834 01835 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1); 01836 if (ret == 0) { 01837 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1); 01838 01839 switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on){ 01840 case IIS2DLPC_NO_DETECTION: 01841 *val = IIS2DLPC_NO_DETECTION; 01842 break; 01843 case IIS2DLPC_DETECT_ACT_INACT: 01844 *val = IIS2DLPC_DETECT_ACT_INACT; 01845 break; 01846 case IIS2DLPC_DETECT_STAT_MOTION: 01847 *val = IIS2DLPC_DETECT_STAT_MOTION; 01848 break; 01849 default: 01850 *val = IIS2DLPC_NO_DETECTION; 01851 break; 01852 } 01853 } 01854 return ret; 01855 } 01856 01857 /** 01858 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set] 01859 * 01860 * @param ctx read / write interface definitions 01861 * @param val change the values of sleep_dur in reg WAKE_UP_DUR 01862 * @retval interface status (MANDATORY: return 0 -> no Error) 01863 * 01864 */ 01865 int32_t iis2dlpc_act_sleep_dur_set(iis2dlpc_ctx_t *ctx, uint8_t val) 01866 { 01867 iis2dlpc_wake_up_dur_t reg; 01868 int32_t ret; 01869 01870 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) ®, 1); 01871 if (ret == 0) { 01872 reg.sleep_dur = val; 01873 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) ®, 1); 01874 } 01875 return ret; 01876 } 01877 01878 /** 01879 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[get] 01880 * 01881 * @param ctx read / write interface definitions 01882 * @param val change the values of sleep_dur in reg WAKE_UP_DUR 01883 * @retval interface status (MANDATORY: return 0 -> no Error) 01884 * 01885 */ 01886 int32_t iis2dlpc_act_sleep_dur_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 01887 { 01888 iis2dlpc_wake_up_dur_t reg; 01889 int32_t ret; 01890 01891 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) ®, 1); 01892 *val = reg.sleep_dur; 01893 01894 return ret; 01895 } 01896 01897 /** 01898 * @} 01899 * 01900 */ 01901 01902 /** 01903 * @defgroup IIS2DLPC_Tap_Generator 01904 * @brief This section groups all the functions that manage the tap 01905 * and double tap event generation. 01906 * @{ 01907 * 01908 */ 01909 01910 /** 01911 * @brief Threshold for tap recognition.[set] 01912 * 01913 * @param ctx read / write interface definitions 01914 * @param val change the values of tap_thsx in reg TAP_THS_X 01915 * @retval interface status (MANDATORY: return 0 -> no Error) 01916 * 01917 */ 01918 int32_t iis2dlpc_tap_threshold_x_set(iis2dlpc_ctx_t *ctx, uint8_t val) 01919 { 01920 iis2dlpc_tap_ths_x_t reg; 01921 int32_t ret; 01922 01923 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1); 01924 if (ret == 0) { 01925 reg.tap_thsx = val; 01926 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1); 01927 } 01928 return ret; 01929 } 01930 01931 /** 01932 * @brief Threshold for tap recognition.[get] 01933 * 01934 * @param ctx read / write interface definitions 01935 * @param val change the values of tap_thsx in reg TAP_THS_X 01936 * @retval interface status (MANDATORY: return 0 -> no Error) 01937 * 01938 */ 01939 int32_t iis2dlpc_tap_threshold_x_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 01940 { 01941 iis2dlpc_tap_ths_x_t reg; 01942 int32_t ret; 01943 01944 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1); 01945 *val = reg.tap_thsx; 01946 01947 return ret; 01948 } 01949 01950 /** 01951 * @brief Threshold for tap recognition.[set] 01952 * 01953 * @param ctx read / write interface definitions 01954 * @param val change the values of tap_thsy in reg TAP_THS_Y 01955 * @retval interface status (MANDATORY: return 0 -> no Error) 01956 * 01957 */ 01958 int32_t iis2dlpc_tap_threshold_y_set(iis2dlpc_ctx_t *ctx, uint8_t val) 01959 { 01960 iis2dlpc_tap_ths_y_t reg; 01961 int32_t ret; 01962 01963 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) ®, 1); 01964 if (ret == 0) { 01965 reg.tap_thsy = val; 01966 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) ®, 1); 01967 } 01968 return ret; 01969 } 01970 01971 /** 01972 * @brief Threshold for tap recognition.[get] 01973 * 01974 * @param ctx read / write interface definitions 01975 * @param val change the values of tap_thsy in reg TAP_THS_Y 01976 * @retval interface status (MANDATORY: return 0 -> no Error) 01977 * 01978 */ 01979 int32_t iis2dlpc_tap_threshold_y_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 01980 { 01981 iis2dlpc_tap_ths_y_t reg; 01982 int32_t ret; 01983 01984 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) ®, 1); 01985 *val = reg.tap_thsy; 01986 01987 return ret; 01988 } 01989 01990 /** 01991 * @brief Selection of axis priority for TAP detection.[set] 01992 * 01993 * @param ctx read / write interface definitions 01994 * @param val change the values of tap_prior in reg TAP_THS_Y 01995 * @retval interface status (MANDATORY: return 0 -> no Error) 01996 * 01997 */ 01998 int32_t iis2dlpc_tap_axis_priority_set(iis2dlpc_ctx_t *ctx, 01999 iis2dlpc_tap_prior_t val) 02000 { 02001 iis2dlpc_tap_ths_y_t reg; 02002 int32_t ret; 02003 02004 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) ®, 1); 02005 if (ret == 0) { 02006 reg.tap_prior = (uint8_t) val; 02007 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) ®, 1); 02008 } 02009 return ret; 02010 } 02011 02012 /** 02013 * @brief Selection of axis priority for TAP detection.[get] 02014 * 02015 * @param ctx read / write interface definitions 02016 * @param val Get the values of tap_prior in reg TAP_THS_Y 02017 * @retval interface status (MANDATORY: return 0 -> no Error) 02018 * 02019 */ 02020 int32_t iis2dlpc_tap_axis_priority_get(iis2dlpc_ctx_t *ctx, 02021 iis2dlpc_tap_prior_t *val) 02022 { 02023 iis2dlpc_tap_ths_y_t reg; 02024 int32_t ret; 02025 02026 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) ®, 1); 02027 02028 switch (reg.tap_prior) { 02029 case IIS2DLPC_XYZ: 02030 *val = IIS2DLPC_XYZ; 02031 break; 02032 case IIS2DLPC_YXZ: 02033 *val = IIS2DLPC_YXZ; 02034 break; 02035 case IIS2DLPC_XZY: 02036 *val = IIS2DLPC_XZY; 02037 break; 02038 case IIS2DLPC_ZYX: 02039 *val = IIS2DLPC_ZYX; 02040 break; 02041 case IIS2DLPC_YZX: 02042 *val = IIS2DLPC_YZX; 02043 break; 02044 case IIS2DLPC_ZXY: 02045 *val = IIS2DLPC_ZXY; 02046 break; 02047 default: 02048 *val = IIS2DLPC_XYZ; 02049 break; 02050 } 02051 return ret; 02052 } 02053 02054 /** 02055 * @brief Threshold for tap recognition.[set] 02056 * 02057 * @param ctx read / write interface definitions 02058 * @param val change the values of tap_thsz in reg TAP_THS_Z 02059 * @retval interface status (MANDATORY: return 0 -> no Error) 02060 * 02061 */ 02062 int32_t iis2dlpc_tap_threshold_z_set(iis2dlpc_ctx_t *ctx, uint8_t val) 02063 { 02064 iis2dlpc_tap_ths_z_t reg; 02065 int32_t ret; 02066 02067 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1); 02068 if (ret == 0) { 02069 reg.tap_thsz = val; 02070 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1); 02071 } 02072 02073 return ret; 02074 } 02075 02076 /** 02077 * @brief Threshold for tap recognition.[get] 02078 * 02079 * @param ctx read / write interface definitions 02080 * @param val change the values of tap_thsz in reg TAP_THS_Z 02081 * @retval interface status (MANDATORY: return 0 -> no Error) 02082 * 02083 */ 02084 int32_t iis2dlpc_tap_threshold_z_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 02085 { 02086 iis2dlpc_tap_ths_z_t reg; 02087 int32_t ret; 02088 02089 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1); 02090 *val = reg.tap_thsz; 02091 02092 return ret; 02093 } 02094 02095 /** 02096 * @brief Enable Z direction in tap recognition.[set] 02097 * 02098 * @param ctx read / write interface definitions 02099 * @param val change the values of tap_z_en in reg TAP_THS_Z 02100 * @retval interface status (MANDATORY: return 0 -> no Error) 02101 * 02102 */ 02103 int32_t iis2dlpc_tap_detection_on_z_set(iis2dlpc_ctx_t *ctx, uint8_t val) 02104 { 02105 iis2dlpc_tap_ths_z_t reg; 02106 int32_t ret; 02107 02108 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1); 02109 if (ret == 0) { 02110 reg.tap_z_en = val; 02111 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1); 02112 } 02113 return ret; 02114 } 02115 02116 /** 02117 * @brief Enable Z direction in tap recognition.[get] 02118 * 02119 * @param ctx read / write interface definitions 02120 * @param val change the values of tap_z_en in reg TAP_THS_Z 02121 * @retval interface status (MANDATORY: return 0 -> no Error) 02122 * 02123 */ 02124 int32_t iis2dlpc_tap_detection_on_z_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 02125 { 02126 iis2dlpc_tap_ths_z_t reg; 02127 int32_t ret; 02128 02129 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1); 02130 *val = reg.tap_z_en; 02131 02132 return ret; 02133 } 02134 02135 /** 02136 * @brief Enable Y direction in tap recognition.[set] 02137 * 02138 * @param ctx read / write interface definitions 02139 * @param val change the values of tap_y_en in reg TAP_THS_Z 02140 * @retval interface status (MANDATORY: return 0 -> no Error) 02141 * 02142 */ 02143 int32_t iis2dlpc_tap_detection_on_y_set(iis2dlpc_ctx_t *ctx, uint8_t val) 02144 { 02145 iis2dlpc_tap_ths_z_t reg; 02146 int32_t ret; 02147 02148 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1); 02149 if (ret == 0) { 02150 reg.tap_y_en = val; 02151 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1); 02152 } 02153 return ret; 02154 } 02155 02156 /** 02157 * @brief Enable Y direction in tap recognition.[get] 02158 * 02159 * @param ctx read / write interface definitions 02160 * @param val change the values of tap_y_en in reg TAP_THS_Z 02161 * @retval interface status (MANDATORY: return 0 -> no Error) 02162 * 02163 */ 02164 int32_t iis2dlpc_tap_detection_on_y_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 02165 { 02166 iis2dlpc_tap_ths_z_t reg; 02167 int32_t ret; 02168 02169 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1); 02170 *val = reg.tap_y_en; 02171 02172 return ret; 02173 } 02174 02175 /** 02176 * @brief Enable X direction in tap recognition.[set] 02177 * 02178 * @param ctx read / write interface definitions 02179 * @param val change the values of tap_x_en in reg TAP_THS_Z 02180 * @retval interface status (MANDATORY: return 0 -> no Error) 02181 * 02182 */ 02183 int32_t iis2dlpc_tap_detection_on_x_set(iis2dlpc_ctx_t *ctx, uint8_t val) 02184 { 02185 iis2dlpc_tap_ths_z_t reg; 02186 int32_t ret; 02187 02188 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1); 02189 if (ret == 0) { 02190 reg.tap_x_en = val; 02191 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1); 02192 } 02193 return ret; 02194 } 02195 02196 /** 02197 * @brief Enable X direction in tap recognition.[get] 02198 * 02199 * @param ctx read / write interface definitions 02200 * @param val change the values of tap_x_en in reg TAP_THS_Z 02201 * @retval interface status (MANDATORY: return 0 -> no Error) 02202 * 02203 */ 02204 int32_t iis2dlpc_tap_detection_on_x_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 02205 { 02206 iis2dlpc_tap_ths_z_t reg; 02207 int32_t ret; 02208 02209 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1); 02210 *val = reg.tap_x_en; 02211 02212 return ret; 02213 } 02214 02215 /** 02216 * @brief Maximum duration is the maximum time of an overthreshold signal 02217 * detection to be recognized as a tap event. The default value 02218 * of these bits is 00b which corresponds to 4*ODR_XL time. 02219 * If the SHOCK[1:0] bits are set to a different value, 1LSB 02220 * corresponds to 8*ODR_XL time.[set] 02221 * 02222 * @param ctx read / write interface definitions 02223 * @param val change the values of shock in reg INT_DUR 02224 * @retval interface status (MANDATORY: return 0 -> no Error) 02225 * 02226 */ 02227 int32_t iis2dlpc_tap_shock_set(iis2dlpc_ctx_t *ctx, uint8_t val) 02228 { 02229 iis2dlpc_int_dur_t reg; 02230 int32_t ret; 02231 02232 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1); 02233 if (ret == 0) { 02234 reg.shock = val; 02235 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1); 02236 } 02237 02238 return ret; 02239 } 02240 02241 /** 02242 * @brief Maximum duration is the maximum time of an overthreshold signal 02243 * detection to be recognized as a tap event. The default value 02244 * of these bits is 00b which corresponds to 4*ODR_XL time. 02245 * If the SHOCK[1:0] bits are set to a different value, 1LSB 02246 * corresponds to 8*ODR_XL time.[get] 02247 * 02248 * @param ctx read / write interface definitions 02249 * @param val change the values of shock in reg INT_DUR 02250 * @retval interface status (MANDATORY: return 0 -> no Error) 02251 * 02252 */ 02253 int32_t iis2dlpc_tap_shock_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 02254 { 02255 iis2dlpc_int_dur_t reg; 02256 int32_t ret; 02257 02258 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1); 02259 *val = reg.shock; 02260 02261 return ret; 02262 } 02263 02264 /** 02265 * @brief Quiet time is the time after the first detected tap in which 02266 * there must not be any overthreshold event. 02267 * The default value of these bits is 00b which corresponds 02268 * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different 02269 * value, 1LSB corresponds to 4*ODR_XL time.[set] 02270 * 02271 * @param ctx read / write interface definitions 02272 * @param val change the values of quiet in reg INT_DUR 02273 * @retval interface status (MANDATORY: return 0 -> no Error) 02274 * 02275 */ 02276 int32_t iis2dlpc_tap_quiet_set(iis2dlpc_ctx_t *ctx, uint8_t val) 02277 { 02278 iis2dlpc_int_dur_t reg; 02279 int32_t ret; 02280 02281 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1); 02282 if (ret == 0) { 02283 reg.quiet = val; 02284 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1); 02285 } 02286 return ret; 02287 } 02288 02289 /** 02290 * @brief Quiet time is the time after the first detected tap in which 02291 * there must not be any overthreshold event. 02292 * The default value of these bits is 00b which corresponds 02293 * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different 02294 * value, 1LSB corresponds to 4*ODR_XL time.[get] 02295 * 02296 * @param ctx read / write interface definitions 02297 * @param val change the values of quiet in reg INT_DUR 02298 * @retval interface status (MANDATORY: return 0 -> no Error) 02299 * 02300 */ 02301 int32_t iis2dlpc_tap_quiet_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 02302 { 02303 iis2dlpc_int_dur_t reg; 02304 int32_t ret; 02305 02306 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1); 02307 *val = reg.quiet; 02308 02309 return ret; 02310 } 02311 02312 /** 02313 * @brief When double tap recognition is enabled, this register expresses 02314 * the maximum time between two consecutive detected taps to 02315 * determine a double tap event. 02316 * The default value of these bits is 0000b which corresponds 02317 * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different 02318 * value, 1LSB corresponds to 32*ODR_XL time.[set] 02319 * 02320 * @param ctx read / write interface definitions 02321 * @param val change the values of latency in reg INT_DUR 02322 * @retval interface status (MANDATORY: return 0 -> no Error) 02323 * 02324 */ 02325 int32_t iis2dlpc_tap_dur_set(iis2dlpc_ctx_t *ctx, uint8_t val) 02326 { 02327 iis2dlpc_int_dur_t reg; 02328 int32_t ret; 02329 02330 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1); 02331 if (ret == 0) { 02332 reg.latency = val; 02333 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1); 02334 } 02335 return ret; 02336 } 02337 02338 /** 02339 * @brief When double tap recognition is enabled, this register expresses 02340 * the maximum time between two consecutive detected taps to 02341 * determine a double tap event. 02342 * The default value of these bits is 0000b which corresponds 02343 * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different 02344 * value, 1LSB corresponds to 32*ODR_XL time.[get] 02345 * 02346 * @param ctx read / write interface definitions 02347 * @param val change the values of latency in reg INT_DUR 02348 * @retval interface status (MANDATORY: return 0 -> no Error) 02349 * 02350 */ 02351 int32_t iis2dlpc_tap_dur_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 02352 { 02353 iis2dlpc_int_dur_t reg; 02354 int32_t ret; 02355 02356 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1); 02357 *val = reg.latency; 02358 02359 return ret; 02360 } 02361 02362 /** 02363 * @brief Single/double-tap event enable.[set] 02364 * 02365 * @param ctx read / write interface definitions 02366 * @param val change the values of single_double_tap in reg WAKE_UP_THS 02367 * @retval interface status (MANDATORY: return 0 -> no Error) 02368 * 02369 */ 02370 int32_t iis2dlpc_tap_mode_set(iis2dlpc_ctx_t *ctx, 02371 iis2dlpc_single_double_tap_t val) 02372 { 02373 iis2dlpc_wake_up_ths_t reg; 02374 int32_t ret; 02375 02376 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) ®, 1); 02377 if (ret == 0) { 02378 reg.single_double_tap = (uint8_t) val; 02379 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) ®, 1); 02380 } 02381 return ret; 02382 } 02383 02384 /** 02385 * @brief Single/double-tap event enable.[get] 02386 * 02387 * @param ctx read / write interface definitions 02388 * @param val Get the values of single_double_tap in reg WAKE_UP_THS 02389 * @retval interface status (MANDATORY: return 0 -> no Error) 02390 * 02391 */ 02392 int32_t iis2dlpc_tap_mode_get(iis2dlpc_ctx_t *ctx, 02393 iis2dlpc_single_double_tap_t *val) 02394 { 02395 iis2dlpc_wake_up_ths_t reg; 02396 int32_t ret; 02397 02398 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) ®, 1); 02399 02400 switch (reg.single_double_tap) { 02401 case IIS2DLPC_ONLY_SINGLE: 02402 *val = IIS2DLPC_ONLY_SINGLE; 02403 break; 02404 case IIS2DLPC_BOTH_SINGLE_DOUBLE: 02405 *val = IIS2DLPC_BOTH_SINGLE_DOUBLE; 02406 break; 02407 default: 02408 *val = IIS2DLPC_ONLY_SINGLE; 02409 break; 02410 } 02411 02412 return ret; 02413 } 02414 02415 /** 02416 * @brief Read the tap / double tap source register.[get] 02417 * 02418 * @param ctx read / write interface definitions 02419 * @param iis2dlpc_tap_src: union of registers from TAP_SRC to 02420 * @retval interface status (MANDATORY: return 0 -> no Error) 02421 * 02422 */ 02423 int32_t iis2dlpc_tap_src_get(iis2dlpc_ctx_t *ctx, iis2dlpc_tap_src_t *val) 02424 { 02425 int32_t ret; 02426 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_SRC, (uint8_t*) val, 1); 02427 return ret; 02428 } 02429 02430 /** 02431 * @} 02432 * 02433 */ 02434 02435 /** 02436 * @defgroup IIS2DLPC_Six_Position_Detection(6D/4D) 02437 * @brief This section groups all the functions concerning six 02438 * position detection (6D). 02439 * @{ 02440 * 02441 */ 02442 02443 /** 02444 * @brief Threshold for 4D/6D function.[set] 02445 * 02446 * @param ctx read / write interface definitions 02447 * @param val change the values of 6d_ths in reg TAP_THS_X 02448 * @retval interface status (MANDATORY: return 0 -> no Error) 02449 * 02450 */ 02451 int32_t iis2dlpc_6d_threshold_set(iis2dlpc_ctx_t *ctx, uint8_t val) 02452 { 02453 iis2dlpc_tap_ths_x_t reg; 02454 int32_t ret; 02455 02456 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1); 02457 if (ret == 0) { 02458 reg._6d_ths = val; 02459 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1); 02460 } 02461 return ret; 02462 } 02463 02464 /** 02465 * @brief Threshold for 4D/6D function.[get] 02466 * 02467 * @param ctx read / write interface definitions 02468 * @param val change the values of 6d_ths in reg TAP_THS_X 02469 * @retval interface status (MANDATORY: return 0 -> no Error) 02470 * 02471 */ 02472 int32_t iis2dlpc_6d_threshold_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 02473 { 02474 iis2dlpc_tap_ths_x_t reg; 02475 int32_t ret; 02476 02477 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1); 02478 *val = reg._6d_ths; 02479 02480 return ret; 02481 } 02482 02483 /** 02484 * @brief 4D orientation detection enable.[set] 02485 * 02486 * @param ctx read / write interface definitions 02487 * @param val change the values of 4d_en in reg TAP_THS_X 02488 * @retval interface status (MANDATORY: return 0 -> no Error) 02489 * 02490 */ 02491 int32_t iis2dlpc_4d_mode_set(iis2dlpc_ctx_t *ctx, uint8_t val) 02492 { 02493 iis2dlpc_tap_ths_x_t reg; 02494 int32_t ret; 02495 02496 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1); 02497 if (ret == 0) { 02498 reg._4d_en = val; 02499 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1); 02500 } 02501 02502 return ret; 02503 } 02504 02505 /** 02506 * @brief 4D orientation detection enable.[get] 02507 * 02508 * @param ctx read / write interface definitions 02509 * @param val change the values of 4d_en in reg TAP_THS_X 02510 * @retval interface status (MANDATORY: return 0 -> no Error) 02511 * 02512 */ 02513 int32_t iis2dlpc_4d_mode_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 02514 { 02515 iis2dlpc_tap_ths_x_t reg; 02516 int32_t ret; 02517 02518 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1); 02519 *val = reg._4d_en; 02520 02521 return ret; 02522 } 02523 02524 /** 02525 * @brief Read the 6D tap source register.[get] 02526 * 02527 * @param ctx read / write interface definitions 02528 * @param val union of registers from SIXD_SRC 02529 * @retval interface status (MANDATORY: return 0 -> no Error) 02530 * 02531 */ 02532 int32_t iis2dlpc_6d_src_get(iis2dlpc_ctx_t *ctx, iis2dlpc_sixd_src_t *val) 02533 { 02534 int32_t ret; 02535 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_SIXD_SRC, (uint8_t*) val, 1); 02536 return ret; 02537 } 02538 /** 02539 * @brief Data sent to 6D interrupt function.[set] 02540 * 02541 * @param ctx read / write interface definitions 02542 * @param val change the values of lpass_on6d in reg CTRL_REG7 02543 * @retval interface status (MANDATORY: return 0 -> no Error) 02544 * 02545 */ 02546 int32_t iis2dlpc_6d_feed_data_set(iis2dlpc_ctx_t *ctx, 02547 iis2dlpc_lpass_on6d_t val) 02548 { 02549 iis2dlpc_ctrl_reg7_t reg; 02550 int32_t ret; 02551 02552 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 02553 if (ret == 0) { 02554 reg.lpass_on6d = (uint8_t) val; 02555 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 02556 } 02557 return ret; 02558 } 02559 02560 /** 02561 * @brief Data sent to 6D interrupt function.[get] 02562 * 02563 * @param ctx read / write interface definitions 02564 * @param val Get the values of lpass_on6d in reg CTRL_REG7 02565 * @retval interface status (MANDATORY: return 0 -> no Error) 02566 * 02567 */ 02568 int32_t iis2dlpc_6d_feed_data_get(iis2dlpc_ctx_t *ctx, 02569 iis2dlpc_lpass_on6d_t *val) 02570 { 02571 iis2dlpc_ctrl_reg7_t reg; 02572 int32_t ret; 02573 02574 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) ®, 1); 02575 02576 switch (reg.lpass_on6d) { 02577 case IIS2DLPC_ODR_DIV_2_FEED: 02578 *val = IIS2DLPC_ODR_DIV_2_FEED; 02579 break; 02580 case IIS2DLPC_LPF2_FEED: 02581 *val = IIS2DLPC_LPF2_FEED; 02582 break; 02583 default: 02584 *val = IIS2DLPC_ODR_DIV_2_FEED; 02585 break; 02586 } 02587 return ret; 02588 } 02589 02590 /** 02591 * @} 02592 * 02593 */ 02594 02595 /** 02596 * @defgroup IIS2DLPC_Free_Fall 02597 * @brief This section group all the functions concerning 02598 * the free fall detection. 02599 * @{ 02600 * 02601 */ 02602 02603 /** 02604 * @brief Wake up duration event(1LSb = 1 / ODR).[set] 02605 * 02606 * @param ctx read / write interface definitions 02607 * @param val change the values of ff_dur in reg 02608 * WAKE_UP_DUR /F REE_FALL 02609 * @retval interface status (MANDATORY: return 0 -> no Error) 02610 * 02611 */ 02612 int32_t iis2dlpc_ff_dur_set(iis2dlpc_ctx_t *ctx, uint8_t val) 02613 { 02614 iis2dlpc_wake_up_dur_t wake_up_dur; 02615 iis2dlpc_free_fall_t free_fall; 02616 int32_t ret; 02617 02618 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1); 02619 if (ret == 0) { 02620 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &free_fall, 1); 02621 } 02622 if(ret == 0) { 02623 wake_up_dur.ff_dur = ( (uint8_t) val & 0x20U) >> 5; 02624 free_fall.ff_dur = (uint8_t) val & 0x1FU; 02625 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1); 02626 } 02627 if(ret == 0) { 02628 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &free_fall, 1); 02629 } 02630 02631 return ret; 02632 } 02633 02634 /** 02635 * @brief Wake up duration event(1LSb = 1 / ODR).[get] 02636 * 02637 * @param ctx read / write interface definitions 02638 * @param val change the values of ff_dur in 02639 * reg WAKE_UP_DUR /F REE_FALL 02640 * @retval interface status (MANDATORY: return 0 -> no Error) 02641 * 02642 */ 02643 int32_t iis2dlpc_ff_dur_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 02644 { 02645 iis2dlpc_wake_up_dur_t wake_up_dur; 02646 iis2dlpc_free_fall_t free_fall; 02647 int32_t ret; 02648 02649 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1); 02650 if (ret == 0) { 02651 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &free_fall, 1); 02652 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; 02653 } 02654 return ret; 02655 } 02656 02657 /** 02658 * @brief Free fall threshold setting.[set] 02659 * 02660 * @param ctx read / write interface definitions 02661 * @param val change the values of ff_ths in reg FREE_FALL 02662 * @retval interface status (MANDATORY: return 0 -> no Error) 02663 * 02664 */ 02665 int32_t iis2dlpc_ff_threshold_set(iis2dlpc_ctx_t *ctx, iis2dlpc_ff_ths_t val) 02666 { 02667 iis2dlpc_free_fall_t reg; 02668 int32_t ret; 02669 02670 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) ®, 1); 02671 if (ret == 0) { 02672 reg.ff_ths = (uint8_t) val; 02673 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) ®, 1); 02674 } 02675 02676 return ret; 02677 } 02678 02679 /** 02680 * @brief Free fall threshold setting.[get] 02681 * 02682 * @param ctx read / write interface definitions 02683 * @param val Get the values of ff_ths in reg FREE_FALL 02684 * @retval interface status (MANDATORY: return 0 -> no Error) 02685 * 02686 */ 02687 int32_t iis2dlpc_ff_threshold_get(iis2dlpc_ctx_t *ctx, 02688 iis2dlpc_ff_ths_t *val) 02689 { 02690 iis2dlpc_free_fall_t reg; 02691 int32_t ret; 02692 02693 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) ®, 1); 02694 02695 switch (reg.ff_ths) { 02696 case IIS2DLPC_FF_TSH_5LSb_FS2g: 02697 *val = IIS2DLPC_FF_TSH_5LSb_FS2g; 02698 break; 02699 case IIS2DLPC_FF_TSH_7LSb_FS2g: 02700 *val = IIS2DLPC_FF_TSH_7LSb_FS2g; 02701 break; 02702 case IIS2DLPC_FF_TSH_8LSb_FS2g: 02703 *val = IIS2DLPC_FF_TSH_8LSb_FS2g; 02704 break; 02705 case IIS2DLPC_FF_TSH_10LSb_FS2g: 02706 *val = IIS2DLPC_FF_TSH_10LSb_FS2g; 02707 break; 02708 case IIS2DLPC_FF_TSH_11LSb_FS2g: 02709 *val = IIS2DLPC_FF_TSH_11LSb_FS2g; 02710 break; 02711 case IIS2DLPC_FF_TSH_13LSb_FS2g: 02712 *val = IIS2DLPC_FF_TSH_13LSb_FS2g; 02713 break; 02714 case IIS2DLPC_FF_TSH_15LSb_FS2g: 02715 *val = IIS2DLPC_FF_TSH_15LSb_FS2g; 02716 break; 02717 case IIS2DLPC_FF_TSH_16LSb_FS2g: 02718 *val = IIS2DLPC_FF_TSH_16LSb_FS2g; 02719 break; 02720 default: 02721 *val = IIS2DLPC_FF_TSH_5LSb_FS2g; 02722 break; 02723 } 02724 return ret; 02725 } 02726 02727 /** 02728 * @} 02729 * 02730 */ 02731 02732 /** 02733 * @defgroup IIS2DLPC_Fifo 02734 * @brief This section group all the functions concerning the fifo usage 02735 * @{ 02736 * 02737 */ 02738 02739 /** 02740 * @brief FIFO watermark level selection.[set] 02741 * 02742 * @param ctx read / write interface definitions 02743 * @param val change the values of fth in reg FIFO_CTRL 02744 * @retval interface status (MANDATORY: return 0 -> no Error) 02745 * 02746 */ 02747 int32_t iis2dlpc_fifo_watermark_set(iis2dlpc_ctx_t *ctx, uint8_t val) 02748 { 02749 iis2dlpc_fifo_ctrl_t reg; 02750 int32_t ret; 02751 02752 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) ®, 1); 02753 if (ret == 0) { 02754 reg.fth = val; 02755 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) ®, 1); 02756 } 02757 02758 return ret; 02759 } 02760 02761 /** 02762 * @brief FIFO watermark level selection.[get] 02763 * 02764 * @param ctx read / write interface definitions 02765 * @param val change the values of fth in reg FIFO_CTRL 02766 * @retval interface status (MANDATORY: return 0 -> no Error) 02767 * 02768 */ 02769 int32_t iis2dlpc_fifo_watermark_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 02770 { 02771 iis2dlpc_fifo_ctrl_t reg; 02772 int32_t ret; 02773 02774 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) ®, 1); 02775 *val = reg.fth; 02776 02777 return ret; 02778 } 02779 02780 /** 02781 * @brief FIFO mode selection.[set] 02782 * 02783 * @param ctx read / write interface definitions 02784 * @param val change the values of fmode in reg FIFO_CTRL 02785 * @retval interface status (MANDATORY: return 0 -> no Error) 02786 * 02787 */ 02788 int32_t iis2dlpc_fifo_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_fmode_t val) 02789 { 02790 iis2dlpc_fifo_ctrl_t reg; 02791 int32_t ret; 02792 02793 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) ®, 1); 02794 if (ret == 0) { 02795 reg.fmode = (uint8_t) val; 02796 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) ®, 1); 02797 } 02798 return ret; 02799 } 02800 02801 /** 02802 * @brief FIFO mode selection.[get] 02803 * 02804 * @param ctx read / write interface definitions 02805 * @param val Get the values of fmode in reg FIFO_CTRL 02806 * @retval interface status (MANDATORY: return 0 -> no Error) 02807 * 02808 */ 02809 int32_t iis2dlpc_fifo_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_fmode_t *val) 02810 { 02811 iis2dlpc_fifo_ctrl_t reg; 02812 int32_t ret; 02813 02814 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) ®, 1); 02815 02816 switch (reg.fmode) { 02817 case IIS2DLPC_BYPASS_MODE: 02818 *val = IIS2DLPC_BYPASS_MODE; 02819 break; 02820 case IIS2DLPC_FIFO_MODE: 02821 *val = IIS2DLPC_FIFO_MODE; 02822 break; 02823 case IIS2DLPC_STREAM_TO_FIFO_MODE: 02824 *val = IIS2DLPC_STREAM_TO_FIFO_MODE; 02825 break; 02826 case IIS2DLPC_BYPASS_TO_STREAM_MODE: 02827 *val = IIS2DLPC_BYPASS_TO_STREAM_MODE; 02828 break; 02829 case IIS2DLPC_STREAM_MODE: 02830 *val = IIS2DLPC_STREAM_MODE; 02831 break; 02832 default: 02833 *val = IIS2DLPC_BYPASS_MODE; 02834 break; 02835 } 02836 return ret; 02837 } 02838 02839 /** 02840 * @brief Number of unread samples stored in FIFO.[get] 02841 * 02842 * @param ctx read / write interface definitions 02843 * @param val change the values of diff in reg FIFO_SAMPLES 02844 * @retval interface status (MANDATORY: return 0 -> no Error) 02845 * 02846 */ 02847 int32_t iis2dlpc_fifo_data_level_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 02848 { 02849 iis2dlpc_fifo_samples_t reg; 02850 int32_t ret; 02851 02852 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES,(uint8_t*) ®, 1); 02853 *val = reg.diff; 02854 02855 return ret; 02856 } 02857 /** 02858 * @brief FIFO overrun status.[get] 02859 * 02860 * @param ctx read / write interface definitions 02861 * @param val change the values of fifo_ovr in reg FIFO_SAMPLES 02862 * @retval interface status (MANDATORY: return 0 -> no Error) 02863 * 02864 */ 02865 int32_t iis2dlpc_fifo_ovr_flag_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 02866 { 02867 iis2dlpc_fifo_samples_t reg; 02868 int32_t ret; 02869 02870 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES,(uint8_t*) ®, 1); 02871 *val = reg.fifo_ovr; 02872 02873 return ret; 02874 } 02875 /** 02876 * @brief FIFO threshold status flag.[get] 02877 * 02878 * @param ctx read / write interface definitions 02879 * @param val change the values of fifo_fth in reg FIFO_SAMPLES 02880 * @retval interface status (MANDATORY: return 0 -> no Error) 02881 * 02882 */ 02883 int32_t iis2dlpc_fifo_wtm_flag_get(iis2dlpc_ctx_t *ctx, uint8_t *val) 02884 { 02885 iis2dlpc_fifo_samples_t reg; 02886 int32_t ret; 02887 02888 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES,(uint8_t*) ®, 1); 02889 *val = reg.fifo_fth; 02890 02891 return ret; 02892 } 02893 /** 02894 * @} 02895 * 02896 */ 02897 02898 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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