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BSP_DISCO_L4R9I
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mx25lm51245g.h
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00001 /** 00002 ****************************************************************************** 00003 * @file mx25lm51245g.h 00004 * @author MCD Application Team 00005 * @brief This file contains all the description of the MX25LM51245G Octal memory. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef __MX25LM51245G_H 00022 #define __MX25LM51245G_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 00030 /** @addtogroup BSP 00031 * @{ 00032 */ 00033 00034 /** @addtogroup Components 00035 * @{ 00036 */ 00037 00038 /** @addtogroup MX25LM51245G 00039 * @{ 00040 */ 00041 00042 /** @defgroup MX25LM51245G_Exported_Types 00043 * @{ 00044 */ 00045 00046 /** 00047 * @} 00048 */ 00049 00050 /** @defgroup MX25LM51245G_Exported_Constants 00051 * @{ 00052 */ 00053 00054 /** 00055 * @brief MX25LM51245G Configuration 00056 */ 00057 #define MX25LM51245G_FLASH_SIZE 0x4000000 /* 512 MBits => 64 MBytes */ 00058 #define MX25LM51245G_BLOCK_SIZE 0x10000 /* 1024 blocks of 64 KBytes */ 00059 #define MX25LM51245G_SECTOR_SIZE 0x1000 /* 16384 sectors of 4 kBytes */ 00060 #define MX25LM51245G_PAGE_SIZE 0x100 /* 262144 pages of 256 bytes */ 00061 00062 #define MX25LM51245G_DUMMY_CYCLES_READ 8 00063 #define MX25LM51245G_DUMMY_CYCLES_READ_OCTAL_66M 6 00064 #define MX25LM51245G_DUMMY_CYCLES_READ_OCTAL_84M 8 00065 #define MX25LM51245G_DUMMY_CYCLES_READ_OCTAL_104M 10 00066 #define MX25LM51245G_DUMMY_CYCLES_READ_OCTAL_133M 14 00067 00068 #define MX25LM51245G_CR2_DC_66M MX25LM51245G_CR2_DC_6_CYCLES 00069 #define MX25LM51245G_CR2_DC_84M MX25LM51245G_CR2_DC_8_CYCLES 00070 #define MX25LM51245G_CR2_DC_104M MX25LM51245G_CR2_DC_10_CYCLES 00071 #define MX25LM51245G_CR2_DC_133M MX25LM51245G_CR2_DC_14_CYCLES 00072 00073 #define MX25LM51245G_CHIP_ERASE_MAX_TIME 300000 00074 #define MX25LM51245G_BLOCK_ERASE_MAX_TIME 2000 00075 #define MX25LM51245G_SECTOR_ERASE_MAX_TIME 400 00076 #define MX25LM51245G_WRITE_REG_MAX_TIME 40 00077 00078 /** 00079 * @brief MX25LM51245G Commands 00080 */ 00081 /* Read Operations */ 00082 #define READ_CMD 0x03 00083 #define READ_4_BYTE_ADDR_CMD 0x13 00084 00085 #define FAST_READ_CMD 0x0B 00086 #define FAST_READ_4_BYTE_ADDR_CMD 0x0C 00087 00088 #define OCTAL_IO_READ_CMD 0xEC13 00089 #define OCTAL_IO_DTR_READ_CMD 0xEE11 00090 00091 /* Program Operations */ 00092 #define PAGE_PROG_CMD 0x02 00093 #define PAGE_PROG_4_BYTE_ADDR_CMD 0x12 00094 00095 #define OCTAL_PAGE_PROG_CMD 0x12ED 00096 00097 /* Erase Operations */ 00098 #define SECTOR_ERASE_CMD 0x20 00099 #define SECTOR_ERASE_4_BYTE_ADDR_CMD 0x21 00100 00101 #define OCTAL_SECTOR_ERASE_CMD 0x21DE 00102 00103 #define BLOCK_ERASE_CMD 0xD8 00104 #define BLOCK_ERASE_4_BYTE_ADDR_CMD 0xDC 00105 00106 #define OCTAL_BLOCK_ERASE_CMD 0xDC23 00107 00108 #define CHIP_ERASE_CMD 0x60 00109 #define CHIP_ERASE_CMD_2 0xC7 00110 00111 #define OCTAL_CHIP_ERASE_CMD 0x609F 00112 #define OCTAL_CHIP_ERASE_CMD_2 0xC738 00113 00114 #define PROG_ERASE_RESUME_CMD 0x30 00115 #define PROG_ERASE_SUSPEND_CMD 0xB0 00116 00117 #define OCTAL_PROG_ERASE_RESUME_CMD 0x30CF 00118 #define OCTAL_PROG_ERASE_SUSPEND_CMD 0xB04F 00119 00120 /* Identification Operations */ 00121 #define READ_ID_CMD 0x9F 00122 #define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A 00123 00124 #define OCTAL_READ_ID_CMD 0x9F60 00125 #define OCTAL_READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5AA5 00126 00127 /* Write Operations */ 00128 #define WRITE_ENABLE_CMD 0x06 00129 #define WRITE_DISABLE_CMD 0x04 00130 00131 #define OCTAL_WRITE_ENABLE_CMD 0x06F9 00132 #define OCTAL_WRITE_DISABLE_CMD 0x04FB 00133 00134 /* Register Operations */ 00135 #define READ_STATUS_REG_CMD 0x05 00136 #define READ_CFG_REG_CMD 0x15 00137 #define WRITE_STATUS_CFG_REG_CMD 0x01 00138 00139 #define OCTAL_READ_STATUS_REG_CMD 0x05FA 00140 #define OCTAL_READ_CFG_REG_CMD 0x15EA 00141 #define OCTAL_WRITE_STATUS_CFG_REG_CMD 0x01FE 00142 00143 #define READ_CFG_REG_2_CMD 0x71 00144 #define WRITE_CFG_REG_2_CMD 0x72 00145 00146 #define OCTAL_READ_CFG_REG_2_CMD 0x718E 00147 #define OCTAL_WRITE_CFG_REG_2_CMD 0x728D 00148 00149 #define READ_FAST_BOOT_REG_CMD 0x16 00150 #define WRITE_FAST_BOOT_REG 0x17 00151 #define ERASE_FAST_BOOT_REG 0x18 00152 00153 #define OCTAL_READ_FAST_BOOT_REG_CMD 0x16E9 00154 #define OCTAL_WRITE_FAST_BOOT_REG 0x17E8 00155 #define OCTAL_ERASE_FAST_BOOT_REG 0x18E7 00156 00157 #define READ_SEC_REG_CMD 0x2B 00158 #define WRITE_SEC_REG_CMD 0x2F 00159 00160 #define OCTAL_READ_SECURITY_REG_CMD 0x2BD4 00161 #define OCTAL_WRITE_SECURITY_REG_CMD 0x2FD0 00162 00163 #define READ_LOCK_REG_CMD 0x2D 00164 #define WRITE_LOCK_REG_CMD 0x2C 00165 00166 #define OCTAL_READ_LOCK_REG_CMD 0x2DD2 00167 #define OCTAL_WRITE_LOCK_REG_CMD 0x2CD3 00168 00169 #define READ_SPB_STATUS_CMD 0xE2 00170 #define PROG_SPB_BIT_CMD 0xE3 00171 #define ERASE_ALL_SPB_BIT_CMD 0xE4 00172 00173 #define OCTAL_READ_SPB_STATUS_CMD 0xE21D 00174 #define OCTAL_PROG_SPB_BIT_CMD 0xE31C 00175 #define OCTAL_ERASE_ALL_SPB_BIT_CMD 0xE41B 00176 00177 #define READ_DPB_REG_CMD 0xE0 00178 #define WRITE_DPB_REG_CMD 0xE1 00179 00180 #define OCTAL_READ_DPB_REG_CMD 0xE01F 00181 #define OCTAL_WRITE_DPB_REG_CMD 0xE11E 00182 00183 /* Power Down Operations */ 00184 #define DEEP_POWER_DOWN_CMD 0xB9 00185 #define RELEASE_DEEP_POWER_DOWN_CMD 0xAB 00186 00187 #define OCTAL_ENTER_DEEP_POWER_DOWN_CMD 0xB946 00188 00189 /* Burst Operations */ 00190 #define SET_BURST_LENGTH_CMD 0xC0 00191 00192 #define OCTAL_SET_BURST_LENGTH_CMD 0xC03F 00193 00194 /* One-Time Programmable Operations */ 00195 #define ENTER_SECURED_OTP_CMD 0xB1 00196 #define EXIT_SECURED_OTP_CMD 0xC1 00197 00198 #define OCTAL_ENTER_SECURED_OTP_CMD 0xB14E 00199 #define OCTAL_EXIT_SECURED_OTP_CMD 0xC13E 00200 00201 /* No Operation */ 00202 #define NO_OPERATION_CMD 0x00 00203 00204 #define OCTAL_NO_OPERATION_CMD 0x00FF 00205 00206 /* Reset Operations */ 00207 #define RESET_ENABLE_CMD 0x66 00208 #define RESET_MEMORY_CMD 0x99 00209 00210 #define OCTAL_RESET_ENABLE_CMD 0x6699 00211 #define OCTAL_RESET_MEMORY_CMD 0x9966 00212 00213 /* Protection Operations */ 00214 #define WRITE_PROTECT_SEL_CMD 0x68 00215 00216 #define OCTAL_WRITE_PROTECT_SEL_CMD 0x6897 00217 00218 #define GANG_BLOCK_LOCK_CMD 0x7E 00219 #define GANG_BLOCK_UNLOCK_CMD 0x98 00220 00221 #define OCTAL_GANG_BLOCK_LOCK_CMD 0x7E81 00222 #define OCTAL_GANG_BLOCK_UNLOCK_CMD 0x9867 00223 00224 /** 00225 * @brief MX25LM51245G Registers 00226 */ 00227 /* Status Register */ 00228 #define MX25LM51245G_SR_WIP ((uint8_t)0x01) /*!< Write in progress */ 00229 #define MX25LM51245G_SR_WEL ((uint8_t)0x02) /*!< Write enable latch */ 00230 #define MX25LM51245G_SR_BP ((uint8_t)0x3C) /*!< Block protect */ 00231 00232 /* Configuration Register 1 */ 00233 #define MX25LM51245G_CR1_ODS ((uint8_t)0x07) /*!< Output driver strength */ 00234 #define MX25LM51245G_CR1_TB ((uint8_t)0x08) /*!< Top / bottom */ 00235 00236 /* Configuration Register 2 */ 00237 /* Address : 0x00000000 */ 00238 #define MX25LM51245G_CR2_REG1_ADDR ((uint32_t)0x00000000) /*!< CR2 register address 0x00000000 */ 00239 #define MX25LM51245G_CR2_SOPI ((uint8_t)0x01) /*!< STR OPI Enable */ 00240 #define MX25LM51245G_CR2_DOPI ((uint8_t)0x02) /*!< DTR OPI Enable */ 00241 /* Address : 0x00000200 */ 00242 #define MX25LM51245G_CR2_REG2_ADDR ((uint32_t)0x00000200) /*!< CR2 register address 0x00000200 */ 00243 #define MX25LM51245G_CR2_DQSPRC ((uint8_t)0x01) /*!< DTR DQS pre-cycle */ 00244 #define MX25LM51245G_CR2_DOS ((uint8_t)0x02) /*!< DQS on STR mode */ 00245 /* Address : 0x00000300 */ 00246 #define MX25LM51245G_CR2_REG3_ADDR ((uint32_t)0x00000300) /*!< CR2 register address 0x00000300 */ 00247 #define MX25LM51245G_CR2_DC ((uint8_t)0x07) /*!< Dummy cycle */ 00248 #define MX25LM51245G_CR2_DC_20_CYCLES ((uint8_t)0x00) /*!< 20 Dummy cycles */ 00249 #define MX25LM51245G_CR2_DC_18_CYCLES ((uint8_t)0x01) /*!< 18 Dummy cycles */ 00250 #define MX25LM51245G_CR2_DC_16_CYCLES ((uint8_t)0x02) /*!< 16 Dummy cycles */ 00251 #define MX25LM51245G_CR2_DC_14_CYCLES ((uint8_t)0x03) /*!< 14 Dummy cycles */ 00252 #define MX25LM51245G_CR2_DC_12_CYCLES ((uint8_t)0x04) /*!< 12 Dummy cycles */ 00253 #define MX25LM51245G_CR2_DC_10_CYCLES ((uint8_t)0x05) /*!< 10 Dummy cycles */ 00254 #define MX25LM51245G_CR2_DC_8_CYCLES ((uint8_t)0x06) /*!< 8 Dummy cycles */ 00255 #define MX25LM51245G_CR2_DC_6_CYCLES ((uint8_t)0x07) /*!< 6 Dummy cycles */ 00256 /* Address : 0x00000500 */ 00257 #define MX25LM51245G_CR2_REG4_ADDR ((uint32_t)0x00000500) /*!< CR2 register address 0x00000500 */ 00258 #define MX25LM51245G_CR2_PPTSEL ((uint8_t)0x01) /*!< Preamble pattern selection */ 00259 /* Address : 0x40000000 */ 00260 #define MX25LM51245G_CR2_REG5_ADDR ((uint32_t)0x40000000) /*!< CR2 register address 0x40000000 */ 00261 #define MX25LM51245G_CR2_DEFSOPI ((uint8_t)0x01) /*!< Enable SOPI after power on reset */ 00262 #define MX25LM51245G_CR2_DEFDOPI ((uint8_t)0x02) /*!< Enable DOPI after power on reset */ 00263 00264 /* Security Register */ 00265 #define MX25LM51245G_SECR_SOI ((uint8_t)0x01) /*!< Secured OTP indicator */ 00266 #define MX25LM51245G_SECR_LDSO ((uint8_t)0x02) /*!< Lock-down secured OTP */ 00267 #define MX25LM51245G_SECR_PSB ((uint8_t)0x04) /*!< Program suspend bit */ 00268 #define MX25LM51245G_SECR_ESB ((uint8_t)0x08) /*!< Erase suspend bit */ 00269 #define MX25LM51245G_SECR_P_FAIL ((uint8_t)0x20) /*!< Program fail flag */ 00270 #define MX25LM51245G_SECR_E_FAIL ((uint8_t)0x40) /*!< Erase fail flag */ 00271 #define MX25LM51245G_SECR_WPSEL ((uint8_t)0x40) /*!< Write protection selection */ 00272 /** 00273 * @} 00274 */ 00275 00276 /** @defgroup MX25LM51245G_Exported_Functions 00277 * @{ 00278 */ 00279 /** 00280 * @} 00281 */ 00282 00283 #ifdef __cplusplus 00284 } 00285 #endif 00286 00287 #endif /* __MX25LM51245G_H */ 00288 00289 /** 00290 * @} 00291 */ 00292 00293 /** 00294 * @} 00295 */ 00296 00297 /** 00298 * @} 00299 */ 00300 00301 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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