ST / BSP_DISCO_L496AG

BSP driver for DISCO_L496AG

Dependents:   DISCO_L496AG-LCD-prova_1 DISCO_L496AG-LCD-prova_2 DISCO_L496AG-LCD-demo DISCO_L496AG-SRAM-demo

Drivers/BSP/STM32L496G-Discovery/stm32l496g_discovery_sram.h@0:d83f1c8ca282, 2018-03-26 (annotated)

Committer:
bcostm
Date:
Mon Mar 26 10:28:18 2018 +0200
Revision:
0:d83f1c8ca282
Child:
2:106c7b82e064
Add BSP files coming from CubeL4 V1.11.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bcostm 0:d83f1c8ca282 1 /**
bcostm 0:d83f1c8ca282 2 ******************************************************************************
bcostm 0:d83f1c8ca282 3 * @file stm32l496g_discovery_sram.h
bcostm 0:d83f1c8ca282 4 * @author MCD Application Team
bcostm 0:d83f1c8ca282 5 * @brief This file contains the common defines and functions prototypes for
bcostm 0:d83f1c8ca282 6 * the stm32l496g_discovery_sram.c driver.
bcostm 0:d83f1c8ca282 7 ******************************************************************************
bcostm 0:d83f1c8ca282 8 * @attention
bcostm 0:d83f1c8ca282 9 *
bcostm 0:d83f1c8ca282 10 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
bcostm 0:d83f1c8ca282 11 *
bcostm 0:d83f1c8ca282 12 * Redistribution and use in source and binary forms, with or without modification,
bcostm 0:d83f1c8ca282 13 * are permitted provided that the following conditions are met:
bcostm 0:d83f1c8ca282 14 * 1. Redistributions of source code must retain the above copyright notice,
bcostm 0:d83f1c8ca282 15 * this list of conditions and the following disclaimer.
bcostm 0:d83f1c8ca282 16 * 2. Redistributions in binary form must reproduce the above copyright notice,
bcostm 0:d83f1c8ca282 17 * this list of conditions and the following disclaimer in the documentation
bcostm 0:d83f1c8ca282 18 * and/or other materials provided with the distribution.
bcostm 0:d83f1c8ca282 19 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bcostm 0:d83f1c8ca282 20 * may be used to endorse or promote products derived from this software
bcostm 0:d83f1c8ca282 21 * without specific prior written permission.
bcostm 0:d83f1c8ca282 22 *
bcostm 0:d83f1c8ca282 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bcostm 0:d83f1c8ca282 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bcostm 0:d83f1c8ca282 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bcostm 0:d83f1c8ca282 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bcostm 0:d83f1c8ca282 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bcostm 0:d83f1c8ca282 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bcostm 0:d83f1c8ca282 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bcostm 0:d83f1c8ca282 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bcostm 0:d83f1c8ca282 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bcostm 0:d83f1c8ca282 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bcostm 0:d83f1c8ca282 33 *
bcostm 0:d83f1c8ca282 34 ******************************************************************************
bcostm 0:d83f1c8ca282 35 */
bcostm 0:d83f1c8ca282 36
bcostm 0:d83f1c8ca282 37 /** @addtogroup BSP
bcostm 0:d83f1c8ca282 38 * @{
bcostm 0:d83f1c8ca282 39 */
bcostm 0:d83f1c8ca282 40
bcostm 0:d83f1c8ca282 41 /** @addtogroup STM32L496G_DISCOVERY
bcostm 0:d83f1c8ca282 42 * @{
bcostm 0:d83f1c8ca282 43 */
bcostm 0:d83f1c8ca282 44
bcostm 0:d83f1c8ca282 45 /* Define to prevent recursive inclusion -------------------------------------*/
bcostm 0:d83f1c8ca282 46 #ifndef __STM32L496G_DISCOVERY_SRAM_H
bcostm 0:d83f1c8ca282 47 #define __STM32L496G_DISCOVERY_SRAM_H
bcostm 0:d83f1c8ca282 48
bcostm 0:d83f1c8ca282 49 #ifdef __cplusplus
bcostm 0:d83f1c8ca282 50 extern "C" {
bcostm 0:d83f1c8ca282 51 #endif
bcostm 0:d83f1c8ca282 52
bcostm 0:d83f1c8ca282 53 /* Includes ------------------------------------------------------------------*/
bcostm 0:d83f1c8ca282 54 #include "stm32l4xx_hal.h"
bcostm 0:d83f1c8ca282 55
bcostm 0:d83f1c8ca282 56 /** @addtogroup STM32L496G_DISCOVERY_SRAM
bcostm 0:d83f1c8ca282 57 * @{
bcostm 0:d83f1c8ca282 58 */
bcostm 0:d83f1c8ca282 59
bcostm 0:d83f1c8ca282 60
bcostm 0:d83f1c8ca282 61 /* Exported constants --------------------------------------------------------*/
bcostm 0:d83f1c8ca282 62
bcostm 0:d83f1c8ca282 63 /** @defgroup STM32L496G_DISCOVERY_SRAM_Exported_Constants Exported Constants
bcostm 0:d83f1c8ca282 64 * @{
bcostm 0:d83f1c8ca282 65 */
bcostm 0:d83f1c8ca282 66
bcostm 0:d83f1c8ca282 67 /**
bcostm 0:d83f1c8ca282 68 * @brief SRAM status structure definition
bcostm 0:d83f1c8ca282 69 */
bcostm 0:d83f1c8ca282 70 #define SRAM_OK 0x00
bcostm 0:d83f1c8ca282 71 #define SRAM_ERROR 0x01
bcostm 0:d83f1c8ca282 72
bcostm 0:d83f1c8ca282 73 #define SRAM_DEVICE_ADDR ((uint32_t)0x64000000)
bcostm 0:d83f1c8ca282 74 #define SRAM_DEVICE_SIZE ((uint32_t)0x80000) /* SRAM device size in MBytes */
bcostm 0:d83f1c8ca282 75
bcostm 0:d83f1c8ca282 76 /* #define SRAM_MEMORY_WIDTH FMC_NORSRAM_MEM_BUS_WIDTH_8 */
bcostm 0:d83f1c8ca282 77 #define SRAM_MEMORY_WIDTH FMC_NORSRAM_MEM_BUS_WIDTH_16
bcostm 0:d83f1c8ca282 78
bcostm 0:d83f1c8ca282 79 #define SRAM_BURSTACCESS FMC_BURST_ACCESS_MODE_DISABLE
bcostm 0:d83f1c8ca282 80 /* #define SRAM_BURSTACCESS FMC_BURST_ACCESS_MODE_ENABLE*/
bcostm 0:d83f1c8ca282 81
bcostm 0:d83f1c8ca282 82 #define SRAM_WRITEBURST FMC_WRITE_BURST_DISABLE
bcostm 0:d83f1c8ca282 83 /* #define SRAM_WRITEBURST FMC_WRITE_BURST_ENABLE */
bcostm 0:d83f1c8ca282 84
bcostm 0:d83f1c8ca282 85 /* DMA definitions for SRAM DMA transfer */
bcostm 0:d83f1c8ca282 86 #define SRAM_DMAx_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
bcostm 0:d83f1c8ca282 87 #define SRAM_DMAx_CHANNEL DMA1_Channel1
bcostm 0:d83f1c8ca282 88 #define SRAM_DMAx_IRQn DMA1_Channel1_IRQn
bcostm 0:d83f1c8ca282 89 #define SRAM_DMAx_IRQHandler DMA1_Channel1_IRQHandler
bcostm 0:d83f1c8ca282 90
bcostm 0:d83f1c8ca282 91 /**
bcostm 0:d83f1c8ca282 92 * @}
bcostm 0:d83f1c8ca282 93 */
bcostm 0:d83f1c8ca282 94
bcostm 0:d83f1c8ca282 95
bcostm 0:d83f1c8ca282 96 /* Exported functions --------------------------------------------------------*/
bcostm 0:d83f1c8ca282 97
bcostm 0:d83f1c8ca282 98 /** @addtogroup STM32L496G_DISCOVERY_SRAM_Exported_Functions
bcostm 0:d83f1c8ca282 99 * @{
bcostm 0:d83f1c8ca282 100 */
bcostm 0:d83f1c8ca282 101 uint8_t BSP_SRAM_Init(void);
bcostm 0:d83f1c8ca282 102 uint8_t BSP_SRAM_ReadData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize);
bcostm 0:d83f1c8ca282 103 uint8_t BSP_SRAM_ReadData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize);
bcostm 0:d83f1c8ca282 104 uint8_t BSP_SRAM_WriteData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize);
bcostm 0:d83f1c8ca282 105 uint8_t BSP_SRAM_WriteData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize);
bcostm 0:d83f1c8ca282 106 void BSP_SRAM_DMA_IRQHandler(void);
bcostm 0:d83f1c8ca282 107
bcostm 0:d83f1c8ca282 108 /**
bcostm 0:d83f1c8ca282 109 * @}
bcostm 0:d83f1c8ca282 110 */
bcostm 0:d83f1c8ca282 111
bcostm 0:d83f1c8ca282 112 /**
bcostm 0:d83f1c8ca282 113 * @}
bcostm 0:d83f1c8ca282 114 */
bcostm 0:d83f1c8ca282 115
bcostm 0:d83f1c8ca282 116 #ifdef __cplusplus
bcostm 0:d83f1c8ca282 117 }
bcostm 0:d83f1c8ca282 118 #endif
bcostm 0:d83f1c8ca282 119
bcostm 0:d83f1c8ca282 120 #endif /* __STM32L496G_DISCOVERY_SRAM_H */
bcostm 0:d83f1c8ca282 121
bcostm 0:d83f1c8ca282 122 /**
bcostm 0:d83f1c8ca282 123 * @}
bcostm 0:d83f1c8ca282 124 */
bcostm 0:d83f1c8ca282 125
bcostm 0:d83f1c8ca282 126 /**
bcostm 0:d83f1c8ca282 127 * @}
bcostm 0:d83f1c8ca282 128 */
bcostm 0:d83f1c8ca282 129
bcostm 0:d83f1c8ca282 130 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/