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l3gd20.h
00001 /** 00002 ****************************************************************************** 00003 * @file l3gd20.h 00004 * @author MCD Application Team 00005 * @brief This file contains all the functions prototypes for the l3gd20.c driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2015 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 00021 /* Define to prevent recursive inclusion -------------------------------------*/ 00022 #ifndef __L3GD20_H 00023 #define __L3GD20_H 00024 00025 #ifdef __cplusplus 00026 extern "C" { 00027 #endif 00028 00029 /* Includes ------------------------------------------------------------------*/ 00030 #include "../Common/gyro.h" 00031 00032 /** @addtogroup BSP 00033 * @{ 00034 */ 00035 00036 /** @addtogroup Components 00037 * @{ 00038 */ 00039 00040 /** @addtogroup L3GD20 00041 * @{ 00042 */ 00043 00044 /** @defgroup L3GD20_Exported_Constants 00045 * @{ 00046 */ 00047 00048 /******************************************************************************/ 00049 /*************************** START REGISTER MAPPING **************************/ 00050 /******************************************************************************/ 00051 #define L3GD20_WHO_AM_I_ADDR 0x0F /* device identification register */ 00052 #define L3GD20_CTRL_REG1_ADDR 0x20 /* Control register 1 */ 00053 #define L3GD20_CTRL_REG2_ADDR 0x21 /* Control register 2 */ 00054 #define L3GD20_CTRL_REG3_ADDR 0x22 /* Control register 3 */ 00055 #define L3GD20_CTRL_REG4_ADDR 0x23 /* Control register 4 */ 00056 #define L3GD20_CTRL_REG5_ADDR 0x24 /* Control register 5 */ 00057 #define L3GD20_REFERENCE_REG_ADDR 0x25 /* Reference register */ 00058 #define L3GD20_OUT_TEMP_ADDR 0x26 /* Out temp register */ 00059 #define L3GD20_STATUS_REG_ADDR 0x27 /* Status register */ 00060 #define L3GD20_OUT_X_L_ADDR 0x28 /* Output Register X */ 00061 #define L3GD20_OUT_X_H_ADDR 0x29 /* Output Register X */ 00062 #define L3GD20_OUT_Y_L_ADDR 0x2A /* Output Register Y */ 00063 #define L3GD20_OUT_Y_H_ADDR 0x2B /* Output Register Y */ 00064 #define L3GD20_OUT_Z_L_ADDR 0x2C /* Output Register Z */ 00065 #define L3GD20_OUT_Z_H_ADDR 0x2D /* Output Register Z */ 00066 #define L3GD20_FIFO_CTRL_REG_ADDR 0x2E /* Fifo control Register */ 00067 #define L3GD20_FIFO_SRC_REG_ADDR 0x2F /* Fifo src Register */ 00068 00069 #define L3GD20_INT1_CFG_ADDR 0x30 /* Interrupt 1 configuration Register */ 00070 #define L3GD20_INT1_SRC_ADDR 0x31 /* Interrupt 1 source Register */ 00071 #define L3GD20_INT1_TSH_XH_ADDR 0x32 /* Interrupt 1 Threshold X register */ 00072 #define L3GD20_INT1_TSH_XL_ADDR 0x33 /* Interrupt 1 Threshold X register */ 00073 #define L3GD20_INT1_TSH_YH_ADDR 0x34 /* Interrupt 1 Threshold Y register */ 00074 #define L3GD20_INT1_TSH_YL_ADDR 0x35 /* Interrupt 1 Threshold Y register */ 00075 #define L3GD20_INT1_TSH_ZH_ADDR 0x36 /* Interrupt 1 Threshold Z register */ 00076 #define L3GD20_INT1_TSH_ZL_ADDR 0x37 /* Interrupt 1 Threshold Z register */ 00077 #define L3GD20_INT1_DURATION_ADDR 0x38 /* Interrupt 1 DURATION register */ 00078 00079 /******************************************************************************/ 00080 /**************************** END REGISTER MAPPING ***************************/ 00081 /******************************************************************************/ 00082 00083 #define I_AM_L3GD20 ((uint8_t)0xD4) 00084 #define I_AM_L3GD20_TR ((uint8_t)0xD5) 00085 00086 /** @defgroup Power_Mode_selection 00087 * @{ 00088 */ 00089 #define L3GD20_MODE_POWERDOWN ((uint8_t)0x00) 00090 #define L3GD20_MODE_ACTIVE ((uint8_t)0x08) 00091 /** 00092 * @} 00093 */ 00094 00095 /** @defgroup OutPut_DataRate_Selection 00096 * @{ 00097 */ 00098 #define L3GD20_OUTPUT_DATARATE_1 ((uint8_t)0x00) 00099 #define L3GD20_OUTPUT_DATARATE_2 ((uint8_t)0x40) 00100 #define L3GD20_OUTPUT_DATARATE_3 ((uint8_t)0x80) 00101 #define L3GD20_OUTPUT_DATARATE_4 ((uint8_t)0xC0) 00102 /** 00103 * @} 00104 */ 00105 00106 /** @defgroup Axes_Selection 00107 * @{ 00108 */ 00109 #define L3GD20_X_ENABLE ((uint8_t)0x02) 00110 #define L3GD20_Y_ENABLE ((uint8_t)0x01) 00111 #define L3GD20_Z_ENABLE ((uint8_t)0x04) 00112 #define L3GD20_AXES_ENABLE ((uint8_t)0x07) 00113 #define L3GD20_AXES_DISABLE ((uint8_t)0x00) 00114 /** 00115 * @} 00116 */ 00117 00118 /** @defgroup Bandwidth_Selection 00119 * @{ 00120 */ 00121 #define L3GD20_BANDWIDTH_1 ((uint8_t)0x00) 00122 #define L3GD20_BANDWIDTH_2 ((uint8_t)0x10) 00123 #define L3GD20_BANDWIDTH_3 ((uint8_t)0x20) 00124 #define L3GD20_BANDWIDTH_4 ((uint8_t)0x30) 00125 /** 00126 * @} 00127 */ 00128 00129 /** @defgroup Full_Scale_Selection 00130 * @{ 00131 */ 00132 #define L3GD20_FULLSCALE_250 ((uint8_t)0x00) 00133 #define L3GD20_FULLSCALE_500 ((uint8_t)0x10) 00134 #define L3GD20_FULLSCALE_2000 ((uint8_t)0x20) 00135 #define L3GD20_FULLSCALE_SELECTION ((uint8_t)0x30) 00136 /** 00137 * @} 00138 */ 00139 00140 /** @defgroup Full_Scale_Sensitivity 00141 * @{ 00142 */ 00143 #define L3GD20_SENSITIVITY_250DPS ((float)8.75f) /*!< gyroscope sensitivity with 250 dps full scale [DPS/LSB] */ 00144 #define L3GD20_SENSITIVITY_500DPS ((float)17.50f) /*!< gyroscope sensitivity with 500 dps full scale [DPS/LSB] */ 00145 #define L3GD20_SENSITIVITY_2000DPS ((float)70.00f) /*!< gyroscope sensitivity with 2000 dps full scale [DPS/LSB] */ 00146 /** 00147 * @} 00148 */ 00149 00150 00151 /** @defgroup Block_Data_Update 00152 * @{ 00153 */ 00154 #define L3GD20_BlockDataUpdate_Continous ((uint8_t)0x00) 00155 #define L3GD20_BlockDataUpdate_Single ((uint8_t)0x80) 00156 /** 00157 * @} 00158 */ 00159 00160 /** @defgroup Endian_Data_selection 00161 * @{ 00162 */ 00163 #define L3GD20_BLE_LSB ((uint8_t)0x00) 00164 #define L3GD20_BLE_MSB ((uint8_t)0x40) 00165 /** 00166 * @} 00167 */ 00168 00169 /** @defgroup High_Pass_Filter_status 00170 * @{ 00171 */ 00172 #define L3GD20_HIGHPASSFILTER_DISABLE ((uint8_t)0x00) 00173 #define L3GD20_HIGHPASSFILTER_ENABLE ((uint8_t)0x10) 00174 /** 00175 * @} 00176 */ 00177 00178 /** @defgroup INT1_INT2_selection 00179 * @{ 00180 */ 00181 #define L3GD20_INT1 ((uint8_t)0x00) 00182 #define L3GD20_INT2 ((uint8_t)0x01) 00183 /** 00184 * @} 00185 */ 00186 00187 /** @defgroup INT1_Interrupt_status 00188 * @{ 00189 */ 00190 #define L3GD20_INT1INTERRUPT_DISABLE ((uint8_t)0x00) 00191 #define L3GD20_INT1INTERRUPT_ENABLE ((uint8_t)0x80) 00192 /** 00193 * @} 00194 */ 00195 00196 /** @defgroup INT2_Interrupt_status 00197 * @{ 00198 */ 00199 #define L3GD20_INT2INTERRUPT_DISABLE ((uint8_t)0x00) 00200 #define L3GD20_INT2INTERRUPT_ENABLE ((uint8_t)0x08) 00201 /** 00202 * @} 00203 */ 00204 00205 /** @defgroup INT1_Interrupt_ActiveEdge 00206 * @{ 00207 */ 00208 #define L3GD20_INT1INTERRUPT_LOW_EDGE ((uint8_t)0x20) 00209 #define L3GD20_INT1INTERRUPT_HIGH_EDGE ((uint8_t)0x00) 00210 /** 00211 * @} 00212 */ 00213 00214 /** @defgroup Boot_Mode_selection 00215 * @{ 00216 */ 00217 #define L3GD20_BOOT_NORMALMODE ((uint8_t)0x00) 00218 #define L3GD20_BOOT_REBOOTMEMORY ((uint8_t)0x80) 00219 /** 00220 * @} 00221 */ 00222 00223 /** @defgroup High_Pass_Filter_Mode 00224 * @{ 00225 */ 00226 #define L3GD20_HPM_NORMAL_MODE_RES ((uint8_t)0x00) 00227 #define L3GD20_HPM_REF_SIGNAL ((uint8_t)0x10) 00228 #define L3GD20_HPM_NORMAL_MODE ((uint8_t)0x20) 00229 #define L3GD20_HPM_AUTORESET_INT ((uint8_t)0x30) 00230 /** 00231 * @} 00232 */ 00233 00234 /** @defgroup High_Pass_CUT OFF_Frequency 00235 * @{ 00236 */ 00237 #define L3GD20_HPFCF_0 0x00 00238 #define L3GD20_HPFCF_1 0x01 00239 #define L3GD20_HPFCF_2 0x02 00240 #define L3GD20_HPFCF_3 0x03 00241 #define L3GD20_HPFCF_4 0x04 00242 #define L3GD20_HPFCF_5 0x05 00243 #define L3GD20_HPFCF_6 0x06 00244 #define L3GD20_HPFCF_7 0x07 00245 #define L3GD20_HPFCF_8 0x08 00246 #define L3GD20_HPFCF_9 0x09 00247 /** 00248 * @} 00249 */ 00250 00251 /** 00252 * @} 00253 */ 00254 /** @defgroup L3GD20_Exported_Functions 00255 * @{ 00256 */ 00257 /* Sensor Configuration Functions */ 00258 void L3GD20_Init(uint16_t InitStruct); 00259 void L3GD20_DeInit(void); 00260 void L3GD20_LowPower(uint16_t InitStruct); 00261 uint8_t L3GD20_ReadID(void); 00262 void L3GD20_RebootCmd(void); 00263 00264 /* Interrupt Configuration Functions */ 00265 void L3GD20_INT1InterruptConfig(uint16_t Int1Config); 00266 void L3GD20_EnableIT(uint8_t IntSel); 00267 void L3GD20_DisableIT(uint8_t IntSel); 00268 00269 /* High Pass Filter Configuration Functions */ 00270 void L3GD20_FilterConfig(uint8_t FilterStruct); 00271 void L3GD20_FilterCmd(uint8_t HighPassFilterState); 00272 void L3GD20_ReadXYZAngRate(float *pfData); 00273 uint8_t L3GD20_GetDataStatus(void); 00274 00275 /* Gyroscope IO functions */ 00276 void GYRO_IO_Init(void); 00277 void GYRO_IO_DeInit(void); 00278 void GYRO_IO_Write(uint8_t *pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite); 00279 void GYRO_IO_Read(uint8_t *pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead); 00280 00281 /* Gyroscope driver structure */ 00282 extern GYRO_DrvTypeDef L3gd20Drv; 00283 00284 /** 00285 * @} 00286 */ 00287 00288 /** 00289 * @} 00290 */ 00291 00292 /** 00293 * @} 00294 */ 00295 00296 /** 00297 * @} 00298 */ 00299 00300 #ifdef __cplusplus 00301 } 00302 #endif 00303 00304 #endif /* __L3GD20_H */ 00305 00306 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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