stm32h747i_discovery_sdram.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32h747i_discovery_sdram.h
00004   * @author  MCD Application Team
00005   * @brief   This file contains the common defines and functions prototypes for
00006   *          the stm32h747i_discovery_sdram.c driver.
00007   ******************************************************************************
00008   * @attention
00009   *
00010   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00011   * All rights reserved.</center></h2>
00012   *
00013   * This software component is licensed by ST under BSD 3-Clause license,
00014   * the "License"; You may not use this file except in compliance with the
00015   * License. You may obtain a copy of the License at:
00016   *                        opensource.org/licenses/BSD-3-Clause
00017   *
00018   ******************************************************************************
00019   */ 
00020 
00021 /* Define to prevent recursive inclusion -------------------------------------*/
00022 #ifndef __STM32H747I_DISCOVERY_SDRAM_H
00023 #define __STM32H747I_DISCOVERY_SDRAM_H
00024 
00025 #ifdef __cplusplus
00026  extern "C" {
00027 #endif 
00028 
00029 /* Includes ------------------------------------------------------------------*/
00030 #include "stm32h7xx_hal.h"
00031 
00032 /** @addtogroup BSP
00033   * @{
00034   */ 
00035 
00036 /** @addtogroup STM32H747I_DISCOVERY
00037   * @{
00038   */
00039     
00040 /** @addtogroup STM32H747I_DISCOVERY_SDRAM
00041   * @{
00042   */    
00043 
00044 /** @defgroup STM32H747I_DISCOVERY_SDRAM_Exported_Constants Exported Constants
00045   * @{
00046   */
00047 /** 
00048   * @brief  SDRAM status structure definition  
00049   */     
00050 #define   SDRAM_OK         ((uint8_t)0x00)
00051 #define   SDRAM_ERROR      ((uint8_t)0x01)
00052 
00053 #define SDRAM_DEVICE_ADDR  ((uint32_t)0xD0000000)
00054 #define SDRAM_DEVICE_SIZE  ((uint32_t)0x2000000)  /* SDRAM device size in MBytes */
00055 
00056 /* #define SDRAM_MEMORY_WIDTH            FMC_SDRAM_MEM_BUS_WIDTH_8  */
00057 /* #define SDRAM_MEMORY_WIDTH            FMC_SDRAM_MEM_BUS_WIDTH_16 */
00058 #define SDRAM_MEMORY_WIDTH               FMC_SDRAM_MEM_BUS_WIDTH_32
00059 
00060 #define SDCLOCK_PERIOD                   FMC_SDRAM_CLOCK_PERIOD_2
00061 /* #define SDCLOCK_PERIOD                FMC_SDRAM_CLOCK_PERIOD_3 */   
00062 
00063 #define REFRESH_COUNT                    ((uint32_t)0x0603)   /* SDRAM refresh counter (100Mhz SD clock) */
00064    
00065 #define SDRAM_TIMEOUT                    ((uint32_t)0xFFFF)
00066 
00067 /* DMA definitions for SDRAM DMA transfer */
00068 #define __MDMAx_CLK_ENABLE                 __HAL_RCC_MDMA_CLK_ENABLE
00069 #define __MDMAx_CLK_DISABLE                __HAL_RCC_MDMA_CLK_DISABLE
00070 #define SDRAM_MDMAx_CHANNEL               MDMA_Channel0  
00071 #define SDRAM_MDMAx_IRQn                  MDMA_IRQn
00072 
00073   
00074 /**
00075   * @brief  FMC SDRAM Mode definition register defines
00076   */
00077 #define SDRAM_MODEREG_BURST_LENGTH_1             ((uint16_t)0x0000)
00078 #define SDRAM_MODEREG_BURST_LENGTH_2             ((uint16_t)0x0001)
00079 #define SDRAM_MODEREG_BURST_LENGTH_4             ((uint16_t)0x0002)
00080 #define SDRAM_MODEREG_BURST_LENGTH_8             ((uint16_t)0x0004)
00081 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
00082 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
00083 #define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
00084 #define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
00085 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
00086 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) 
00087 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200) 
00088 /**
00089   * @}
00090   */ 
00091   
00092    
00093 /** @addtogroup STM32H747I_DISCOVERY_SDRAM_Exported_Functions
00094   * @{
00095   */  
00096 uint8_t BSP_SDRAM_Init(void);
00097 uint8_t BSP_SDRAM_DeInit(void);
00098 void    BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
00099 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
00100 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
00101 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
00102 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
00103 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
00104    
00105 /* These functions can be modified in case the current settings (e.g. DMA stream)
00106    need to be changed for specific application needs */
00107 void    BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram, void *Params);
00108 void    BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef  *hsdram, void *Params);
00109 
00110 
00111 /**
00112   * @}
00113   */ 
00114 
00115 /**
00116   * @}
00117   */ 
00118 
00119 /**
00120   * @}
00121   */ 
00122 
00123 /**
00124   * @}
00125   */ 
00126 
00127 #ifdef __cplusplus
00128 }
00129 #endif
00130 
00131 #endif /* __STM32H747I_DISCOVERY_SDRAM_H */
00132 
00133 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/