stm32h747i_discovery_sdram.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32h747i_discovery_sdram.c
00004   * @author  MCD Application Team
00005   * @brief   This file includes the SDRAM driver for the MT48LC4M32B2B5-6A memory 
00006   *          device mounted on STM32H747I-DISCOVERY boards.
00007   @verbatim
00008   How To use this driver:
00009   -----------------------
00010    - This driver is used to drive the MT48LC4M32B2B5-6A SDRAM external memory mounted
00011      on STM32H747I-DISCOVERY board.
00012    - This driver does not need a specific component driver for the SDRAM device
00013      to be included with.
00014 
00015   Driver description:
00016   ------------------
00017   + Initialization steps:
00018      o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This 
00019        function includes the MSP layer hardware resources initialization and the
00020        FMC controller configuration to interface with the external SDRAM memory.
00021      o It contains the SDRAM initialization sequence to program the SDRAM external 
00022        device using the function BSP_SDRAM_Initialization_sequence(). Note that this 
00023        sequence is standard for all SDRAM devices, but can include some differences
00024        from a device to another. If it is the case, the right sequence should be 
00025        implemented separately.
00026   
00027   + SDRAM read/write operations
00028      o SDRAM external memory can be accessed with read/write operations once it is
00029        initialized.
00030        Read/write operation can be performed with AHB access using the functions
00031        BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by MDMA transfer using the functions
00032        BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
00033      o The AHB access is performed with 32-bit width transaction, the MDMA transfer
00034        configuration is fixed at single (no burst) word transfer (see the 
00035        SDRAM_MspInit() static function).
00036      o User can implement his own functions for read/write access with his desired 
00037        configurations.
00038      o If interrupt mode is used for MDMA transfer, the function BSP_SDRAM_MDMA_IRQHandler()
00039        is called in IRQ handler file, to serve the generated interrupt once the MDMA 
00040        transfer is complete.
00041      o You can send a command to the SDRAM device in runtime using the function 
00042        BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between 
00043        the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure. 
00044   @endverbatim
00045   ******************************************************************************
00046   * @attention
00047   *
00048   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00049   * All rights reserved.</center></h2>
00050   *
00051   * This software component is licensed by ST under BSD 3-Clause license,
00052   * the "License"; You may not use this file except in compliance with the
00053   * License. You may obtain a copy of the License at:
00054   *                        opensource.org/licenses/BSD-3-Clause
00055   *
00056   ******************************************************************************
00057   */
00058 
00059 /* Includes ------------------------------------------------------------------*/
00060 #include "stm32h747i_discovery_sdram.h"
00061 
00062 /** @addtogroup BSP
00063   * @{
00064   */
00065 
00066 /** @addtogroup STM32H747I_DISCOVERY
00067   * @{
00068   */ 
00069   
00070 /** @defgroup STM32H747I_DISCOVERY_SDRAM STM32H747I_DISCOVERY_SDRAM
00071   * @{
00072   */ 
00073 
00074 /** @defgroup STM32H747I_DISCOVERY_SDRAM_Exported_Variables Exported Variables
00075   * @{
00076   */       
00077 SDRAM_HandleTypeDef sdramHandle;
00078 /**
00079   * @}
00080   */ 
00081   
00082 /** @defgroup STM32H747I_DISCOVERY_SDRAM_Private_Variables Private Variables
00083   * @{
00084   */       
00085 static FMC_SDRAM_TimingTypeDef Timing;
00086 static FMC_SDRAM_CommandTypeDef Command;
00087 /**
00088   * @}
00089   */ 
00090     
00091 /** @defgroup STM32H747I_DISCOVERY_SDRAM_Exported_Functions Exported_Functions
00092   * @{
00093   */ 
00094 
00095 /**
00096   * @brief  Initializes the SDRAM device.
00097   * @retval SDRAM status
00098   */
00099 uint8_t BSP_SDRAM_Init(void)
00100 { 
00101   static uint8_t sdramstatus = SDRAM_OK;
00102   /* SDRAM device configuration */
00103   sdramHandle.Instance = FMC_SDRAM_DEVICE;
00104     
00105   /* Timing configuration for 100Mhz as SDRAM clock frequency (System clock is up to 200Mhz) */
00106   Timing.LoadToActiveDelay    = 2;
00107   Timing.ExitSelfRefreshDelay = 7;
00108   Timing.SelfRefreshTime      = 4;
00109   Timing.RowCycleDelay        = 7;
00110   Timing.WriteRecoveryTime    = 2;
00111   Timing.RPDelay              = 2;
00112   Timing.RCDDelay             = 2;
00113   
00114   sdramHandle.Init.SDBank             = FMC_SDRAM_BANK2;
00115   sdramHandle.Init.ColumnBitsNumber   = FMC_SDRAM_COLUMN_BITS_NUM_9;
00116   sdramHandle.Init.RowBitsNumber      = FMC_SDRAM_ROW_BITS_NUM_12;
00117   sdramHandle.Init.MemoryDataWidth    = SDRAM_MEMORY_WIDTH;
00118   sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
00119   sdramHandle.Init.CASLatency         = FMC_SDRAM_CAS_LATENCY_3;
00120   sdramHandle.Init.WriteProtection    = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
00121   sdramHandle.Init.SDClockPeriod      = SDCLOCK_PERIOD;
00122   sdramHandle.Init.ReadBurst          = FMC_SDRAM_RBURST_ENABLE;
00123   sdramHandle.Init.ReadPipeDelay      = FMC_SDRAM_RPIPE_DELAY_0;
00124   
00125   /* SDRAM controller initialization */
00126 
00127   BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */
00128 
00129   if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
00130   {
00131     sdramstatus = SDRAM_ERROR;
00132   }
00133   else
00134   {
00135     /* SDRAM initialization sequence */
00136     BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
00137   }
00138 
00139   return sdramstatus;
00140 }
00141 
00142 /**
00143   * @brief  DeInitializes the SDRAM device.
00144   * @retval SDRAM status
00145   */
00146 uint8_t BSP_SDRAM_DeInit(void)
00147 { 
00148   static uint8_t sdramstatus = SDRAM_OK;
00149   /* SDRAM device de-initialization */
00150   sdramHandle.Instance = FMC_SDRAM_DEVICE;
00151 
00152   if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK)
00153   {
00154     sdramstatus = SDRAM_ERROR;
00155   }
00156   else
00157   {
00158     /* SDRAM controller de-initialization */
00159     BSP_SDRAM_MspDeInit(&sdramHandle, NULL);
00160   }
00161 
00162   return sdramstatus;
00163 }
00164 
00165 /**
00166   * @brief  Programs the SDRAM device.
00167   * @param  RefreshCount: SDRAM refresh counter value 
00168   * @retval None
00169   */
00170 void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
00171 {
00172   __IO uint32_t tmpmrd = 0;
00173   
00174   /* Step 1: Configure a clock configuration enable command */
00175   Command.CommandMode            = FMC_SDRAM_CMD_CLK_ENABLE;
00176   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK2;
00177   Command.AutoRefreshNumber      = 1;
00178   Command.ModeRegisterDefinition = 0;
00179 
00180   /* Send the command */
00181   HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
00182 
00183   /* Step 2: Insert 100 us minimum delay */ 
00184   /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
00185   HAL_Delay(1);
00186     
00187   /* Step 3: Configure a PALL (precharge all) command */ 
00188   Command.CommandMode            = FMC_SDRAM_CMD_PALL;
00189   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK2;
00190   Command.AutoRefreshNumber      = 1;
00191   Command.ModeRegisterDefinition = 0;
00192 
00193   /* Send the command */
00194   HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);  
00195   
00196   /* Step 4: Configure an Auto Refresh command */ 
00197   Command.CommandMode            = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
00198   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK2;
00199   Command.AutoRefreshNumber      = 8;
00200   Command.ModeRegisterDefinition = 0;
00201 
00202   /* Send the command */
00203   HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
00204   
00205   /* Step 5: Program the external memory mode register */
00206   tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1          |\
00207                      SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL   |\
00208                      SDRAM_MODEREG_CAS_LATENCY_3           |\
00209                      SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
00210                      SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
00211   
00212   Command.CommandMode            = FMC_SDRAM_CMD_LOAD_MODE;
00213   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK2;
00214   Command.AutoRefreshNumber      = 1;
00215   Command.ModeRegisterDefinition = tmpmrd;
00216 
00217   /* Send the command */
00218   HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
00219   
00220   /* Step 6: Set the refresh rate counter */
00221   /* Set the device refresh rate */
00222   HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); 
00223 }
00224 
00225 /**
00226   * @brief  Reads an amount of data from the SDRAM memory in polling mode.
00227   * @param  uwStartAddress: Read start address
00228   * @param  pData: Pointer to data to be read  
00229   * @param  uwDataSize: Size of read data from the memory
00230   * @retval SDRAM status
00231   */
00232 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
00233 {
00234   if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00235   {
00236     return SDRAM_ERROR;
00237   }
00238   else
00239   {
00240     return SDRAM_OK;
00241   } 
00242 }
00243 
00244 /**
00245   * @brief  Reads an amount of data from the SDRAM memory in DMA mode.
00246   * @param  uwStartAddress: Read start address
00247   * @param  pData: Pointer to data to be read  
00248   * @param  uwDataSize: Size of read data from the memory
00249   * @retval SDRAM status
00250   */
00251 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
00252 {
00253   if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00254   {
00255     return SDRAM_ERROR;
00256   }
00257   else
00258   {
00259     return SDRAM_OK;
00260   }     
00261 }
00262 
00263 /**
00264   * @brief  Writes an amount of data to the SDRAM memory in polling mode.
00265   * @param  uwStartAddress: Write start address
00266   * @param  pData: Pointer to data to be written  
00267   * @param  uwDataSize: Size of written data from the memory
00268   * @retval SDRAM status
00269   */
00270 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 
00271 {
00272   if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00273   {
00274     return SDRAM_ERROR;
00275   }
00276   else
00277   {
00278     return SDRAM_OK;
00279   }
00280 }
00281 
00282 /**
00283   * @brief  Writes an amount of data to the SDRAM memory in DMA mode.
00284   * @param  uwStartAddress: Write start address
00285   * @param  pData: Pointer to data to be written  
00286   * @param  uwDataSize: Size of written data from the memory
00287   * @retval SDRAM status
00288   */
00289 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 
00290 {
00291   if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00292   {
00293     return SDRAM_ERROR;
00294   }
00295   else
00296   {
00297     return SDRAM_OK;
00298   } 
00299 }
00300 
00301 /**
00302   * @brief  Sends command to the SDRAM bank.
00303   * @param  SdramCmd: Pointer to SDRAM command structure 
00304   * @retval SDRAM status
00305   */  
00306 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
00307 {
00308   if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
00309   {
00310     return SDRAM_ERROR;
00311   }
00312   else
00313   {
00314     return SDRAM_OK;
00315   }
00316 }
00317 
00318 /**
00319   * @brief  Initializes SDRAM MSP.
00320   * @param  hsdram SDRAM handle
00321   * @param  Params User parameters
00322   * @retval None
00323   */
00324 __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram, void *Params)
00325 {  
00326   static MDMA_HandleTypeDef mdma_handle;
00327   GPIO_InitTypeDef gpio_init_structure;
00328   
00329   /* Enable FMC clock */
00330   __HAL_RCC_FMC_CLK_ENABLE();
00331   
00332   /* Enable chosen MDMAx clock */
00333   __MDMAx_CLK_ENABLE();
00334 
00335   /* Enable GPIOs clock */
00336   __HAL_RCC_GPIOD_CLK_ENABLE();
00337   __HAL_RCC_GPIOE_CLK_ENABLE();
00338   __HAL_RCC_GPIOF_CLK_ENABLE();
00339   __HAL_RCC_GPIOG_CLK_ENABLE();
00340   __HAL_RCC_GPIOH_CLK_ENABLE();
00341   __HAL_RCC_GPIOI_CLK_ENABLE();
00342   
00343   /* Common GPIO configuration */
00344   gpio_init_structure.Mode      = GPIO_MODE_AF_PP;
00345   gpio_init_structure.Pull      = GPIO_PULLUP;
00346   gpio_init_structure.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
00347   gpio_init_structure.Alternate = GPIO_AF12_FMC;
00348   
00349   /* GPIOD configuration */
00350   gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\
00351                               GPIO_PIN_14 | GPIO_PIN_15;
00352  
00353    
00354   HAL_GPIO_Init(GPIOD, &gpio_init_structure);
00355 
00356   /* GPIOE configuration */  
00357   gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
00358                               GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
00359                               GPIO_PIN_15;
00360       
00361   HAL_GPIO_Init(GPIOE, &gpio_init_structure);
00362   
00363   /* GPIOF configuration */  
00364   gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
00365                               GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
00366                               GPIO_PIN_15;
00367     
00368   HAL_GPIO_Init(GPIOF, &gpio_init_structure);
00369   
00370   /* GPIOG configuration */  
00371   gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 /*| GPIO_PIN_3 */|\
00372                               GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15;
00373   HAL_GPIO_Init(GPIOG, &gpio_init_structure);
00374 
00375   /* GPIOH configuration */  
00376   gpio_init_structure.Pin   = GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 |\
00377                               GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
00378                               GPIO_PIN_15;
00379   HAL_GPIO_Init(GPIOH, &gpio_init_structure); 
00380   
00381   /* GPIOI configuration */  
00382   gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 |\
00383                               GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10;
00384   HAL_GPIO_Init(GPIOI, &gpio_init_structure);  
00385   
00386   /* Configure common MDMA parameters */
00387   mdma_handle.Init.Request = MDMA_REQUEST_SW;
00388   mdma_handle.Init.TransferTriggerMode = MDMA_BLOCK_TRANSFER;
00389   mdma_handle.Init.Priority = MDMA_PRIORITY_HIGH;
00390   mdma_handle.Init.Endianness = MDMA_LITTLE_ENDIANNESS_PRESERVE;
00391   mdma_handle.Init.SourceInc = MDMA_SRC_INC_WORD;
00392   mdma_handle.Init.DestinationInc = MDMA_DEST_INC_WORD;
00393   mdma_handle.Init.SourceDataSize = MDMA_SRC_DATASIZE_WORD;
00394   mdma_handle.Init.DestDataSize = MDMA_DEST_DATASIZE_WORD;
00395   mdma_handle.Init.DataAlignment = MDMA_DATAALIGN_PACKENABLE;                            
00396   mdma_handle.Init.SourceBurst = MDMA_SOURCE_BURST_SINGLE;
00397   mdma_handle.Init.DestBurst = MDMA_DEST_BURST_SINGLE;
00398   mdma_handle.Init.BufferTransferLength = 128;
00399   mdma_handle.Init.SourceBlockAddressOffset = 0;
00400   mdma_handle.Init.DestBlockAddressOffset = 0; 
00401    
00402   
00403   mdma_handle.Instance = SDRAM_MDMAx_CHANNEL;
00404   
00405    /* Associate the DMA handle */
00406   __HAL_LINKDMA(hsdram, hmdma, mdma_handle);
00407   
00408   /* Deinitialize the stream for new transfer */
00409   HAL_MDMA_DeInit(&mdma_handle);
00410   
00411   /* Configure the DMA stream */
00412   HAL_MDMA_Init(&mdma_handle); 
00413   
00414   /* NVIC configuration for DMA transfer complete interrupt */
00415   HAL_NVIC_SetPriority(SDRAM_MDMAx_IRQn, 0x0F, 0);
00416   HAL_NVIC_EnableIRQ(SDRAM_MDMAx_IRQn);
00417 }
00418 
00419 /**
00420   * @brief  DeInitializes SDRAM MSP.
00421   * @param  hsdram SDRAM handle
00422   * @param  Params User parameters
00423   * @retval None
00424   */
00425 __weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef  *hsdram, void *Params)
00426 {  
00427     static MDMA_HandleTypeDef mdma_handle;
00428   
00429     /* Disable NVIC configuration for DMA interrupt */
00430     HAL_NVIC_DisableIRQ(SDRAM_MDMAx_IRQn);
00431 
00432     /* Deinitialize the stream for new transfer */
00433     mdma_handle.Instance = SDRAM_MDMAx_CHANNEL;
00434     HAL_MDMA_DeInit(&mdma_handle);
00435 
00436     /* GPIO pins clock, FMC clock and MDMA clock can be shut down in the applications
00437        by surcharging this __weak function */ 
00438 }
00439 
00440 /**
00441   * @}
00442   */  
00443   
00444 /**
00445   * @}
00446   */ 
00447   
00448 /**
00449   * @}
00450   */ 
00451   
00452 /**
00453   * @}
00454   */ 
00455 
00456 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/