mt25tl01g.h

00001 /**
00002   ******************************************************************************
00003   * @file    MT25TL01G.h
00004   * @author  MCD Application Team
00005   * @version V1.0.0
00006   * @date    08-August-2016
00007   * @brief   This file contains all the description of the MT25TL01G QSPI memory.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */ 
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __MT25TL01G_H
00040 #define __MT25TL01G_H
00041 
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif 
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 
00048 /** @addtogroup BSP
00049   * @{
00050   */ 
00051 
00052 /** @addtogroup Components
00053   * @{
00054   */ 
00055   
00056 /** @addtogroup MT25TL01G
00057   * @{
00058   */
00059 
00060 /** @defgroup MT25TL01G_Exported_Types
00061   * @{
00062   */
00063    
00064 /**
00065   * @}
00066   */ 
00067 
00068 /** @defgroup MT25TL01G_Exported_Constants
00069   * @{
00070   */
00071    
00072 /** 
00073   * @brief  MT25TL01G Configuration  
00074   */  
00075 #define MT25TL01G_FLASH_SIZE                  0x8000000 /* 2 * 512 MBits => 2 * 64MBytes => 128MBytes*/
00076 #define MT25TL01G_SECTOR_SIZE                 0x10000   /* 2 * 1024 sectors of 64KBytes */
00077 #define MT25TL01G_SUBSECTOR_SIZE              0x1000    /* 2 * 16384 subsectors of 4kBytes */
00078 #define MT25TL01G_PAGE_SIZE                   0x100     /* 2 * 262144 pages of 256 bytes */
00079 
00080 #define MT25TL01G_DUMMY_CYCLES_READ_QUAD      8
00081 #define MT25TL01G_DUMMY_CYCLES_READ           8
00082 #define MT25TL01G_DUMMY_CYCLES_READ_DTR       6
00083 #define MT25TL01G_DUMMY_CYCLES_READ_QUAD_DTR  6
00084 
00085 #define MT25TL01G_DIE_ERASE_MAX_TIME          460000
00086 #define MT25TL01G_SECTOR_ERASE_MAX_TIME       1000
00087 #define MT25TL01G_SUBSECTOR_ERASE_MAX_TIME    400
00088 
00089 /** 
00090   * @brief  MT25TL01G Commands  
00091   */  
00092 /* Reset Operations */
00093 #define RESET_ENABLE_CMD                     0x66
00094 #define RESET_MEMORY_CMD                     0x99
00095 
00096 /* Identification Operations */
00097 #define READ_ID_CMD                          0x9E
00098 #define READ_ID_CMD2                         0x9F
00099 #define MULTIPLE_IO_READ_ID_CMD              0xAF
00100 #define READ_SERIAL_FLASH_DISCO_PARAM_CMD    0x5A
00101 
00102 /* Read Operations */
00103 #define READ_CMD                             0x03
00104 #define READ_4_BYTE_ADDR_CMD                 0x13
00105 
00106 #define FAST_READ_CMD                        0x0B
00107 #define FAST_READ_DTR_CMD                    0x0D
00108 #define FAST_READ_4_BYTE_ADDR_CMD            0x0C
00109 
00110 #define DUAL_OUT_FAST_READ_CMD               0x3B
00111 #define DUAL_OUT_FAST_READ_DTR_CMD           0x3D
00112 #define DUAL_OUT_FAST_READ_4_BYTE_ADDR_CMD   0x3C
00113 
00114 #define DUAL_INOUT_FAST_READ_CMD             0xBB
00115 #define DUAL_INOUT_FAST_READ_DTR_CMD         0xBD
00116 #define DUAL_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xBC
00117 
00118 #define QUAD_OUT_FAST_READ_CMD               0x6B
00119 #define QUAD_OUT_FAST_READ_DTR_CMD           0x6D
00120 #define QUAD_OUT_FAST_READ_4_BYTE_ADDR_CMD   0x6C
00121 
00122 #define QUAD_INOUT_FAST_READ_CMD             0xEB
00123 #define QUAD_INOUT_FAST_READ_DTR_CMD         0xED  
00124 #define QUAD_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xEC
00125 
00126 /* Write Operations */
00127 #define WRITE_ENABLE_CMD                     0x06
00128 #define WRITE_DISABLE_CMD                    0x04
00129 
00130 /* Register Operations */
00131 #define READ_STATUS_REG_CMD                  0x05
00132 #define WRITE_STATUS_REG_CMD                 0x01
00133 
00134 #define READ_LOCK_REG_CMD                    0xE8
00135 #define WRITE_LOCK_REG_CMD                   0xE5
00136 
00137 #define READ_FLAG_STATUS_REG_CMD             0x70
00138 #define CLEAR_FLAG_STATUS_REG_CMD            0x50
00139 
00140 #define READ_NONVOL_CFG_REG_CMD              0xB5
00141 #define WRITE_NONVOL_CFG_REG_CMD             0xB1
00142 
00143 #define READ_VOL_CFG_REG_CMD                 0x85
00144 #define WRITE_VOL_CFG_REG_CMD                0x81
00145 
00146 #define READ_ENHANCED_VOL_CFG_REG_CMD        0x65
00147 #define WRITE_ENHANCED_VOL_CFG_REG_CMD       0x61
00148 
00149 #define READ_EXT_ADDR_REG_CMD                0xC8
00150 #define WRITE_EXT_ADDR_REG_CMD               0xC5
00151 
00152 /* Program Operations */
00153 #define PAGE_PROG_CMD                        0x02
00154 #define PAGE_PROG_4_BYTE_ADDR_CMD            0x12
00155 
00156 #define DUAL_IN_FAST_PROG_CMD                0xA2
00157 #define EXT_DUAL_IN_FAST_PROG_CMD            0xD2
00158 
00159 #define QUAD_IN_FAST_PROG_CMD                0x32
00160 #define EXT_QUAD_IN_FAST_PROG_CMD            0x38
00161 #define QUAD_IN_FAST_PROG_4_BYTE_ADDR_CMD    0x34
00162 
00163 /* Erase Operations */
00164 #define SUBSECTOR_ERASE_CMD                  0x20
00165 #define SUBSECTOR_ERASE_4_BYTE_ADDR_CMD      0x21
00166    
00167 #define SECTOR_ERASE_CMD                     0xD8
00168 #define SECTOR_ERASE_4_BYTE_ADDR_CMD         0xDC
00169 
00170 #define DIE_ERASE_CMD                        0xC4
00171 
00172 #define PROG_ERASE_RESUME_CMD                0x7A
00173 #define PROG_ERASE_SUSPEND_CMD               0x75
00174 
00175 /* One-Time Programmable Operations */
00176 #define READ_OTP_ARRAY_CMD                   0x4B
00177 #define PROG_OTP_ARRAY_CMD                   0x42
00178 
00179 /* 4-byte Address Mode Operations */
00180 #define ENTER_4_BYTE_ADDR_MODE_CMD           0xB7
00181 #define EXIT_4_BYTE_ADDR_MODE_CMD            0xE9
00182 
00183 /* Quad Operations */
00184 #define ENTER_QUAD_CMD                       0x35
00185 #define EXIT_QUAD_CMD                        0xF5
00186    
00187 /** 
00188   * @brief  MT25TL01G Registers  
00189   */ 
00190 /* Status Register */
00191 #define MT25TL01G_SR_WIP                      ((uint8_t)0x01)    /*!< Write in progress */
00192 #define MT25TL01G_SR_WREN                     ((uint8_t)0x02)    /*!< Write enable latch */
00193 #define MT25TL01G_SR_BLOCKPR                  ((uint8_t)0x5C)    /*!< Block protected against program and erase operations */
00194 #define MT25TL01G_SR_PRBOTTOM                 ((uint8_t)0x20)    /*!< Protected memory area defined by BLOCKPR starts from top or bottom */
00195 #define MT25TL01G_SR_SRWREN                   ((uint8_t)0x80)    /*!< Status register write enable/disable */
00196 
00197 /* Non volatile Configuration Register */
00198 #define MT25TL01G_NVCR_NBADDR                 ((uint16_t)0x0001) /*!< 3-bytes or 4-bytes addressing */
00199 #define MT25TL01G_NVCR_SEGMENT                ((uint16_t)0x0002) /*!< Upper or lower 128Mb segment selected by default */
00200 #define MT25TL01G_NVCR_DUAL                   ((uint16_t)0x0004) /*!< Dual I/O protocol */
00201 #define MT25TL01G_NVCR_QUAB                   ((uint16_t)0x0008) /*!< Quad I/O protocol */
00202 #define MT25TL01G_NVCR_RH                     ((uint16_t)0x0010) /*!< Reset/hold */
00203 #define MT25TL01G_NVCR_DTRP                   ((uint16_t)0x0020) /*!< Double transfer rate protocol */
00204 #define MT25TL01G_NVCR_ODS                    ((uint16_t)0x01C0) /*!< Output driver strength */
00205 #define MT25TL01G_NVCR_XIP                    ((uint16_t)0x0E00) /*!< XIP mode at power-on reset */
00206 #define MT25TL01G_NVCR_NB_DUMMY               ((uint16_t)0xF000) /*!< Number of dummy clock cycles */
00207 
00208 /* Volatile Configuration Register */
00209 #define MT25TL01G_VCR_WRAP                    ((uint8_t)0x03)    /*!< Wrap */
00210 #define MT25TL01G_VCR_XIP                     ((uint8_t)0x08)    /*!< XIP */
00211 #define MT25TL01G_VCR_NB_DUMMY                ((uint8_t)0xF0)    /*!< Number of dummy clock cycles */
00212 
00213 /* Extended Address Register */
00214 #define MT25TL01G_EAR_HIGHEST_SE              ((uint8_t)0x03)    /*!< Select the Highest 128Mb segment */
00215 #define MT25TL01G_EAR_THIRD_SEG               ((uint8_t)0x02)    /*!< Select the Third 128Mb segment */
00216 #define MT25TL01G_EAR_SECOND_SEG              ((uint8_t)0x01)    /*!< Select the Second 128Mb segment */
00217 #define MT25TL01G_EAR_LOWEST_SEG              ((uint8_t)0x00)    /*!< Select the Lowest 128Mb segment (default) */
00218 
00219 /* Enhanced Volatile Configuration Register */
00220 #define MT25TL01G_EVCR_ODS                    ((uint8_t)0x07)    /*!< Output driver strength */
00221 #define MT25TL01G_EVCR_RH                     ((uint8_t)0x10)    /*!< Reset/hold */
00222 #define MT25TL01G_EVCR_DTRP                   ((uint8_t)0x20)    /*!< Double transfer rate protocol */
00223 #define MT25TL01G_EVCR_DUAL                   ((uint8_t)0x40)    /*!< Dual I/O protocol */
00224 #define MT25TL01G_EVCR_QUAD                   ((uint8_t)0x80)    /*!< Quad I/O protocol */
00225 
00226 /* Flag Status Register */
00227 #define MT25TL01G_FSR_NBADDR                  ((uint8_t)0x01)    /*!< 3-bytes or 4-bytes addressing */
00228 #define MT25TL01G_FSR_PRERR                   ((uint8_t)0x02)    /*!< Protection error */
00229 #define MT25TL01G_FSR_PGSUS                   ((uint8_t)0x04)    /*!< Program operation suspended */
00230 #define MT25TL01G_FSR_PGERR                   ((uint8_t)0x10)    /*!< Program error */
00231 #define MT25TL01G_FSR_ERERR                   ((uint8_t)0x20)    /*!< Erase error */
00232 #define MT25TL01G_FSR_ERSUS                   ((uint8_t)0x40)    /*!< Erase operation suspended */
00233 #define MT25TL01G_FSR_READY                   ((uint8_t)0x80)    /*!< Ready or command in progress */
00234 
00235 
00236 /**
00237   * @}
00238   */
00239   
00240 /** @defgroup MT25TL01G_Exported_Functions
00241   * @{
00242   */ 
00243 /**
00244   * @}
00245   */ 
00246       
00247 #ifdef __cplusplus
00248 }
00249 #endif
00250 
00251 #endif /* __MT25TL01G_H */
00252 
00253 /**
00254   * @}
00255   */ 
00256 
00257 /**
00258   * @}
00259   */ 
00260 
00261 /**
00262   * @}
00263   */
00264   
00265 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/